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MdeModulePkg: ATA performance tuning.
[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AtaAtapiPassThru / IdeMode.c
1 /** @file
2 Header file for AHCI mode of ATA host controller.
3
4 Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "AtaAtapiPassThru.h"
16
17 /**
18 read a one-byte data from a IDE port.
19
20 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
21 @param Port The IDE Port number
22
23 @return the one-byte data read from IDE port
24 **/
25 UINT8
26 EFIAPI
27 IdeReadPortB (
28 IN EFI_PCI_IO_PROTOCOL *PciIo,
29 IN UINT16 Port
30 )
31 {
32 UINT8 Data;
33
34 ASSERT (PciIo != NULL);
35
36 Data = 0;
37 //
38 // perform 1-byte data read from register
39 //
40 PciIo->Io.Read (
41 PciIo,
42 EfiPciIoWidthUint8,
43 EFI_PCI_IO_PASS_THROUGH_BAR,
44 (UINT64) Port,
45 1,
46 &Data
47 );
48 return Data;
49 }
50
51 /**
52 write a 1-byte data to a specific IDE port.
53
54 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
55 @param Port The IDE port to be writen
56 @param Data The data to write to the port
57 **/
58 VOID
59 EFIAPI
60 IdeWritePortB (
61 IN EFI_PCI_IO_PROTOCOL *PciIo,
62 IN UINT16 Port,
63 IN UINT8 Data
64 )
65 {
66 ASSERT (PciIo != NULL);
67
68 //
69 // perform 1-byte data write to register
70 //
71 PciIo->Io.Write (
72 PciIo,
73 EfiPciIoWidthUint8,
74 EFI_PCI_IO_PASS_THROUGH_BAR,
75 (UINT64) Port,
76 1,
77 &Data
78 );
79 }
80
81 /**
82 write a 1-word data to a specific IDE port.
83
84 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
85 @param Port The IDE port to be writen
86 @param Data The data to write to the port
87 **/
88 VOID
89 EFIAPI
90 IdeWritePortW (
91 IN EFI_PCI_IO_PROTOCOL *PciIo,
92 IN UINT16 Port,
93 IN UINT16 Data
94 )
95 {
96 ASSERT (PciIo != NULL);
97
98 //
99 // perform 1-word data write to register
100 //
101 PciIo->Io.Write (
102 PciIo,
103 EfiPciIoWidthUint16,
104 EFI_PCI_IO_PASS_THROUGH_BAR,
105 (UINT64) Port,
106 1,
107 &Data
108 );
109 }
110
111 /**
112 write a 2-word data to a specific IDE port.
113
114 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
115 @param Port The IDE port to be writen
116 @param Data The data to write to the port
117 **/
118 VOID
119 EFIAPI
120 IdeWritePortDW (
121 IN EFI_PCI_IO_PROTOCOL *PciIo,
122 IN UINT16 Port,
123 IN UINT32 Data
124 )
125 {
126 ASSERT (PciIo != NULL);
127
128 //
129 // perform 2-word data write to register
130 //
131 PciIo->Io.Write (
132 PciIo,
133 EfiPciIoWidthUint32,
134 EFI_PCI_IO_PASS_THROUGH_BAR,
135 (UINT64) Port,
136 1,
137 &Data
138 );
139 }
140
141 /**
142 Write multiple words of data to the IDE data port.
143 Call the IO abstraction once to do the complete read,
144 not one word at a time
145
146 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
147 @param Port IO port to read
148 @param Count No. of UINT16's to read
149 @param Buffer Pointer to the data buffer for read
150
151 **/
152 VOID
153 EFIAPI
154 IdeWritePortWMultiple (
155 IN EFI_PCI_IO_PROTOCOL *PciIo,
156 IN UINT16 Port,
157 IN UINTN Count,
158 IN VOID *Buffer
159 )
160 {
161 ASSERT (PciIo != NULL);
162 ASSERT (Buffer != NULL);
163
164 //
165 // perform UINT16 data write to the FIFO
166 //
167 PciIo->Io.Write (
168 PciIo,
169 EfiPciIoWidthFifoUint16,
170 EFI_PCI_IO_PASS_THROUGH_BAR,
171 (UINT64) Port,
172 Count,
173 (UINT16 *) Buffer
174 );
175
176 }
177
178 /**
179 Reads multiple words of data from the IDE data port.
180 Call the IO abstraction once to do the complete read,
181 not one word at a time
182
183 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
184 @param Port IO port to read
185 @param Count Number of UINT16's to read
186 @param Buffer Pointer to the data buffer for read
187
188 **/
189 VOID
190 EFIAPI
191 IdeReadPortWMultiple (
192 IN EFI_PCI_IO_PROTOCOL *PciIo,
193 IN UINT16 Port,
194 IN UINTN Count,
195 IN VOID *Buffer
196 )
197 {
198 ASSERT (PciIo != NULL);
199 ASSERT (Buffer != NULL);
200
201 //
202 // Perform UINT16 data read from FIFO
203 //
204 PciIo->Io.Read (
205 PciIo,
206 EfiPciIoWidthFifoUint16,
207 EFI_PCI_IO_PASS_THROUGH_BAR,
208 (UINT64) Port,
209 Count,
210 (UINT16 *) Buffer
211 );
212
213 }
214
215 /**
216 This function is used to analyze the Status Register and print out
217 some debug information and if there is ERR bit set in the Status
218 Register, the Error Register's value is also be parsed and print out.
219
220 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
221 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
222 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
223
224 **/
225 VOID
226 EFIAPI
227 DumpAllIdeRegisters (
228 IN EFI_PCI_IO_PROTOCOL *PciIo,
229 IN EFI_IDE_REGISTERS *IdeRegisters,
230 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
231 )
232 {
233 EFI_ATA_STATUS_BLOCK StatusBlock;
234
235 ASSERT (PciIo != NULL);
236 ASSERT (IdeRegisters != NULL);
237
238 ZeroMem (&StatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
239
240 StatusBlock.AtaStatus = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
241 StatusBlock.AtaError = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
242 StatusBlock.AtaSectorCount = IdeReadPortB (PciIo, IdeRegisters->SectorCount);
243 StatusBlock.AtaSectorCountExp = IdeReadPortB (PciIo, IdeRegisters->SectorCount);
244 StatusBlock.AtaSectorNumber = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);
245 StatusBlock.AtaSectorNumberExp = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);
246 StatusBlock.AtaCylinderLow = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
247 StatusBlock.AtaCylinderLowExp = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
248 StatusBlock.AtaCylinderHigh = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);
249 StatusBlock.AtaCylinderHighExp = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);
250 StatusBlock.AtaDeviceHead = IdeReadPortB (PciIo, IdeRegisters->Head);
251
252 if (AtaStatusBlock != NULL) {
253 //
254 // Dump the content of all ATA registers.
255 //
256 CopyMem (AtaStatusBlock, &StatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
257 }
258
259 DEBUG_CODE_BEGIN ();
260 if ((StatusBlock.AtaStatus & ATA_STSREG_DWF) != 0) {
261 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Write Fault\n", StatusBlock.AtaStatus));
262 }
263
264 if ((StatusBlock.AtaStatus & ATA_STSREG_CORR) != 0) {
265 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Corrected Data\n", StatusBlock.AtaStatus));
266 }
267
268 if ((StatusBlock.AtaStatus & ATA_STSREG_ERR) != 0) {
269 if ((StatusBlock.AtaError & ATA_ERRREG_BBK) != 0) {
270 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Bad Block Detected\n", StatusBlock.AtaError));
271 }
272
273 if ((StatusBlock.AtaError & ATA_ERRREG_UNC) != 0) {
274 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Uncorrectable Data\n", StatusBlock.AtaError));
275 }
276
277 if ((StatusBlock.AtaError & ATA_ERRREG_MC) != 0) {
278 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Media Change\n", StatusBlock.AtaError));
279 }
280
281 if ((StatusBlock.AtaError & ATA_ERRREG_ABRT) != 0) {
282 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Abort\n", StatusBlock.AtaError));
283 }
284
285 if ((StatusBlock.AtaError & ATA_ERRREG_TK0NF) != 0) {
286 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Track 0 Not Found\n", StatusBlock.AtaError));
287 }
288
289 if ((StatusBlock.AtaError & ATA_ERRREG_AMNF) != 0) {
290 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Address Mark Not Found\n", StatusBlock.AtaError));
291 }
292 }
293 DEBUG_CODE_END ();
294 }
295
296 /**
297 This function is used to analyze the Status Register at the condition that BSY is zero.
298 if there is ERR bit set in the Status Register, then return error.
299
300 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
301 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
302
303 @retval EFI_SUCCESS No err information in the Status Register.
304 @retval EFI_DEVICE_ERROR Any err information in the Status Register.
305
306 **/
307 EFI_STATUS
308 EFIAPI
309 CheckStatusRegister (
310 IN EFI_PCI_IO_PROTOCOL *PciIo,
311 IN EFI_IDE_REGISTERS *IdeRegisters
312 )
313 {
314 UINT8 StatusRegister;
315
316 ASSERT (PciIo != NULL);
317 ASSERT (IdeRegisters != NULL);
318
319 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
320
321 if ((StatusRegister & ATA_STSREG_BSY) == 0) {
322 if ((StatusRegister & (ATA_STSREG_ERR | ATA_STSREG_DWF | ATA_STSREG_CORR)) == 0) {
323 return EFI_SUCCESS;
324 } else {
325 return EFI_DEVICE_ERROR;
326 }
327 }
328 return EFI_SUCCESS;
329 }
330
331 /**
332 This function is used to poll for the DRQ bit clear in the Status
333 Register. DRQ is cleared when the device is finished transferring data.
334 So this function is called after data transfer is finished.
335
336 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
337 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
338 @param Timeout The time to complete the command, uses 100ns as a unit.
339
340 @retval EFI_SUCCESS DRQ bit clear within the time out.
341
342 @retval EFI_TIMEOUT DRQ bit not clear within the time out.
343
344 @note
345 Read Status Register will clear interrupt status.
346
347 **/
348 EFI_STATUS
349 EFIAPI
350 DRQClear (
351 IN EFI_PCI_IO_PROTOCOL *PciIo,
352 IN EFI_IDE_REGISTERS *IdeRegisters,
353 IN UINT64 Timeout
354 )
355 {
356 UINT32 Delay;
357 UINT8 StatusRegister;
358
359 ASSERT (PciIo != NULL);
360 ASSERT (IdeRegisters != NULL);
361
362 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
363 do {
364 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
365
366 //
367 // Wait for BSY == 0, then judge if DRQ is clear
368 //
369 if ((StatusRegister & ATA_STSREG_BSY) == 0) {
370 if ((StatusRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
371 return EFI_DEVICE_ERROR;
372 } else {
373 return EFI_SUCCESS;
374 }
375 }
376
377 //
378 // Stall for 100 microseconds.
379 //
380 MicroSecondDelay (100);
381
382 Delay--;
383
384 } while (Delay > 0);
385
386 return EFI_TIMEOUT;
387 }
388 /**
389 This function is used to poll for the DRQ bit clear in the Alternate
390 Status Register. DRQ is cleared when the device is finished
391 transferring data. So this function is called after data transfer
392 is finished.
393
394 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
395 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
396 @param Timeout The time to complete the command, uses 100ns as a unit.
397
398 @retval EFI_SUCCESS DRQ bit clear within the time out.
399
400 @retval EFI_TIMEOUT DRQ bit not clear within the time out.
401 @note Read Alternate Status Register will not clear interrupt status.
402
403 **/
404 EFI_STATUS
405 EFIAPI
406 DRQClear2 (
407 IN EFI_PCI_IO_PROTOCOL *PciIo,
408 IN EFI_IDE_REGISTERS *IdeRegisters,
409 IN UINT64 Timeout
410 )
411 {
412 UINT32 Delay;
413 UINT8 AltRegister;
414
415 ASSERT (PciIo != NULL);
416 ASSERT (IdeRegisters != NULL);
417
418 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
419 do {
420 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
421
422 //
423 // Wait for BSY == 0, then judge if DRQ is clear
424 //
425 if ((AltRegister & ATA_STSREG_BSY) == 0) {
426 if ((AltRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
427 return EFI_DEVICE_ERROR;
428 } else {
429 return EFI_SUCCESS;
430 }
431 }
432
433 //
434 // Stall for 100 microseconds.
435 //
436 MicroSecondDelay (100);
437
438 Delay--;
439
440 } while (Delay > 0);
441
442 return EFI_TIMEOUT;
443 }
444
445 /**
446 This function is used to poll for the DRQ bit set in the
447 Status Register.
448 DRQ is set when the device is ready to transfer data. So this function
449 is called after the command is sent to the device and before required
450 data is transferred.
451
452 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
453 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
454 @param Timeout The time to complete the command, uses 100ns as a unit.
455
456 @retval EFI_SUCCESS DRQ bit set within the time out.
457 @retval EFI_TIMEOUT DRQ bit not set within the time out.
458 @retval EFI_ABORTED DRQ bit not set caused by the command abort.
459
460 @note Read Status Register will clear interrupt status.
461
462 **/
463 EFI_STATUS
464 EFIAPI
465 DRQReady (
466 IN EFI_PCI_IO_PROTOCOL *PciIo,
467 IN EFI_IDE_REGISTERS *IdeRegisters,
468 IN UINT64 Timeout
469 )
470 {
471 UINT32 Delay;
472 UINT8 StatusRegister;
473 UINT8 ErrorRegister;
474
475 ASSERT (PciIo != NULL);
476 ASSERT (IdeRegisters != NULL);
477
478 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
479 do {
480 //
481 // Read Status Register will clear interrupt
482 //
483 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
484
485 //
486 // Wait for BSY == 0, then judge if DRQ is clear or ERR is set
487 //
488 if ((StatusRegister & ATA_STSREG_BSY) == 0) {
489 if ((StatusRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {
490 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
491
492 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
493 return EFI_ABORTED;
494 }
495 return EFI_DEVICE_ERROR;
496 }
497
498 if ((StatusRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
499 return EFI_SUCCESS;
500 } else {
501 return EFI_NOT_READY;
502 }
503 }
504
505 //
506 // Stall for 100 microseconds.
507 //
508 MicroSecondDelay (100);
509
510 Delay--;
511 } while (Delay > 0);
512
513 return EFI_TIMEOUT;
514 }
515 /**
516 This function is used to poll for the DRQ bit set in the Alternate Status Register.
517 DRQ is set when the device is ready to transfer data. So this function is called after
518 the command is sent to the device and before required data is transferred.
519
520 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
521 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
522 @param Timeout The time to complete the command, uses 100ns as a unit.
523
524 @retval EFI_SUCCESS DRQ bit set within the time out.
525 @retval EFI_TIMEOUT DRQ bit not set within the time out.
526 @retval EFI_ABORTED DRQ bit not set caused by the command abort.
527 @note Read Alternate Status Register will not clear interrupt status.
528
529 **/
530 EFI_STATUS
531 EFIAPI
532 DRQReady2 (
533 IN EFI_PCI_IO_PROTOCOL *PciIo,
534 IN EFI_IDE_REGISTERS *IdeRegisters,
535 IN UINT64 Timeout
536 )
537 {
538 UINT32 Delay;
539 UINT8 AltRegister;
540 UINT8 ErrorRegister;
541
542 ASSERT (PciIo != NULL);
543 ASSERT (IdeRegisters != NULL);
544
545 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
546
547 do {
548 //
549 // Read Alternate Status Register will not clear interrupt status
550 //
551 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
552 //
553 // Wait for BSY == 0, then judge if DRQ is clear or ERR is set
554 //
555 if ((AltRegister & ATA_STSREG_BSY) == 0) {
556 if ((AltRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {
557 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
558
559 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
560 return EFI_ABORTED;
561 }
562 return EFI_DEVICE_ERROR;
563 }
564
565 if ((AltRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
566 return EFI_SUCCESS;
567 } else {
568 return EFI_NOT_READY;
569 }
570 }
571
572 //
573 // Stall for 100 microseconds.
574 //
575 MicroSecondDelay (100);
576
577 Delay--;
578 } while (Delay > 0);
579
580 return EFI_TIMEOUT;
581 }
582
583 /**
584 This function is used to poll for the DRDY bit set in the Status Register. DRDY
585 bit is set when the device is ready to accept command. Most ATA commands must be
586 sent after DRDY set except the ATAPI Packet Command.
587
588 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
589 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
590 @param Timeout The time to complete the command, uses 100ns as a unit.
591
592 @retval EFI_SUCCESS DRDY bit set within the time out.
593 @retval EFI_TIMEOUT DRDY bit not set within the time out.
594
595 @note Read Status Register will clear interrupt status.
596 **/
597 EFI_STATUS
598 EFIAPI
599 DRDYReady (
600 IN EFI_PCI_IO_PROTOCOL *PciIo,
601 IN EFI_IDE_REGISTERS *IdeRegisters,
602 IN UINT64 Timeout
603 )
604 {
605 UINT32 Delay;
606 UINT8 StatusRegister;
607 UINT8 ErrorRegister;
608
609 ASSERT (PciIo != NULL);
610 ASSERT (IdeRegisters != NULL);
611
612 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
613 do {
614 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
615 //
616 // Wait for BSY == 0, then judge if DRDY is set or ERR is set
617 //
618 if ((StatusRegister & ATA_STSREG_BSY) == 0) {
619 if ((StatusRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {
620 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
621
622 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
623 return EFI_ABORTED;
624 }
625 return EFI_DEVICE_ERROR;
626 }
627
628 if ((StatusRegister & ATA_STSREG_DRDY) == ATA_STSREG_DRDY) {
629 return EFI_SUCCESS;
630 } else {
631 return EFI_DEVICE_ERROR;
632 }
633 }
634
635 //
636 // Stall for 100 microseconds.
637 //
638 MicroSecondDelay (100);
639
640 Delay--;
641 } while (Delay > 0);
642
643 return EFI_TIMEOUT;
644 }
645
646 /**
647 This function is used to poll for the DRDY bit set in the Alternate Status Register.
648 DRDY bit is set when the device is ready to accept command. Most ATA commands must
649 be sent after DRDY set except the ATAPI Packet Command.
650
651 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
652 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
653 @param Timeout The time to complete the command, uses 100ns as a unit.
654
655 @retval EFI_SUCCESS DRDY bit set within the time out.
656 @retval EFI_TIMEOUT DRDY bit not set within the time out.
657
658 @note Read Alternate Status Register will clear interrupt status.
659
660 **/
661 EFI_STATUS
662 EFIAPI
663 DRDYReady2 (
664 IN EFI_PCI_IO_PROTOCOL *PciIo,
665 IN EFI_IDE_REGISTERS *IdeRegisters,
666 IN UINT64 Timeout
667 )
668 {
669 UINT32 Delay;
670 UINT8 AltRegister;
671 UINT8 ErrorRegister;
672
673 ASSERT (PciIo != NULL);
674 ASSERT (IdeRegisters != NULL);
675
676 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
677 do {
678 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
679 //
680 // Wait for BSY == 0, then judge if DRDY is set or ERR is set
681 //
682 if ((AltRegister & ATA_STSREG_BSY) == 0) {
683 if ((AltRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {
684 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
685
686 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
687 return EFI_ABORTED;
688 }
689 return EFI_DEVICE_ERROR;
690 }
691
692 if ((AltRegister & ATA_STSREG_DRDY) == ATA_STSREG_DRDY) {
693 return EFI_SUCCESS;
694 } else {
695 return EFI_DEVICE_ERROR;
696 }
697 }
698
699 //
700 // Stall for 100 microseconds.
701 //
702 MicroSecondDelay (100);
703
704 Delay--;
705 } while (Delay > 0);
706
707 return EFI_TIMEOUT;
708 }
709
710 /**
711 This function is used to poll for the BSY bit clear in the Status Register. BSY
712 is clear when the device is not busy. Every command must be sent after device is not busy.
713
714 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
715 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
716 @param Timeout The time to complete the command, uses 100ns as a unit.
717
718 @retval EFI_SUCCESS BSY bit clear within the time out.
719 @retval EFI_TIMEOUT BSY bit not clear within the time out.
720
721 @note Read Status Register will clear interrupt status.
722 **/
723 EFI_STATUS
724 EFIAPI
725 WaitForBSYClear (
726 IN EFI_PCI_IO_PROTOCOL *PciIo,
727 IN EFI_IDE_REGISTERS *IdeRegisters,
728 IN UINT64 Timeout
729 )
730 {
731 UINT32 Delay;
732 UINT8 StatusRegister;
733
734 ASSERT (PciIo != NULL);
735 ASSERT (IdeRegisters != NULL);
736
737 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
738 do {
739 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
740
741 if ((StatusRegister & ATA_STSREG_BSY) == 0x00) {
742 return EFI_SUCCESS;
743 }
744
745 //
746 // Stall for 100 microseconds.
747 //
748 MicroSecondDelay (100);
749
750 Delay--;
751
752 } while (Delay > 0);
753
754 return EFI_TIMEOUT;
755 }
756
757 /**
758 This function is used to poll for the BSY bit clear in the Status Register. BSY
759 is clear when the device is not busy. Every command must be sent after device is not busy.
760
761 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
762 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
763 @param Timeout The time to complete the command, uses 100ns as a unit.
764
765 @retval EFI_SUCCESS BSY bit clear within the time out.
766 @retval EFI_TIMEOUT BSY bit not clear within the time out.
767
768 @note Read Status Register will clear interrupt status.
769 **/
770 EFI_STATUS
771 EFIAPI
772 WaitForBSYClear2 (
773 IN EFI_PCI_IO_PROTOCOL *PciIo,
774 IN EFI_IDE_REGISTERS *IdeRegisters,
775 IN UINT64 Timeout
776 )
777 {
778 UINT32 Delay;
779 UINT8 AltStatusRegister;
780
781 ASSERT (PciIo != NULL);
782 ASSERT (IdeRegisters != NULL);
783
784 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
785 do {
786 AltStatusRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
787
788 if ((AltStatusRegister & ATA_STSREG_BSY) == 0x00) {
789 return EFI_SUCCESS;
790 }
791
792 //
793 // Stall for 100 microseconds.
794 //
795 MicroSecondDelay (100);
796
797 Delay--;
798
799 } while (Delay > 0);
800
801 return EFI_TIMEOUT;
802 }
803
804 /**
805 Get IDE i/o port registers' base addresses by mode.
806
807 In 'Compatibility' mode, use fixed addresses.
808 In Native-PCI mode, get base addresses from BARs in the PCI IDE controller's
809 Configuration Space.
810
811 The steps to get IDE i/o port registers' base addresses for each channel
812 as follows:
813
814 1. Examine the Programming Interface byte of the Class Code fields in PCI IDE
815 controller's Configuration Space to determine the operating mode.
816
817 2. a) In 'Compatibility' mode, use fixed addresses shown in the Table 1 below.
818 ___________________________________________
819 | | Command Block | Control Block |
820 | Channel | Registers | Registers |
821 |___________|_______________|_______________|
822 | Primary | 1F0h - 1F7h | 3F6h - 3F7h |
823 |___________|_______________|_______________|
824 | Secondary | 170h - 177h | 376h - 377h |
825 |___________|_______________|_______________|
826
827 Table 1. Compatibility resource mappings
828
829 b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs
830 in IDE controller's PCI Configuration Space, shown in the Table 2 below.
831 ___________________________________________________
832 | | Command Block | Control Block |
833 | Channel | Registers | Registers |
834 |___________|___________________|___________________|
835 | Primary | BAR at offset 0x10| BAR at offset 0x14|
836 |___________|___________________|___________________|
837 | Secondary | BAR at offset 0x18| BAR at offset 0x1C|
838 |___________|___________________|___________________|
839
840 Table 2. BARs for Register Mapping
841
842 @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance
843 @param[in, out] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to
844 store the IDE i/o port registers' base addresses
845
846 @retval EFI_UNSUPPORTED Return this value when the BARs is not IO type
847 @retval EFI_SUCCESS Get the Base address successfully
848 @retval Other Read the pci configureation data error
849
850 **/
851 EFI_STATUS
852 EFIAPI
853 GetIdeRegisterIoAddr (
854 IN EFI_PCI_IO_PROTOCOL *PciIo,
855 IN OUT EFI_IDE_REGISTERS *IdeRegisters
856 )
857 {
858 EFI_STATUS Status;
859 PCI_TYPE00 PciData;
860 UINT16 CommandBlockBaseAddr;
861 UINT16 ControlBlockBaseAddr;
862 UINT16 BusMasterBaseAddr;
863
864 if ((PciIo == NULL) || (IdeRegisters == NULL)) {
865 return EFI_INVALID_PARAMETER;
866 }
867
868 Status = PciIo->Pci.Read (
869 PciIo,
870 EfiPciIoWidthUint8,
871 0,
872 sizeof (PciData),
873 &PciData
874 );
875
876 if (EFI_ERROR (Status)) {
877 return Status;
878 }
879
880 BusMasterBaseAddr = (UINT16) ((PciData.Device.Bar[4] & 0x0000fff0));
881
882 if ((PciData.Hdr.ClassCode[0] & IDE_PRIMARY_OPERATING_MODE) == 0) {
883 CommandBlockBaseAddr = 0x1f0;
884 ControlBlockBaseAddr = 0x3f6;
885 } else {
886 //
887 // The BARs should be of IO type
888 //
889 if ((PciData.Device.Bar[0] & BIT0) == 0 ||
890 (PciData.Device.Bar[1] & BIT0) == 0) {
891 return EFI_UNSUPPORTED;
892 }
893
894 CommandBlockBaseAddr = (UINT16) (PciData.Device.Bar[0] & 0x0000fff8);
895 ControlBlockBaseAddr = (UINT16) ((PciData.Device.Bar[1] & 0x0000fffc) + 2);
896 }
897
898 //
899 // Calculate IDE primary channel I/O register base address.
900 //
901 IdeRegisters[EfiIdePrimary].Data = CommandBlockBaseAddr;
902 IdeRegisters[EfiIdePrimary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);
903 IdeRegisters[EfiIdePrimary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);
904 IdeRegisters[EfiIdePrimary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);
905 IdeRegisters[EfiIdePrimary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);
906 IdeRegisters[EfiIdePrimary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);
907 IdeRegisters[EfiIdePrimary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);
908 IdeRegisters[EfiIdePrimary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);
909 IdeRegisters[EfiIdePrimary].AltOrDev = ControlBlockBaseAddr;
910 IdeRegisters[EfiIdePrimary].BusMasterBaseAddr = BusMasterBaseAddr;
911
912 if ((PciData.Hdr.ClassCode[0] & IDE_SECONDARY_OPERATING_MODE) == 0) {
913 CommandBlockBaseAddr = 0x170;
914 ControlBlockBaseAddr = 0x376;
915 } else {
916 //
917 // The BARs should be of IO type
918 //
919 if ((PciData.Device.Bar[2] & BIT0) == 0 ||
920 (PciData.Device.Bar[3] & BIT0) == 0) {
921 return EFI_UNSUPPORTED;
922 }
923
924 CommandBlockBaseAddr = (UINT16) (PciData.Device.Bar[2] & 0x0000fff8);
925 ControlBlockBaseAddr = (UINT16) ((PciData.Device.Bar[3] & 0x0000fffc) + 2);
926 }
927
928 //
929 // Calculate IDE secondary channel I/O register base address.
930 //
931 IdeRegisters[EfiIdeSecondary].Data = CommandBlockBaseAddr;
932 IdeRegisters[EfiIdeSecondary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);
933 IdeRegisters[EfiIdeSecondary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);
934 IdeRegisters[EfiIdeSecondary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);
935 IdeRegisters[EfiIdeSecondary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);
936 IdeRegisters[EfiIdeSecondary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);
937 IdeRegisters[EfiIdeSecondary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);
938 IdeRegisters[EfiIdeSecondary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);
939 IdeRegisters[EfiIdeSecondary].AltOrDev = ControlBlockBaseAddr;
940 IdeRegisters[EfiIdeSecondary].BusMasterBaseAddr = (UINT16) (BusMasterBaseAddr + 0x8);
941
942 return EFI_SUCCESS;
943 }
944
945 /**
946 This function is used to implement the Soft Reset on the specified device. But,
947 the ATA Soft Reset mechanism is so strong a reset method that it will force
948 resetting on both devices connected to the same cable.
949
950 It is called by IdeBlkIoReset(), a interface function of Block
951 I/O protocol.
952
953 This function can also be used by the ATAPI device to perform reset when
954 ATAPI Reset command is failed.
955
956 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
957 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
958 @param Timeout The time to complete the command, uses 100ns as a unit.
959
960 @retval EFI_SUCCESS Soft reset completes successfully.
961 @retval EFI_DEVICE_ERROR Any step during the reset process is failed.
962
963 @note The registers initial values after ATA soft reset are different
964 to the ATA device and ATAPI device.
965 **/
966 EFI_STATUS
967 EFIAPI
968 AtaSoftReset (
969 IN EFI_PCI_IO_PROTOCOL *PciIo,
970 IN EFI_IDE_REGISTERS *IdeRegisters,
971 IN UINT64 Timeout
972 )
973 {
974 UINT8 DeviceControl;
975
976 DeviceControl = 0;
977 //
978 // disable Interrupt and set SRST bit to initiate soft reset
979 //
980 DeviceControl = ATA_CTLREG_SRST | ATA_CTLREG_IEN_L;
981
982 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
983
984 //
985 // SRST should assert for at least 5 us, we use 10 us for
986 // better compatibility
987 //
988 MicroSecondDelay (10);
989
990 //
991 // Enable interrupt to support UDMA, and clear SRST bit
992 //
993 DeviceControl = 0;
994 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
995
996 //
997 // Wait for at least 10 ms to check BSY status, we use 10 ms
998 // for better compatibility
999 //
1000 MicroSecondDelay (10000);
1001
1002 //
1003 // slave device needs at most 31ms to clear BSY
1004 //
1005 if (WaitForBSYClear (PciIo, IdeRegisters, Timeout) == EFI_TIMEOUT) {
1006 return EFI_DEVICE_ERROR;
1007 }
1008
1009 return EFI_SUCCESS;
1010 }
1011
1012 /**
1013 Send ATA Ext command into device with NON_DATA protocol.
1014
1015 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
1016 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1017 @param AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.
1018 @param Timeout The time to complete the command, uses 100ns as a unit.
1019
1020 @retval EFI_SUCCESS Reading succeed
1021 @retval EFI_DEVICE_ERROR Error executing commands on this device.
1022
1023 **/
1024 EFI_STATUS
1025 EFIAPI
1026 AtaIssueCommand (
1027 IN EFI_PCI_IO_PROTOCOL *PciIo,
1028 IN EFI_IDE_REGISTERS *IdeRegisters,
1029 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1030 IN UINT64 Timeout
1031 )
1032 {
1033 EFI_STATUS Status;
1034 UINT8 DeviceHead;
1035 UINT8 AtaCommand;
1036
1037 ASSERT (PciIo != NULL);
1038 ASSERT (IdeRegisters != NULL);
1039 ASSERT (AtaCommandBlock != NULL);
1040
1041 DeviceHead = AtaCommandBlock->AtaDeviceHead;
1042 AtaCommand = AtaCommandBlock->AtaCommand;
1043
1044 Status = WaitForBSYClear (PciIo, IdeRegisters, Timeout);
1045 if (EFI_ERROR (Status)) {
1046 return EFI_DEVICE_ERROR;
1047 }
1048
1049 //
1050 // Select device (bit4), set LBA mode(bit6) (use 0xe0 for compatibility)
1051 //
1052 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8) (0xe0 | DeviceHead));
1053
1054 //
1055 // set all the command parameters
1056 // Before write to all the following registers, BSY and DRQ must be 0.
1057 //
1058 Status = DRQClear2 (PciIo, IdeRegisters, Timeout);
1059 if (EFI_ERROR (Status)) {
1060 return EFI_DEVICE_ERROR;
1061 }
1062
1063 //
1064 // Fill the feature register, which is a two-byte FIFO. Need write twice.
1065 //
1066 IdeWritePortB (PciIo, IdeRegisters->ErrOrFeature, AtaCommandBlock->AtaFeaturesExp);
1067 IdeWritePortB (PciIo, IdeRegisters->ErrOrFeature, AtaCommandBlock->AtaFeatures);
1068
1069 //
1070 // Fill the sector count register, which is a two-byte FIFO. Need write twice.
1071 //
1072 IdeWritePortB (PciIo, IdeRegisters->SectorCount, AtaCommandBlock->AtaSectorCountExp);
1073 IdeWritePortB (PciIo, IdeRegisters->SectorCount, AtaCommandBlock->AtaSectorCount);
1074
1075 //
1076 // Fill the start LBA registers, which are also two-byte FIFO
1077 //
1078 IdeWritePortB (PciIo, IdeRegisters->SectorNumber, AtaCommandBlock->AtaSectorNumberExp);
1079 IdeWritePortB (PciIo, IdeRegisters->SectorNumber, AtaCommandBlock->AtaSectorNumber);
1080
1081 IdeWritePortB (PciIo, IdeRegisters->CylinderLsb, AtaCommandBlock->AtaCylinderLowExp);
1082 IdeWritePortB (PciIo, IdeRegisters->CylinderLsb, AtaCommandBlock->AtaCylinderLow);
1083
1084 IdeWritePortB (PciIo, IdeRegisters->CylinderMsb, AtaCommandBlock->AtaCylinderHighExp);
1085 IdeWritePortB (PciIo, IdeRegisters->CylinderMsb, AtaCommandBlock->AtaCylinderHigh);
1086
1087 //
1088 // Send command via Command Register
1089 //
1090 IdeWritePortB (PciIo, IdeRegisters->CmdOrStatus, AtaCommand);
1091
1092 //
1093 // Stall at least 400 microseconds.
1094 //
1095 MicroSecondDelay (400);
1096
1097 return EFI_SUCCESS;
1098 }
1099
1100 /**
1101 This function is used to send out ATA commands conforms to the PIO Data In Protocol.
1102
1103 @param[in] PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data
1104 structure.
1105 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1106 @param[in, out] Buffer A pointer to the source buffer for the data.
1107 @param[in] ByteCount The length of the data.
1108 @param[in] Read Flag used to determine the data transfer direction.
1109 Read equals 1, means data transferred from device
1110 to host;Read equals 0, means data transferred
1111 from host to device.
1112 @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.
1113 @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1114 @param[in] Timeout The time to complete the command, uses 100ns as a unit.
1115 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1116 used by non-blocking mode.
1117
1118 @retval EFI_SUCCESS send out the ATA command and device send required data successfully.
1119 @retval EFI_DEVICE_ERROR command sent failed.
1120
1121 **/
1122 EFI_STATUS
1123 EFIAPI
1124 AtaPioDataInOut (
1125 IN EFI_PCI_IO_PROTOCOL *PciIo,
1126 IN EFI_IDE_REGISTERS *IdeRegisters,
1127 IN OUT VOID *Buffer,
1128 IN UINT64 ByteCount,
1129 IN BOOLEAN Read,
1130 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1131 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1132 IN UINT64 Timeout,
1133 IN ATA_NONBLOCK_TASK *Task
1134 )
1135 {
1136 UINTN WordCount;
1137 UINTN Increment;
1138 UINT16 *Buffer16;
1139 EFI_STATUS Status;
1140
1141 if ((PciIo == NULL) || (IdeRegisters == NULL) || (Buffer == NULL) || (AtaCommandBlock == NULL)) {
1142 return EFI_INVALID_PARAMETER;
1143 }
1144
1145 //
1146 // Issue ATA command
1147 //
1148 Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);
1149 if (EFI_ERROR (Status)) {
1150 Status = EFI_DEVICE_ERROR;
1151 goto Exit;
1152 }
1153
1154 Buffer16 = (UINT16 *) Buffer;
1155
1156 //
1157 // According to PIO data in protocol, host can perform a series of reads to
1158 // the data register after each time device set DRQ ready;
1159 // The data size of "a series of read" is command specific.
1160 // For most ATA command, data size received from device will not exceed
1161 // 1 sector, hence the data size for "a series of read" can be the whole data
1162 // size of one command request.
1163 // For ATA command such as Read Sector command, the data size of one ATA
1164 // command request is often larger than 1 sector, according to the
1165 // Read Sector command, the data size of "a series of read" is exactly 1
1166 // sector.
1167 // Here for simplification reason, we specify the data size for
1168 // "a series of read" to 1 sector (256 words) if data size of one ATA command
1169 // request is larger than 256 words.
1170 //
1171 Increment = 256;
1172
1173 //
1174 // used to record bytes of currently transfered data
1175 //
1176 WordCount = 0;
1177
1178 while (WordCount < RShiftU64(ByteCount, 1)) {
1179 //
1180 // Poll DRQ bit set, data transfer can be performed only when DRQ is ready
1181 //
1182 Status = DRQReady2 (PciIo, IdeRegisters, Timeout);
1183 if (EFI_ERROR (Status)) {
1184 Status = EFI_DEVICE_ERROR;
1185 goto Exit;
1186 }
1187
1188 //
1189 // Get the byte count for one series of read
1190 //
1191 if ((WordCount + Increment) > RShiftU64(ByteCount, 1)) {
1192 Increment = (UINTN)(RShiftU64(ByteCount, 1) - WordCount);
1193 }
1194
1195 if (Read) {
1196 IdeReadPortWMultiple (
1197 PciIo,
1198 IdeRegisters->Data,
1199 Increment,
1200 Buffer16
1201 );
1202 } else {
1203 IdeWritePortWMultiple (
1204 PciIo,
1205 IdeRegisters->Data,
1206 Increment,
1207 Buffer16
1208 );
1209 }
1210
1211 Status = CheckStatusRegister (PciIo, IdeRegisters);
1212 if (EFI_ERROR (Status)) {
1213 Status = EFI_DEVICE_ERROR;
1214 goto Exit;
1215 }
1216
1217 WordCount += Increment;
1218 Buffer16 += Increment;
1219 }
1220
1221 Status = DRQClear (PciIo, IdeRegisters, Timeout);
1222 if (EFI_ERROR (Status)) {
1223 Status = EFI_DEVICE_ERROR;
1224 goto Exit;
1225 }
1226
1227 Exit:
1228 //
1229 // Dump All Ide registers to ATA_STATUS_BLOCK
1230 //
1231 DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);
1232
1233 //
1234 // Not support the Non-blocking now,just do the blocking process.
1235 //
1236 return Status;
1237 }
1238
1239 /**
1240 Send ATA command into device with NON_DATA protocol
1241
1242 @param[in] PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE
1243 data structure.
1244 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1245 @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data
1246 structure.
1247 @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1248 @param[in] Timeout The time to complete the command, uses 100ns as a unit.
1249 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1250 used by non-blocking mode.
1251
1252 @retval EFI_SUCCESS Reading succeed
1253 @retval EFI_ABORTED Command failed
1254 @retval EFI_DEVICE_ERROR Device status error.
1255
1256 **/
1257 EFI_STATUS
1258 EFIAPI
1259 AtaNonDataCommandIn (
1260 IN EFI_PCI_IO_PROTOCOL *PciIo,
1261 IN EFI_IDE_REGISTERS *IdeRegisters,
1262 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1263 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1264 IN UINT64 Timeout,
1265 IN ATA_NONBLOCK_TASK *Task
1266 )
1267 {
1268 EFI_STATUS Status;
1269
1270 if ((PciIo == NULL) || (IdeRegisters == NULL) || (AtaCommandBlock == NULL)) {
1271 return EFI_INVALID_PARAMETER;
1272 }
1273
1274 //
1275 // Issue ATA command
1276 //
1277 Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);
1278 if (EFI_ERROR (Status)) {
1279 Status = EFI_DEVICE_ERROR;
1280 goto Exit;
1281 }
1282
1283 //
1284 // Wait for command completion
1285 //
1286 Status = WaitForBSYClear (PciIo, IdeRegisters, Timeout);
1287 if (EFI_ERROR (Status)) {
1288 Status = EFI_DEVICE_ERROR;
1289 goto Exit;
1290 }
1291
1292 Status = CheckStatusRegister (PciIo, IdeRegisters);
1293 if (EFI_ERROR (Status)) {
1294 Status = EFI_DEVICE_ERROR;
1295 goto Exit;
1296 }
1297
1298 Exit:
1299 //
1300 // Dump All Ide registers to ATA_STATUS_BLOCK
1301 //
1302 DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);
1303
1304 //
1305 // Not support the Non-blocking now,just do the blocking process.
1306 //
1307 return Status;
1308 }
1309
1310 /**
1311 Wait for memory to be set.
1312
1313 @param[in] PciIo The PCI IO protocol instance.
1314 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1315
1316 @retval EFI_DEVICE_ERROR The memory is not set.
1317 @retval EFI_TIMEOUT The memory setting is time out.
1318 @retval EFI_SUCCESS The memory is correct set.
1319
1320 **/
1321 EFI_STATUS
1322 AtaUdmStatusWait (
1323 IN EFI_PCI_IO_PROTOCOL *PciIo,
1324 IN EFI_IDE_REGISTERS *IdeRegisters
1325 )
1326 {
1327 UINT8 RegisterValue;
1328 EFI_STATUS Status;
1329 UINT16 IoPortForBmis;
1330 UINT64 Timeout;
1331
1332 Timeout = 2000;
1333
1334 while (TRUE) {
1335 Status = CheckStatusRegister (PciIo, IdeRegisters);
1336 if (EFI_ERROR (Status)) {
1337 Status = EFI_DEVICE_ERROR;
1338 break;
1339 }
1340
1341 IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);
1342 RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);
1343 if (((RegisterValue & BMIS_ERROR) != 0) || (Timeout == 0)) {
1344 DEBUG ((EFI_D_ERROR, "ATA UDMA operation fails\n"));
1345 Status = EFI_DEVICE_ERROR;
1346 break;
1347 }
1348
1349 if ((RegisterValue & BMIS_INTERRUPT) != 0) {
1350 Status = EFI_SUCCESS;
1351 break;
1352 }
1353 //
1354 // Stall for 1 milliseconds.
1355 //
1356 MicroSecondDelay (1000);
1357 Timeout--;
1358 }
1359
1360 return Status;
1361 }
1362
1363 /**
1364 Check if the memory to be set.
1365
1366 @param[in] PciIo The PCI IO protocol instance.
1367 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1368 used by non-blocking mode.
1369 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1370
1371 @retval EFI_DEVICE_ERROR The memory setting met a issue.
1372 @retval EFI_NOT_READY The memory is not set.
1373 @retval EFI_TIMEOUT The memory setting is time out.
1374 @retval EFI_SUCCESS The memory is correct set.
1375
1376 **/
1377 EFI_STATUS
1378 AtaUdmStatusCheck (
1379 IN EFI_PCI_IO_PROTOCOL *PciIo,
1380 IN ATA_NONBLOCK_TASK *Task,
1381 IN EFI_IDE_REGISTERS *IdeRegisters
1382 )
1383 {
1384 UINT8 RegisterValue;
1385 UINT16 IoPortForBmis;
1386 EFI_STATUS Status;
1387
1388 Task->RetryTimes--;
1389
1390 Status = CheckStatusRegister (PciIo, IdeRegisters);
1391 if (EFI_ERROR (Status)) {
1392 return EFI_DEVICE_ERROR;
1393 }
1394
1395 IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);
1396 RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);
1397
1398 if ((RegisterValue & BMIS_ERROR) != 0) {
1399 DEBUG ((EFI_D_ERROR, "ATA UDMA operation fails\n"));
1400 return EFI_DEVICE_ERROR;
1401 }
1402
1403 if ((RegisterValue & BMIS_INTERRUPT) != 0) {
1404 return EFI_SUCCESS;
1405 }
1406
1407 if (Task->RetryTimes == 0) {
1408 return EFI_TIMEOUT;
1409 } else {
1410 //
1411 // The memory is not set.
1412 //
1413 return EFI_NOT_READY;
1414 }
1415 }
1416
1417 /**
1418 Perform an ATA Udma operation (Read, ReadExt, Write, WriteExt).
1419
1420 @param[in] Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data
1421 structure.
1422 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1423 @param[in] Read Flag used to determine the data transfer
1424 direction. Read equals 1, means data transferred
1425 from device to host;Read equals 0, means data
1426 transferred from host to device.
1427 @param[in] DataBuffer A pointer to the source buffer for the data.
1428 @param[in] DataLength The length of the data.
1429 @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.
1430 @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1431 @param[in] Timeout The time to complete the command, uses 100ns as a unit.
1432 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1433 used by non-blocking mode.
1434
1435 @retval EFI_SUCCESS the operation is successful.
1436 @retval EFI_OUT_OF_RESOURCES Build PRD table failed
1437 @retval EFI_UNSUPPORTED Unknown channel or operations command
1438 @retval EFI_DEVICE_ERROR Ata command execute failed
1439
1440 **/
1441 EFI_STATUS
1442 EFIAPI
1443 AtaUdmaInOut (
1444 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
1445 IN EFI_IDE_REGISTERS *IdeRegisters,
1446 IN BOOLEAN Read,
1447 IN VOID *DataBuffer,
1448 IN UINT64 DataLength,
1449 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1450 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1451 IN UINT64 Timeout,
1452 IN ATA_NONBLOCK_TASK *Task
1453 )
1454 {
1455 EFI_STATUS Status;
1456 UINT16 IoPortForBmic;
1457 UINT16 IoPortForBmis;
1458 UINT16 IoPortForBmid;
1459
1460 UINTN PrdTableSize;
1461 EFI_PHYSICAL_ADDRESS PrdTableMapAddr;
1462 VOID *PrdTableMap;
1463 EFI_ATA_DMA_PRD *PrdBaseAddr;
1464 EFI_ATA_DMA_PRD *TempPrdBaseAddr;
1465 UINTN PrdTableNum;
1466
1467 UINT8 RegisterValue;
1468 UINTN PageCount;
1469 UINTN ByteCount;
1470 UINTN ByteRemaining;
1471 UINT8 DeviceControl;
1472
1473 VOID *BufferMap;
1474 EFI_PHYSICAL_ADDRESS BufferMapAddress;
1475 EFI_PCI_IO_PROTOCOL_OPERATION PciIoOperation;
1476
1477 UINT8 DeviceHead;
1478 EFI_PCI_IO_PROTOCOL *PciIo;
1479 EFI_TPL OldTpl;
1480
1481
1482 Status = EFI_SUCCESS;
1483 PrdBaseAddr = NULL;
1484 PrdTableMap = NULL;
1485 BufferMap = NULL;
1486 PageCount = 0;
1487 PciIo = Instance->PciIo;
1488
1489 if ((PciIo == NULL) || (IdeRegisters == NULL) || (DataBuffer == NULL) || (AtaCommandBlock == NULL)) {
1490 return EFI_INVALID_PARAMETER;
1491 }
1492
1493 //
1494 // Before starting the Blocking BlockIO operation, push to finish all non-blocking
1495 // BlockIO tasks.
1496 // Delay 1ms to simulate the blocking time out checking.
1497 //
1498 while ((Task == NULL) && (!IsListEmpty (&Instance->NonBlockingTaskList))) {
1499 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1500 AsyncNonBlockingTransferRoutine (NULL, Instance);
1501 gBS->RestoreTPL (OldTpl);
1502 //
1503 // Stall for 1 milliseconds.
1504 //
1505 MicroSecondDelay (1000);
1506 }
1507
1508 //
1509 // The data buffer should be even alignment
1510 //
1511 if (((UINTN)DataBuffer & 0x1) != 0) {
1512 return EFI_INVALID_PARAMETER;
1513 }
1514
1515 //
1516 // Set relevant IO Port address.
1517 //
1518 IoPortForBmic = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIC_OFFSET);
1519 IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);
1520 IoPortForBmid = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMID_OFFSET);
1521
1522 //
1523 // For Blocking mode, start the command.
1524 // For non-blocking mode, when the command is not started, start it, otherwise
1525 // go to check the status.
1526 //
1527 if (((Task != NULL) && (!Task->IsStart)) || (Task == NULL)) {
1528 //
1529 // Calculate the number of PRD entry.
1530 // Every entry in PRD table can specify a 64K memory region.
1531 //
1532 PrdTableNum = (UINTN)(RShiftU64(DataLength, 16) + 1);
1533
1534 //
1535 // Make sure that the memory region of PRD table is not cross 64K boundary
1536 //
1537 PrdTableSize = PrdTableNum * sizeof (EFI_ATA_DMA_PRD);
1538 if (PrdTableSize > 0x10000) {
1539 return EFI_INVALID_PARAMETER;
1540 }
1541
1542 //
1543 // Allocate buffer for PRD table initialization.
1544 //
1545 PageCount = EFI_SIZE_TO_PAGES (PrdTableSize);
1546 Status = PciIo->AllocateBuffer (
1547 PciIo,
1548 AllocateAnyPages,
1549 EfiBootServicesData,
1550 PageCount,
1551 (VOID **)&PrdBaseAddr,
1552 0
1553 );
1554 if (EFI_ERROR (Status)) {
1555 return EFI_OUT_OF_RESOURCES;
1556 }
1557
1558 ByteCount = EFI_PAGES_TO_SIZE (PageCount);
1559 Status = PciIo->Map (
1560 PciIo,
1561 EfiPciIoOperationBusMasterCommonBuffer,
1562 PrdBaseAddr,
1563 &ByteCount,
1564 &PrdTableMapAddr,
1565 &PrdTableMap
1566 );
1567 if (EFI_ERROR (Status) || (ByteCount != EFI_PAGES_TO_SIZE (PageCount))) {
1568 //
1569 // If the data length actually mapped is not equal to the requested amount,
1570 // it means the DMA operation may be broken into several discontinuous smaller chunks.
1571 // Can't handle this case.
1572 //
1573 PciIo->FreeBuffer (PciIo, PageCount, PrdBaseAddr);
1574 return EFI_OUT_OF_RESOURCES;
1575 }
1576
1577 ZeroMem ((VOID *) ((UINTN) PrdBaseAddr), ByteCount);
1578
1579 //
1580 // Map the host address of DataBuffer to DMA master address.
1581 //
1582 if (Read) {
1583 PciIoOperation = EfiPciIoOperationBusMasterWrite;
1584 } else {
1585 PciIoOperation = EfiPciIoOperationBusMasterRead;
1586 }
1587
1588 ByteCount = (UINTN)DataLength;
1589 Status = PciIo->Map (
1590 PciIo,
1591 PciIoOperation,
1592 DataBuffer,
1593 &ByteCount,
1594 &BufferMapAddress,
1595 &BufferMap
1596 );
1597 if (EFI_ERROR (Status) || (ByteCount != DataLength)) {
1598 PciIo->Unmap (PciIo, PrdTableMap);
1599 PciIo->FreeBuffer (PciIo, PageCount, PrdBaseAddr);
1600 return EFI_OUT_OF_RESOURCES;
1601 }
1602
1603 //
1604 // According to Ata spec, it requires the buffer address and size to be even.
1605 //
1606 ASSERT ((BufferMapAddress & 0x1) == 0);
1607 ASSERT ((ByteCount & 0x1) == 0);
1608
1609 //
1610 // Fill the PRD table with appropriate bus master address of data buffer and data length.
1611 //
1612 ByteRemaining = ByteCount;
1613 TempPrdBaseAddr = PrdBaseAddr;
1614 while (ByteRemaining != 0) {
1615 if (ByteRemaining <= 0x10000) {
1616 TempPrdBaseAddr->RegionBaseAddr = (UINT32) ((UINTN) BufferMapAddress);
1617 TempPrdBaseAddr->ByteCount = (UINT16) ByteRemaining;
1618 TempPrdBaseAddr->EndOfTable = 0x8000;
1619 break;
1620 }
1621
1622 TempPrdBaseAddr->RegionBaseAddr = (UINT32) ((UINTN) BufferMapAddress);
1623 TempPrdBaseAddr->ByteCount = (UINT16) 0x0;
1624
1625 ByteRemaining -= 0x10000;
1626 BufferMapAddress += 0x10000;
1627 TempPrdBaseAddr++;
1628 }
1629
1630 //
1631 // Start to enable the DMA operation
1632 //
1633 DeviceHead = AtaCommandBlock->AtaDeviceHead;
1634
1635 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)(0xe0 | DeviceHead));
1636
1637 //
1638 // Enable interrupt to support UDMA
1639 //
1640 DeviceControl = 0;
1641 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
1642
1643 //
1644 // Read BMIS register and clear ERROR and INTR bit
1645 //
1646 RegisterValue = IdeReadPortB(PciIo, IoPortForBmis);
1647 RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);
1648 IdeWritePortB (PciIo, IoPortForBmis, RegisterValue);
1649
1650 //
1651 // Set the base address to BMID register
1652 //
1653 IdeWritePortDW (PciIo, IoPortForBmid, (UINT32)PrdTableMapAddr);
1654
1655 //
1656 // Set BMIC register to identify the operation direction
1657 //
1658 RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);
1659 if (Read) {
1660 RegisterValue |= BMIC_NREAD;
1661 } else {
1662 RegisterValue &= ~((UINT8) BMIC_NREAD);
1663 }
1664 IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);
1665
1666 //
1667 // Issue ATA command
1668 //
1669 Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);
1670
1671 if (EFI_ERROR (Status)) {
1672 Status = EFI_DEVICE_ERROR;
1673 goto Exit;
1674 }
1675
1676 Status = CheckStatusRegister (PciIo, IdeRegisters);
1677 if (EFI_ERROR (Status)) {
1678 Status = EFI_DEVICE_ERROR;
1679 goto Exit;
1680 }
1681 //
1682 // Set START bit of BMIC register
1683 //
1684 RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);
1685 RegisterValue |= BMIC_START;
1686 IdeWritePortB(PciIo, IoPortForBmic, RegisterValue);
1687
1688 if (Task != NULL) {
1689 //
1690 // Max transfer number of sectors for one command is 65536(32Mbyte),
1691 // it will cost 1 second to transfer these data in UDMA mode 2(33.3MBps).
1692 // So set the variable Count to 2000, for about 2 second Timeout time.
1693 //
1694 Task->RetryTimes = 2000;
1695 Task->Map = BufferMap;
1696 Task->TableMap = PrdTableMap;
1697 Task->MapBaseAddress = PrdBaseAddr;
1698 Task->PageCount = PageCount;
1699 Task->IsStart = TRUE;
1700 }
1701 }
1702
1703 //
1704 // Check the INTERRUPT and ERROR bit of BMIS
1705 // Max transfer number of sectors for one command is 65536(32Mbyte),
1706 // it will cost 1 second to transfer these data in UDMA mode 2(33.3MBps).
1707 // So set the variable Count to 2000, for about 2 second Timeout time.
1708 //
1709 if (Task != NULL) {
1710 Status = AtaUdmStatusCheck (PciIo, Task, IdeRegisters);
1711 } else {
1712 Status = AtaUdmStatusWait (PciIo, IdeRegisters);
1713 }
1714
1715 //
1716 // For blocking mode, clear registers and free buffers.
1717 // For non blocking mode, when the related registers have been set or time
1718 // out, or a error has been happened, it needs to clear the register and free
1719 // buffer.
1720 //
1721 if ((Task == NULL) || Status != EFI_NOT_READY) {
1722 //
1723 // Read BMIS register and clear ERROR and INTR bit
1724 //
1725 RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);
1726 RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);
1727 IdeWritePortB (PciIo, IoPortForBmis, RegisterValue);
1728
1729 //
1730 // Read Status Register of IDE device to clear interrupt
1731 //
1732 RegisterValue = IdeReadPortB(PciIo, IdeRegisters->CmdOrStatus);
1733
1734 //
1735 // Clear START bit of BMIC register
1736 //
1737 RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);
1738 RegisterValue &= ~((UINT8) BMIC_START);
1739 IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);
1740
1741 //
1742 // Disable interrupt of Select device
1743 //
1744 DeviceControl = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
1745 DeviceControl |= ATA_CTLREG_IEN_L;
1746 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
1747 //
1748 // Stall for 10 milliseconds.
1749 //
1750 MicroSecondDelay (10000);
1751
1752 }
1753
1754 Exit:
1755 //
1756 // Free all allocated resource
1757 //
1758 if ((Task == NULL) || Status != EFI_NOT_READY) {
1759 if (Task != NULL) {
1760 PciIo->Unmap (PciIo, Task->TableMap);
1761 PciIo->FreeBuffer (PciIo, Task->PageCount, Task->MapBaseAddress);
1762 PciIo->Unmap (PciIo, Task->Map);
1763 } else {
1764 PciIo->Unmap (PciIo, PrdTableMap);
1765 PciIo->FreeBuffer (PciIo, PageCount, PrdBaseAddr);
1766 PciIo->Unmap (PciIo, BufferMap);
1767 }
1768
1769 //
1770 // Dump All Ide registers to ATA_STATUS_BLOCK
1771 //
1772 DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);
1773 }
1774
1775 return Status;
1776 }
1777
1778 /**
1779 This function reads the pending data in the device.
1780
1781 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
1782 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1783
1784 @retval EFI_SUCCESS Successfully read.
1785 @retval EFI_NOT_READY The BSY is set avoiding reading.
1786
1787 **/
1788 EFI_STATUS
1789 EFIAPI
1790 AtaPacketReadPendingData (
1791 IN EFI_PCI_IO_PROTOCOL *PciIo,
1792 IN EFI_IDE_REGISTERS *IdeRegisters
1793 )
1794 {
1795 UINT8 AltRegister;
1796 UINT16 TempWordBuffer;
1797
1798 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
1799 if ((AltRegister & ATA_STSREG_BSY) == ATA_STSREG_BSY) {
1800 return EFI_NOT_READY;
1801 }
1802
1803 if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
1804 TempWordBuffer = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
1805 while ((TempWordBuffer & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
1806 IdeReadPortWMultiple (
1807 PciIo,
1808 IdeRegisters->Data,
1809 1,
1810 &TempWordBuffer
1811 );
1812 TempWordBuffer = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
1813 }
1814 }
1815 return EFI_SUCCESS;
1816 }
1817
1818 /**
1819 This function is called by AtaPacketCommandExecute().
1820 It is used to transfer data between host and device. The data direction is specified
1821 by the fourth parameter.
1822
1823 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
1824 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1825 @param Buffer Buffer contained data transferred between host and device.
1826 @param ByteCount Data size in byte unit of the buffer.
1827 @param Read Flag used to determine the data transfer direction.
1828 Read equals 1, means data transferred from device to host;
1829 Read equals 0, means data transferred from host to device.
1830 @param Timeout Timeout value for wait DRQ ready before each data stream's transfer
1831 , uses 100ns as a unit.
1832
1833 @retval EFI_SUCCESS data is transferred successfully.
1834 @retval EFI_DEVICE_ERROR the device failed to transfer data.
1835 **/
1836 EFI_STATUS
1837 EFIAPI
1838 AtaPacketReadWrite (
1839 IN EFI_PCI_IO_PROTOCOL *PciIo,
1840 IN EFI_IDE_REGISTERS *IdeRegisters,
1841 IN OUT VOID *Buffer,
1842 IN UINT64 ByteCount,
1843 IN BOOLEAN Read,
1844 IN UINT64 Timeout
1845 )
1846 {
1847 UINT32 RequiredWordCount;
1848 UINT32 ActualWordCount;
1849 UINT32 WordCount;
1850 EFI_STATUS Status;
1851 UINT16 *PtrBuffer;
1852
1853 //
1854 // No data transfer is premitted.
1855 //
1856 if (ByteCount == 0) {
1857 return EFI_SUCCESS;
1858 }
1859
1860 PtrBuffer = Buffer;
1861 RequiredWordCount = (UINT32)RShiftU64(ByteCount, 1);
1862 //
1863 // ActuralWordCount means the word count of data really transferred.
1864 //
1865 ActualWordCount = 0;
1866
1867 while (ActualWordCount < RequiredWordCount) {
1868 //
1869 // before each data transfer stream, the host should poll DRQ bit ready,
1870 // to see whether indicates device is ready to transfer data.
1871 //
1872 Status = DRQReady2 (PciIo, IdeRegisters, Timeout);
1873 if (EFI_ERROR (Status)) {
1874 return CheckStatusRegister (PciIo, IdeRegisters);
1875 }
1876
1877 //
1878 // get current data transfer size from Cylinder Registers.
1879 //
1880 WordCount = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb) << 8;
1881 WordCount = WordCount | IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
1882 WordCount = WordCount & 0xffff;
1883 WordCount /= 2;
1884
1885 WordCount = MIN (WordCount, (RequiredWordCount - ActualWordCount));
1886
1887 if (Read) {
1888 IdeReadPortWMultiple (
1889 PciIo,
1890 IdeRegisters->Data,
1891 WordCount,
1892 PtrBuffer
1893 );
1894 } else {
1895 IdeWritePortWMultiple (
1896 PciIo,
1897 IdeRegisters->Data,
1898 WordCount,
1899 PtrBuffer
1900 );
1901 }
1902
1903 //
1904 // read status register to check whether error happens.
1905 //
1906 Status = CheckStatusRegister (PciIo, IdeRegisters);
1907 if (EFI_ERROR (Status)) {
1908 return EFI_DEVICE_ERROR;
1909 }
1910
1911 PtrBuffer += WordCount;
1912 ActualWordCount += WordCount;
1913 }
1914
1915 if (Read) {
1916 //
1917 // In the case where the drive wants to send more data than we need to read,
1918 // the DRQ bit will be set and cause delays from DRQClear2().
1919 // We need to read data from the drive until it clears DRQ so we can move on.
1920 //
1921 AtaPacketReadPendingData (PciIo, IdeRegisters);
1922 }
1923
1924 //
1925 // read status register to check whether error happens.
1926 //
1927 Status = CheckStatusRegister (PciIo, IdeRegisters);
1928 if (EFI_ERROR (Status)) {
1929 return EFI_DEVICE_ERROR;
1930 }
1931
1932 //
1933 // After data transfer is completed, normally, DRQ bit should clear.
1934 //
1935 Status = DRQClear (PciIo, IdeRegisters, Timeout);
1936 if (EFI_ERROR (Status)) {
1937 return EFI_DEVICE_ERROR;
1938 }
1939
1940 return Status;
1941 }
1942
1943 /**
1944 Sumbit ATAPI request sense command.
1945
1946 @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance
1947 @param[in] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to
1948 store the IDE i/o port registers' base addresses
1949 @param[in] Channel The channel number of device.
1950 @param[in] Device The device number of device.
1951 @param[in] SenseData A pointer to store sense data.
1952 @param[in] SenseDataLength The sense data length.
1953 @param[in] Timeout The timeout value to execute this cmd, uses 100ns as a unit.
1954
1955 @retval EFI_SUCCESS Send out the ATAPI packet command successfully.
1956 @retval EFI_DEVICE_ERROR The device failed to send data.
1957
1958 **/
1959 EFI_STATUS
1960 EFIAPI
1961 AtaPacketRequestSense (
1962 IN EFI_PCI_IO_PROTOCOL *PciIo,
1963 IN EFI_IDE_REGISTERS *IdeRegisters,
1964 IN UINT8 Channel,
1965 IN UINT8 Device,
1966 IN VOID *SenseData,
1967 IN UINT8 SenseDataLength,
1968 IN UINT64 Timeout
1969 )
1970 {
1971 EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET Packet;
1972 UINT8 Cdb[12];
1973 EFI_STATUS Status;
1974
1975 ZeroMem (&Packet, sizeof (EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET));
1976 ZeroMem (Cdb, 12);
1977
1978 Cdb[0] = ATA_CMD_REQUEST_SENSE;
1979 Cdb[4] = SenseDataLength;
1980
1981 Packet.Timeout = Timeout;
1982 Packet.Cdb = Cdb;
1983 Packet.CdbLength = 12;
1984 Packet.DataDirection = EFI_EXT_SCSI_DATA_DIRECTION_READ;
1985 Packet.InDataBuffer = SenseData;
1986 Packet.InTransferLength = SenseDataLength;
1987
1988 Status = AtaPacketCommandExecute (PciIo, IdeRegisters, Channel, Device, &Packet);
1989
1990 return Status;
1991 }
1992
1993 /**
1994 This function is used to send out ATAPI commands conforms to the Packet Command
1995 with PIO Data In Protocol.
1996
1997 @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance
1998 @param[in] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to
1999 store the IDE i/o port registers' base addresses
2000 @param[in] Channel The channel number of device.
2001 @param[in] Device The device number of device.
2002 @param[in] Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET data structure.
2003
2004 @retval EFI_SUCCESS send out the ATAPI packet command successfully
2005 and device sends data successfully.
2006 @retval EFI_DEVICE_ERROR the device failed to send data.
2007
2008 **/
2009 EFI_STATUS
2010 EFIAPI
2011 AtaPacketCommandExecute (
2012 IN EFI_PCI_IO_PROTOCOL *PciIo,
2013 IN EFI_IDE_REGISTERS *IdeRegisters,
2014 IN UINT8 Channel,
2015 IN UINT8 Device,
2016 IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
2017 )
2018 {
2019 EFI_STATUS PacketCommandStatus;
2020 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2021 EFI_STATUS Status;
2022 UINT8 Count;
2023 UINT8 PacketCommand[12];
2024
2025 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2026
2027 //
2028 // Fill ATAPI Command Packet according to CDB.
2029 // For Atapi cmd, its length should be less than or equal to 12 bytes.
2030 //
2031 if (Packet->CdbLength > 12) {
2032 return EFI_INVALID_PARAMETER;
2033 }
2034
2035 ZeroMem (PacketCommand, 12);
2036 CopyMem (PacketCommand, Packet->Cdb, Packet->CdbLength);
2037
2038 //
2039 // No OVL; No DMA
2040 //
2041 AtaCommandBlock.AtaFeatures = 0x00;
2042 //
2043 // set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device
2044 // determine how many data should be transferred.
2045 //
2046 AtaCommandBlock.AtaCylinderLow = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);
2047 AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);
2048 AtaCommandBlock.AtaDeviceHead = (UINT8) (Device << 0x4);
2049 AtaCommandBlock.AtaCommand = ATA_CMD_PACKET;
2050
2051 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)(0xe0 | (Device << 0x4)));
2052 //
2053 // Disable interrupt
2054 //
2055 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, ATA_DEFAULT_CTL);
2056
2057 //
2058 // Issue ATA PACKET command firstly
2059 //
2060 Status = AtaIssueCommand (PciIo, IdeRegisters, &AtaCommandBlock, Packet->Timeout);
2061 if (EFI_ERROR (Status)) {
2062 return Status;
2063 }
2064
2065 Status = DRQReady (PciIo, IdeRegisters, Packet->Timeout);
2066 if (EFI_ERROR (Status)) {
2067 return Status;
2068 }
2069
2070 //
2071 // Send out ATAPI command packet
2072 //
2073 for (Count = 0; Count < 6; Count++) {
2074 IdeWritePortW (PciIo, IdeRegisters->Data, *((UINT16*)PacketCommand + Count));
2075 //
2076 // Stall for 10 microseconds.
2077 //
2078 MicroSecondDelay (10);
2079 }
2080
2081 //
2082 // Read/Write the data of ATAPI Command
2083 //
2084 if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {
2085 PacketCommandStatus = AtaPacketReadWrite (
2086 PciIo,
2087 IdeRegisters,
2088 Packet->InDataBuffer,
2089 Packet->InTransferLength,
2090 TRUE,
2091 Packet->Timeout
2092 );
2093 } else {
2094 PacketCommandStatus = AtaPacketReadWrite (
2095 PciIo,
2096 IdeRegisters,
2097 Packet->OutDataBuffer,
2098 Packet->OutTransferLength,
2099 FALSE,
2100 Packet->Timeout
2101 );
2102 }
2103
2104 if (!EFI_ERROR (PacketCommandStatus)) {
2105 return PacketCommandStatus;
2106 }
2107
2108 //
2109 // Return SenseData if PacketCommandStatus matches
2110 // the following return codes.
2111 //
2112 if ((PacketCommandStatus == EFI_BAD_BUFFER_SIZE) ||
2113 (PacketCommandStatus == EFI_DEVICE_ERROR) ||
2114 (PacketCommandStatus == EFI_TIMEOUT)) {
2115
2116 //
2117 // avoid submit request sense command continuously.
2118 //
2119 if ((Packet->SenseData == NULL) || (((UINT8 *)Packet->Cdb)[0] == ATA_CMD_REQUEST_SENSE)) {
2120 return PacketCommandStatus;
2121 }
2122
2123 AtaPacketRequestSense (
2124 PciIo,
2125 IdeRegisters,
2126 Channel,
2127 Device,
2128 Packet->SenseData,
2129 Packet->SenseDataLength,
2130 Packet->Timeout
2131 );
2132 }
2133
2134 return PacketCommandStatus;
2135 }
2136
2137
2138 /**
2139 Set the calculated Best transfer mode to a detected device.
2140
2141 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2142 @param Channel The channel number of device.
2143 @param Device The device number of device.
2144 @param TransferMode A pointer to EFI_ATA_TRANSFER_MODE data structure.
2145 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2146
2147 @retval EFI_SUCCESS Set transfer mode successfully.
2148 @retval EFI_DEVICE_ERROR Set transfer mode failed.
2149 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
2150
2151 **/
2152 EFI_STATUS
2153 EFIAPI
2154 SetDeviceTransferMode (
2155 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2156 IN UINT8 Channel,
2157 IN UINT8 Device,
2158 IN EFI_ATA_TRANSFER_MODE *TransferMode,
2159 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2160 )
2161 {
2162 EFI_STATUS Status;
2163 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2164
2165 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2166
2167 AtaCommandBlock.AtaCommand = ATA_CMD_SET_FEATURES;
2168 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
2169 AtaCommandBlock.AtaFeatures = 0x03;
2170 AtaCommandBlock.AtaSectorCount = *((UINT8 *)TransferMode);
2171
2172 //
2173 // Send SET FEATURE command (sub command 0x03) to set pio mode.
2174 //
2175 Status = AtaNonDataCommandIn (
2176 Instance->PciIo,
2177 &Instance->IdeRegisters[Channel],
2178 &AtaCommandBlock,
2179 AtaStatusBlock,
2180 ATA_ATAPI_TIMEOUT,
2181 NULL
2182 );
2183
2184 return Status;
2185 }
2186
2187 /**
2188 Set drive parameters for devices not support PACKETS command.
2189
2190 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2191 @param Channel The channel number of device.
2192 @param Device The device number of device.
2193 @param DriveParameters A pointer to EFI_ATA_DRIVE_PARMS data structure.
2194 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2195
2196 @retval EFI_SUCCESS Set drive parameter successfully.
2197 @retval EFI_DEVICE_ERROR Set drive parameter failed.
2198 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
2199
2200 **/
2201 EFI_STATUS
2202 EFIAPI
2203 SetDriveParameters (
2204 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2205 IN UINT8 Channel,
2206 IN UINT8 Device,
2207 IN EFI_ATA_DRIVE_PARMS *DriveParameters,
2208 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2209 )
2210 {
2211 EFI_STATUS Status;
2212 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2213
2214 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2215
2216 AtaCommandBlock.AtaCommand = ATA_CMD_INIT_DRIVE_PARAM;
2217 AtaCommandBlock.AtaSectorCount = DriveParameters->Sector;
2218 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) + DriveParameters->Heads);
2219
2220 //
2221 // Send Init drive parameters
2222 //
2223 Status = AtaNonDataCommandIn (
2224 Instance->PciIo,
2225 &Instance->IdeRegisters[Channel],
2226 &AtaCommandBlock,
2227 AtaStatusBlock,
2228 ATA_ATAPI_TIMEOUT,
2229 NULL
2230 );
2231
2232 //
2233 // Send Set Multiple parameters
2234 //
2235 AtaCommandBlock.AtaCommand = ATA_CMD_SET_MULTIPLE_MODE;
2236 AtaCommandBlock.AtaSectorCount = DriveParameters->MultipleSector;
2237 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
2238
2239 Status = AtaNonDataCommandIn (
2240 Instance->PciIo,
2241 &Instance->IdeRegisters[Channel],
2242 &AtaCommandBlock,
2243 AtaStatusBlock,
2244 ATA_ATAPI_TIMEOUT,
2245 NULL
2246 );
2247
2248 return Status;
2249 }
2250
2251 /**
2252 Send SMART Return Status command to check if the execution of SMART cmd is successful or not.
2253
2254 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2255 @param Channel The channel number of device.
2256 @param Device The device number of device.
2257 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2258
2259 @retval EFI_SUCCESS Successfully get the return status of S.M.A.R.T command execution.
2260 @retval Others Fail to get return status data.
2261
2262 **/
2263 EFI_STATUS
2264 EFIAPI
2265 IdeAtaSmartReturnStatusCheck (
2266 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2267 IN UINT8 Channel,
2268 IN UINT8 Device,
2269 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2270 )
2271 {
2272 EFI_STATUS Status;
2273 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2274 UINT8 LBAMid;
2275 UINT8 LBAHigh;
2276
2277 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2278
2279 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
2280 AtaCommandBlock.AtaFeatures = ATA_SMART_RETURN_STATUS;
2281 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
2282 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
2283 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);
2284
2285 //
2286 // Send S.M.A.R.T Read Return Status command to device
2287 //
2288 Status = AtaNonDataCommandIn (
2289 Instance->PciIo,
2290 &Instance->IdeRegisters[Channel],
2291 &AtaCommandBlock,
2292 AtaStatusBlock,
2293 ATA_ATAPI_TIMEOUT,
2294 NULL
2295 );
2296
2297 if (EFI_ERROR (Status)) {
2298 return EFI_DEVICE_ERROR;
2299 }
2300
2301 LBAMid = IdeReadPortB (Instance->PciIo, Instance->IdeRegisters[Channel].CylinderLsb);
2302 LBAHigh = IdeReadPortB (Instance->PciIo, Instance->IdeRegisters[Channel].CylinderMsb);
2303
2304 if ((LBAMid == 0x4f) && (LBAHigh == 0xc2)) {
2305 //
2306 // The threshold exceeded condition is not detected by the device
2307 //
2308 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));
2309
2310 } else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {
2311 //
2312 // The threshold exceeded condition is detected by the device
2313 //
2314 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));
2315 }
2316
2317 return EFI_SUCCESS;
2318 }
2319
2320 /**
2321 Enable SMART command of the disk if supported.
2322
2323 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2324 @param Channel The channel number of device.
2325 @param Device The device number of device.
2326 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
2327 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2328
2329 **/
2330 VOID
2331 EFIAPI
2332 IdeAtaSmartSupport (
2333 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2334 IN UINT8 Channel,
2335 IN UINT8 Device,
2336 IN EFI_IDENTIFY_DATA *IdentifyData,
2337 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2338 )
2339 {
2340 EFI_STATUS Status;
2341 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2342
2343 //
2344 // Detect if the device supports S.M.A.R.T.
2345 //
2346 if ((IdentifyData->AtaData.command_set_supported_82 & 0x0001) != 0x0001) {
2347 //
2348 // S.M.A.R.T is not supported by the device
2349 //
2350 DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at [%a] channel [%a] device!\n",
2351 (Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));
2352 } else {
2353 //
2354 // Check if the feature is enabled. If not, then enable S.M.A.R.T.
2355 //
2356 if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {
2357
2358 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2359
2360 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
2361 AtaCommandBlock.AtaFeatures = ATA_SMART_ENABLE_OPERATION;
2362 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
2363 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
2364 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);
2365
2366 //
2367 // Send S.M.A.R.T Enable command to device
2368 //
2369 Status = AtaNonDataCommandIn (
2370 Instance->PciIo,
2371 &Instance->IdeRegisters[Channel],
2372 &AtaCommandBlock,
2373 AtaStatusBlock,
2374 ATA_ATAPI_TIMEOUT,
2375 NULL
2376 );
2377
2378 if (!EFI_ERROR (Status)) {
2379 //
2380 // Send S.M.A.R.T AutoSave command to device
2381 //
2382 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2383
2384 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
2385 AtaCommandBlock.AtaFeatures = 0xD2;
2386 AtaCommandBlock.AtaSectorCount = 0xF1;
2387 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
2388 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
2389 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);
2390
2391 Status = AtaNonDataCommandIn (
2392 Instance->PciIo,
2393 &Instance->IdeRegisters[Channel],
2394 &AtaCommandBlock,
2395 AtaStatusBlock,
2396 ATA_ATAPI_TIMEOUT,
2397 NULL
2398 );
2399 if (!EFI_ERROR (Status)) {
2400 Status = IdeAtaSmartReturnStatusCheck (
2401 Instance,
2402 Channel,
2403 Device,
2404 AtaStatusBlock
2405 );
2406 }
2407 }
2408 }
2409
2410 DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at [%a] channel [%a] device!\n",
2411 (Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));
2412
2413 }
2414
2415 return ;
2416 }
2417
2418
2419 /**
2420 Sends out an ATA Identify Command to the specified device.
2421
2422 This function is called by DiscoverIdeDevice() during its device
2423 identification. It sends out the ATA Identify Command to the
2424 specified device. Only ATA device responses to this command. If
2425 the command succeeds, it returns the Identify data structure which
2426 contains information about the device. This function extracts the
2427 information it needs to fill the IDE_BLK_IO_DEV data structure,
2428 including device type, media block size, media capacity, and etc.
2429
2430 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2431 @param Channel The channel number of device.
2432 @param Device The device number of device.
2433 @param Buffer A pointer to data buffer which is used to contain IDENTIFY data.
2434 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2435
2436 @retval EFI_SUCCESS Identify ATA device successfully.
2437 @retval EFI_DEVICE_ERROR ATA Identify Device Command failed or device is not ATA device.
2438 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
2439
2440 **/
2441 EFI_STATUS
2442 EFIAPI
2443 AtaIdentify (
2444 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2445 IN UINT8 Channel,
2446 IN UINT8 Device,
2447 IN OUT EFI_IDENTIFY_DATA *Buffer,
2448 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2449 )
2450 {
2451 EFI_STATUS Status;
2452 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2453
2454 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2455
2456 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DRIVE;
2457 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
2458
2459 Status = AtaPioDataInOut (
2460 Instance->PciIo,
2461 &Instance->IdeRegisters[Channel],
2462 Buffer,
2463 sizeof (EFI_IDENTIFY_DATA),
2464 TRUE,
2465 &AtaCommandBlock,
2466 AtaStatusBlock,
2467 ATA_ATAPI_TIMEOUT,
2468 NULL
2469 );
2470
2471 return Status;
2472 }
2473
2474 /**
2475 This function is called by DiscoverIdeDevice() during its device
2476 identification.
2477 Its main purpose is to get enough information for the device media
2478 to fill in the Media data structure of the Block I/O Protocol interface.
2479
2480 There are 5 steps to reach such objective:
2481 1. Sends out the ATAPI Identify Command to the specified device.
2482 Only ATAPI device responses to this command. If the command succeeds,
2483 it returns the Identify data structure which filled with information
2484 about the device. Since the ATAPI device contains removable media,
2485 the only meaningful information is the device module name.
2486 2. Sends out ATAPI Inquiry Packet Command to the specified device.
2487 This command will return inquiry data of the device, which contains
2488 the device type information.
2489 3. Allocate sense data space for future use. We don't detect the media
2490 presence here to improvement boot performance, especially when CD
2491 media is present. The media detection will be performed just before
2492 each BLK_IO read/write
2493
2494 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2495 @param Channel The channel number of device.
2496 @param Device The device number of device.
2497 @param Buffer A pointer to data buffer which is used to contain IDENTIFY data.
2498 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2499
2500 @retval EFI_SUCCESS Identify ATAPI device successfully.
2501 @retval EFI_DEVICE_ERROR ATA Identify Packet Device Command failed or device type
2502 is not supported by this IDE driver.
2503 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
2504
2505 **/
2506 EFI_STATUS
2507 EFIAPI
2508 AtaIdentifyPacket (
2509 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2510 IN UINT8 Channel,
2511 IN UINT8 Device,
2512 IN OUT EFI_IDENTIFY_DATA *Buffer,
2513 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2514 )
2515 {
2516 EFI_STATUS Status;
2517 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2518
2519 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2520
2521 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DEVICE;
2522 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
2523
2524 //
2525 // Send ATAPI Identify Command to get IDENTIFY data.
2526 //
2527 Status = AtaPioDataInOut (
2528 Instance->PciIo,
2529 &Instance->IdeRegisters[Channel],
2530 (VOID *) Buffer,
2531 sizeof (EFI_IDENTIFY_DATA),
2532 TRUE,
2533 &AtaCommandBlock,
2534 AtaStatusBlock,
2535 ATA_ATAPI_TIMEOUT,
2536 NULL
2537 );
2538
2539 return Status;
2540 }
2541
2542
2543 /**
2544 This function is used for detect whether the IDE device exists in the
2545 specified Channel as the specified Device Number.
2546
2547 There is two IDE channels: one is Primary Channel, the other is
2548 Secondary Channel.(Channel is the logical name for the physical "Cable".)
2549 Different channel has different register group.
2550
2551 On each IDE channel, at most two IDE devices attach,
2552 one is called Device 0 (Master device), the other is called Device 1
2553 (Slave device). The devices on the same channel co-use the same register
2554 group, so before sending out a command for a specified device via command
2555 register, it is a must to select the current device to accept the command
2556 by set the device number in the Head/Device Register.
2557
2558 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2559 @param IdeChannel The channel number of device.
2560
2561 @retval EFI_SUCCESS successfully detects device.
2562 @retval other any failure during detection process will return this value.
2563
2564 **/
2565 EFI_STATUS
2566 EFIAPI
2567 DetectAndConfigIdeDevice (
2568 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2569 IN UINT8 IdeChannel
2570 )
2571 {
2572 EFI_STATUS Status;
2573 UINT8 SectorCountReg;
2574 UINT8 LBALowReg;
2575 UINT8 LBAMidReg;
2576 UINT8 LBAHighReg;
2577 EFI_ATA_DEVICE_TYPE DeviceType;
2578 UINT8 IdeDevice;
2579 EFI_IDE_REGISTERS *IdeRegisters;
2580 EFI_IDENTIFY_DATA Buffer;
2581
2582 EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
2583 EFI_PCI_IO_PROTOCOL *PciIo;
2584
2585 EFI_ATA_COLLECTIVE_MODE *SupportedModes;
2586 EFI_ATA_TRANSFER_MODE TransferMode;
2587 EFI_ATA_DRIVE_PARMS DriveParameters;
2588
2589 IdeRegisters = &Instance->IdeRegisters[IdeChannel];
2590 IdeInit = Instance->IdeControllerInit;
2591 PciIo = Instance->PciIo;
2592
2593 for (IdeDevice = 0; IdeDevice < EfiIdeMaxDevice; IdeDevice++) {
2594 //
2595 // Send ATA Device Execut Diagnostic command.
2596 // This command should work no matter DRDY is ready or not
2597 //
2598 IdeWritePortB (PciIo, IdeRegisters->CmdOrStatus, ATA_CMD_EXEC_DRIVE_DIAG);
2599
2600 Status = WaitForBSYClear (PciIo, IdeRegisters, 350000000);
2601 if (EFI_ERROR (Status)) {
2602 DEBUG((EFI_D_ERROR, "New detecting method: Send Execute Diagnostic Command: WaitForBSYClear: Status: %d\n", Status));
2603 continue;
2604 }
2605
2606 //
2607 // Select Master or Slave device to get the return signature for ATA DEVICE DIAGNOSTIC cmd.
2608 //
2609 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)((IdeDevice << 4) | 0xe0));
2610 //
2611 // Stall for 1 milliseconds.
2612 //
2613 MicroSecondDelay (1000);
2614
2615 SectorCountReg = IdeReadPortB (PciIo, IdeRegisters->SectorCount);
2616 LBALowReg = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);
2617 LBAMidReg = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
2618 LBAHighReg = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);
2619
2620 //
2621 // Refer to ATA/ATAPI 4 Spec, section 9.1
2622 //
2623 if ((SectorCountReg == 0x1) && (LBALowReg == 0x1) && (LBAMidReg == 0x0) && (LBAHighReg == 0x0)) {
2624 DeviceType = EfiIdeHarddisk;
2625 } else if ((LBAMidReg == 0x14) && (LBAHighReg == 0xeb)) {
2626 DeviceType = EfiIdeCdrom;
2627 } else {
2628 continue;
2629 }
2630
2631 //
2632 // Send IDENTIFY cmd to the device to test if it is really attached.
2633 //
2634 if (DeviceType == EfiIdeHarddisk) {
2635 Status = AtaIdentify (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
2636 //
2637 // if identifying ata device is failure, then try to send identify packet cmd.
2638 //
2639 if (EFI_ERROR (Status)) {
2640 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED));
2641
2642 DeviceType = EfiIdeCdrom;
2643 Status = AtaIdentifyPacket (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
2644 }
2645 } else {
2646 Status = AtaIdentifyPacket (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
2647 //
2648 // if identifying atapi device is failure, then try to send identify cmd.
2649 //
2650 if (EFI_ERROR (Status)) {
2651 DeviceType = EfiIdeHarddisk;
2652 Status = AtaIdentify (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
2653 }
2654 }
2655
2656 if (EFI_ERROR (Status)) {
2657 //
2658 // No device is found at this port
2659 //
2660 continue;
2661 }
2662
2663 DEBUG ((EFI_D_INFO, "[%a] channel [%a] [%a] device\n",
2664 (IdeChannel == 1) ? "secondary" : "primary ", (IdeDevice == 1) ? "slave " : "master",
2665 DeviceType == EfiIdeCdrom ? "cdrom " : "harddisk"));
2666 //
2667 // If the device is a hard disk, then try to enable S.M.A.R.T feature
2668 //
2669 if (DeviceType == EfiIdeHarddisk) {
2670 IdeAtaSmartSupport (
2671 Instance,
2672 IdeChannel,
2673 IdeDevice,
2674 &Buffer,
2675 NULL
2676 );
2677 }
2678
2679 //
2680 // Submit identify data to IDE controller init driver
2681 //
2682 IdeInit->SubmitData (IdeInit, IdeChannel, IdeDevice, &Buffer);
2683
2684 //
2685 // Now start to config ide device parameter and transfer mode.
2686 //
2687 Status = IdeInit->CalculateMode (
2688 IdeInit,
2689 IdeChannel,
2690 IdeDevice,
2691 &SupportedModes
2692 );
2693 if (EFI_ERROR (Status)) {
2694 DEBUG ((EFI_D_ERROR, "Calculate Mode Fail, Status = %r\n", Status));
2695 continue;
2696 }
2697
2698 //
2699 // Set best supported PIO mode on this IDE device
2700 //
2701 if (SupportedModes->PioMode.Mode <= EfiAtaPioMode2) {
2702 TransferMode.ModeCategory = EFI_ATA_MODE_DEFAULT_PIO;
2703 } else {
2704 TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;
2705 }
2706
2707 TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);
2708
2709 if (SupportedModes->ExtModeCount == 0){
2710 Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);
2711
2712 if (EFI_ERROR (Status)) {
2713 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
2714 continue;
2715 }
2716 }
2717
2718 //
2719 // Set supported DMA mode on this IDE device. Note that UDMA & MDMA cann't
2720 // be set together. Only one DMA mode can be set to a device. If setting
2721 // DMA mode operation fails, we can continue moving on because we only use
2722 // PIO mode at boot time. DMA modes are used by certain kind of OS booting
2723 //
2724 if (SupportedModes->UdmaMode.Valid) {
2725 TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;
2726 TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);
2727 Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);
2728
2729 if (EFI_ERROR (Status)) {
2730 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
2731 continue;
2732 }
2733 } else if (SupportedModes->MultiWordDmaMode.Valid) {
2734 TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;
2735 TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
2736 Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);
2737
2738 if (EFI_ERROR (Status)) {
2739 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
2740 continue;
2741 }
2742 }
2743
2744 //
2745 // Set Parameters for the device:
2746 // 1) Init
2747 // 2) Establish the block count for READ/WRITE MULTIPLE (EXT) command
2748 //
2749 if (DeviceType == EfiIdeHarddisk) {
2750 //
2751 // Init driver parameters
2752 //
2753 DriveParameters.Sector = (UINT8) ((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->sectors_per_track;
2754 DriveParameters.Heads = (UINT8) (((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->heads - 1);
2755 DriveParameters.MultipleSector = (UINT8) ((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->multi_sector_cmd_max_sct_cnt;
2756
2757 Status = SetDriveParameters (Instance, IdeChannel, IdeDevice, &DriveParameters, NULL);
2758 }
2759
2760 //
2761 // Set IDE controller Timing Blocks in the PCI Configuration Space
2762 //
2763 IdeInit->SetTiming (IdeInit, IdeChannel, IdeDevice, SupportedModes);
2764
2765 //
2766 // IDE controller and IDE device timing is configured successfully.
2767 // Now insert the device into device list.
2768 //
2769 Status = CreateNewDeviceInfo (Instance, IdeChannel, IdeDevice, DeviceType, &Buffer);
2770 if (EFI_ERROR (Status)) {
2771 continue;
2772 }
2773
2774 if (DeviceType == EfiIdeHarddisk) {
2775 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));
2776 }
2777 }
2778 return EFI_SUCCESS;
2779 }
2780
2781
2782 /**
2783 Initialize ATA host controller at IDE mode.
2784
2785 The function is designed to initialize ATA host controller.
2786
2787 @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
2788
2789 **/
2790 EFI_STATUS
2791 EFIAPI
2792 IdeModeInitialization (
2793 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance
2794 )
2795 {
2796 EFI_STATUS Status;
2797 EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
2798 EFI_PCI_IO_PROTOCOL *PciIo;
2799 UINT8 Channel;
2800 UINT8 IdeChannel;
2801 BOOLEAN ChannelEnabled;
2802 UINT8 MaxDevices;
2803
2804 IdeInit = Instance->IdeControllerInit;
2805 PciIo = Instance->PciIo;
2806 Channel = IdeInit->ChannelCount;
2807
2808 //
2809 // Obtain IDE IO port registers' base addresses
2810 //
2811 Status = GetIdeRegisterIoAddr (PciIo, Instance->IdeRegisters);
2812 if (EFI_ERROR (Status)) {
2813 goto ErrorExit;
2814 }
2815
2816 for (IdeChannel = 0; IdeChannel < Channel; IdeChannel++) {
2817 IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, IdeChannel);
2818
2819 //
2820 // now obtain channel information fron IdeControllerInit protocol.
2821 //
2822 Status = IdeInit->GetChannelInfo (
2823 IdeInit,
2824 IdeChannel,
2825 &ChannelEnabled,
2826 &MaxDevices
2827 );
2828 if (EFI_ERROR (Status)) {
2829 DEBUG ((EFI_D_ERROR, "[GetChannel, Status=%x]", Status));
2830 continue;
2831 }
2832
2833 if (!ChannelEnabled) {
2834 continue;
2835 }
2836
2837 ASSERT (MaxDevices <= 2);
2838 //
2839 // Now inform the IDE Controller Init Module.
2840 //
2841 IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelReset, IdeChannel);
2842
2843 //
2844 // No reset channel function implemented.
2845 //
2846 IdeInit->NotifyPhase (IdeInit, EfiIdeAfterChannelReset, IdeChannel);
2847
2848 //
2849 // Now inform the IDE Controller Init Module.
2850 //
2851 IdeInit->NotifyPhase (IdeInit, EfiIdeBusBeforeDevicePresenceDetection, IdeChannel);
2852
2853 //
2854 // Detect all attached ATA devices and set the transfer mode for each device.
2855 //
2856 DetectAndConfigIdeDevice (Instance, IdeChannel);
2857 }
2858
2859 //
2860 // All configurations done! Notify IdeController to do post initialization
2861 // work such as saving IDE controller PCI settings for S3 resume
2862 //
2863 IdeInit->NotifyPhase (IdeInit, EfiIdeBusPhaseMaximum, 0);
2864
2865 ErrorExit:
2866 return Status;
2867 }
2868
EFI Development Kit II mirror for PVE