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MdeModulePkg AtaAtapiPassThru: Remove redundant functions
[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AtaAtapiPassThru / IdeMode.c
1 /** @file
2 Header file for AHCI mode of ATA host controller.
3
4 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "AtaAtapiPassThru.h"
16
17 /**
18 read a one-byte data from a IDE port.
19
20 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
21 @param Port The IDE Port number
22
23 @return the one-byte data read from IDE port
24 **/
25 UINT8
26 EFIAPI
27 IdeReadPortB (
28 IN EFI_PCI_IO_PROTOCOL *PciIo,
29 IN UINT16 Port
30 )
31 {
32 UINT8 Data;
33
34 ASSERT (PciIo != NULL);
35
36 Data = 0;
37 //
38 // perform 1-byte data read from register
39 //
40 PciIo->Io.Read (
41 PciIo,
42 EfiPciIoWidthUint8,
43 EFI_PCI_IO_PASS_THROUGH_BAR,
44 (UINT64) Port,
45 1,
46 &Data
47 );
48 return Data;
49 }
50
51 /**
52 write a 1-byte data to a specific IDE port.
53
54 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
55 @param Port The IDE port to be writen
56 @param Data The data to write to the port
57 **/
58 VOID
59 EFIAPI
60 IdeWritePortB (
61 IN EFI_PCI_IO_PROTOCOL *PciIo,
62 IN UINT16 Port,
63 IN UINT8 Data
64 )
65 {
66 ASSERT (PciIo != NULL);
67
68 //
69 // perform 1-byte data write to register
70 //
71 PciIo->Io.Write (
72 PciIo,
73 EfiPciIoWidthUint8,
74 EFI_PCI_IO_PASS_THROUGH_BAR,
75 (UINT64) Port,
76 1,
77 &Data
78 );
79 }
80
81 /**
82 write a 1-word data to a specific IDE port.
83
84 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
85 @param Port The IDE port to be writen
86 @param Data The data to write to the port
87 **/
88 VOID
89 EFIAPI
90 IdeWritePortW (
91 IN EFI_PCI_IO_PROTOCOL *PciIo,
92 IN UINT16 Port,
93 IN UINT16 Data
94 )
95 {
96 ASSERT (PciIo != NULL);
97
98 //
99 // perform 1-word data write to register
100 //
101 PciIo->Io.Write (
102 PciIo,
103 EfiPciIoWidthUint16,
104 EFI_PCI_IO_PASS_THROUGH_BAR,
105 (UINT64) Port,
106 1,
107 &Data
108 );
109 }
110
111 /**
112 write a 2-word data to a specific IDE port.
113
114 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
115 @param Port The IDE port to be writen
116 @param Data The data to write to the port
117 **/
118 VOID
119 EFIAPI
120 IdeWritePortDW (
121 IN EFI_PCI_IO_PROTOCOL *PciIo,
122 IN UINT16 Port,
123 IN UINT32 Data
124 )
125 {
126 ASSERT (PciIo != NULL);
127
128 //
129 // perform 2-word data write to register
130 //
131 PciIo->Io.Write (
132 PciIo,
133 EfiPciIoWidthUint32,
134 EFI_PCI_IO_PASS_THROUGH_BAR,
135 (UINT64) Port,
136 1,
137 &Data
138 );
139 }
140
141 /**
142 Write multiple words of data to the IDE data port.
143 Call the IO abstraction once to do the complete read,
144 not one word at a time
145
146 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
147 @param Port IO port to read
148 @param Count No. of UINT16's to read
149 @param Buffer Pointer to the data buffer for read
150
151 **/
152 VOID
153 EFIAPI
154 IdeWritePortWMultiple (
155 IN EFI_PCI_IO_PROTOCOL *PciIo,
156 IN UINT16 Port,
157 IN UINTN Count,
158 IN VOID *Buffer
159 )
160 {
161 ASSERT (PciIo != NULL);
162 ASSERT (Buffer != NULL);
163
164 //
165 // perform UINT16 data write to the FIFO
166 //
167 PciIo->Io.Write (
168 PciIo,
169 EfiPciIoWidthFifoUint16,
170 EFI_PCI_IO_PASS_THROUGH_BAR,
171 (UINT64) Port,
172 Count,
173 (UINT16 *) Buffer
174 );
175
176 }
177
178 /**
179 Reads multiple words of data from the IDE data port.
180 Call the IO abstraction once to do the complete read,
181 not one word at a time
182
183 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure
184 @param Port IO port to read
185 @param Count Number of UINT16's to read
186 @param Buffer Pointer to the data buffer for read
187
188 **/
189 VOID
190 EFIAPI
191 IdeReadPortWMultiple (
192 IN EFI_PCI_IO_PROTOCOL *PciIo,
193 IN UINT16 Port,
194 IN UINTN Count,
195 IN VOID *Buffer
196 )
197 {
198 ASSERT (PciIo != NULL);
199 ASSERT (Buffer != NULL);
200
201 //
202 // Perform UINT16 data read from FIFO
203 //
204 PciIo->Io.Read (
205 PciIo,
206 EfiPciIoWidthFifoUint16,
207 EFI_PCI_IO_PASS_THROUGH_BAR,
208 (UINT64) Port,
209 Count,
210 (UINT16 *) Buffer
211 );
212
213 }
214
215 /**
216 This function is used to analyze the Status Register and print out
217 some debug information and if there is ERR bit set in the Status
218 Register, the Error Register's value is also be parsed and print out.
219
220 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
221 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
222 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
223
224 **/
225 VOID
226 EFIAPI
227 DumpAllIdeRegisters (
228 IN EFI_PCI_IO_PROTOCOL *PciIo,
229 IN EFI_IDE_REGISTERS *IdeRegisters,
230 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
231 )
232 {
233 EFI_ATA_STATUS_BLOCK StatusBlock;
234
235 ASSERT (PciIo != NULL);
236 ASSERT (IdeRegisters != NULL);
237
238 ZeroMem (&StatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
239
240 StatusBlock.AtaStatus = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
241 StatusBlock.AtaError = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
242 StatusBlock.AtaSectorCount = IdeReadPortB (PciIo, IdeRegisters->SectorCount);
243 StatusBlock.AtaSectorCountExp = IdeReadPortB (PciIo, IdeRegisters->SectorCount);
244 StatusBlock.AtaSectorNumber = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);
245 StatusBlock.AtaSectorNumberExp = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);
246 StatusBlock.AtaCylinderLow = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
247 StatusBlock.AtaCylinderLowExp = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
248 StatusBlock.AtaCylinderHigh = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);
249 StatusBlock.AtaCylinderHighExp = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);
250 StatusBlock.AtaDeviceHead = IdeReadPortB (PciIo, IdeRegisters->Head);
251
252 if (AtaStatusBlock != NULL) {
253 //
254 // Dump the content of all ATA registers.
255 //
256 CopyMem (AtaStatusBlock, &StatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
257 }
258
259 DEBUG_CODE_BEGIN ();
260 if ((StatusBlock.AtaStatus & ATA_STSREG_DWF) != 0) {
261 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Write Fault\n", StatusBlock.AtaStatus));
262 }
263
264 if ((StatusBlock.AtaStatus & ATA_STSREG_CORR) != 0) {
265 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Corrected Data\n", StatusBlock.AtaStatus));
266 }
267
268 if ((StatusBlock.AtaStatus & ATA_STSREG_ERR) != 0) {
269 if ((StatusBlock.AtaError & ATA_ERRREG_BBK) != 0) {
270 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Bad Block Detected\n", StatusBlock.AtaError));
271 }
272
273 if ((StatusBlock.AtaError & ATA_ERRREG_UNC) != 0) {
274 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Uncorrectable Data\n", StatusBlock.AtaError));
275 }
276
277 if ((StatusBlock.AtaError & ATA_ERRREG_MC) != 0) {
278 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Media Change\n", StatusBlock.AtaError));
279 }
280
281 if ((StatusBlock.AtaError & ATA_ERRREG_ABRT) != 0) {
282 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Abort\n", StatusBlock.AtaError));
283 }
284
285 if ((StatusBlock.AtaError & ATA_ERRREG_TK0NF) != 0) {
286 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Track 0 Not Found\n", StatusBlock.AtaError));
287 }
288
289 if ((StatusBlock.AtaError & ATA_ERRREG_AMNF) != 0) {
290 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Address Mark Not Found\n", StatusBlock.AtaError));
291 }
292 }
293 DEBUG_CODE_END ();
294 }
295
296 /**
297 This function is used to analyze the Status Register at the condition that BSY is zero.
298 if there is ERR bit set in the Status Register, then return error.
299
300 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
301 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
302
303 @retval EFI_SUCCESS No err information in the Status Register.
304 @retval EFI_DEVICE_ERROR Any err information in the Status Register.
305
306 **/
307 EFI_STATUS
308 EFIAPI
309 CheckStatusRegister (
310 IN EFI_PCI_IO_PROTOCOL *PciIo,
311 IN EFI_IDE_REGISTERS *IdeRegisters
312 )
313 {
314 UINT8 StatusRegister;
315
316 ASSERT (PciIo != NULL);
317 ASSERT (IdeRegisters != NULL);
318
319 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
320
321 if ((StatusRegister & ATA_STSREG_BSY) == 0) {
322 if ((StatusRegister & (ATA_STSREG_ERR | ATA_STSREG_DWF | ATA_STSREG_CORR)) == 0) {
323 return EFI_SUCCESS;
324 } else {
325 return EFI_DEVICE_ERROR;
326 }
327 }
328 return EFI_SUCCESS;
329 }
330
331 /**
332 This function is used to poll for the DRQ bit clear in the Status
333 Register. DRQ is cleared when the device is finished transferring data.
334 So this function is called after data transfer is finished.
335
336 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
337 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
338 @param Timeout The time to complete the command, uses 100ns as a unit.
339
340 @retval EFI_SUCCESS DRQ bit clear within the time out.
341
342 @retval EFI_TIMEOUT DRQ bit not clear within the time out.
343
344 @note
345 Read Status Register will clear interrupt status.
346
347 **/
348 EFI_STATUS
349 EFIAPI
350 DRQClear (
351 IN EFI_PCI_IO_PROTOCOL *PciIo,
352 IN EFI_IDE_REGISTERS *IdeRegisters,
353 IN UINT64 Timeout
354 )
355 {
356 UINT64 Delay;
357 UINT8 StatusRegister;
358 BOOLEAN InfiniteWait;
359
360 ASSERT (PciIo != NULL);
361 ASSERT (IdeRegisters != NULL);
362
363 if (Timeout == 0) {
364 InfiniteWait = TRUE;
365 } else {
366 InfiniteWait = FALSE;
367 }
368
369 Delay = DivU64x32(Timeout, 1000) + 1;
370 do {
371 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
372
373 //
374 // Wait for BSY == 0, then judge if DRQ is clear
375 //
376 if ((StatusRegister & ATA_STSREG_BSY) == 0) {
377 if ((StatusRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
378 return EFI_DEVICE_ERROR;
379 } else {
380 return EFI_SUCCESS;
381 }
382 }
383
384 //
385 // Stall for 100 microseconds.
386 //
387 MicroSecondDelay (100);
388
389 Delay--;
390
391 } while (InfiniteWait || (Delay > 0));
392
393 return EFI_TIMEOUT;
394 }
395 /**
396 This function is used to poll for the DRQ bit clear in the Alternate
397 Status Register. DRQ is cleared when the device is finished
398 transferring data. So this function is called after data transfer
399 is finished.
400
401 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
402 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
403 @param Timeout The time to complete the command, uses 100ns as a unit.
404
405 @retval EFI_SUCCESS DRQ bit clear within the time out.
406
407 @retval EFI_TIMEOUT DRQ bit not clear within the time out.
408 @note Read Alternate Status Register will not clear interrupt status.
409
410 **/
411 EFI_STATUS
412 EFIAPI
413 DRQClear2 (
414 IN EFI_PCI_IO_PROTOCOL *PciIo,
415 IN EFI_IDE_REGISTERS *IdeRegisters,
416 IN UINT64 Timeout
417 )
418 {
419 UINT64 Delay;
420 UINT8 AltRegister;
421 BOOLEAN InfiniteWait;
422
423 ASSERT (PciIo != NULL);
424 ASSERT (IdeRegisters != NULL);
425
426 if (Timeout == 0) {
427 InfiniteWait = TRUE;
428 } else {
429 InfiniteWait = FALSE;
430 }
431
432 Delay = DivU64x32(Timeout, 1000) + 1;
433 do {
434 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
435
436 //
437 // Wait for BSY == 0, then judge if DRQ is clear
438 //
439 if ((AltRegister & ATA_STSREG_BSY) == 0) {
440 if ((AltRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
441 return EFI_DEVICE_ERROR;
442 } else {
443 return EFI_SUCCESS;
444 }
445 }
446
447 //
448 // Stall for 100 microseconds.
449 //
450 MicroSecondDelay (100);
451
452 Delay--;
453
454 } while (InfiniteWait || (Delay > 0));
455
456 return EFI_TIMEOUT;
457 }
458
459 /**
460 This function is used to poll for the DRQ bit set in the
461 Status Register.
462 DRQ is set when the device is ready to transfer data. So this function
463 is called after the command is sent to the device and before required
464 data is transferred.
465
466 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
467 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
468 @param Timeout The time to complete the command, uses 100ns as a unit.
469
470 @retval EFI_SUCCESS BSY bit cleared and DRQ bit set within the
471 timeout.
472
473 @retval EFI_TIMEOUT BSY bit not cleared within the timeout.
474
475 @retval EFI_ABORTED Polling abandoned due to command abort.
476
477 @retval EFI_DEVICE_ERROR Polling abandoned due to a non-abort error.
478
479 @retval EFI_NOT_READY BSY bit cleared within timeout, and device
480 reported "command complete" by clearing DRQ
481 bit.
482
483 @note Read Status Register will clear interrupt status.
484
485 **/
486 EFI_STATUS
487 EFIAPI
488 DRQReady (
489 IN EFI_PCI_IO_PROTOCOL *PciIo,
490 IN EFI_IDE_REGISTERS *IdeRegisters,
491 IN UINT64 Timeout
492 )
493 {
494 UINT64 Delay;
495 UINT8 StatusRegister;
496 UINT8 ErrorRegister;
497 BOOLEAN InfiniteWait;
498
499 ASSERT (PciIo != NULL);
500 ASSERT (IdeRegisters != NULL);
501
502 if (Timeout == 0) {
503 InfiniteWait = TRUE;
504 } else {
505 InfiniteWait = FALSE;
506 }
507
508 Delay = DivU64x32(Timeout, 1000) + 1;
509 do {
510 //
511 // Read Status Register will clear interrupt
512 //
513 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
514
515 //
516 // Wait for BSY == 0, then judge if DRQ is clear or ERR is set
517 //
518 if ((StatusRegister & ATA_STSREG_BSY) == 0) {
519 if ((StatusRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {
520 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
521
522 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
523 return EFI_ABORTED;
524 }
525 return EFI_DEVICE_ERROR;
526 }
527
528 if ((StatusRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
529 return EFI_SUCCESS;
530 } else {
531 return EFI_NOT_READY;
532 }
533 }
534
535 //
536 // Stall for 100 microseconds.
537 //
538 MicroSecondDelay (100);
539
540 Delay--;
541 } while (InfiniteWait || (Delay > 0));
542
543 return EFI_TIMEOUT;
544 }
545 /**
546 This function is used to poll for the DRQ bit set in the Alternate Status Register.
547 DRQ is set when the device is ready to transfer data. So this function is called after
548 the command is sent to the device and before required data is transferred.
549
550 @param PciIo A pointer to EFI_PCI_IO_PROTOCOL data structure.
551 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
552 @param Timeout The time to complete the command, uses 100ns as a unit.
553
554 @retval EFI_SUCCESS BSY bit cleared and DRQ bit set within the
555 timeout.
556
557 @retval EFI_TIMEOUT BSY bit not cleared within the timeout.
558
559 @retval EFI_ABORTED Polling abandoned due to command abort.
560
561 @retval EFI_DEVICE_ERROR Polling abandoned due to a non-abort error.
562
563 @retval EFI_NOT_READY BSY bit cleared within timeout, and device
564 reported "command complete" by clearing DRQ
565 bit.
566
567 @note Read Alternate Status Register will not clear interrupt status.
568
569 **/
570 EFI_STATUS
571 EFIAPI
572 DRQReady2 (
573 IN EFI_PCI_IO_PROTOCOL *PciIo,
574 IN EFI_IDE_REGISTERS *IdeRegisters,
575 IN UINT64 Timeout
576 )
577 {
578 UINT64 Delay;
579 UINT8 AltRegister;
580 UINT8 ErrorRegister;
581 BOOLEAN InfiniteWait;
582
583 ASSERT (PciIo != NULL);
584 ASSERT (IdeRegisters != NULL);
585
586 if (Timeout == 0) {
587 InfiniteWait = TRUE;
588 } else {
589 InfiniteWait = FALSE;
590 }
591
592 Delay = DivU64x32(Timeout, 1000) + 1;
593
594 do {
595 //
596 // Read Alternate Status Register will not clear interrupt status
597 //
598 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
599 //
600 // Wait for BSY == 0, then judge if DRQ is clear or ERR is set
601 //
602 if ((AltRegister & ATA_STSREG_BSY) == 0) {
603 if ((AltRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {
604 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
605
606 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
607 return EFI_ABORTED;
608 }
609 return EFI_DEVICE_ERROR;
610 }
611
612 if ((AltRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
613 return EFI_SUCCESS;
614 } else {
615 return EFI_NOT_READY;
616 }
617 }
618
619 //
620 // Stall for 100 microseconds.
621 //
622 MicroSecondDelay (100);
623
624 Delay--;
625 } while (InfiniteWait || (Delay > 0));
626
627 return EFI_TIMEOUT;
628 }
629
630
631
632
633 /**
634 This function is used to poll for the BSY bit clear in the Status Register. BSY
635 is clear when the device is not busy. Every command must be sent after device is not busy.
636
637 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
638 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
639 @param Timeout The time to complete the command, uses 100ns as a unit.
640
641 @retval EFI_SUCCESS BSY bit clear within the time out.
642 @retval EFI_TIMEOUT BSY bit not clear within the time out.
643
644 @note Read Status Register will clear interrupt status.
645 **/
646 EFI_STATUS
647 EFIAPI
648 WaitForBSYClear (
649 IN EFI_PCI_IO_PROTOCOL *PciIo,
650 IN EFI_IDE_REGISTERS *IdeRegisters,
651 IN UINT64 Timeout
652 )
653 {
654 UINT64 Delay;
655 UINT8 StatusRegister;
656 BOOLEAN InfiniteWait;
657
658 ASSERT (PciIo != NULL);
659 ASSERT (IdeRegisters != NULL);
660
661 if (Timeout == 0) {
662 InfiniteWait = TRUE;
663 } else {
664 InfiniteWait = FALSE;
665 }
666
667 Delay = DivU64x32(Timeout, 1000) + 1;
668 do {
669 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
670
671 if ((StatusRegister & ATA_STSREG_BSY) == 0x00) {
672 return EFI_SUCCESS;
673 }
674
675 //
676 // Stall for 100 microseconds.
677 //
678 MicroSecondDelay (100);
679
680 Delay--;
681
682 } while (InfiniteWait || (Delay > 0));
683
684 return EFI_TIMEOUT;
685 }
686
687
688 /**
689 Get IDE i/o port registers' base addresses by mode.
690
691 In 'Compatibility' mode, use fixed addresses.
692 In Native-PCI mode, get base addresses from BARs in the PCI IDE controller's
693 Configuration Space.
694
695 The steps to get IDE i/o port registers' base addresses for each channel
696 as follows:
697
698 1. Examine the Programming Interface byte of the Class Code fields in PCI IDE
699 controller's Configuration Space to determine the operating mode.
700
701 2. a) In 'Compatibility' mode, use fixed addresses shown in the Table 1 below.
702 ___________________________________________
703 | | Command Block | Control Block |
704 | Channel | Registers | Registers |
705 |___________|_______________|_______________|
706 | Primary | 1F0h - 1F7h | 3F6h - 3F7h |
707 |___________|_______________|_______________|
708 | Secondary | 170h - 177h | 376h - 377h |
709 |___________|_______________|_______________|
710
711 Table 1. Compatibility resource mappings
712
713 b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs
714 in IDE controller's PCI Configuration Space, shown in the Table 2 below.
715 ___________________________________________________
716 | | Command Block | Control Block |
717 | Channel | Registers | Registers |
718 |___________|___________________|___________________|
719 | Primary | BAR at offset 0x10| BAR at offset 0x14|
720 |___________|___________________|___________________|
721 | Secondary | BAR at offset 0x18| BAR at offset 0x1C|
722 |___________|___________________|___________________|
723
724 Table 2. BARs for Register Mapping
725
726 @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance
727 @param[in, out] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to
728 store the IDE i/o port registers' base addresses
729
730 @retval EFI_UNSUPPORTED Return this value when the BARs is not IO type
731 @retval EFI_SUCCESS Get the Base address successfully
732 @retval Other Read the pci configureation data error
733
734 **/
735 EFI_STATUS
736 EFIAPI
737 GetIdeRegisterIoAddr (
738 IN EFI_PCI_IO_PROTOCOL *PciIo,
739 IN OUT EFI_IDE_REGISTERS *IdeRegisters
740 )
741 {
742 EFI_STATUS Status;
743 PCI_TYPE00 PciData;
744 UINT16 CommandBlockBaseAddr;
745 UINT16 ControlBlockBaseAddr;
746 UINT16 BusMasterBaseAddr;
747
748 if ((PciIo == NULL) || (IdeRegisters == NULL)) {
749 return EFI_INVALID_PARAMETER;
750 }
751
752 Status = PciIo->Pci.Read (
753 PciIo,
754 EfiPciIoWidthUint8,
755 0,
756 sizeof (PciData),
757 &PciData
758 );
759
760 if (EFI_ERROR (Status)) {
761 return Status;
762 }
763
764 BusMasterBaseAddr = (UINT16) ((PciData.Device.Bar[4] & 0x0000fff0));
765
766 if ((PciData.Hdr.ClassCode[0] & IDE_PRIMARY_OPERATING_MODE) == 0) {
767 CommandBlockBaseAddr = 0x1f0;
768 ControlBlockBaseAddr = 0x3f6;
769 } else {
770 //
771 // The BARs should be of IO type
772 //
773 if ((PciData.Device.Bar[0] & BIT0) == 0 ||
774 (PciData.Device.Bar[1] & BIT0) == 0) {
775 return EFI_UNSUPPORTED;
776 }
777
778 CommandBlockBaseAddr = (UINT16) (PciData.Device.Bar[0] & 0x0000fff8);
779 ControlBlockBaseAddr = (UINT16) ((PciData.Device.Bar[1] & 0x0000fffc) + 2);
780 }
781
782 //
783 // Calculate IDE primary channel I/O register base address.
784 //
785 IdeRegisters[EfiIdePrimary].Data = CommandBlockBaseAddr;
786 IdeRegisters[EfiIdePrimary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);
787 IdeRegisters[EfiIdePrimary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);
788 IdeRegisters[EfiIdePrimary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);
789 IdeRegisters[EfiIdePrimary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);
790 IdeRegisters[EfiIdePrimary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);
791 IdeRegisters[EfiIdePrimary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);
792 IdeRegisters[EfiIdePrimary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);
793 IdeRegisters[EfiIdePrimary].AltOrDev = ControlBlockBaseAddr;
794 IdeRegisters[EfiIdePrimary].BusMasterBaseAddr = BusMasterBaseAddr;
795
796 if ((PciData.Hdr.ClassCode[0] & IDE_SECONDARY_OPERATING_MODE) == 0) {
797 CommandBlockBaseAddr = 0x170;
798 ControlBlockBaseAddr = 0x376;
799 } else {
800 //
801 // The BARs should be of IO type
802 //
803 if ((PciData.Device.Bar[2] & BIT0) == 0 ||
804 (PciData.Device.Bar[3] & BIT0) == 0) {
805 return EFI_UNSUPPORTED;
806 }
807
808 CommandBlockBaseAddr = (UINT16) (PciData.Device.Bar[2] & 0x0000fff8);
809 ControlBlockBaseAddr = (UINT16) ((PciData.Device.Bar[3] & 0x0000fffc) + 2);
810 }
811
812 //
813 // Calculate IDE secondary channel I/O register base address.
814 //
815 IdeRegisters[EfiIdeSecondary].Data = CommandBlockBaseAddr;
816 IdeRegisters[EfiIdeSecondary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);
817 IdeRegisters[EfiIdeSecondary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);
818 IdeRegisters[EfiIdeSecondary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);
819 IdeRegisters[EfiIdeSecondary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);
820 IdeRegisters[EfiIdeSecondary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);
821 IdeRegisters[EfiIdeSecondary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);
822 IdeRegisters[EfiIdeSecondary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);
823 IdeRegisters[EfiIdeSecondary].AltOrDev = ControlBlockBaseAddr;
824 IdeRegisters[EfiIdeSecondary].BusMasterBaseAddr = (UINT16) (BusMasterBaseAddr + 0x8);
825
826 return EFI_SUCCESS;
827 }
828
829
830 /**
831 Send ATA Ext command into device with NON_DATA protocol.
832
833 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
834 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
835 @param AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.
836 @param Timeout The time to complete the command, uses 100ns as a unit.
837
838 @retval EFI_SUCCESS Reading succeed
839 @retval EFI_DEVICE_ERROR Error executing commands on this device.
840
841 **/
842 EFI_STATUS
843 EFIAPI
844 AtaIssueCommand (
845 IN EFI_PCI_IO_PROTOCOL *PciIo,
846 IN EFI_IDE_REGISTERS *IdeRegisters,
847 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
848 IN UINT64 Timeout
849 )
850 {
851 EFI_STATUS Status;
852 UINT8 DeviceHead;
853 UINT8 AtaCommand;
854
855 ASSERT (PciIo != NULL);
856 ASSERT (IdeRegisters != NULL);
857 ASSERT (AtaCommandBlock != NULL);
858
859 DeviceHead = AtaCommandBlock->AtaDeviceHead;
860 AtaCommand = AtaCommandBlock->AtaCommand;
861
862 Status = WaitForBSYClear (PciIo, IdeRegisters, Timeout);
863 if (EFI_ERROR (Status)) {
864 return EFI_DEVICE_ERROR;
865 }
866
867 //
868 // Select device (bit4), set LBA mode(bit6) (use 0xe0 for compatibility)
869 //
870 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8) (0xe0 | DeviceHead));
871
872 //
873 // set all the command parameters
874 // Before write to all the following registers, BSY and DRQ must be 0.
875 //
876 Status = DRQClear2 (PciIo, IdeRegisters, Timeout);
877 if (EFI_ERROR (Status)) {
878 return EFI_DEVICE_ERROR;
879 }
880
881 //
882 // Fill the feature register, which is a two-byte FIFO. Need write twice.
883 //
884 IdeWritePortB (PciIo, IdeRegisters->ErrOrFeature, AtaCommandBlock->AtaFeaturesExp);
885 IdeWritePortB (PciIo, IdeRegisters->ErrOrFeature, AtaCommandBlock->AtaFeatures);
886
887 //
888 // Fill the sector count register, which is a two-byte FIFO. Need write twice.
889 //
890 IdeWritePortB (PciIo, IdeRegisters->SectorCount, AtaCommandBlock->AtaSectorCountExp);
891 IdeWritePortB (PciIo, IdeRegisters->SectorCount, AtaCommandBlock->AtaSectorCount);
892
893 //
894 // Fill the start LBA registers, which are also two-byte FIFO
895 //
896 IdeWritePortB (PciIo, IdeRegisters->SectorNumber, AtaCommandBlock->AtaSectorNumberExp);
897 IdeWritePortB (PciIo, IdeRegisters->SectorNumber, AtaCommandBlock->AtaSectorNumber);
898
899 IdeWritePortB (PciIo, IdeRegisters->CylinderLsb, AtaCommandBlock->AtaCylinderLowExp);
900 IdeWritePortB (PciIo, IdeRegisters->CylinderLsb, AtaCommandBlock->AtaCylinderLow);
901
902 IdeWritePortB (PciIo, IdeRegisters->CylinderMsb, AtaCommandBlock->AtaCylinderHighExp);
903 IdeWritePortB (PciIo, IdeRegisters->CylinderMsb, AtaCommandBlock->AtaCylinderHigh);
904
905 //
906 // Send command via Command Register
907 //
908 IdeWritePortB (PciIo, IdeRegisters->CmdOrStatus, AtaCommand);
909
910 //
911 // Stall at least 400 microseconds.
912 //
913 MicroSecondDelay (400);
914
915 return EFI_SUCCESS;
916 }
917
918 /**
919 This function is used to send out ATA commands conforms to the PIO Data In Protocol.
920
921 @param[in] PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data
922 structure.
923 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
924 @param[in, out] Buffer A pointer to the source buffer for the data.
925 @param[in] ByteCount The length of the data.
926 @param[in] Read Flag used to determine the data transfer direction.
927 Read equals 1, means data transferred from device
928 to host;Read equals 0, means data transferred
929 from host to device.
930 @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.
931 @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
932 @param[in] Timeout The time to complete the command, uses 100ns as a unit.
933 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
934 used by non-blocking mode.
935
936 @retval EFI_SUCCESS send out the ATA command and device send required data successfully.
937 @retval EFI_DEVICE_ERROR command sent failed.
938
939 **/
940 EFI_STATUS
941 EFIAPI
942 AtaPioDataInOut (
943 IN EFI_PCI_IO_PROTOCOL *PciIo,
944 IN EFI_IDE_REGISTERS *IdeRegisters,
945 IN OUT VOID *Buffer,
946 IN UINT64 ByteCount,
947 IN BOOLEAN Read,
948 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
949 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
950 IN UINT64 Timeout,
951 IN ATA_NONBLOCK_TASK *Task
952 )
953 {
954 UINTN WordCount;
955 UINTN Increment;
956 UINT16 *Buffer16;
957 EFI_STATUS Status;
958
959 if ((PciIo == NULL) || (IdeRegisters == NULL) || (Buffer == NULL) || (AtaCommandBlock == NULL)) {
960 return EFI_INVALID_PARAMETER;
961 }
962
963 //
964 // Issue ATA command
965 //
966 Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);
967 if (EFI_ERROR (Status)) {
968 Status = EFI_DEVICE_ERROR;
969 goto Exit;
970 }
971
972 Buffer16 = (UINT16 *) Buffer;
973
974 //
975 // According to PIO data in protocol, host can perform a series of reads to
976 // the data register after each time device set DRQ ready;
977 // The data size of "a series of read" is command specific.
978 // For most ATA command, data size received from device will not exceed
979 // 1 sector, hence the data size for "a series of read" can be the whole data
980 // size of one command request.
981 // For ATA command such as Read Sector command, the data size of one ATA
982 // command request is often larger than 1 sector, according to the
983 // Read Sector command, the data size of "a series of read" is exactly 1
984 // sector.
985 // Here for simplification reason, we specify the data size for
986 // "a series of read" to 1 sector (256 words) if data size of one ATA command
987 // request is larger than 256 words.
988 //
989 Increment = 256;
990
991 //
992 // used to record bytes of currently transfered data
993 //
994 WordCount = 0;
995
996 while (WordCount < RShiftU64(ByteCount, 1)) {
997 //
998 // Poll DRQ bit set, data transfer can be performed only when DRQ is ready
999 //
1000 Status = DRQReady2 (PciIo, IdeRegisters, Timeout);
1001 if (EFI_ERROR (Status)) {
1002 Status = EFI_DEVICE_ERROR;
1003 goto Exit;
1004 }
1005
1006 //
1007 // Get the byte count for one series of read
1008 //
1009 if ((WordCount + Increment) > RShiftU64(ByteCount, 1)) {
1010 Increment = (UINTN)(RShiftU64(ByteCount, 1) - WordCount);
1011 }
1012
1013 if (Read) {
1014 IdeReadPortWMultiple (
1015 PciIo,
1016 IdeRegisters->Data,
1017 Increment,
1018 Buffer16
1019 );
1020 } else {
1021 IdeWritePortWMultiple (
1022 PciIo,
1023 IdeRegisters->Data,
1024 Increment,
1025 Buffer16
1026 );
1027 }
1028
1029 Status = CheckStatusRegister (PciIo, IdeRegisters);
1030 if (EFI_ERROR (Status)) {
1031 Status = EFI_DEVICE_ERROR;
1032 goto Exit;
1033 }
1034
1035 WordCount += Increment;
1036 Buffer16 += Increment;
1037 }
1038
1039 Status = DRQClear (PciIo, IdeRegisters, Timeout);
1040 if (EFI_ERROR (Status)) {
1041 Status = EFI_DEVICE_ERROR;
1042 goto Exit;
1043 }
1044
1045 Exit:
1046 //
1047 // Dump All Ide registers to ATA_STATUS_BLOCK
1048 //
1049 DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);
1050
1051 //
1052 // Not support the Non-blocking now,just do the blocking process.
1053 //
1054 return Status;
1055 }
1056
1057 /**
1058 Send ATA command into device with NON_DATA protocol
1059
1060 @param[in] PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE
1061 data structure.
1062 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1063 @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data
1064 structure.
1065 @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1066 @param[in] Timeout The time to complete the command, uses 100ns as a unit.
1067 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1068 used by non-blocking mode.
1069
1070 @retval EFI_SUCCESS Reading succeed
1071 @retval EFI_ABORTED Command failed
1072 @retval EFI_DEVICE_ERROR Device status error.
1073
1074 **/
1075 EFI_STATUS
1076 EFIAPI
1077 AtaNonDataCommandIn (
1078 IN EFI_PCI_IO_PROTOCOL *PciIo,
1079 IN EFI_IDE_REGISTERS *IdeRegisters,
1080 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1081 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1082 IN UINT64 Timeout,
1083 IN ATA_NONBLOCK_TASK *Task
1084 )
1085 {
1086 EFI_STATUS Status;
1087
1088 if ((PciIo == NULL) || (IdeRegisters == NULL) || (AtaCommandBlock == NULL)) {
1089 return EFI_INVALID_PARAMETER;
1090 }
1091
1092 //
1093 // Issue ATA command
1094 //
1095 Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);
1096 if (EFI_ERROR (Status)) {
1097 Status = EFI_DEVICE_ERROR;
1098 goto Exit;
1099 }
1100
1101 //
1102 // Wait for command completion
1103 //
1104 Status = WaitForBSYClear (PciIo, IdeRegisters, Timeout);
1105 if (EFI_ERROR (Status)) {
1106 Status = EFI_DEVICE_ERROR;
1107 goto Exit;
1108 }
1109
1110 Status = CheckStatusRegister (PciIo, IdeRegisters);
1111 if (EFI_ERROR (Status)) {
1112 Status = EFI_DEVICE_ERROR;
1113 goto Exit;
1114 }
1115
1116 Exit:
1117 //
1118 // Dump All Ide registers to ATA_STATUS_BLOCK
1119 //
1120 DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);
1121
1122 //
1123 // Not support the Non-blocking now,just do the blocking process.
1124 //
1125 return Status;
1126 }
1127
1128 /**
1129 Wait for memory to be set.
1130
1131 @param[in] PciIo The PCI IO protocol instance.
1132 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1133 @param[in] Timeout The time to complete the command, uses 100ns as a unit.
1134
1135 @retval EFI_DEVICE_ERROR The memory is not set.
1136 @retval EFI_TIMEOUT The memory setting is time out.
1137 @retval EFI_SUCCESS The memory is correct set.
1138
1139 **/
1140 EFI_STATUS
1141 AtaUdmStatusWait (
1142 IN EFI_PCI_IO_PROTOCOL *PciIo,
1143 IN EFI_IDE_REGISTERS *IdeRegisters,
1144 IN UINT64 Timeout
1145 )
1146 {
1147 UINT8 RegisterValue;
1148 EFI_STATUS Status;
1149 UINT16 IoPortForBmis;
1150 UINT64 Delay;
1151 BOOLEAN InfiniteWait;
1152
1153 if (Timeout == 0) {
1154 InfiniteWait = TRUE;
1155 } else {
1156 InfiniteWait = FALSE;
1157 }
1158
1159 Delay = DivU64x32 (Timeout, 1000) + 1;
1160
1161 do {
1162 Status = CheckStatusRegister (PciIo, IdeRegisters);
1163 if (EFI_ERROR (Status)) {
1164 Status = EFI_DEVICE_ERROR;
1165 break;
1166 }
1167
1168 IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);
1169 RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);
1170 if (((RegisterValue & BMIS_ERROR) != 0) || (Timeout == 0)) {
1171 DEBUG ((EFI_D_ERROR, "ATA UDMA operation fails\n"));
1172 Status = EFI_DEVICE_ERROR;
1173 break;
1174 }
1175
1176 if ((RegisterValue & BMIS_INTERRUPT) != 0) {
1177 Status = EFI_SUCCESS;
1178 break;
1179 }
1180 //
1181 // Stall for 100 microseconds.
1182 //
1183 MicroSecondDelay (100);
1184 Delay--;
1185 } while (InfiniteWait || (Delay > 0));
1186
1187 return Status;
1188 }
1189
1190 /**
1191 Check if the memory to be set.
1192
1193 @param[in] PciIo The PCI IO protocol instance.
1194 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1195 used by non-blocking mode.
1196 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1197
1198 @retval EFI_DEVICE_ERROR The memory setting met a issue.
1199 @retval EFI_NOT_READY The memory is not set.
1200 @retval EFI_TIMEOUT The memory setting is time out.
1201 @retval EFI_SUCCESS The memory is correct set.
1202
1203 **/
1204 EFI_STATUS
1205 AtaUdmStatusCheck (
1206 IN EFI_PCI_IO_PROTOCOL *PciIo,
1207 IN ATA_NONBLOCK_TASK *Task,
1208 IN EFI_IDE_REGISTERS *IdeRegisters
1209 )
1210 {
1211 UINT8 RegisterValue;
1212 UINT16 IoPortForBmis;
1213 EFI_STATUS Status;
1214
1215 Task->RetryTimes--;
1216
1217 Status = CheckStatusRegister (PciIo, IdeRegisters);
1218 if (EFI_ERROR (Status)) {
1219 return EFI_DEVICE_ERROR;
1220 }
1221
1222 IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);
1223 RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);
1224
1225 if ((RegisterValue & BMIS_ERROR) != 0) {
1226 DEBUG ((EFI_D_ERROR, "ATA UDMA operation fails\n"));
1227 return EFI_DEVICE_ERROR;
1228 }
1229
1230 if ((RegisterValue & BMIS_INTERRUPT) != 0) {
1231 return EFI_SUCCESS;
1232 }
1233
1234 if (!Task->InfiniteWait && (Task->RetryTimes == 0)) {
1235 return EFI_TIMEOUT;
1236 } else {
1237 //
1238 // The memory is not set.
1239 //
1240 return EFI_NOT_READY;
1241 }
1242 }
1243
1244 /**
1245 Perform an ATA Udma operation (Read, ReadExt, Write, WriteExt).
1246
1247 @param[in] Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data
1248 structure.
1249 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1250 @param[in] Read Flag used to determine the data transfer
1251 direction. Read equals 1, means data transferred
1252 from device to host;Read equals 0, means data
1253 transferred from host to device.
1254 @param[in] DataBuffer A pointer to the source buffer for the data.
1255 @param[in] DataLength The length of the data.
1256 @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.
1257 @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1258 @param[in] Timeout The time to complete the command, uses 100ns as a unit.
1259 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1260 used by non-blocking mode.
1261
1262 @retval EFI_SUCCESS the operation is successful.
1263 @retval EFI_OUT_OF_RESOURCES Build PRD table failed
1264 @retval EFI_UNSUPPORTED Unknown channel or operations command
1265 @retval EFI_DEVICE_ERROR Ata command execute failed
1266
1267 **/
1268 EFI_STATUS
1269 EFIAPI
1270 AtaUdmaInOut (
1271 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
1272 IN EFI_IDE_REGISTERS *IdeRegisters,
1273 IN BOOLEAN Read,
1274 IN VOID *DataBuffer,
1275 IN UINT64 DataLength,
1276 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1277 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1278 IN UINT64 Timeout,
1279 IN ATA_NONBLOCK_TASK *Task
1280 )
1281 {
1282 EFI_STATUS Status;
1283 UINT16 IoPortForBmic;
1284 UINT16 IoPortForBmis;
1285 UINT16 IoPortForBmid;
1286
1287 UINTN PrdTableSize;
1288 EFI_PHYSICAL_ADDRESS PrdTableMapAddr;
1289 VOID *PrdTableMap;
1290 EFI_PHYSICAL_ADDRESS PrdTableBaseAddr;
1291 EFI_ATA_DMA_PRD *TempPrdBaseAddr;
1292 UINTN PrdTableNum;
1293
1294 UINT8 RegisterValue;
1295 UINTN PageCount;
1296 UINTN ByteCount;
1297 UINTN ByteRemaining;
1298 UINT8 DeviceControl;
1299
1300 VOID *BufferMap;
1301 EFI_PHYSICAL_ADDRESS BufferMapAddress;
1302 EFI_PCI_IO_PROTOCOL_OPERATION PciIoOperation;
1303
1304 UINT8 DeviceHead;
1305 EFI_PCI_IO_PROTOCOL *PciIo;
1306 EFI_TPL OldTpl;
1307
1308 UINTN AlignmentMask;
1309 UINTN RealPageCount;
1310 EFI_PHYSICAL_ADDRESS BaseAddr;
1311 EFI_PHYSICAL_ADDRESS BaseMapAddr;
1312
1313 Status = EFI_SUCCESS;
1314 PrdTableMap = NULL;
1315 BufferMap = NULL;
1316 PageCount = 0;
1317 RealPageCount = 0;
1318 BaseAddr = 0;
1319 PciIo = Instance->PciIo;
1320
1321 if ((PciIo == NULL) || (IdeRegisters == NULL) || (DataBuffer == NULL) || (AtaCommandBlock == NULL)) {
1322 return EFI_INVALID_PARAMETER;
1323 }
1324
1325 //
1326 // Before starting the Blocking BlockIO operation, push to finish all non-blocking
1327 // BlockIO tasks.
1328 // Delay 1ms to simulate the blocking time out checking.
1329 //
1330 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1331 while ((Task == NULL) && (!IsListEmpty (&Instance->NonBlockingTaskList))) {
1332 AsyncNonBlockingTransferRoutine (NULL, Instance);
1333 //
1334 // Stall for 1 milliseconds.
1335 //
1336 MicroSecondDelay (1000);
1337 }
1338 gBS->RestoreTPL (OldTpl);
1339
1340 //
1341 // The data buffer should be even alignment
1342 //
1343 if (((UINTN)DataBuffer & 0x1) != 0) {
1344 return EFI_INVALID_PARAMETER;
1345 }
1346
1347 //
1348 // Set relevant IO Port address.
1349 //
1350 IoPortForBmic = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIC_OFFSET);
1351 IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);
1352 IoPortForBmid = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMID_OFFSET);
1353
1354 //
1355 // For Blocking mode, start the command.
1356 // For non-blocking mode, when the command is not started, start it, otherwise
1357 // go to check the status.
1358 //
1359 if (((Task != NULL) && (!Task->IsStart)) || (Task == NULL)) {
1360 //
1361 // Calculate the number of PRD entry.
1362 // Every entry in PRD table can specify a 64K memory region.
1363 //
1364 PrdTableNum = (UINTN)(RShiftU64(DataLength, 16) + 1);
1365
1366 //
1367 // Make sure that the memory region of PRD table is not cross 64K boundary
1368 //
1369 PrdTableSize = PrdTableNum * sizeof (EFI_ATA_DMA_PRD);
1370 if (PrdTableSize > 0x10000) {
1371 return EFI_INVALID_PARAMETER;
1372 }
1373
1374 //
1375 // Allocate buffer for PRD table initialization.
1376 // Note Ide Bus Master spec said the descriptor table must be aligned on a 4 byte
1377 // boundary and the table cannot cross a 64K boundary in memory.
1378 //
1379 PageCount = EFI_SIZE_TO_PAGES (PrdTableSize);
1380 RealPageCount = PageCount + EFI_SIZE_TO_PAGES (SIZE_64KB);
1381
1382 //
1383 // Make sure that PageCount plus EFI_SIZE_TO_PAGES (SIZE_64KB) does not overflow.
1384 //
1385 ASSERT (RealPageCount > PageCount);
1386
1387 Status = PciIo->AllocateBuffer (
1388 PciIo,
1389 AllocateAnyPages,
1390 EfiBootServicesData,
1391 RealPageCount,
1392 (VOID **)&BaseAddr,
1393 0
1394 );
1395 if (EFI_ERROR (Status)) {
1396 return EFI_OUT_OF_RESOURCES;
1397 }
1398
1399 ByteCount = EFI_PAGES_TO_SIZE (RealPageCount);
1400 Status = PciIo->Map (
1401 PciIo,
1402 EfiPciIoOperationBusMasterCommonBuffer,
1403 (VOID*)(UINTN)BaseAddr,
1404 &ByteCount,
1405 &BaseMapAddr,
1406 &PrdTableMap
1407 );
1408 if (EFI_ERROR (Status) || (ByteCount != EFI_PAGES_TO_SIZE (RealPageCount))) {
1409 //
1410 // If the data length actually mapped is not equal to the requested amount,
1411 // it means the DMA operation may be broken into several discontinuous smaller chunks.
1412 // Can't handle this case.
1413 //
1414 PciIo->FreeBuffer (PciIo, RealPageCount, (VOID*)(UINTN)BaseAddr);
1415 return EFI_OUT_OF_RESOURCES;
1416 }
1417
1418 ZeroMem ((VOID *) ((UINTN) BaseAddr), ByteCount);
1419
1420 //
1421 // Calculate the 64K align address as PRD Table base address.
1422 //
1423 AlignmentMask = SIZE_64KB - 1;
1424 PrdTableBaseAddr = ((UINTN) BaseAddr + AlignmentMask) & ~AlignmentMask;
1425 PrdTableMapAddr = ((UINTN) BaseMapAddr + AlignmentMask) & ~AlignmentMask;
1426
1427 //
1428 // Map the host address of DataBuffer to DMA master address.
1429 //
1430 if (Read) {
1431 PciIoOperation = EfiPciIoOperationBusMasterWrite;
1432 } else {
1433 PciIoOperation = EfiPciIoOperationBusMasterRead;
1434 }
1435
1436 ByteCount = (UINTN)DataLength;
1437 Status = PciIo->Map (
1438 PciIo,
1439 PciIoOperation,
1440 DataBuffer,
1441 &ByteCount,
1442 &BufferMapAddress,
1443 &BufferMap
1444 );
1445 if (EFI_ERROR (Status) || (ByteCount != DataLength)) {
1446 PciIo->Unmap (PciIo, PrdTableMap);
1447 PciIo->FreeBuffer (PciIo, RealPageCount, (VOID*)(UINTN)BaseAddr);
1448 return EFI_OUT_OF_RESOURCES;
1449 }
1450
1451 //
1452 // According to Ata spec, it requires the buffer address and size to be even.
1453 //
1454 ASSERT ((BufferMapAddress & 0x1) == 0);
1455 ASSERT ((ByteCount & 0x1) == 0);
1456
1457 //
1458 // Fill the PRD table with appropriate bus master address of data buffer and data length.
1459 //
1460 ByteRemaining = ByteCount;
1461 TempPrdBaseAddr = (EFI_ATA_DMA_PRD*)(UINTN)PrdTableBaseAddr;
1462 while (ByteRemaining != 0) {
1463 if (ByteRemaining <= 0x10000) {
1464 TempPrdBaseAddr->RegionBaseAddr = (UINT32) ((UINTN) BufferMapAddress);
1465 TempPrdBaseAddr->ByteCount = (UINT16) ByteRemaining;
1466 TempPrdBaseAddr->EndOfTable = 0x8000;
1467 break;
1468 }
1469
1470 TempPrdBaseAddr->RegionBaseAddr = (UINT32) ((UINTN) BufferMapAddress);
1471 TempPrdBaseAddr->ByteCount = (UINT16) 0x0;
1472
1473 ByteRemaining -= 0x10000;
1474 BufferMapAddress += 0x10000;
1475 TempPrdBaseAddr++;
1476 }
1477
1478 //
1479 // Start to enable the DMA operation
1480 //
1481 DeviceHead = AtaCommandBlock->AtaDeviceHead;
1482
1483 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)(0xe0 | DeviceHead));
1484
1485 //
1486 // Enable interrupt to support UDMA
1487 //
1488 DeviceControl = 0;
1489 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
1490
1491 //
1492 // Read BMIS register and clear ERROR and INTR bit
1493 //
1494 RegisterValue = IdeReadPortB(PciIo, IoPortForBmis);
1495 RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);
1496 IdeWritePortB (PciIo, IoPortForBmis, RegisterValue);
1497
1498 //
1499 // Set the base address to BMID register
1500 //
1501 IdeWritePortDW (PciIo, IoPortForBmid, (UINT32)PrdTableMapAddr);
1502
1503 //
1504 // Set BMIC register to identify the operation direction
1505 //
1506 RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);
1507 if (Read) {
1508 RegisterValue |= BMIC_NREAD;
1509 } else {
1510 RegisterValue &= ~((UINT8) BMIC_NREAD);
1511 }
1512 IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);
1513
1514 if (Task != NULL) {
1515 Task->Map = BufferMap;
1516 Task->TableMap = PrdTableMap;
1517 Task->MapBaseAddress = (EFI_ATA_DMA_PRD*)(UINTN)BaseAddr;
1518 Task->PageCount = RealPageCount;
1519 Task->IsStart = TRUE;
1520 }
1521
1522 //
1523 // Issue ATA command
1524 //
1525 Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);
1526
1527 if (EFI_ERROR (Status)) {
1528 Status = EFI_DEVICE_ERROR;
1529 goto Exit;
1530 }
1531
1532 Status = CheckStatusRegister (PciIo, IdeRegisters);
1533 if (EFI_ERROR (Status)) {
1534 Status = EFI_DEVICE_ERROR;
1535 goto Exit;
1536 }
1537 //
1538 // Set START bit of BMIC register
1539 //
1540 RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);
1541 RegisterValue |= BMIC_START;
1542 IdeWritePortB(PciIo, IoPortForBmic, RegisterValue);
1543
1544 }
1545
1546 //
1547 // Check the INTERRUPT and ERROR bit of BMIS
1548 //
1549 if (Task != NULL) {
1550 Status = AtaUdmStatusCheck (PciIo, Task, IdeRegisters);
1551 } else {
1552 Status = AtaUdmStatusWait (PciIo, IdeRegisters, Timeout);
1553 }
1554
1555 //
1556 // For blocking mode, clear registers and free buffers.
1557 // For non blocking mode, when the related registers have been set or time
1558 // out, or a error has been happened, it needs to clear the register and free
1559 // buffer.
1560 //
1561 if ((Task == NULL) || Status != EFI_NOT_READY) {
1562 //
1563 // Read BMIS register and clear ERROR and INTR bit
1564 //
1565 RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);
1566 RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);
1567 IdeWritePortB (PciIo, IoPortForBmis, RegisterValue);
1568
1569 //
1570 // Read Status Register of IDE device to clear interrupt
1571 //
1572 RegisterValue = IdeReadPortB(PciIo, IdeRegisters->CmdOrStatus);
1573
1574 //
1575 // Clear START bit of BMIC register
1576 //
1577 RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);
1578 RegisterValue &= ~((UINT8) BMIC_START);
1579 IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);
1580
1581 //
1582 // Disable interrupt of Select device
1583 //
1584 DeviceControl = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
1585 DeviceControl |= ATA_CTLREG_IEN_L;
1586 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
1587 //
1588 // Stall for 10 milliseconds.
1589 //
1590 MicroSecondDelay (10000);
1591
1592 }
1593
1594 Exit:
1595 //
1596 // Free all allocated resource
1597 //
1598 if ((Task == NULL) || Status != EFI_NOT_READY) {
1599 if (Task != NULL) {
1600 PciIo->Unmap (PciIo, Task->TableMap);
1601 PciIo->FreeBuffer (PciIo, Task->PageCount, Task->MapBaseAddress);
1602 PciIo->Unmap (PciIo, Task->Map);
1603 } else {
1604 PciIo->Unmap (PciIo, PrdTableMap);
1605 PciIo->FreeBuffer (PciIo, RealPageCount, (VOID*)(UINTN)BaseAddr);
1606 PciIo->Unmap (PciIo, BufferMap);
1607 }
1608
1609 //
1610 // Dump All Ide registers to ATA_STATUS_BLOCK
1611 //
1612 DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);
1613 }
1614
1615 return Status;
1616 }
1617
1618 /**
1619 This function reads the pending data in the device.
1620
1621 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
1622 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1623
1624 @retval EFI_SUCCESS Successfully read.
1625 @retval EFI_NOT_READY The BSY is set avoiding reading.
1626
1627 **/
1628 EFI_STATUS
1629 EFIAPI
1630 AtaPacketReadPendingData (
1631 IN EFI_PCI_IO_PROTOCOL *PciIo,
1632 IN EFI_IDE_REGISTERS *IdeRegisters
1633 )
1634 {
1635 UINT8 AltRegister;
1636 UINT16 TempWordBuffer;
1637
1638 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
1639 if ((AltRegister & ATA_STSREG_BSY) == ATA_STSREG_BSY) {
1640 return EFI_NOT_READY;
1641 }
1642
1643 if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
1644 TempWordBuffer = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
1645 while ((TempWordBuffer & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
1646 IdeReadPortWMultiple (
1647 PciIo,
1648 IdeRegisters->Data,
1649 1,
1650 &TempWordBuffer
1651 );
1652 TempWordBuffer = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
1653 }
1654 }
1655 return EFI_SUCCESS;
1656 }
1657
1658 /**
1659 This function is called by AtaPacketCommandExecute().
1660 It is used to transfer data between host and device. The data direction is specified
1661 by the fourth parameter.
1662
1663 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
1664 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1665 @param Buffer Buffer contained data transferred between host and device.
1666 @param ByteCount Data size in byte unit of the buffer.
1667 @param Read Flag used to determine the data transfer direction.
1668 Read equals 1, means data transferred from device to host;
1669 Read equals 0, means data transferred from host to device.
1670 @param Timeout Timeout value for wait DRQ ready before each data stream's transfer
1671 , uses 100ns as a unit.
1672
1673 @retval EFI_SUCCESS data is transferred successfully.
1674 @retval EFI_DEVICE_ERROR the device failed to transfer data.
1675 **/
1676 EFI_STATUS
1677 EFIAPI
1678 AtaPacketReadWrite (
1679 IN EFI_PCI_IO_PROTOCOL *PciIo,
1680 IN EFI_IDE_REGISTERS *IdeRegisters,
1681 IN OUT VOID *Buffer,
1682 IN OUT UINT32 *ByteCount,
1683 IN BOOLEAN Read,
1684 IN UINT64 Timeout
1685 )
1686 {
1687 UINT32 RequiredWordCount;
1688 UINT32 ActualWordCount;
1689 UINT32 WordCount;
1690 EFI_STATUS Status;
1691 UINT16 *PtrBuffer;
1692
1693 PtrBuffer = Buffer;
1694 RequiredWordCount = *ByteCount >> 1;
1695
1696 //
1697 // No data transfer is premitted.
1698 //
1699 if (RequiredWordCount == 0) {
1700 return EFI_SUCCESS;
1701 }
1702
1703 //
1704 // ActualWordCount means the word count of data really transferred.
1705 //
1706 ActualWordCount = 0;
1707
1708 while (ActualWordCount < RequiredWordCount) {
1709 //
1710 // before each data transfer stream, the host should poll DRQ bit ready,
1711 // to see whether indicates device is ready to transfer data.
1712 //
1713 Status = DRQReady2 (PciIo, IdeRegisters, Timeout);
1714 if (EFI_ERROR (Status)) {
1715 if (Status == EFI_NOT_READY) {
1716 //
1717 // Device provided less data than we intended to read, or wanted less
1718 // data than we intended to write, but it may still be successful.
1719 //
1720 break;
1721 } else {
1722 return Status;
1723 }
1724 }
1725
1726 //
1727 // get current data transfer size from Cylinder Registers.
1728 //
1729 WordCount = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb) << 8;
1730 WordCount = WordCount | IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
1731 WordCount = WordCount & 0xffff;
1732 WordCount /= 2;
1733
1734 WordCount = MIN (WordCount, (RequiredWordCount - ActualWordCount));
1735
1736 if (Read) {
1737 IdeReadPortWMultiple (
1738 PciIo,
1739 IdeRegisters->Data,
1740 WordCount,
1741 PtrBuffer
1742 );
1743 } else {
1744 IdeWritePortWMultiple (
1745 PciIo,
1746 IdeRegisters->Data,
1747 WordCount,
1748 PtrBuffer
1749 );
1750 }
1751
1752 //
1753 // read status register to check whether error happens.
1754 //
1755 Status = CheckStatusRegister (PciIo, IdeRegisters);
1756 if (EFI_ERROR (Status)) {
1757 return EFI_DEVICE_ERROR;
1758 }
1759
1760 PtrBuffer += WordCount;
1761 ActualWordCount += WordCount;
1762 }
1763
1764 if (Read) {
1765 //
1766 // In the case where the drive wants to send more data than we need to read,
1767 // the DRQ bit will be set and cause delays from DRQClear2().
1768 // We need to read data from the drive until it clears DRQ so we can move on.
1769 //
1770 AtaPacketReadPendingData (PciIo, IdeRegisters);
1771 }
1772
1773 //
1774 // read status register to check whether error happens.
1775 //
1776 Status = CheckStatusRegister (PciIo, IdeRegisters);
1777 if (EFI_ERROR (Status)) {
1778 return EFI_DEVICE_ERROR;
1779 }
1780
1781 //
1782 // After data transfer is completed, normally, DRQ bit should clear.
1783 //
1784 Status = DRQClear (PciIo, IdeRegisters, Timeout);
1785 if (EFI_ERROR (Status)) {
1786 return EFI_DEVICE_ERROR;
1787 }
1788
1789 *ByteCount = ActualWordCount << 1;
1790 return Status;
1791 }
1792
1793 /**
1794 This function is used to send out ATAPI commands conforms to the Packet Command
1795 with PIO Data In Protocol.
1796
1797 @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance
1798 @param[in] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to
1799 store the IDE i/o port registers' base addresses
1800 @param[in] Channel The channel number of device.
1801 @param[in] Device The device number of device.
1802 @param[in] Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET data structure.
1803
1804 @retval EFI_SUCCESS send out the ATAPI packet command successfully
1805 and device sends data successfully.
1806 @retval EFI_DEVICE_ERROR the device failed to send data.
1807
1808 **/
1809 EFI_STATUS
1810 EFIAPI
1811 AtaPacketCommandExecute (
1812 IN EFI_PCI_IO_PROTOCOL *PciIo,
1813 IN EFI_IDE_REGISTERS *IdeRegisters,
1814 IN UINT8 Channel,
1815 IN UINT8 Device,
1816 IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
1817 )
1818 {
1819 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1820 EFI_STATUS Status;
1821 UINT8 Count;
1822 UINT8 PacketCommand[12];
1823
1824 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1825
1826 //
1827 // Fill ATAPI Command Packet according to CDB.
1828 // For Atapi cmd, its length should be less than or equal to 12 bytes.
1829 //
1830 if (Packet->CdbLength > 12) {
1831 return EFI_INVALID_PARAMETER;
1832 }
1833
1834 ZeroMem (PacketCommand, 12);
1835 CopyMem (PacketCommand, Packet->Cdb, Packet->CdbLength);
1836
1837 //
1838 // No OVL; No DMA
1839 //
1840 AtaCommandBlock.AtaFeatures = 0x00;
1841 //
1842 // set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device
1843 // determine how many data should be transferred.
1844 //
1845 AtaCommandBlock.AtaCylinderLow = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);
1846 AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);
1847 AtaCommandBlock.AtaDeviceHead = (UINT8) (Device << 0x4);
1848 AtaCommandBlock.AtaCommand = ATA_CMD_PACKET;
1849
1850 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)(0xe0 | (Device << 0x4)));
1851 //
1852 // Disable interrupt
1853 //
1854 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, ATA_DEFAULT_CTL);
1855
1856 //
1857 // Issue ATA PACKET command firstly
1858 //
1859 Status = AtaIssueCommand (PciIo, IdeRegisters, &AtaCommandBlock, Packet->Timeout);
1860 if (EFI_ERROR (Status)) {
1861 return Status;
1862 }
1863
1864 Status = DRQReady (PciIo, IdeRegisters, Packet->Timeout);
1865 if (EFI_ERROR (Status)) {
1866 return Status;
1867 }
1868
1869 //
1870 // Send out ATAPI command packet
1871 //
1872 for (Count = 0; Count < 6; Count++) {
1873 IdeWritePortW (PciIo, IdeRegisters->Data, *((UINT16*)PacketCommand + Count));
1874 //
1875 // Stall for 10 microseconds.
1876 //
1877 MicroSecondDelay (10);
1878 }
1879
1880 //
1881 // Read/Write the data of ATAPI Command
1882 //
1883 if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {
1884 Status = AtaPacketReadWrite (
1885 PciIo,
1886 IdeRegisters,
1887 Packet->InDataBuffer,
1888 &Packet->InTransferLength,
1889 TRUE,
1890 Packet->Timeout
1891 );
1892 } else {
1893 Status = AtaPacketReadWrite (
1894 PciIo,
1895 IdeRegisters,
1896 Packet->OutDataBuffer,
1897 &Packet->OutTransferLength,
1898 FALSE,
1899 Packet->Timeout
1900 );
1901 }
1902
1903 return Status;
1904 }
1905
1906
1907 /**
1908 Set the calculated Best transfer mode to a detected device.
1909
1910 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
1911 @param Channel The channel number of device.
1912 @param Device The device number of device.
1913 @param TransferMode A pointer to EFI_ATA_TRANSFER_MODE data structure.
1914 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1915
1916 @retval EFI_SUCCESS Set transfer mode successfully.
1917 @retval EFI_DEVICE_ERROR Set transfer mode failed.
1918 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
1919
1920 **/
1921 EFI_STATUS
1922 EFIAPI
1923 SetDeviceTransferMode (
1924 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
1925 IN UINT8 Channel,
1926 IN UINT8 Device,
1927 IN EFI_ATA_TRANSFER_MODE *TransferMode,
1928 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
1929 )
1930 {
1931 EFI_STATUS Status;
1932 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1933
1934 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1935
1936 AtaCommandBlock.AtaCommand = ATA_CMD_SET_FEATURES;
1937 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
1938 AtaCommandBlock.AtaFeatures = 0x03;
1939 AtaCommandBlock.AtaSectorCount = *((UINT8 *)TransferMode);
1940
1941 //
1942 // Send SET FEATURE command (sub command 0x03) to set pio mode.
1943 //
1944 Status = AtaNonDataCommandIn (
1945 Instance->PciIo,
1946 &Instance->IdeRegisters[Channel],
1947 &AtaCommandBlock,
1948 AtaStatusBlock,
1949 ATA_ATAPI_TIMEOUT,
1950 NULL
1951 );
1952
1953 return Status;
1954 }
1955
1956 /**
1957 Set drive parameters for devices not support PACKETS command.
1958
1959 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
1960 @param Channel The channel number of device.
1961 @param Device The device number of device.
1962 @param DriveParameters A pointer to EFI_ATA_DRIVE_PARMS data structure.
1963 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1964
1965 @retval EFI_SUCCESS Set drive parameter successfully.
1966 @retval EFI_DEVICE_ERROR Set drive parameter failed.
1967 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
1968
1969 **/
1970 EFI_STATUS
1971 EFIAPI
1972 SetDriveParameters (
1973 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
1974 IN UINT8 Channel,
1975 IN UINT8 Device,
1976 IN EFI_ATA_DRIVE_PARMS *DriveParameters,
1977 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
1978 )
1979 {
1980 EFI_STATUS Status;
1981 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1982
1983 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1984
1985 AtaCommandBlock.AtaCommand = ATA_CMD_INIT_DRIVE_PARAM;
1986 AtaCommandBlock.AtaSectorCount = DriveParameters->Sector;
1987 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) + DriveParameters->Heads);
1988
1989 //
1990 // Send Init drive parameters
1991 //
1992 Status = AtaNonDataCommandIn (
1993 Instance->PciIo,
1994 &Instance->IdeRegisters[Channel],
1995 &AtaCommandBlock,
1996 AtaStatusBlock,
1997 ATA_ATAPI_TIMEOUT,
1998 NULL
1999 );
2000
2001 //
2002 // Send Set Multiple parameters
2003 //
2004 AtaCommandBlock.AtaCommand = ATA_CMD_SET_MULTIPLE_MODE;
2005 AtaCommandBlock.AtaSectorCount = DriveParameters->MultipleSector;
2006 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
2007
2008 Status = AtaNonDataCommandIn (
2009 Instance->PciIo,
2010 &Instance->IdeRegisters[Channel],
2011 &AtaCommandBlock,
2012 AtaStatusBlock,
2013 ATA_ATAPI_TIMEOUT,
2014 NULL
2015 );
2016
2017 return Status;
2018 }
2019
2020 /**
2021 Send SMART Return Status command to check if the execution of SMART cmd is successful or not.
2022
2023 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2024 @param Channel The channel number of device.
2025 @param Device The device number of device.
2026 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2027
2028 @retval EFI_SUCCESS Successfully get the return status of S.M.A.R.T command execution.
2029 @retval Others Fail to get return status data.
2030
2031 **/
2032 EFI_STATUS
2033 EFIAPI
2034 IdeAtaSmartReturnStatusCheck (
2035 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2036 IN UINT8 Channel,
2037 IN UINT8 Device,
2038 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2039 )
2040 {
2041 EFI_STATUS Status;
2042 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2043 UINT8 LBAMid;
2044 UINT8 LBAHigh;
2045
2046 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2047
2048 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
2049 AtaCommandBlock.AtaFeatures = ATA_SMART_RETURN_STATUS;
2050 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
2051 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
2052 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);
2053
2054 //
2055 // Send S.M.A.R.T Read Return Status command to device
2056 //
2057 Status = AtaNonDataCommandIn (
2058 Instance->PciIo,
2059 &Instance->IdeRegisters[Channel],
2060 &AtaCommandBlock,
2061 AtaStatusBlock,
2062 ATA_ATAPI_TIMEOUT,
2063 NULL
2064 );
2065
2066 if (EFI_ERROR (Status)) {
2067 REPORT_STATUS_CODE (
2068 EFI_ERROR_CODE | EFI_ERROR_MINOR,
2069 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLED)
2070 );
2071 return EFI_DEVICE_ERROR;
2072 }
2073
2074 REPORT_STATUS_CODE (
2075 EFI_PROGRESS_CODE,
2076 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_ENABLE)
2077 );
2078
2079 LBAMid = IdeReadPortB (Instance->PciIo, Instance->IdeRegisters[Channel].CylinderLsb);
2080 LBAHigh = IdeReadPortB (Instance->PciIo, Instance->IdeRegisters[Channel].CylinderMsb);
2081
2082 if ((LBAMid == 0x4f) && (LBAHigh == 0xc2)) {
2083 //
2084 // The threshold exceeded condition is not detected by the device
2085 //
2086 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));
2087 REPORT_STATUS_CODE (
2088 EFI_PROGRESS_CODE,
2089 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)
2090 );
2091 } else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {
2092 //
2093 // The threshold exceeded condition is detected by the device
2094 //
2095 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));
2096 REPORT_STATUS_CODE (
2097 EFI_PROGRESS_CODE,
2098 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)
2099 );
2100 }
2101
2102 return EFI_SUCCESS;
2103 }
2104
2105 /**
2106 Enable SMART command of the disk if supported.
2107
2108 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2109 @param Channel The channel number of device.
2110 @param Device The device number of device.
2111 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
2112 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2113
2114 **/
2115 VOID
2116 EFIAPI
2117 IdeAtaSmartSupport (
2118 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2119 IN UINT8 Channel,
2120 IN UINT8 Device,
2121 IN EFI_IDENTIFY_DATA *IdentifyData,
2122 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2123 )
2124 {
2125 EFI_STATUS Status;
2126 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2127
2128 //
2129 // Detect if the device supports S.M.A.R.T.
2130 //
2131 if ((IdentifyData->AtaData.command_set_supported_82 & 0x0001) != 0x0001) {
2132 //
2133 // S.M.A.R.T is not supported by the device
2134 //
2135 DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at [%a] channel [%a] device!\n",
2136 (Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));
2137 REPORT_STATUS_CODE (
2138 EFI_ERROR_CODE | EFI_ERROR_MINOR,
2139 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED)
2140 );
2141 } else {
2142 //
2143 // Check if the feature is enabled. If not, then enable S.M.A.R.T.
2144 //
2145 if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {
2146
2147 REPORT_STATUS_CODE (
2148 EFI_PROGRESS_CODE,
2149 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLE)
2150 );
2151
2152 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2153
2154 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
2155 AtaCommandBlock.AtaFeatures = ATA_SMART_ENABLE_OPERATION;
2156 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
2157 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
2158 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);
2159
2160 //
2161 // Send S.M.A.R.T Enable command to device
2162 //
2163 Status = AtaNonDataCommandIn (
2164 Instance->PciIo,
2165 &Instance->IdeRegisters[Channel],
2166 &AtaCommandBlock,
2167 AtaStatusBlock,
2168 ATA_ATAPI_TIMEOUT,
2169 NULL
2170 );
2171
2172 if (!EFI_ERROR (Status)) {
2173 //
2174 // Send S.M.A.R.T AutoSave command to device
2175 //
2176 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2177
2178 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
2179 AtaCommandBlock.AtaFeatures = 0xD2;
2180 AtaCommandBlock.AtaSectorCount = 0xF1;
2181 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
2182 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
2183 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);
2184
2185 Status = AtaNonDataCommandIn (
2186 Instance->PciIo,
2187 &Instance->IdeRegisters[Channel],
2188 &AtaCommandBlock,
2189 AtaStatusBlock,
2190 ATA_ATAPI_TIMEOUT,
2191 NULL
2192 );
2193 if (!EFI_ERROR (Status)) {
2194 Status = IdeAtaSmartReturnStatusCheck (
2195 Instance,
2196 Channel,
2197 Device,
2198 AtaStatusBlock
2199 );
2200 }
2201 }
2202 }
2203
2204 DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at [%a] channel [%a] device!\n",
2205 (Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));
2206
2207 }
2208
2209 return ;
2210 }
2211
2212
2213 /**
2214 Sends out an ATA Identify Command to the specified device.
2215
2216 This function is called by DiscoverIdeDevice() during its device
2217 identification. It sends out the ATA Identify Command to the
2218 specified device. Only ATA device responses to this command. If
2219 the command succeeds, it returns the Identify data structure which
2220 contains information about the device. This function extracts the
2221 information it needs to fill the IDE_BLK_IO_DEV data structure,
2222 including device type, media block size, media capacity, and etc.
2223
2224 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2225 @param Channel The channel number of device.
2226 @param Device The device number of device.
2227 @param Buffer A pointer to data buffer which is used to contain IDENTIFY data.
2228 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2229
2230 @retval EFI_SUCCESS Identify ATA device successfully.
2231 @retval EFI_DEVICE_ERROR ATA Identify Device Command failed or device is not ATA device.
2232 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
2233
2234 **/
2235 EFI_STATUS
2236 EFIAPI
2237 AtaIdentify (
2238 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2239 IN UINT8 Channel,
2240 IN UINT8 Device,
2241 IN OUT EFI_IDENTIFY_DATA *Buffer,
2242 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2243 )
2244 {
2245 EFI_STATUS Status;
2246 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2247
2248 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2249
2250 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DRIVE;
2251 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
2252
2253 Status = AtaPioDataInOut (
2254 Instance->PciIo,
2255 &Instance->IdeRegisters[Channel],
2256 Buffer,
2257 sizeof (EFI_IDENTIFY_DATA),
2258 TRUE,
2259 &AtaCommandBlock,
2260 AtaStatusBlock,
2261 ATA_ATAPI_TIMEOUT,
2262 NULL
2263 );
2264
2265 return Status;
2266 }
2267
2268 /**
2269 This function is called by DiscoverIdeDevice() during its device
2270 identification.
2271 Its main purpose is to get enough information for the device media
2272 to fill in the Media data structure of the Block I/O Protocol interface.
2273
2274 There are 5 steps to reach such objective:
2275 1. Sends out the ATAPI Identify Command to the specified device.
2276 Only ATAPI device responses to this command. If the command succeeds,
2277 it returns the Identify data structure which filled with information
2278 about the device. Since the ATAPI device contains removable media,
2279 the only meaningful information is the device module name.
2280 2. Sends out ATAPI Inquiry Packet Command to the specified device.
2281 This command will return inquiry data of the device, which contains
2282 the device type information.
2283 3. Allocate sense data space for future use. We don't detect the media
2284 presence here to improvement boot performance, especially when CD
2285 media is present. The media detection will be performed just before
2286 each BLK_IO read/write
2287
2288 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2289 @param Channel The channel number of device.
2290 @param Device The device number of device.
2291 @param Buffer A pointer to data buffer which is used to contain IDENTIFY data.
2292 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2293
2294 @retval EFI_SUCCESS Identify ATAPI device successfully.
2295 @retval EFI_DEVICE_ERROR ATA Identify Packet Device Command failed or device type
2296 is not supported by this IDE driver.
2297 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
2298
2299 **/
2300 EFI_STATUS
2301 EFIAPI
2302 AtaIdentifyPacket (
2303 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2304 IN UINT8 Channel,
2305 IN UINT8 Device,
2306 IN OUT EFI_IDENTIFY_DATA *Buffer,
2307 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2308 )
2309 {
2310 EFI_STATUS Status;
2311 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2312
2313 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2314
2315 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DEVICE;
2316 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
2317
2318 //
2319 // Send ATAPI Identify Command to get IDENTIFY data.
2320 //
2321 Status = AtaPioDataInOut (
2322 Instance->PciIo,
2323 &Instance->IdeRegisters[Channel],
2324 (VOID *) Buffer,
2325 sizeof (EFI_IDENTIFY_DATA),
2326 TRUE,
2327 &AtaCommandBlock,
2328 AtaStatusBlock,
2329 ATA_ATAPI_TIMEOUT,
2330 NULL
2331 );
2332
2333 return Status;
2334 }
2335
2336
2337 /**
2338 This function is used for detect whether the IDE device exists in the
2339 specified Channel as the specified Device Number.
2340
2341 There is two IDE channels: one is Primary Channel, the other is
2342 Secondary Channel.(Channel is the logical name for the physical "Cable".)
2343 Different channel has different register group.
2344
2345 On each IDE channel, at most two IDE devices attach,
2346 one is called Device 0 (Master device), the other is called Device 1
2347 (Slave device). The devices on the same channel co-use the same register
2348 group, so before sending out a command for a specified device via command
2349 register, it is a must to select the current device to accept the command
2350 by set the device number in the Head/Device Register.
2351
2352 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2353 @param IdeChannel The channel number of device.
2354
2355 @retval EFI_SUCCESS successfully detects device.
2356 @retval other any failure during detection process will return this value.
2357
2358 **/
2359 EFI_STATUS
2360 EFIAPI
2361 DetectAndConfigIdeDevice (
2362 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2363 IN UINT8 IdeChannel
2364 )
2365 {
2366 EFI_STATUS Status;
2367 UINT8 SectorCountReg;
2368 UINT8 LBALowReg;
2369 UINT8 LBAMidReg;
2370 UINT8 LBAHighReg;
2371 EFI_ATA_DEVICE_TYPE DeviceType;
2372 UINT8 IdeDevice;
2373 EFI_IDE_REGISTERS *IdeRegisters;
2374 EFI_IDENTIFY_DATA Buffer;
2375
2376 EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
2377 EFI_PCI_IO_PROTOCOL *PciIo;
2378
2379 EFI_ATA_COLLECTIVE_MODE *SupportedModes;
2380 EFI_ATA_TRANSFER_MODE TransferMode;
2381 EFI_ATA_DRIVE_PARMS DriveParameters;
2382
2383 IdeRegisters = &Instance->IdeRegisters[IdeChannel];
2384 IdeInit = Instance->IdeControllerInit;
2385 PciIo = Instance->PciIo;
2386
2387 for (IdeDevice = 0; IdeDevice < EfiIdeMaxDevice; IdeDevice++) {
2388 //
2389 // Select Master or Slave device to get the return signature for ATA DEVICE DIAGNOSTIC cmd.
2390 //
2391 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)((IdeDevice << 4) | 0xe0));
2392
2393 //
2394 // Send ATA Device Execut Diagnostic command.
2395 // This command should work no matter DRDY is ready or not
2396 //
2397 IdeWritePortB (PciIo, IdeRegisters->CmdOrStatus, ATA_CMD_EXEC_DRIVE_DIAG);
2398
2399 Status = WaitForBSYClear (PciIo, IdeRegisters, 350000000);
2400 if (EFI_ERROR (Status)) {
2401 DEBUG((EFI_D_ERROR, "New detecting method: Send Execute Diagnostic Command: WaitForBSYClear: Status: %d\n", Status));
2402 continue;
2403 }
2404
2405 //
2406 // Select Master or Slave device to get the return signature for ATA DEVICE DIAGNOSTIC cmd.
2407 //
2408 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)((IdeDevice << 4) | 0xe0));
2409 //
2410 // Stall for 1 milliseconds.
2411 //
2412 MicroSecondDelay (1000);
2413
2414 SectorCountReg = IdeReadPortB (PciIo, IdeRegisters->SectorCount);
2415 LBALowReg = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);
2416 LBAMidReg = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
2417 LBAHighReg = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);
2418
2419 //
2420 // Refer to ATA/ATAPI 4 Spec, section 9.1
2421 //
2422 if ((SectorCountReg == 0x1) && (LBALowReg == 0x1) && (LBAMidReg == 0x0) && (LBAHighReg == 0x0)) {
2423 DeviceType = EfiIdeHarddisk;
2424 } else if ((LBAMidReg == 0x14) && (LBAHighReg == 0xeb)) {
2425 DeviceType = EfiIdeCdrom;
2426 } else {
2427 continue;
2428 }
2429
2430 //
2431 // Send IDENTIFY cmd to the device to test if it is really attached.
2432 //
2433 if (DeviceType == EfiIdeHarddisk) {
2434 Status = AtaIdentify (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
2435 //
2436 // if identifying ata device is failure, then try to send identify packet cmd.
2437 //
2438 if (EFI_ERROR (Status)) {
2439 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED));
2440
2441 DeviceType = EfiIdeCdrom;
2442 Status = AtaIdentifyPacket (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
2443 }
2444 } else {
2445 Status = AtaIdentifyPacket (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
2446 //
2447 // if identifying atapi device is failure, then try to send identify cmd.
2448 //
2449 if (EFI_ERROR (Status)) {
2450 DeviceType = EfiIdeHarddisk;
2451 Status = AtaIdentify (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
2452 }
2453 }
2454
2455 if (EFI_ERROR (Status)) {
2456 //
2457 // No device is found at this port
2458 //
2459 continue;
2460 }
2461
2462 DEBUG ((EFI_D_INFO, "[%a] channel [%a] [%a] device\n",
2463 (IdeChannel == 1) ? "secondary" : "primary ", (IdeDevice == 1) ? "slave " : "master",
2464 DeviceType == EfiIdeCdrom ? "cdrom " : "harddisk"));
2465 //
2466 // If the device is a hard disk, then try to enable S.M.A.R.T feature
2467 //
2468 if ((DeviceType == EfiIdeHarddisk) && PcdGetBool (PcdAtaSmartEnable)) {
2469 IdeAtaSmartSupport (
2470 Instance,
2471 IdeChannel,
2472 IdeDevice,
2473 &Buffer,
2474 NULL
2475 );
2476 }
2477
2478 //
2479 // Submit identify data to IDE controller init driver
2480 //
2481 IdeInit->SubmitData (IdeInit, IdeChannel, IdeDevice, &Buffer);
2482
2483 //
2484 // Now start to config ide device parameter and transfer mode.
2485 //
2486 Status = IdeInit->CalculateMode (
2487 IdeInit,
2488 IdeChannel,
2489 IdeDevice,
2490 &SupportedModes
2491 );
2492 if (EFI_ERROR (Status)) {
2493 DEBUG ((EFI_D_ERROR, "Calculate Mode Fail, Status = %r\n", Status));
2494 continue;
2495 }
2496
2497 //
2498 // Set best supported PIO mode on this IDE device
2499 //
2500 if (SupportedModes->PioMode.Mode <= EfiAtaPioMode2) {
2501 TransferMode.ModeCategory = EFI_ATA_MODE_DEFAULT_PIO;
2502 } else {
2503 TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;
2504 }
2505
2506 TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);
2507
2508 if (SupportedModes->ExtModeCount == 0){
2509 Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);
2510
2511 if (EFI_ERROR (Status)) {
2512 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
2513 continue;
2514 }
2515 }
2516
2517 //
2518 // Set supported DMA mode on this IDE device. Note that UDMA & MDMA cann't
2519 // be set together. Only one DMA mode can be set to a device. If setting
2520 // DMA mode operation fails, we can continue moving on because we only use
2521 // PIO mode at boot time. DMA modes are used by certain kind of OS booting
2522 //
2523 if (SupportedModes->UdmaMode.Valid) {
2524 TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;
2525 TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);
2526 Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);
2527
2528 if (EFI_ERROR (Status)) {
2529 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
2530 continue;
2531 }
2532 } else if (SupportedModes->MultiWordDmaMode.Valid) {
2533 TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;
2534 TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
2535 Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);
2536
2537 if (EFI_ERROR (Status)) {
2538 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
2539 continue;
2540 }
2541 }
2542
2543 //
2544 // Set Parameters for the device:
2545 // 1) Init
2546 // 2) Establish the block count for READ/WRITE MULTIPLE (EXT) command
2547 //
2548 if (DeviceType == EfiIdeHarddisk) {
2549 //
2550 // Init driver parameters
2551 //
2552 DriveParameters.Sector = (UINT8) ((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->sectors_per_track;
2553 DriveParameters.Heads = (UINT8) (((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->heads - 1);
2554 DriveParameters.MultipleSector = (UINT8) ((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->multi_sector_cmd_max_sct_cnt;
2555
2556 Status = SetDriveParameters (Instance, IdeChannel, IdeDevice, &DriveParameters, NULL);
2557 }
2558
2559 //
2560 // Set IDE controller Timing Blocks in the PCI Configuration Space
2561 //
2562 IdeInit->SetTiming (IdeInit, IdeChannel, IdeDevice, SupportedModes);
2563
2564 //
2565 // IDE controller and IDE device timing is configured successfully.
2566 // Now insert the device into device list.
2567 //
2568 Status = CreateNewDeviceInfo (Instance, IdeChannel, IdeDevice, DeviceType, &Buffer);
2569 if (EFI_ERROR (Status)) {
2570 continue;
2571 }
2572
2573 if (DeviceType == EfiIdeHarddisk) {
2574 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));
2575 }
2576 }
2577 return EFI_SUCCESS;
2578 }
2579
2580
2581 /**
2582 Initialize ATA host controller at IDE mode.
2583
2584 The function is designed to initialize ATA host controller.
2585
2586 @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
2587
2588 **/
2589 EFI_STATUS
2590 EFIAPI
2591 IdeModeInitialization (
2592 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance
2593 )
2594 {
2595 EFI_STATUS Status;
2596 EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
2597 EFI_PCI_IO_PROTOCOL *PciIo;
2598 UINT8 Channel;
2599 UINT8 IdeChannel;
2600 BOOLEAN ChannelEnabled;
2601 UINT8 MaxDevices;
2602
2603 IdeInit = Instance->IdeControllerInit;
2604 PciIo = Instance->PciIo;
2605 Channel = IdeInit->ChannelCount;
2606
2607 //
2608 // Obtain IDE IO port registers' base addresses
2609 //
2610 Status = GetIdeRegisterIoAddr (PciIo, Instance->IdeRegisters);
2611 if (EFI_ERROR (Status)) {
2612 goto ErrorExit;
2613 }
2614
2615 for (IdeChannel = 0; IdeChannel < Channel; IdeChannel++) {
2616 IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, IdeChannel);
2617
2618 //
2619 // now obtain channel information fron IdeControllerInit protocol.
2620 //
2621 Status = IdeInit->GetChannelInfo (
2622 IdeInit,
2623 IdeChannel,
2624 &ChannelEnabled,
2625 &MaxDevices
2626 );
2627 if (EFI_ERROR (Status)) {
2628 DEBUG ((EFI_D_ERROR, "[GetChannel, Status=%x]", Status));
2629 continue;
2630 }
2631
2632 if (!ChannelEnabled) {
2633 continue;
2634 }
2635
2636 ASSERT (MaxDevices <= 2);
2637 //
2638 // Now inform the IDE Controller Init Module.
2639 //
2640 IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelReset, IdeChannel);
2641
2642 //
2643 // No reset channel function implemented.
2644 //
2645 IdeInit->NotifyPhase (IdeInit, EfiIdeAfterChannelReset, IdeChannel);
2646
2647 //
2648 // Now inform the IDE Controller Init Module.
2649 //
2650 IdeInit->NotifyPhase (IdeInit, EfiIdeBusBeforeDevicePresenceDetection, IdeChannel);
2651
2652 //
2653 // Detect all attached ATA devices and set the transfer mode for each device.
2654 //
2655 DetectAndConfigIdeDevice (Instance, IdeChannel);
2656 }
2657
2658 //
2659 // All configurations done! Notify IdeController to do post initialization
2660 // work such as saving IDE controller PCI settings for S3 resume
2661 //
2662 IdeInit->NotifyPhase (IdeInit, EfiIdeBusPhaseMaximum, 0);
2663
2664 ErrorExit:
2665 return Status;
2666 }
2667
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