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[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AtaAtapiPassThru / IdeMode.c
1 /** @file
2 Header file for AHCI mode of ATA host controller.
3
4 Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "AtaAtapiPassThru.h"
16
17 /**
18 read a one-byte data from a IDE port.
19
20 @param PciIo The PCI IO protocol instance
21 @param Port The IDE Port number
22
23 @return the one-byte data read from IDE port
24 **/
25 UINT8
26 EFIAPI
27 IdeReadPortB (
28 IN EFI_PCI_IO_PROTOCOL *PciIo,
29 IN UINT16 Port
30 )
31 {
32 UINT8 Data;
33
34 ASSERT (PciIo != NULL);
35
36 Data = 0;
37 //
38 // perform 1-byte data read from register
39 //
40 PciIo->Io.Read (
41 PciIo,
42 EfiPciIoWidthUint8,
43 EFI_PCI_IO_PASS_THROUGH_BAR,
44 (UINT64) Port,
45 1,
46 &Data
47 );
48 return Data;
49 }
50
51 /**
52 write a 1-byte data to a specific IDE port.
53
54 @param PciIo The PCI IO protocol instance
55 @param Port The IDE port to be writen
56 @param Data The data to write to the port
57 **/
58 VOID
59 EFIAPI
60 IdeWritePortB (
61 IN EFI_PCI_IO_PROTOCOL *PciIo,
62 IN UINT16 Port,
63 IN UINT8 Data
64 )
65 {
66 ASSERT (PciIo != NULL);
67
68 //
69 // perform 1-byte data write to register
70 //
71 PciIo->Io.Write (
72 PciIo,
73 EfiPciIoWidthUint8,
74 EFI_PCI_IO_PASS_THROUGH_BAR,
75 (UINT64) Port,
76 1,
77 &Data
78 );
79 }
80
81 /**
82 write a 1-word data to a specific IDE port.
83
84 @param PciIo PCI IO protocol instance
85 @param Port The IDE port to be writen
86 @param Data The data to write to the port
87 **/
88 VOID
89 EFIAPI
90 IdeWritePortW (
91 IN EFI_PCI_IO_PROTOCOL *PciIo,
92 IN UINT16 Port,
93 IN UINT16 Data
94 )
95 {
96 ASSERT (PciIo != NULL);
97
98 //
99 // perform 1-word data write to register
100 //
101 PciIo->Io.Write (
102 PciIo,
103 EfiPciIoWidthUint16,
104 EFI_PCI_IO_PASS_THROUGH_BAR,
105 (UINT64) Port,
106 1,
107 &Data
108 );
109 }
110
111 /**
112 write a 2-word data to a specific IDE port.
113
114 @param PciIo PCI IO protocol instance
115 @param Port The IDE port to be writen
116 @param Data The data to write to the port
117 **/
118 VOID
119 EFIAPI
120 IdeWritePortDW (
121 IN EFI_PCI_IO_PROTOCOL *PciIo,
122 IN UINT16 Port,
123 IN UINT32 Data
124 )
125 {
126 ASSERT (PciIo != NULL);
127
128 //
129 // perform 2-word data write to register
130 //
131 PciIo->Io.Write (
132 PciIo,
133 EfiPciIoWidthUint32,
134 EFI_PCI_IO_PASS_THROUGH_BAR,
135 (UINT64) Port,
136 1,
137 &Data
138 );
139 }
140
141 /**
142 Write multiple words of data to the IDE data port.
143 Call the IO abstraction once to do the complete read,
144 not one word at a time
145
146 @param PciIo Pointer to the EFI_PCI_IO instance
147 @param Port IO port to read
148 @param Count No. of UINT16's to read
149 @param Buffer Pointer to the data buffer for read
150
151 **/
152 VOID
153 EFIAPI
154 IdeWritePortWMultiple (
155 IN EFI_PCI_IO_PROTOCOL *PciIo,
156 IN UINT16 Port,
157 IN UINTN Count,
158 IN VOID *Buffer
159 )
160 {
161 ASSERT (PciIo != NULL);
162 ASSERT (Buffer != NULL);
163
164 //
165 // perform UINT16 data write to the FIFO
166 //
167 PciIo->Io.Write (
168 PciIo,
169 EfiPciIoWidthFifoUint16,
170 EFI_PCI_IO_PASS_THROUGH_BAR,
171 (UINT64) Port,
172 Count,
173 (UINT16 *) Buffer
174 );
175
176 }
177
178 /**
179 Reads multiple words of data from the IDE data port.
180 Call the IO abstraction once to do the complete read,
181 not one word at a time
182
183 @param PciIo Pointer to the EFI_PCI_IO instance
184 @param Port IO port to read
185 @param Count Number of UINT16's to read
186 @param Buffer Pointer to the data buffer for read
187
188 **/
189 VOID
190 EFIAPI
191 IdeReadPortWMultiple (
192 IN EFI_PCI_IO_PROTOCOL *PciIo,
193 IN UINT16 Port,
194 IN UINTN Count,
195 IN VOID *Buffer
196 )
197 {
198 ASSERT (PciIo != NULL);
199 ASSERT (Buffer != NULL);
200
201 //
202 // Perform UINT16 data read from FIFO
203 //
204 PciIo->Io.Read (
205 PciIo,
206 EfiPciIoWidthFifoUint16,
207 EFI_PCI_IO_PASS_THROUGH_BAR,
208 (UINT64) Port,
209 Count,
210 (UINT16 *) Buffer
211 );
212
213 }
214
215 /**
216 This function is used to analyze the Status Register and print out
217 some debug information and if there is ERR bit set in the Status
218 Register, the Error Register's value is also be parsed and print out.
219
220 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
221 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
222 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
223
224 **/
225 VOID
226 EFIAPI
227 DumpAllIdeRegisters (
228 IN EFI_PCI_IO_PROTOCOL *PciIo,
229 IN EFI_IDE_REGISTERS *IdeRegisters,
230 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
231 )
232 {
233 EFI_ATA_STATUS_BLOCK StatusBlock;
234
235 ASSERT (PciIo != NULL);
236 ASSERT (IdeRegisters != NULL);
237
238 ZeroMem (&StatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
239
240 StatusBlock.AtaStatus = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
241 StatusBlock.AtaError = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
242 StatusBlock.AtaSectorCount = IdeReadPortB (PciIo, IdeRegisters->SectorCount);
243 StatusBlock.AtaSectorCountExp = IdeReadPortB (PciIo, IdeRegisters->SectorCount);
244 StatusBlock.AtaSectorNumber = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);
245 StatusBlock.AtaSectorNumberExp = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);
246 StatusBlock.AtaCylinderLow = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
247 StatusBlock.AtaCylinderLowExp = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
248 StatusBlock.AtaCylinderHigh = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);
249 StatusBlock.AtaCylinderHighExp = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);
250 StatusBlock.AtaDeviceHead = IdeReadPortB (PciIo, IdeRegisters->Head);
251
252 if (AtaStatusBlock != NULL) {
253 //
254 // Dump the content of all ATA registers.
255 //
256 CopyMem (AtaStatusBlock, &StatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
257 }
258
259 DEBUG_CODE_BEGIN ();
260 if ((StatusBlock.AtaStatus & ATA_STSREG_DWF) != 0) {
261 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Write Fault\n", StatusBlock.AtaStatus));
262 }
263
264 if ((StatusBlock.AtaStatus & ATA_STSREG_CORR) != 0) {
265 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Corrected Data\n", StatusBlock.AtaStatus));
266 }
267
268 if ((StatusBlock.AtaStatus & ATA_STSREG_ERR) != 0) {
269 if ((StatusBlock.AtaError & ATA_ERRREG_BBK) != 0) {
270 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Bad Block Detected\n", StatusBlock.AtaError));
271 }
272
273 if ((StatusBlock.AtaError & ATA_ERRREG_UNC) != 0) {
274 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Uncorrectable Data\n", StatusBlock.AtaError));
275 }
276
277 if ((StatusBlock.AtaError & ATA_ERRREG_MC) != 0) {
278 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Media Change\n", StatusBlock.AtaError));
279 }
280
281 if ((StatusBlock.AtaError & ATA_ERRREG_ABRT) != 0) {
282 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Abort\n", StatusBlock.AtaError));
283 }
284
285 if ((StatusBlock.AtaError & ATA_ERRREG_TK0NF) != 0) {
286 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Track 0 Not Found\n", StatusBlock.AtaError));
287 }
288
289 if ((StatusBlock.AtaError & ATA_ERRREG_AMNF) != 0) {
290 DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Address Mark Not Found\n", StatusBlock.AtaError));
291 }
292 }
293 DEBUG_CODE_END ();
294 }
295
296 /**
297 This function is used to analyze the Status Register and print out
298 some debug information and if there is ERR bit set in the Status
299 Register, the Error Register's value is also be parsed and print out.
300
301 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
302 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
303
304 @retval EFI_SUCCESS No err information in the Status Register.
305 @retval EFI_DEVICE_ERROR Any err information in the Status Register.
306
307 **/
308 EFI_STATUS
309 EFIAPI
310 CheckStatusRegister (
311 IN EFI_PCI_IO_PROTOCOL *PciIo,
312 IN EFI_IDE_REGISTERS *IdeRegisters
313 )
314 {
315 EFI_STATUS Status;
316 UINT8 StatusRegister;
317
318 ASSERT (PciIo != NULL);
319 ASSERT (IdeRegisters != NULL);
320
321 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
322
323 if ((StatusRegister & (ATA_STSREG_ERR | ATA_STSREG_DWF | ATA_STSREG_CORR)) == 0) {
324 Status = EFI_SUCCESS;
325 } else {
326 Status = EFI_DEVICE_ERROR;
327 }
328
329 return Status;
330 }
331
332 /**
333 This function is used to poll for the DRQ bit clear in the Status
334 Register. DRQ is cleared when the device is finished transferring data.
335 So this function is called after data transfer is finished.
336
337 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
338 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
339 @param Timeout The time to complete the command.
340
341 @retval EFI_SUCCESS DRQ bit clear within the time out.
342
343 @retval EFI_TIMEOUT DRQ bit not clear within the time out.
344
345 @note
346 Read Status Register will clear interrupt status.
347
348 **/
349 EFI_STATUS
350 EFIAPI
351 DRQClear (
352 IN EFI_PCI_IO_PROTOCOL *PciIo,
353 IN EFI_IDE_REGISTERS *IdeRegisters,
354 IN UINT64 Timeout
355 )
356 {
357 UINT32 Delay;
358 UINT8 StatusRegister;
359 UINT8 ErrorRegister;
360
361 ASSERT (PciIo != NULL);
362 ASSERT (IdeRegisters != NULL);
363
364 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
365 do {
366 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
367
368 //
369 // wait for BSY == 0 and DRQ == 0
370 //
371 if ((StatusRegister & (ATA_STSREG_DRQ | ATA_STSREG_BSY)) == 0) {
372 break;
373 }
374
375 if ((StatusRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
376 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
377
378 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
379 return EFI_ABORTED;
380 }
381 }
382
383 //
384 // Stall for 100 microseconds.
385 //
386 MicroSecondDelay (100);
387
388 Delay--;
389
390 } while (Delay > 0);
391
392 if (Delay == 0) {
393 return EFI_TIMEOUT;
394 }
395
396 return EFI_SUCCESS;
397 }
398 /**
399 This function is used to poll for the DRQ bit clear in the Alternate
400 Status Register. DRQ is cleared when the device is finished
401 transferring data. So this function is called after data transfer
402 is finished.
403
404 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
405 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
406 @param Timeout The time to complete the command.
407
408 @retval EFI_SUCCESS DRQ bit clear within the time out.
409
410 @retval EFI_TIMEOUT DRQ bit not clear within the time out.
411 @note Read Alternate Status Register will not clear interrupt status.
412
413 **/
414 EFI_STATUS
415 EFIAPI
416 DRQClear2 (
417 IN EFI_PCI_IO_PROTOCOL *PciIo,
418 IN EFI_IDE_REGISTERS *IdeRegisters,
419 IN UINT64 Timeout
420 )
421 {
422 UINT32 Delay;
423 UINT8 AltRegister;
424 UINT8 ErrorRegister;
425
426 ASSERT (PciIo != NULL);
427 ASSERT (IdeRegisters != NULL);
428
429 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
430 do {
431 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
432
433 //
434 // wait for BSY == 0 and DRQ == 0
435 //
436 if ((AltRegister & (ATA_STSREG_DRQ | ATA_STSREG_BSY)) == 0) {
437 break;
438 }
439
440 if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
441 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
442
443 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
444 return EFI_ABORTED;
445 }
446 }
447
448 //
449 // Stall for 100 microseconds.
450 //
451 MicroSecondDelay (100);
452
453 Delay--;
454
455 } while (Delay > 0);
456
457 if (Delay == 0) {
458 return EFI_TIMEOUT;
459 }
460
461 return EFI_SUCCESS;
462 }
463
464 /**
465 This function is used to poll for the DRQ bit set in the
466 Status Register.
467 DRQ is set when the device is ready to transfer data. So this function
468 is called after the command is sent to the device and before required
469 data is transferred.
470
471 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
472 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
473 @param Timeout The time to complete the command.
474
475 @retval EFI_SUCCESS DRQ bit set within the time out.
476 @retval EFI_TIMEOUT DRQ bit not set within the time out.
477 @retval EFI_ABORTED DRQ bit not set caused by the command abort.
478
479 @note Read Status Register will clear interrupt status.
480
481 **/
482 EFI_STATUS
483 EFIAPI
484 DRQReady (
485 IN EFI_PCI_IO_PROTOCOL *PciIo,
486 IN EFI_IDE_REGISTERS *IdeRegisters,
487 IN UINT64 Timeout
488 )
489 {
490 UINT32 Delay;
491 UINT8 StatusRegister;
492 UINT8 ErrorRegister;
493
494 ASSERT (PciIo != NULL);
495 ASSERT (IdeRegisters != NULL);
496
497 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
498 do {
499 //
500 // read Status Register will clear interrupt
501 //
502 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
503
504 //
505 // BSY==0,DRQ==1
506 //
507 if ((StatusRegister & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
508 break;
509 }
510
511 if ((StatusRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
512 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
513
514 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
515 return EFI_ABORTED;
516 }
517 }
518
519 //
520 // Stall for 100 microseconds.
521 //
522 MicroSecondDelay (100);
523
524 Delay--;
525 } while (Delay > 0);
526
527 if (Delay == 0) {
528 return EFI_TIMEOUT;
529 }
530
531 return EFI_SUCCESS;
532 }
533 /**
534 This function is used to poll for the DRQ bit set in the Alternate Status Register.
535 DRQ is set when the device is ready to transfer data. So this function is called after
536 the command is sent to the device and before required data is transferred.
537
538 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
539 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
540 @param Timeout The time to complete the command.
541
542 @retval EFI_SUCCESS DRQ bit set within the time out.
543 @retval EFI_TIMEOUT DRQ bit not set within the time out.
544 @retval EFI_ABORTED DRQ bit not set caused by the command abort.
545 @note Read Alternate Status Register will not clear interrupt status.
546
547 **/
548 EFI_STATUS
549 EFIAPI
550 DRQReady2 (
551 IN EFI_PCI_IO_PROTOCOL *PciIo,
552 IN EFI_IDE_REGISTERS *IdeRegisters,
553 IN UINT64 Timeout
554 )
555 {
556 UINT32 Delay;
557 UINT8 AltRegister;
558 UINT8 ErrorRegister;
559
560 ASSERT (PciIo != NULL);
561 ASSERT (IdeRegisters != NULL);
562
563 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
564
565 do {
566 //
567 // Read Alternate Status Register will not clear interrupt status
568 //
569 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
570 //
571 // BSY == 0 , DRQ == 1
572 //
573 if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
574 break;
575 }
576
577 if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
578 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
579
580 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
581 return EFI_ABORTED;
582 }
583 }
584
585 //
586 // Stall for 100 microseconds.
587 //
588 MicroSecondDelay (100);
589
590 Delay--;
591 } while (Delay > 0);
592
593 if (Delay == 0) {
594 return EFI_TIMEOUT;
595 }
596
597 return EFI_SUCCESS;
598 }
599
600 /**
601 This function is used to poll for the DRDY bit set in the Status Register. DRDY
602 bit is set when the device is ready to accept command. Most ATA commands must be
603 sent after DRDY set except the ATAPI Packet Command.
604
605 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
606 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
607 @param Timeout The time to complete the command.
608
609 @retval EFI_SUCCESS DRDY bit set within the time out.
610 @retval EFI_TIMEOUT DRDY bit not set within the time out.
611
612 @note Read Status Register will clear interrupt status.
613 **/
614 EFI_STATUS
615 EFIAPI
616 DRDYReady (
617 IN EFI_PCI_IO_PROTOCOL *PciIo,
618 IN EFI_IDE_REGISTERS *IdeRegisters,
619 IN UINT64 Timeout
620 )
621 {
622 UINT32 Delay;
623 UINT8 StatusRegister;
624 UINT8 ErrorRegister;
625
626 ASSERT (PciIo != NULL);
627 ASSERT (IdeRegisters != NULL);
628
629 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
630 do {
631 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
632 //
633 // BSY == 0 , DRDY == 1
634 //
635 if ((StatusRegister & (ATA_STSREG_DRDY | ATA_STSREG_BSY)) == ATA_STSREG_DRDY) {
636 break;
637 }
638
639 if ((StatusRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
640 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
641
642 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
643 return EFI_ABORTED;
644 }
645 }
646
647 //
648 // Stall for 100 microseconds.
649 //
650 MicroSecondDelay (100);
651
652 Delay--;
653 } while (Delay > 0);
654
655 if (Delay == 0) {
656 return EFI_TIMEOUT;
657 }
658
659 return EFI_SUCCESS;
660 }
661
662 /**
663 This function is used to poll for the DRDY bit set in the Alternate Status Register.
664 DRDY bit is set when the device is ready to accept command. Most ATA commands must
665 be sent after DRDY set except the ATAPI Packet Command.
666
667 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
668 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
669 @param Timeout The time to complete the command.
670
671 @retval EFI_SUCCESS DRDY bit set within the time out.
672 @retval EFI_TIMEOUT DRDY bit not set within the time out.
673
674 @note Read Alternate Status Register will clear interrupt status.
675
676 **/
677 EFI_STATUS
678 EFIAPI
679 DRDYReady2 (
680 IN EFI_PCI_IO_PROTOCOL *PciIo,
681 IN EFI_IDE_REGISTERS *IdeRegisters,
682 IN UINT64 Timeout
683 )
684 {
685 UINT32 Delay;
686 UINT8 AltRegister;
687 UINT8 ErrorRegister;
688
689 ASSERT (PciIo != NULL);
690 ASSERT (IdeRegisters != NULL);
691
692 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
693 do {
694 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
695 //
696 // BSY == 0 , DRDY == 1
697 //
698 if ((AltRegister & (ATA_STSREG_DRDY | ATA_STSREG_BSY)) == ATA_STSREG_DRDY) {
699 break;
700 }
701
702 if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_ERR)) == ATA_STSREG_ERR) {
703 ErrorRegister = IdeReadPortB (PciIo, IdeRegisters->ErrOrFeature);
704
705 if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
706 return EFI_ABORTED;
707 }
708 }
709
710 //
711 // Stall for 100 microseconds.
712 //
713 MicroSecondDelay (100);
714
715 Delay--;
716 } while (Delay > 0);
717
718 if (Delay == 0) {
719 return EFI_TIMEOUT;
720 }
721
722 return EFI_SUCCESS;
723 }
724
725 /**
726 This function is used to poll for the BSY bit clear in the Status Register. BSY
727 is clear when the device is not busy. Every command must be sent after device is not busy.
728
729 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
730 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
731 @param Timeout The time to complete the command.
732
733 @retval EFI_SUCCESS BSY bit clear within the time out.
734 @retval EFI_TIMEOUT BSY bit not clear within the time out.
735
736 @note Read Status Register will clear interrupt status.
737 **/
738 EFI_STATUS
739 EFIAPI
740 WaitForBSYClear (
741 IN EFI_PCI_IO_PROTOCOL *PciIo,
742 IN EFI_IDE_REGISTERS *IdeRegisters,
743 IN UINT64 Timeout
744 )
745 {
746 UINT32 Delay;
747 UINT8 StatusRegister;
748
749 ASSERT (PciIo != NULL);
750 ASSERT (IdeRegisters != NULL);
751
752 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
753 do {
754 StatusRegister = IdeReadPortB (PciIo, IdeRegisters->CmdOrStatus);
755
756 if ((StatusRegister & ATA_STSREG_BSY) == 0x00) {
757 break;
758 }
759
760 //
761 // Stall for 100 microseconds.
762 //
763 MicroSecondDelay (100);
764
765 Delay--;
766
767 } while (Delay > 0);
768
769 if (Delay == 0) {
770 return EFI_TIMEOUT;
771 }
772
773 return EFI_SUCCESS;
774 }
775
776 /**
777 This function is used to poll for the BSY bit clear in the Status Register. BSY
778 is clear when the device is not busy. Every command must be sent after device is not busy.
779
780 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
781 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
782 @param Timeout The time to complete the command.
783
784 @retval EFI_SUCCESS BSY bit clear within the time out.
785 @retval EFI_TIMEOUT BSY bit not clear within the time out.
786
787 @note Read Status Register will clear interrupt status.
788 **/
789 EFI_STATUS
790 EFIAPI
791 WaitForBSYClear2 (
792 IN EFI_PCI_IO_PROTOCOL *PciIo,
793 IN EFI_IDE_REGISTERS *IdeRegisters,
794 IN UINT64 Timeout
795 )
796 {
797 UINT32 Delay;
798 UINT8 AltStatusRegister;
799
800 ASSERT (PciIo != NULL);
801 ASSERT (IdeRegisters != NULL);
802
803 Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
804 do {
805 AltStatusRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
806
807 if ((AltStatusRegister & ATA_STSREG_BSY) == 0x00) {
808 break;
809 }
810
811 //
812 // Stall for 100 microseconds.
813 //
814 MicroSecondDelay (100);
815
816 Delay--;
817
818 } while (Delay > 0);
819
820 if (Delay == 0) {
821 return EFI_TIMEOUT;
822 }
823
824 return EFI_SUCCESS;
825 }
826
827 /**
828 Get IDE i/o port registers' base addresses by mode.
829
830 In 'Compatibility' mode, use fixed addresses.
831 In Native-PCI mode, get base addresses from BARs in the PCI IDE controller's
832 Configuration Space.
833
834 The steps to get IDE i/o port registers' base addresses for each channel
835 as follows:
836
837 1. Examine the Programming Interface byte of the Class Code fields in PCI IDE
838 controller's Configuration Space to determine the operating mode.
839
840 2. a) In 'Compatibility' mode, use fixed addresses shown in the Table 1 below.
841 ___________________________________________
842 | | Command Block | Control Block |
843 | Channel | Registers | Registers |
844 |___________|_______________|_______________|
845 | Primary | 1F0h - 1F7h | 3F6h - 3F7h |
846 |___________|_______________|_______________|
847 | Secondary | 170h - 177h | 376h - 377h |
848 |___________|_______________|_______________|
849
850 Table 1. Compatibility resource mappings
851
852 b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs
853 in IDE controller's PCI Configuration Space, shown in the Table 2 below.
854 ___________________________________________________
855 | | Command Block | Control Block |
856 | Channel | Registers | Registers |
857 |___________|___________________|___________________|
858 | Primary | BAR at offset 0x10| BAR at offset 0x14|
859 |___________|___________________|___________________|
860 | Secondary | BAR at offset 0x18| BAR at offset 0x1C|
861 |___________|___________________|___________________|
862
863 Table 2. BARs for Register Mapping
864
865 @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance
866 @param[in, out] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to
867 store the IDE i/o port registers' base addresses
868
869 @retval EFI_UNSUPPORTED Return this value when the BARs is not IO type
870 @retval EFI_SUCCESS Get the Base address successfully
871 @retval Other Read the pci configureation data error
872
873 **/
874 EFI_STATUS
875 EFIAPI
876 GetIdeRegisterIoAddr (
877 IN EFI_PCI_IO_PROTOCOL *PciIo,
878 IN OUT EFI_IDE_REGISTERS *IdeRegisters
879 )
880 {
881 EFI_STATUS Status;
882 PCI_TYPE00 PciData;
883 UINT16 CommandBlockBaseAddr;
884 UINT16 ControlBlockBaseAddr;
885 UINT16 BusMasterBaseAddr;
886
887 if ((PciIo == NULL) || (IdeRegisters == NULL)) {
888 return EFI_INVALID_PARAMETER;
889 }
890
891 Status = PciIo->Pci.Read (
892 PciIo,
893 EfiPciIoWidthUint8,
894 0,
895 sizeof (PciData),
896 &PciData
897 );
898
899 if (EFI_ERROR (Status)) {
900 return Status;
901 }
902
903 BusMasterBaseAddr = (UINT16) ((PciData.Device.Bar[4] & 0x0000fff0));
904
905 if ((PciData.Hdr.ClassCode[0] & IDE_PRIMARY_OPERATING_MODE) == 0) {
906 CommandBlockBaseAddr = 0x1f0;
907 ControlBlockBaseAddr = 0x3f6;
908 } else {
909 //
910 // The BARs should be of IO type
911 //
912 if ((PciData.Device.Bar[0] & BIT0) == 0 ||
913 (PciData.Device.Bar[1] & BIT0) == 0) {
914 return EFI_UNSUPPORTED;
915 }
916
917 CommandBlockBaseAddr = (UINT16) (PciData.Device.Bar[0] & 0x0000fff8);
918 ControlBlockBaseAddr = (UINT16) ((PciData.Device.Bar[1] & 0x0000fffc) + 2);
919 }
920
921 //
922 // Calculate IDE primary channel I/O register base address.
923 //
924 IdeRegisters[EfiIdePrimary].Data = CommandBlockBaseAddr;
925 IdeRegisters[EfiIdePrimary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);
926 IdeRegisters[EfiIdePrimary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);
927 IdeRegisters[EfiIdePrimary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);
928 IdeRegisters[EfiIdePrimary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);
929 IdeRegisters[EfiIdePrimary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);
930 IdeRegisters[EfiIdePrimary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);
931 IdeRegisters[EfiIdePrimary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);
932 IdeRegisters[EfiIdePrimary].AltOrDev = ControlBlockBaseAddr;
933 IdeRegisters[EfiIdePrimary].BusMasterBaseAddr = BusMasterBaseAddr;
934
935 if ((PciData.Hdr.ClassCode[0] & IDE_SECONDARY_OPERATING_MODE) == 0) {
936 CommandBlockBaseAddr = 0x170;
937 ControlBlockBaseAddr = 0x376;
938 } else {
939 //
940 // The BARs should be of IO type
941 //
942 if ((PciData.Device.Bar[2] & BIT0) == 0 ||
943 (PciData.Device.Bar[3] & BIT0) == 0) {
944 return EFI_UNSUPPORTED;
945 }
946
947 CommandBlockBaseAddr = (UINT16) (PciData.Device.Bar[2] & 0x0000fff8);
948 ControlBlockBaseAddr = (UINT16) ((PciData.Device.Bar[3] & 0x0000fffc) + 2);
949 }
950
951 //
952 // Calculate IDE secondary channel I/O register base address.
953 //
954 IdeRegisters[EfiIdeSecondary].Data = CommandBlockBaseAddr;
955 IdeRegisters[EfiIdeSecondary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);
956 IdeRegisters[EfiIdeSecondary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);
957 IdeRegisters[EfiIdeSecondary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);
958 IdeRegisters[EfiIdeSecondary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);
959 IdeRegisters[EfiIdeSecondary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);
960 IdeRegisters[EfiIdeSecondary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);
961 IdeRegisters[EfiIdeSecondary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);
962 IdeRegisters[EfiIdeSecondary].AltOrDev = ControlBlockBaseAddr;
963 IdeRegisters[EfiIdeSecondary].BusMasterBaseAddr = (UINT16) (BusMasterBaseAddr + 0x8);
964
965 return EFI_SUCCESS;
966 }
967
968 /**
969 This function is used to implement the Soft Reset on the specified device. But,
970 the ATA Soft Reset mechanism is so strong a reset method that it will force
971 resetting on both devices connected to the same cable.
972
973 It is called by IdeBlkIoReset(), a interface function of Block
974 I/O protocol.
975
976 This function can also be used by the ATAPI device to perform reset when
977 ATAPI Reset command is failed.
978
979 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
980 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
981 @param Timeout The time to complete the command.
982
983 @retval EFI_SUCCESS Soft reset completes successfully.
984 @retval EFI_DEVICE_ERROR Any step during the reset process is failed.
985
986 @note The registers initial values after ATA soft reset are different
987 to the ATA device and ATAPI device.
988 **/
989 EFI_STATUS
990 EFIAPI
991 AtaSoftReset (
992 IN EFI_PCI_IO_PROTOCOL *PciIo,
993 IN EFI_IDE_REGISTERS *IdeRegisters,
994 IN UINT64 Timeout
995 )
996 {
997 UINT8 DeviceControl;
998
999 DeviceControl = 0;
1000 //
1001 // disable Interrupt and set SRST bit to initiate soft reset
1002 //
1003 DeviceControl = ATA_CTLREG_SRST | ATA_CTLREG_IEN_L;
1004
1005 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
1006
1007 //
1008 // SRST should assert for at least 5 us, we use 10 us for
1009 // better compatibility
1010 //
1011 MicroSecondDelay (10);
1012
1013 //
1014 // Enable interrupt to support UDMA, and clear SRST bit
1015 //
1016 DeviceControl = 0;
1017 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
1018
1019 //
1020 // Wait for at least 10 ms to check BSY status, we use 10 ms
1021 // for better compatibility
1022 //
1023 MicroSecondDelay (10000);
1024
1025 //
1026 // slave device needs at most 31ms to clear BSY
1027 //
1028 if (WaitForBSYClear (PciIo, IdeRegisters, Timeout) == EFI_TIMEOUT) {
1029 return EFI_DEVICE_ERROR;
1030 }
1031
1032 return EFI_SUCCESS;
1033 }
1034
1035 /**
1036 Send ATA Ext command into device with NON_DATA protocol.
1037
1038 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
1039 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1040 @param AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.
1041 @param Timeout The time to complete the command.
1042
1043 @retval EFI_SUCCESS Reading succeed
1044 @retval EFI_DEVICE_ERROR Error executing commands on this device.
1045
1046 **/
1047 EFI_STATUS
1048 EFIAPI
1049 AtaIssueCommand (
1050 IN EFI_PCI_IO_PROTOCOL *PciIo,
1051 IN EFI_IDE_REGISTERS *IdeRegisters,
1052 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1053 IN UINT64 Timeout
1054 )
1055 {
1056 EFI_STATUS Status;
1057 UINT8 DeviceHead;
1058 UINT8 AtaCommand;
1059
1060 ASSERT (PciIo != NULL);
1061 ASSERT (IdeRegisters != NULL);
1062 ASSERT (AtaCommandBlock != NULL);
1063
1064 DeviceHead = AtaCommandBlock->AtaDeviceHead;
1065 AtaCommand = AtaCommandBlock->AtaCommand;
1066
1067 Status = WaitForBSYClear (PciIo, IdeRegisters, Timeout);
1068 if (EFI_ERROR (Status)) {
1069 return EFI_DEVICE_ERROR;
1070 }
1071
1072 //
1073 // Select device (bit4), set LBA mode(bit6) (use 0xe0 for compatibility)
1074 //
1075 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8) (0xe0 | DeviceHead));
1076
1077 //
1078 // set all the command parameters
1079 // Before write to all the following registers, BSY and DRQ must be 0.
1080 //
1081 Status = DRQClear2 (PciIo, IdeRegisters, Timeout);
1082 if (EFI_ERROR (Status)) {
1083 return EFI_DEVICE_ERROR;
1084 }
1085
1086 //
1087 // Fill the feature register, which is a two-byte FIFO. Need write twice.
1088 //
1089 IdeWritePortB (PciIo, IdeRegisters->ErrOrFeature, AtaCommandBlock->AtaFeaturesExp);
1090 IdeWritePortB (PciIo, IdeRegisters->ErrOrFeature, AtaCommandBlock->AtaFeatures);
1091
1092 //
1093 // Fill the sector count register, which is a two-byte FIFO. Need write twice.
1094 //
1095 IdeWritePortB (PciIo, IdeRegisters->SectorCount, AtaCommandBlock->AtaSectorCountExp);
1096 IdeWritePortB (PciIo, IdeRegisters->SectorCount, AtaCommandBlock->AtaSectorCount);
1097
1098 //
1099 // Fill the start LBA registers, which are also two-byte FIFO
1100 //
1101 IdeWritePortB (PciIo, IdeRegisters->SectorNumber, AtaCommandBlock->AtaSectorNumberExp);
1102 IdeWritePortB (PciIo, IdeRegisters->SectorNumber, AtaCommandBlock->AtaSectorNumber);
1103
1104 IdeWritePortB (PciIo, IdeRegisters->CylinderLsb, AtaCommandBlock->AtaCylinderLowExp);
1105 IdeWritePortB (PciIo, IdeRegisters->CylinderLsb, AtaCommandBlock->AtaCylinderLow);
1106
1107 IdeWritePortB (PciIo, IdeRegisters->CylinderMsb, AtaCommandBlock->AtaCylinderHighExp);
1108 IdeWritePortB (PciIo, IdeRegisters->CylinderMsb, AtaCommandBlock->AtaCylinderHigh);
1109
1110 //
1111 // Send command via Command Register
1112 //
1113 IdeWritePortB (PciIo, IdeRegisters->CmdOrStatus, AtaCommand);
1114
1115 //
1116 // Stall at least 400 microseconds.
1117 //
1118 MicroSecondDelay (400);
1119
1120 return EFI_SUCCESS;
1121 }
1122
1123 /**
1124 This function is used to send out ATA commands conforms to the PIO Data In Protocol.
1125
1126 @param[in] PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data
1127 structure.
1128 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1129 @param[in, out] Buffer A pointer to the source buffer for the data.
1130 @param[in] ByteCount The length of the data.
1131 @param[in] Read Flag used to determine the data transfer direction.
1132 Read equals 1, means data transferred from device
1133 to host;Read equals 0, means data transferred
1134 from host to device.
1135 @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.
1136 @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1137 @param[in] Timeout The time to complete the command.
1138 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1139 used by non-blocking mode.
1140
1141 @retval EFI_SUCCESS send out the ATA command and device send required data successfully.
1142 @retval EFI_DEVICE_ERROR command sent failed.
1143
1144 **/
1145 EFI_STATUS
1146 EFIAPI
1147 AtaPioDataInOut (
1148 IN EFI_PCI_IO_PROTOCOL *PciIo,
1149 IN EFI_IDE_REGISTERS *IdeRegisters,
1150 IN OUT VOID *Buffer,
1151 IN UINT64 ByteCount,
1152 IN BOOLEAN Read,
1153 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1154 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1155 IN UINT64 Timeout,
1156 IN ATA_NONBLOCK_TASK *Task
1157 )
1158 {
1159 UINTN WordCount;
1160 UINTN Increment;
1161 UINT16 *Buffer16;
1162 EFI_STATUS Status;
1163
1164 if ((PciIo == NULL) || (IdeRegisters == NULL) || (Buffer == NULL) || (AtaCommandBlock == NULL)) {
1165 return EFI_INVALID_PARAMETER;
1166 }
1167
1168 //
1169 // Issue ATA command
1170 //
1171 Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);
1172 if (EFI_ERROR (Status)) {
1173 Status = EFI_DEVICE_ERROR;
1174 goto Exit;
1175 }
1176
1177 Buffer16 = (UINT16 *) Buffer;
1178
1179 //
1180 // According to PIO data in protocol, host can perform a series of reads to
1181 // the data register after each time device set DRQ ready;
1182 // The data size of "a series of read" is command specific.
1183 // For most ATA command, data size received from device will not exceed
1184 // 1 sector, hence the data size for "a series of read" can be the whole data
1185 // size of one command request.
1186 // For ATA command such as Read Sector command, the data size of one ATA
1187 // command request is often larger than 1 sector, according to the
1188 // Read Sector command, the data size of "a series of read" is exactly 1
1189 // sector.
1190 // Here for simplification reason, we specify the data size for
1191 // "a series of read" to 1 sector (256 words) if data size of one ATA command
1192 // request is larger than 256 words.
1193 //
1194 Increment = 256;
1195
1196 //
1197 // used to record bytes of currently transfered data
1198 //
1199 WordCount = 0;
1200
1201 while (WordCount < RShiftU64(ByteCount, 1)) {
1202 //
1203 // Poll DRQ bit set, data transfer can be performed only when DRQ is ready
1204 //
1205 Status = DRQReady2 (PciIo, IdeRegisters, Timeout);
1206 if (EFI_ERROR (Status)) {
1207 Status = EFI_DEVICE_ERROR;
1208 goto Exit;
1209 }
1210
1211 //
1212 // Get the byte count for one series of read
1213 //
1214 if ((WordCount + Increment) > RShiftU64(ByteCount, 1)) {
1215 Increment = (UINTN)(RShiftU64(ByteCount, 1) - WordCount);
1216 }
1217
1218 if (Read) {
1219 IdeReadPortWMultiple (
1220 PciIo,
1221 IdeRegisters->Data,
1222 Increment,
1223 Buffer16
1224 );
1225 } else {
1226 IdeWritePortWMultiple (
1227 PciIo,
1228 IdeRegisters->Data,
1229 Increment,
1230 Buffer16
1231 );
1232 }
1233
1234 Status = CheckStatusRegister (PciIo, IdeRegisters);
1235 if (EFI_ERROR (Status)) {
1236 Status = EFI_DEVICE_ERROR;
1237 goto Exit;
1238 }
1239
1240 WordCount += Increment;
1241 Buffer16 += Increment;
1242 }
1243
1244 Status = DRQClear (PciIo, IdeRegisters, Timeout);
1245 if (EFI_ERROR (Status)) {
1246 Status = EFI_DEVICE_ERROR;
1247 goto Exit;
1248 }
1249
1250 Exit:
1251 //
1252 // Dump All Ide registers to ATA_STATUS_BLOCK
1253 //
1254 DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);
1255
1256 //
1257 // Not support the Non-blocking now,just do the blocking process.
1258 //
1259 return Status;
1260 }
1261
1262 /**
1263 Send ATA command into device with NON_DATA protocol
1264
1265 @param[in] PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE
1266 data structure.
1267 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1268 @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data
1269 structure.
1270 @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1271 @param[in] Timeout The time to complete the command.
1272 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1273 used by non-blocking mode.
1274
1275 @retval EFI_SUCCESS Reading succeed
1276 @retval EFI_ABORTED Command failed
1277 @retval EFI_DEVICE_ERROR Device status error.
1278
1279 **/
1280 EFI_STATUS
1281 EFIAPI
1282 AtaNonDataCommandIn (
1283 IN EFI_PCI_IO_PROTOCOL *PciIo,
1284 IN EFI_IDE_REGISTERS *IdeRegisters,
1285 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1286 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1287 IN UINT64 Timeout,
1288 IN ATA_NONBLOCK_TASK *Task
1289 )
1290 {
1291 EFI_STATUS Status;
1292
1293 if ((PciIo == NULL) || (IdeRegisters == NULL) || (AtaCommandBlock == NULL)) {
1294 return EFI_INVALID_PARAMETER;
1295 }
1296
1297 //
1298 // Issue ATA command
1299 //
1300 Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);
1301 if (EFI_ERROR (Status)) {
1302 Status = EFI_DEVICE_ERROR;
1303 goto Exit;
1304 }
1305
1306 //
1307 // Wait for command completion
1308 //
1309 Status = WaitForBSYClear (PciIo, IdeRegisters, Timeout);
1310 if (EFI_ERROR (Status)) {
1311 Status = EFI_DEVICE_ERROR;
1312 goto Exit;
1313 }
1314
1315 Status = CheckStatusRegister (PciIo, IdeRegisters);
1316 if (EFI_ERROR (Status)) {
1317 Status = EFI_DEVICE_ERROR;
1318 goto Exit;
1319 }
1320
1321 Exit:
1322 //
1323 // Dump All Ide registers to ATA_STATUS_BLOCK
1324 //
1325 DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);
1326
1327 //
1328 // Not support the Non-blocking now,just do the blocking process.
1329 //
1330 return Status;
1331 }
1332
1333 /**
1334 Wait for memory to be set.
1335
1336 @param[in] PciIo The PCI IO protocol instance.
1337 @param[in] PortNum The IDE Port number.
1338
1339 @retval EFI_DEVICE_ERROR The memory is not set.
1340 @retval EFI_TIMEOUT The memory setting is time out.
1341 @retval EFI_SUCCESS The memory is correct set.
1342
1343 **/
1344 EFI_STATUS
1345 AtaUdmStatusWait (
1346 IN EFI_PCI_IO_PROTOCOL *PciIo,
1347 IN UINT16 PortNum
1348 )
1349 {
1350 UINT8 RegisterValue;
1351 EFI_STATUS Status;
1352 UINT64 Timeout;
1353
1354 Timeout = 2000;
1355
1356 while (TRUE) {
1357 RegisterValue = IdeReadPortB (PciIo, PortNum);
1358
1359 if (((RegisterValue & BMIS_ERROR) != 0) || (Timeout == 0)) {
1360 DEBUG ((EFI_D_ERROR, "ATA UDMA operation fails\n"));
1361 Status = EFI_DEVICE_ERROR;
1362 break;
1363 }
1364
1365 if ((RegisterValue & BMIS_INTERRUPT) != 0) {
1366 Status = EFI_SUCCESS;
1367 break;
1368 }
1369 //
1370 // Stall for 1 milliseconds.
1371 //
1372 MicroSecondDelay (1000);
1373 Timeout--;
1374 }
1375
1376 return Status;
1377 }
1378
1379 /**
1380 Check if the memory to be set.
1381
1382 @param[in] PciIo The PCI IO protocol instance.
1383 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1384 used by non-blocking mode.
1385 @param[in] PortForBit The bit to be checked.
1386
1387 @retval EFI_DEVICE_ERROR The memory setting met a issue.
1388 @retval EFI_NOT_READY The memory is not set.
1389 @retval EFI_TIMEOUT The memory setting is time out.
1390 @retval EFI_SUCCESS The memory is correct set.
1391
1392 **/
1393 EFI_STATUS
1394 AtaUdmStatusCheck (
1395 IN EFI_PCI_IO_PROTOCOL *PciIo,
1396 IN ATA_NONBLOCK_TASK *Task,
1397 IN UINT16 PortForBit
1398 )
1399 {
1400 UINT8 RegisterValue;
1401
1402 Task->RetryTimes--;
1403 RegisterValue = IdeReadPortB(PciIo, PortForBit);
1404
1405 if ((RegisterValue & BMIS_ERROR) != 0) {
1406 DEBUG ((EFI_D_ERROR, "ATA UDMA operation fails\n"));
1407 return EFI_DEVICE_ERROR;
1408 }
1409
1410 if ((RegisterValue & BMIS_INTERRUPT) != 0) {
1411 return EFI_SUCCESS;
1412 }
1413
1414 if (Task->RetryTimes == 0) {
1415 return EFI_TIMEOUT;
1416 } else {
1417 //
1418 // The memory is not set.
1419 //
1420 return EFI_NOT_READY;
1421 }
1422 }
1423
1424 /**
1425 Perform an ATA Udma operation (Read, ReadExt, Write, WriteExt).
1426
1427 @param[in] Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data
1428 structure.
1429 @param[in] IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1430 @param[in] Read Flag used to determine the data transfer
1431 direction. Read equals 1, means data transferred
1432 from device to host;Read equals 0, means data
1433 transferred from host to device.
1434 @param[in] DataBuffer A pointer to the source buffer for the data.
1435 @param[in] DataLength The length of the data.
1436 @param[in] AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK data structure.
1437 @param[in, out] AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1438 @param[in] Timeout The time to complete the command.
1439 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1440 used by non-blocking mode.
1441
1442 @retval EFI_SUCCESS the operation is successful.
1443 @retval EFI_OUT_OF_RESOURCES Build PRD table failed
1444 @retval EFI_UNSUPPORTED Unknown channel or operations command
1445 @retval EFI_DEVICE_ERROR Ata command execute failed
1446
1447 **/
1448 EFI_STATUS
1449 EFIAPI
1450 AtaUdmaInOut (
1451 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
1452 IN EFI_IDE_REGISTERS *IdeRegisters,
1453 IN BOOLEAN Read,
1454 IN VOID *DataBuffer,
1455 IN UINT64 DataLength,
1456 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1457 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1458 IN UINT64 Timeout,
1459 IN ATA_NONBLOCK_TASK *Task
1460 )
1461 {
1462 EFI_STATUS Status;
1463 UINT16 IoPortForBmic;
1464 UINT16 IoPortForBmis;
1465 UINT16 IoPortForBmid;
1466
1467 UINTN PrdTableSize;
1468 EFI_PHYSICAL_ADDRESS PrdTableMapAddr;
1469 VOID *PrdTableMap;
1470 EFI_ATA_DMA_PRD *PrdBaseAddr;
1471 EFI_ATA_DMA_PRD *TempPrdBaseAddr;
1472 UINTN PrdTableNum;
1473
1474 UINT8 RegisterValue;
1475 UINTN PageCount;
1476 UINTN ByteCount;
1477 UINTN ByteRemaining;
1478 UINT8 DeviceControl;
1479
1480 VOID *BufferMap;
1481 EFI_PHYSICAL_ADDRESS BufferMapAddress;
1482 EFI_PCI_IO_PROTOCOL_OPERATION PciIoOperation;
1483
1484 UINT8 DeviceHead;
1485 EFI_PCI_IO_PROTOCOL *PciIo;
1486 EFI_TPL OldTpl;
1487
1488
1489 Status = EFI_SUCCESS;
1490 PrdBaseAddr = NULL;
1491 PrdTableMap = NULL;
1492 BufferMap = NULL;
1493 PageCount = 0;
1494 PciIo = Instance->PciIo;
1495
1496 if ((PciIo == NULL) || (IdeRegisters == NULL) || (DataBuffer == NULL) || (AtaCommandBlock == NULL)) {
1497 return EFI_INVALID_PARAMETER;
1498 }
1499
1500 //
1501 // Before starting the Blocking BlockIO operation, push to finish all non-blocking
1502 // BlockIO tasks.
1503 // Delay 1ms to simulate the blocking time out checking.
1504 //
1505 while ((Task == NULL) && (!IsListEmpty (&Instance->NonBlockingTaskList))) {
1506 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1507 AsyncNonBlockingTransferRoutine (NULL, Instance);
1508 gBS->RestoreTPL (OldTpl);
1509 //
1510 // Stall for 1 milliseconds.
1511 //
1512 MicroSecondDelay (1000);
1513 }
1514
1515 //
1516 // The data buffer should be even alignment
1517 //
1518 if (((UINTN)DataBuffer & 0x1) != 0) {
1519 return EFI_INVALID_PARAMETER;
1520 }
1521
1522 //
1523 // Set relevant IO Port address.
1524 //
1525 IoPortForBmic = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIC_OFFSET);
1526 IoPortForBmis = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMIS_OFFSET);
1527 IoPortForBmid = (UINT16) (IdeRegisters->BusMasterBaseAddr + BMID_OFFSET);
1528
1529 //
1530 // For Blocking mode, start the command.
1531 // For non-blocking mode, when the command is not started, start it, otherwise
1532 // go to check the status.
1533 //
1534 if (((Task != NULL) && (!Task->IsStart)) || (Task == NULL)) {
1535 //
1536 // Calculate the number of PRD entry.
1537 // Every entry in PRD table can specify a 64K memory region.
1538 //
1539 PrdTableNum = (UINTN)(RShiftU64(DataLength, 16) + 1);
1540
1541 //
1542 // Make sure that the memory region of PRD table is not cross 64K boundary
1543 //
1544 PrdTableSize = PrdTableNum * sizeof (EFI_ATA_DMA_PRD);
1545 if (PrdTableSize > 0x10000) {
1546 return EFI_INVALID_PARAMETER;
1547 }
1548
1549 //
1550 // Allocate buffer for PRD table initialization.
1551 //
1552 PageCount = EFI_SIZE_TO_PAGES (PrdTableSize);
1553 Status = PciIo->AllocateBuffer (
1554 PciIo,
1555 AllocateAnyPages,
1556 EfiBootServicesData,
1557 PageCount,
1558 (VOID **)&PrdBaseAddr,
1559 0
1560 );
1561 if (EFI_ERROR (Status)) {
1562 return EFI_OUT_OF_RESOURCES;
1563 }
1564
1565 ByteCount = EFI_PAGES_TO_SIZE (PageCount);
1566 Status = PciIo->Map (
1567 PciIo,
1568 EfiPciIoOperationBusMasterCommonBuffer,
1569 PrdBaseAddr,
1570 &ByteCount,
1571 &PrdTableMapAddr,
1572 &PrdTableMap
1573 );
1574 if (EFI_ERROR (Status) || (ByteCount != EFI_PAGES_TO_SIZE (PageCount))) {
1575 //
1576 // If the data length actually mapped is not equal to the requested amount,
1577 // it means the DMA operation may be broken into several discontinuous smaller chunks.
1578 // Can't handle this case.
1579 //
1580 PciIo->FreeBuffer (PciIo, PageCount, PrdBaseAddr);
1581 return EFI_OUT_OF_RESOURCES;
1582 }
1583
1584 ZeroMem ((VOID *) ((UINTN) PrdBaseAddr), ByteCount);
1585
1586 //
1587 // Map the host address of DataBuffer to DMA master address.
1588 //
1589 if (Read) {
1590 PciIoOperation = EfiPciIoOperationBusMasterWrite;
1591 } else {
1592 PciIoOperation = EfiPciIoOperationBusMasterRead;
1593 }
1594
1595 ByteCount = (UINTN)DataLength;
1596 Status = PciIo->Map (
1597 PciIo,
1598 PciIoOperation,
1599 DataBuffer,
1600 &ByteCount,
1601 &BufferMapAddress,
1602 &BufferMap
1603 );
1604 if (EFI_ERROR (Status) || (ByteCount != DataLength)) {
1605 PciIo->Unmap (PciIo, PrdTableMap);
1606 PciIo->FreeBuffer (PciIo, PageCount, PrdBaseAddr);
1607 return EFI_OUT_OF_RESOURCES;
1608 }
1609
1610 //
1611 // According to Ata spec, it requires the buffer address and size to be even.
1612 //
1613 ASSERT ((BufferMapAddress & 0x1) == 0);
1614 ASSERT ((ByteCount & 0x1) == 0);
1615
1616 //
1617 // Fill the PRD table with appropriate bus master address of data buffer and data length.
1618 //
1619 ByteRemaining = ByteCount;
1620 TempPrdBaseAddr = PrdBaseAddr;
1621 while (ByteRemaining != 0) {
1622 if (ByteRemaining <= 0x10000) {
1623 TempPrdBaseAddr->RegionBaseAddr = (UINT32) ((UINTN) BufferMapAddress);
1624 TempPrdBaseAddr->ByteCount = (UINT16) ByteRemaining;
1625 TempPrdBaseAddr->EndOfTable = 0x8000;
1626 break;
1627 }
1628
1629 TempPrdBaseAddr->RegionBaseAddr = (UINT32) ((UINTN) BufferMapAddress);
1630 TempPrdBaseAddr->ByteCount = (UINT16) 0x0;
1631
1632 ByteRemaining -= 0x10000;
1633 BufferMapAddress += 0x10000;
1634 TempPrdBaseAddr++;
1635 }
1636
1637 //
1638 // Start to enable the DMA operation
1639 //
1640 DeviceHead = AtaCommandBlock->AtaDeviceHead;
1641
1642 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)(0xe0 | DeviceHead));
1643
1644 //
1645 // Enable interrupt to support UDMA
1646 //
1647 DeviceControl = 0;
1648 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
1649
1650 //
1651 // Read BMIS register and clear ERROR and INTR bit
1652 //
1653 RegisterValue = IdeReadPortB(PciIo, IoPortForBmis);
1654 RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);
1655 IdeWritePortB(PciIo, IoPortForBmis, RegisterValue);
1656
1657 //
1658 // Set the base address to BMID register
1659 //
1660 IdeWritePortDW (PciIo, IoPortForBmid, (UINT32)PrdTableMapAddr);
1661
1662 //
1663 // Set BMIC register to identify the operation direction
1664 //
1665 RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);
1666 if (Read) {
1667 RegisterValue |= BMIC_NREAD;
1668 } else {
1669 RegisterValue &= ~((UINT8) BMIC_NREAD);
1670 }
1671 IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);
1672
1673 //
1674 // Issue ATA command
1675 //
1676 Status = AtaIssueCommand (PciIo, IdeRegisters, AtaCommandBlock, Timeout);
1677
1678 if (EFI_ERROR (Status)) {
1679 Status = EFI_DEVICE_ERROR;
1680 goto Exit;
1681 }
1682
1683 //
1684 // Set START bit of BMIC register
1685 //
1686 RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);
1687 RegisterValue |= BMIC_START;
1688 IdeWritePortB(PciIo, IoPortForBmic, RegisterValue);
1689
1690 if (Task != NULL) {
1691 //
1692 // Max transfer number of sectors for one command is 65536(32Mbyte),
1693 // it will cost 1 second to transfer these data in UDMA mode 2(33.3MBps).
1694 // So set the variable Count to 2000, for about 2 second Timeout time.
1695 //
1696 Task->RetryTimes = 2000;
1697 Task->Map = BufferMap;
1698 Task->TableMap = PrdTableMap;
1699 Task->MapBaseAddress = PrdBaseAddr;
1700 Task->PageCount = PageCount;
1701 Task->IsStart = TRUE;
1702 }
1703 }
1704
1705 //
1706 // Check the INTERRUPT and ERROR bit of BMIS
1707 // Max transfer number of sectors for one command is 65536(32Mbyte),
1708 // it will cost 1 second to transfer these data in UDMA mode 2(33.3MBps).
1709 // So set the variable Count to 2000, for about 2 second Timeout time.
1710 //
1711 if (Task != NULL) {
1712 Status = AtaUdmStatusCheck (PciIo, Task, IoPortForBmis);
1713 } else {
1714 Status = AtaUdmStatusWait (PciIo, IoPortForBmis);
1715 }
1716
1717 //
1718 // For blocking mode, clear registers and free buffers.
1719 // For non blocking mode, when the related registers have been set or time
1720 // out, or a error has been happened, it needs to clear the register and free
1721 // buffer.
1722 //
1723 if ((Task == NULL) || Status != EFI_NOT_READY) {
1724 //
1725 // Read BMIS register and clear ERROR and INTR bit
1726 //
1727 RegisterValue = IdeReadPortB (PciIo, IoPortForBmis);
1728 RegisterValue |= (BMIS_INTERRUPT | BMIS_ERROR);
1729 IdeWritePortB (PciIo, IoPortForBmis, RegisterValue);
1730
1731 //
1732 // Read Status Register of IDE device to clear interrupt
1733 //
1734 RegisterValue = IdeReadPortB(PciIo, IdeRegisters->CmdOrStatus);
1735
1736 //
1737 // Clear START bit of BMIC register
1738 //
1739 RegisterValue = IdeReadPortB(PciIo, IoPortForBmic);
1740 RegisterValue &= ~((UINT8) BMIC_START);
1741 IdeWritePortB (PciIo, IoPortForBmic, RegisterValue);
1742
1743 //
1744 // Disable interrupt of Select device
1745 //
1746 DeviceControl = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
1747 DeviceControl |= ATA_CTLREG_IEN_L;
1748 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, DeviceControl);
1749 //
1750 // Stall for 10 milliseconds.
1751 //
1752 MicroSecondDelay (10000);
1753
1754 }
1755
1756 Exit:
1757 //
1758 // Free all allocated resource
1759 //
1760 if ((Task == NULL) || Status != EFI_NOT_READY) {
1761 if (Task != NULL) {
1762 PciIo->Unmap (PciIo, Task->TableMap);
1763 PciIo->FreeBuffer (PciIo, Task->PageCount, Task->MapBaseAddress);
1764 PciIo->Unmap (PciIo, Task->Map);
1765 } else {
1766 PciIo->Unmap (PciIo, PrdTableMap);
1767 PciIo->FreeBuffer (PciIo, PageCount, PrdBaseAddr);
1768 PciIo->Unmap (PciIo, BufferMap);
1769 }
1770
1771 //
1772 // Dump All Ide registers to ATA_STATUS_BLOCK
1773 //
1774 DumpAllIdeRegisters (PciIo, IdeRegisters, AtaStatusBlock);
1775 }
1776
1777 return Status;
1778 }
1779
1780 /**
1781 This function reads the pending data in the device.
1782
1783 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
1784 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1785
1786 @retval EFI_SUCCESS Successfully read.
1787 @retval EFI_NOT_READY The BSY is set avoiding reading.
1788
1789 **/
1790 EFI_STATUS
1791 EFIAPI
1792 AtaPacketReadPendingData (
1793 IN EFI_PCI_IO_PROTOCOL *PciIo,
1794 IN EFI_IDE_REGISTERS *IdeRegisters
1795 )
1796 {
1797 UINT8 AltRegister;
1798 UINT16 TempWordBuffer;
1799
1800 AltRegister = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
1801 if ((AltRegister & ATA_STSREG_BSY) == ATA_STSREG_BSY) {
1802 return EFI_NOT_READY;
1803 }
1804
1805 if ((AltRegister & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
1806 TempWordBuffer = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
1807 while ((TempWordBuffer & (ATA_STSREG_BSY | ATA_STSREG_DRQ)) == ATA_STSREG_DRQ) {
1808 IdeReadPortWMultiple (
1809 PciIo,
1810 IdeRegisters->Data,
1811 1,
1812 &TempWordBuffer
1813 );
1814 TempWordBuffer = IdeReadPortB (PciIo, IdeRegisters->AltOrDev);
1815 }
1816 }
1817 return EFI_SUCCESS;
1818 }
1819
1820 /**
1821 This function is called by AtaPacketCommandExecute().
1822 It is used to transfer data between host and device. The data direction is specified
1823 by the fourth parameter.
1824
1825 @param PciIo A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
1826 @param IdeRegisters A pointer to EFI_IDE_REGISTERS data structure.
1827 @param Buffer Buffer contained data transferred between host and device.
1828 @param ByteCount Data size in byte unit of the buffer.
1829 @param Read Flag used to determine the data transfer direction.
1830 Read equals 1, means data transferred from device to host;
1831 Read equals 0, means data transferred from host to device.
1832 @param Timeout Timeout value for wait DRQ ready before each data stream's transfer.
1833
1834 @retval EFI_SUCCESS data is transferred successfully.
1835 @retval EFI_DEVICE_ERROR the device failed to transfer data.
1836 **/
1837 EFI_STATUS
1838 EFIAPI
1839 AtaPacketReadWrite (
1840 IN EFI_PCI_IO_PROTOCOL *PciIo,
1841 IN EFI_IDE_REGISTERS *IdeRegisters,
1842 IN OUT VOID *Buffer,
1843 IN UINT64 ByteCount,
1844 IN BOOLEAN Read,
1845 IN UINT64 Timeout
1846 )
1847 {
1848 UINT32 RequiredWordCount;
1849 UINT32 ActualWordCount;
1850 UINT32 WordCount;
1851 EFI_STATUS Status;
1852 UINT16 *PtrBuffer;
1853
1854 //
1855 // No data transfer is premitted.
1856 //
1857 if (ByteCount == 0) {
1858 return EFI_SUCCESS;
1859 }
1860
1861 PtrBuffer = Buffer;
1862 RequiredWordCount = (UINT32)RShiftU64(ByteCount, 1);
1863 //
1864 // ActuralWordCount means the word count of data really transferred.
1865 //
1866 ActualWordCount = 0;
1867
1868 while (ActualWordCount < RequiredWordCount) {
1869 //
1870 // before each data transfer stream, the host should poll DRQ bit ready,
1871 // to see whether indicates device is ready to transfer data.
1872 //
1873 Status = DRQReady2 (PciIo, IdeRegisters, Timeout);
1874 if (EFI_ERROR (Status)) {
1875 return CheckStatusRegister (PciIo, IdeRegisters);
1876 }
1877
1878 //
1879 // get current data transfer size from Cylinder Registers.
1880 //
1881 WordCount = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb) << 8;
1882 WordCount = WordCount | IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
1883 WordCount = WordCount & 0xffff;
1884 WordCount /= 2;
1885
1886 WordCount = MIN (WordCount, (RequiredWordCount - ActualWordCount));
1887
1888 if (Read) {
1889 IdeReadPortWMultiple (
1890 PciIo,
1891 IdeRegisters->Data,
1892 WordCount,
1893 PtrBuffer
1894 );
1895 } else {
1896 IdeWritePortWMultiple (
1897 PciIo,
1898 IdeRegisters->Data,
1899 WordCount,
1900 PtrBuffer
1901 );
1902 }
1903
1904 //
1905 // read status register to check whether error happens.
1906 //
1907 Status = CheckStatusRegister (PciIo, IdeRegisters);
1908 if (EFI_ERROR (Status)) {
1909 return EFI_DEVICE_ERROR;
1910 }
1911
1912 PtrBuffer += WordCount;
1913 ActualWordCount += WordCount;
1914 }
1915
1916 if (Read) {
1917 //
1918 // In the case where the drive wants to send more data than we need to read,
1919 // the DRQ bit will be set and cause delays from DRQClear2().
1920 // We need to read data from the drive until it clears DRQ so we can move on.
1921 //
1922 AtaPacketReadPendingData (PciIo, IdeRegisters);
1923 }
1924
1925 //
1926 // read status register to check whether error happens.
1927 //
1928 Status = CheckStatusRegister (PciIo, IdeRegisters);
1929 if (EFI_ERROR (Status)) {
1930 return EFI_DEVICE_ERROR;
1931 }
1932
1933 //
1934 // After data transfer is completed, normally, DRQ bit should clear.
1935 //
1936 Status = DRQClear2 (PciIo, IdeRegisters, Timeout);
1937 if (EFI_ERROR (Status)) {
1938 return EFI_DEVICE_ERROR;
1939 }
1940
1941 return Status;
1942 }
1943
1944 /**
1945 Sumbit ATAPI request sense command.
1946
1947 @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance
1948 @param[in] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to
1949 store the IDE i/o port registers' base addresses
1950 @param[in] Channel The channel number of device.
1951 @param[in] Device The device number of device.
1952 @param[in] SenseData A pointer to store sense data.
1953 @param[in] SenseDataLength The sense data length.
1954 @param[in] Timeout The timeout value to execute this cmd.
1955
1956 @retval EFI_SUCCESS Send out the ATAPI packet command successfully.
1957 @retval EFI_DEVICE_ERROR The device failed to send data.
1958
1959 **/
1960 EFI_STATUS
1961 EFIAPI
1962 AtaPacketRequestSense (
1963 IN EFI_PCI_IO_PROTOCOL *PciIo,
1964 IN EFI_IDE_REGISTERS *IdeRegisters,
1965 IN UINT8 Channel,
1966 IN UINT8 Device,
1967 IN VOID *SenseData,
1968 IN UINT8 SenseDataLength,
1969 IN UINT64 Timeout
1970 )
1971 {
1972 EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET Packet;
1973 UINT8 Cdb[12];
1974 EFI_STATUS Status;
1975
1976 ZeroMem (&Packet, sizeof (EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET));
1977 ZeroMem (Cdb, 12);
1978
1979 Cdb[0] = ATA_CMD_REQUEST_SENSE;
1980 Cdb[4] = SenseDataLength;
1981
1982 Packet.Timeout = Timeout;
1983 Packet.Cdb = Cdb;
1984 Packet.CdbLength = 12;
1985 Packet.DataDirection = EFI_EXT_SCSI_DATA_DIRECTION_READ;
1986 Packet.InDataBuffer = SenseData;
1987 Packet.InTransferLength = SenseDataLength;
1988
1989 Status = AtaPacketCommandExecute (PciIo, IdeRegisters, Channel, Device, &Packet);
1990
1991 return Status;
1992 }
1993
1994 /**
1995 This function is used to send out ATAPI commands conforms to the Packet Command
1996 with PIO Data In Protocol.
1997
1998 @param[in] PciIo Pointer to the EFI_PCI_IO_PROTOCOL instance
1999 @param[in] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to
2000 store the IDE i/o port registers' base addresses
2001 @param[in] Channel The channel number of device.
2002 @param[in] Device The device number of device.
2003 @param[in] Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET data structure.
2004
2005 @retval EFI_SUCCESS send out the ATAPI packet command successfully
2006 and device sends data successfully.
2007 @retval EFI_DEVICE_ERROR the device failed to send data.
2008
2009 **/
2010 EFI_STATUS
2011 EFIAPI
2012 AtaPacketCommandExecute (
2013 IN EFI_PCI_IO_PROTOCOL *PciIo,
2014 IN EFI_IDE_REGISTERS *IdeRegisters,
2015 IN UINT8 Channel,
2016 IN UINT8 Device,
2017 IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
2018 )
2019 {
2020 EFI_STATUS PacketCommandStatus;
2021 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2022 EFI_STATUS Status;
2023 UINT8 Count;
2024 UINT8 PacketCommand[12];
2025
2026 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2027
2028 //
2029 // Fill ATAPI Command Packet according to CDB.
2030 // For Atapi cmd, its length should be less than or equal to 12 bytes.
2031 //
2032 if (Packet->CdbLength > 12) {
2033 return EFI_INVALID_PARAMETER;
2034 }
2035
2036 ZeroMem (PacketCommand, 12);
2037 CopyMem (PacketCommand, Packet->Cdb, Packet->CdbLength);
2038
2039 //
2040 // No OVL; No DMA
2041 //
2042 AtaCommandBlock.AtaFeatures = 0x00;
2043 //
2044 // set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device
2045 // determine how many data should be transferred.
2046 //
2047 AtaCommandBlock.AtaCylinderLow = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);
2048 AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);
2049 AtaCommandBlock.AtaDeviceHead = (UINT8) (Device << 0x4);
2050 AtaCommandBlock.AtaCommand = ATA_CMD_PACKET;
2051
2052 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)(0xe0 | (Device << 0x4)));
2053 //
2054 // Disable interrupt
2055 //
2056 IdeWritePortB (PciIo, IdeRegisters->AltOrDev, ATA_DEFAULT_CTL);
2057
2058 //
2059 // Issue ATA PACKET command firstly
2060 //
2061 Status = AtaIssueCommand (PciIo, IdeRegisters, &AtaCommandBlock, Packet->Timeout);
2062 if (EFI_ERROR (Status)) {
2063 return Status;
2064 }
2065
2066 Status = DRQReady (PciIo, IdeRegisters, Packet->Timeout);
2067 if (EFI_ERROR (Status)) {
2068 return Status;
2069 }
2070
2071 //
2072 // Send out ATAPI command packet
2073 //
2074 for (Count = 0; Count < 6; Count++) {
2075 IdeWritePortW (PciIo, IdeRegisters->Data, *((UINT16*)PacketCommand + Count));
2076 //
2077 // Stall for 10 microseconds.
2078 //
2079 MicroSecondDelay (10);
2080 }
2081
2082 //
2083 // Read/Write the data of ATAPI Command
2084 //
2085 if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {
2086 PacketCommandStatus = AtaPacketReadWrite (
2087 PciIo,
2088 IdeRegisters,
2089 Packet->InDataBuffer,
2090 Packet->InTransferLength,
2091 TRUE,
2092 Packet->Timeout
2093 );
2094 } else {
2095 PacketCommandStatus = AtaPacketReadWrite (
2096 PciIo,
2097 IdeRegisters,
2098 Packet->OutDataBuffer,
2099 Packet->OutTransferLength,
2100 FALSE,
2101 Packet->Timeout
2102 );
2103 }
2104
2105 if (!EFI_ERROR (PacketCommandStatus)) {
2106 return PacketCommandStatus;
2107 }
2108
2109 //
2110 // Return SenseData if PacketCommandStatus matches
2111 // the following return codes.
2112 //
2113 if ((PacketCommandStatus == EFI_BAD_BUFFER_SIZE) ||
2114 (PacketCommandStatus == EFI_DEVICE_ERROR) ||
2115 (PacketCommandStatus == EFI_TIMEOUT)) {
2116
2117 //
2118 // avoid submit request sense command continuously.
2119 //
2120 if ((Packet->SenseData == NULL) || (((UINT8 *)Packet->Cdb)[0] == ATA_CMD_REQUEST_SENSE)) {
2121 return PacketCommandStatus;
2122 }
2123
2124 AtaPacketRequestSense (
2125 PciIo,
2126 IdeRegisters,
2127 Channel,
2128 Device,
2129 Packet->SenseData,
2130 Packet->SenseDataLength,
2131 Packet->Timeout
2132 );
2133 }
2134
2135 return PacketCommandStatus;
2136 }
2137
2138
2139 /**
2140 Set the calculated Best transfer mode to a detected device.
2141
2142 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2143 @param Channel The channel number of device.
2144 @param Device The device number of device.
2145 @param TransferMode A pointer to EFI_ATA_TRANSFER_MODE data structure.
2146 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2147
2148 @retval EFI_SUCCESS Set transfer mode successfully.
2149 @retval EFI_DEVICE_ERROR Set transfer mode failed.
2150 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
2151
2152 **/
2153 EFI_STATUS
2154 EFIAPI
2155 SetDeviceTransferMode (
2156 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2157 IN UINT8 Channel,
2158 IN UINT8 Device,
2159 IN EFI_ATA_TRANSFER_MODE *TransferMode,
2160 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2161 )
2162 {
2163 EFI_STATUS Status;
2164 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2165
2166 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2167
2168 AtaCommandBlock.AtaCommand = ATA_CMD_SET_FEATURES;
2169 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
2170 AtaCommandBlock.AtaFeatures = 0x03;
2171 AtaCommandBlock.AtaSectorCount = *((UINT8 *)TransferMode);
2172
2173 //
2174 // Send SET FEATURE command (sub command 0x03) to set pio mode.
2175 //
2176 Status = AtaNonDataCommandIn (
2177 Instance->PciIo,
2178 &Instance->IdeRegisters[Channel],
2179 &AtaCommandBlock,
2180 AtaStatusBlock,
2181 ATA_ATAPI_TIMEOUT,
2182 NULL
2183 );
2184
2185 return Status;
2186 }
2187
2188 /**
2189 Set drive parameters for devices not support PACKETS command.
2190
2191 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2192 @param Channel The channel number of device.
2193 @param Device The device number of device.
2194 @param DriveParameters A pointer to EFI_ATA_DRIVE_PARMS data structure.
2195 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2196
2197 @retval EFI_SUCCESS Set drive parameter successfully.
2198 @retval EFI_DEVICE_ERROR Set drive parameter failed.
2199 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
2200
2201 **/
2202 EFI_STATUS
2203 EFIAPI
2204 SetDriveParameters (
2205 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2206 IN UINT8 Channel,
2207 IN UINT8 Device,
2208 IN EFI_ATA_DRIVE_PARMS *DriveParameters,
2209 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2210
2211 )
2212 {
2213 EFI_STATUS Status;
2214 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2215
2216 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2217
2218 AtaCommandBlock.AtaCommand = ATA_CMD_INIT_DRIVE_PARAM;
2219 AtaCommandBlock.AtaSectorCount = DriveParameters->Sector;
2220 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) + DriveParameters->Heads);
2221
2222 //
2223 // Send Init drive parameters
2224 //
2225 Status = AtaNonDataCommandIn (
2226 Instance->PciIo,
2227 &Instance->IdeRegisters[Channel],
2228 &AtaCommandBlock,
2229 AtaStatusBlock,
2230 ATA_ATAPI_TIMEOUT,
2231 NULL
2232 );
2233
2234 //
2235 // Send Set Multiple parameters
2236 //
2237 AtaCommandBlock.AtaCommand = ATA_CMD_SET_MULTIPLE_MODE;
2238 AtaCommandBlock.AtaSectorCount = DriveParameters->MultipleSector;
2239 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
2240
2241 Status = AtaNonDataCommandIn (
2242 Instance->PciIo,
2243 &Instance->IdeRegisters[Channel],
2244 &AtaCommandBlock,
2245 AtaStatusBlock,
2246 ATA_ATAPI_TIMEOUT,
2247 NULL
2248 );
2249
2250 return Status;
2251 }
2252
2253 /**
2254 Send SMART Return Status command to check if the execution of SMART cmd is successful or not.
2255
2256 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2257 @param Channel The channel number of device.
2258 @param Device The device number of device.
2259 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2260
2261 @retval EFI_SUCCESS Successfully get the return status of S.M.A.R.T command execution.
2262 @retval Others Fail to get return status data.
2263
2264 **/
2265 EFI_STATUS
2266 EFIAPI
2267 IdeAtaSmartReturnStatusCheck (
2268 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2269 IN UINT8 Channel,
2270 IN UINT8 Device,
2271 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2272 )
2273 {
2274 EFI_STATUS Status;
2275 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2276 UINT8 LBAMid;
2277 UINT8 LBAHigh;
2278
2279 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2280
2281 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
2282 AtaCommandBlock.AtaFeatures = ATA_SMART_RETURN_STATUS;
2283 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
2284 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
2285 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);
2286
2287 //
2288 // Send S.M.A.R.T Read Return Status command to device
2289 //
2290 Status = AtaNonDataCommandIn (
2291 Instance->PciIo,
2292 &Instance->IdeRegisters[Channel],
2293 &AtaCommandBlock,
2294 AtaStatusBlock,
2295 ATA_ATAPI_TIMEOUT,
2296 NULL
2297 );
2298
2299 if (EFI_ERROR (Status)) {
2300 return EFI_DEVICE_ERROR;
2301 }
2302
2303 LBAMid = IdeReadPortB (Instance->PciIo, Instance->IdeRegisters[Channel].CylinderLsb);
2304 LBAHigh = IdeReadPortB (Instance->PciIo, Instance->IdeRegisters[Channel].CylinderMsb);
2305
2306 if ((LBAMid == 0x4f) && (LBAHigh == 0xc2)) {
2307 //
2308 // The threshold exceeded condition is not detected by the device
2309 //
2310 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));
2311
2312 } else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {
2313 //
2314 // The threshold exceeded condition is detected by the device
2315 //
2316 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));
2317 }
2318
2319 return EFI_SUCCESS;
2320 }
2321
2322 /**
2323 Enable SMART command of the disk if supported.
2324
2325 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2326 @param Channel The channel number of device.
2327 @param Device The device number of device.
2328 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
2329 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2330
2331 **/
2332 VOID
2333 EFIAPI
2334 IdeAtaSmartSupport (
2335 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2336 IN UINT8 Channel,
2337 IN UINT8 Device,
2338 IN EFI_IDENTIFY_DATA *IdentifyData,
2339 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2340 )
2341 {
2342 EFI_STATUS Status;
2343 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2344
2345 //
2346 // Detect if the device supports S.M.A.R.T.
2347 //
2348 if ((IdentifyData->AtaData.command_set_supported_82 & 0x0001) != 0x0001) {
2349 //
2350 // S.M.A.R.T is not supported by the device
2351 //
2352 DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at [%a] channel [%a] device!\n",
2353 (Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));
2354 } else {
2355 //
2356 // Check if the feature is enabled. If not, then enable S.M.A.R.T.
2357 //
2358 if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {
2359
2360 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2361
2362 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
2363 AtaCommandBlock.AtaFeatures = ATA_SMART_ENABLE_OPERATION;
2364 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
2365 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
2366 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);
2367
2368 //
2369 // Send S.M.A.R.T Enable command to device
2370 //
2371 Status = AtaNonDataCommandIn (
2372 Instance->PciIo,
2373 &Instance->IdeRegisters[Channel],
2374 &AtaCommandBlock,
2375 AtaStatusBlock,
2376 ATA_ATAPI_TIMEOUT,
2377 NULL
2378 );
2379
2380 if (!EFI_ERROR (Status)) {
2381 //
2382 // Send S.M.A.R.T AutoSave command to device
2383 //
2384 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2385
2386 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
2387 AtaCommandBlock.AtaFeatures = 0xD2;
2388 AtaCommandBlock.AtaSectorCount = 0xF1;
2389 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
2390 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
2391 AtaCommandBlock.AtaDeviceHead = (UINT8) ((Device << 0x4) | 0xe0);
2392
2393 Status = AtaNonDataCommandIn (
2394 Instance->PciIo,
2395 &Instance->IdeRegisters[Channel],
2396 &AtaCommandBlock,
2397 AtaStatusBlock,
2398 ATA_ATAPI_TIMEOUT,
2399 NULL
2400 );
2401 if (!EFI_ERROR (Status)) {
2402 Status = IdeAtaSmartReturnStatusCheck (
2403 Instance,
2404 Channel,
2405 Device,
2406 AtaStatusBlock
2407 );
2408 }
2409 }
2410 }
2411
2412 DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at [%a] channel [%a] device!\n",
2413 (Channel == 1) ? "secondary" : "primary", (Device == 1) ? "slave" : "master"));
2414
2415 }
2416
2417 return ;
2418 }
2419
2420
2421 /**
2422 Sends out an ATA Identify Command to the specified device.
2423
2424 This function is called by DiscoverIdeDevice() during its device
2425 identification. It sends out the ATA Identify Command to the
2426 specified device. Only ATA device responses to this command. If
2427 the command succeeds, it returns the Identify data structure which
2428 contains information about the device. This function extracts the
2429 information it needs to fill the IDE_BLK_IO_DEV data structure,
2430 including device type, media block size, media capacity, and etc.
2431
2432 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2433 @param Channel The channel number of device.
2434 @param Device The device number of device.
2435 @param Buffer A pointer to data buffer which is used to contain IDENTIFY data.
2436 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2437
2438 @retval EFI_SUCCESS Identify ATA device successfully.
2439 @retval EFI_DEVICE_ERROR ATA Identify Device Command failed or device is not ATA device.
2440 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
2441
2442 **/
2443 EFI_STATUS
2444 EFIAPI
2445 AtaIdentify (
2446 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2447 IN UINT8 Channel,
2448 IN UINT8 Device,
2449 IN OUT EFI_IDENTIFY_DATA *Buffer,
2450 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2451 )
2452 {
2453 EFI_STATUS Status;
2454 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2455
2456 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2457
2458 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DRIVE;
2459 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
2460
2461 Status = AtaPioDataInOut (
2462 Instance->PciIo,
2463 &Instance->IdeRegisters[Channel],
2464 Buffer,
2465 sizeof (EFI_IDENTIFY_DATA),
2466 TRUE,
2467 &AtaCommandBlock,
2468 AtaStatusBlock,
2469 ATA_ATAPI_TIMEOUT,
2470 NULL
2471 );
2472
2473 return Status;
2474 }
2475
2476 /**
2477 This function is called by DiscoverIdeDevice() during its device
2478 identification.
2479 Its main purpose is to get enough information for the device media
2480 to fill in the Media data structure of the Block I/O Protocol interface.
2481
2482 There are 5 steps to reach such objective:
2483 1. Sends out the ATAPI Identify Command to the specified device.
2484 Only ATAPI device responses to this command. If the command succeeds,
2485 it returns the Identify data structure which filled with information
2486 about the device. Since the ATAPI device contains removable media,
2487 the only meaningful information is the device module name.
2488 2. Sends out ATAPI Inquiry Packet Command to the specified device.
2489 This command will return inquiry data of the device, which contains
2490 the device type information.
2491 3. Allocate sense data space for future use. We don't detect the media
2492 presence here to improvement boot performance, especially when CD
2493 media is present. The media detection will be performed just before
2494 each BLK_IO read/write
2495
2496 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2497 @param Channel The channel number of device.
2498 @param Device The device number of device.
2499 @param Buffer A pointer to data buffer which is used to contain IDENTIFY data.
2500 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
2501
2502 @retval EFI_SUCCESS Identify ATAPI device successfully.
2503 @retval EFI_DEVICE_ERROR ATA Identify Packet Device Command failed or device type
2504 is not supported by this IDE driver.
2505 @retval EFI_OUT_OF_RESOURCES Allocate memory failed.
2506
2507 **/
2508 EFI_STATUS
2509 EFIAPI
2510 AtaIdentifyPacket (
2511 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2512 IN UINT8 Channel,
2513 IN UINT8 Device,
2514 IN OUT EFI_IDENTIFY_DATA *Buffer,
2515 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
2516 )
2517 {
2518 EFI_STATUS Status;
2519 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2520
2521 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2522
2523 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DEVICE;
2524 AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
2525
2526 //
2527 // Send ATAPI Identify Command to get IDENTIFY data.
2528 //
2529 Status = AtaPioDataInOut (
2530 Instance->PciIo,
2531 &Instance->IdeRegisters[Channel],
2532 (VOID *) Buffer,
2533 sizeof (EFI_IDENTIFY_DATA),
2534 TRUE,
2535 &AtaCommandBlock,
2536 AtaStatusBlock,
2537 ATA_ATAPI_TIMEOUT,
2538 NULL
2539 );
2540
2541 return Status;
2542 }
2543
2544
2545 /**
2546 This function is used for detect whether the IDE device exists in the
2547 specified Channel as the specified Device Number.
2548
2549 There is two IDE channels: one is Primary Channel, the other is
2550 Secondary Channel.(Channel is the logical name for the physical "Cable".)
2551 Different channel has different register group.
2552
2553 On each IDE channel, at most two IDE devices attach,
2554 one is called Device 0 (Master device), the other is called Device 1
2555 (Slave device). The devices on the same channel co-use the same register
2556 group, so before sending out a command for a specified device via command
2557 register, it is a must to select the current device to accept the command
2558 by set the device number in the Head/Device Register.
2559
2560 @param Instance A pointer to ATA_ATAPI_PASS_THRU_INSTANCE data structure.
2561 @param IdeChannel The channel number of device.
2562
2563 @retval EFI_SUCCESS successfully detects device.
2564 @retval other any failure during detection process will return this value.
2565
2566 **/
2567 EFI_STATUS
2568 EFIAPI
2569 DetectAndConfigIdeDevice (
2570 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
2571 IN UINT8 IdeChannel
2572 )
2573 {
2574 EFI_STATUS Status;
2575 UINT8 SectorCountReg;
2576 UINT8 LBALowReg;
2577 UINT8 LBAMidReg;
2578 UINT8 LBAHighReg;
2579 EFI_ATA_DEVICE_TYPE DeviceType;
2580 UINT8 IdeDevice;
2581 EFI_IDE_REGISTERS *IdeRegisters;
2582 EFI_IDENTIFY_DATA Buffer;
2583
2584 EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
2585 EFI_PCI_IO_PROTOCOL *PciIo;
2586
2587 EFI_ATA_COLLECTIVE_MODE *SupportedModes;
2588 EFI_ATA_TRANSFER_MODE TransferMode;
2589 EFI_ATA_DRIVE_PARMS DriveParameters;
2590
2591 IdeRegisters = &Instance->IdeRegisters[IdeChannel];
2592 IdeInit = Instance->IdeControllerInit;
2593 PciIo = Instance->PciIo;
2594
2595 for (IdeDevice = 0; IdeDevice < EfiIdeMaxDevice; IdeDevice++) {
2596 //
2597 // Send ATA Device Execut Diagnostic command.
2598 // This command should work no matter DRDY is ready or not
2599 //
2600 IdeWritePortB (PciIo, IdeRegisters->CmdOrStatus, ATA_CMD_EXEC_DRIVE_DIAG);
2601
2602 Status = WaitForBSYClear (PciIo, IdeRegisters, 350000000);
2603 if (EFI_ERROR (Status)) {
2604 DEBUG((EFI_D_ERROR, "New detecting method: Send Execute Diagnostic Command: WaitForBSYClear: Status: %d\n", Status));
2605 continue;
2606 }
2607
2608 //
2609 // Select Master or Slave device to get the return signature for ATA DEVICE DIAGNOSTIC cmd.
2610 //
2611 IdeWritePortB (PciIo, IdeRegisters->Head, (UINT8)((IdeDevice << 4) | 0xe0));
2612 //
2613 // Stall for 1 milliseconds.
2614 //
2615 MicroSecondDelay (1000);
2616
2617 SectorCountReg = IdeReadPortB (PciIo, IdeRegisters->SectorCount);
2618 LBALowReg = IdeReadPortB (PciIo, IdeRegisters->SectorNumber);
2619 LBAMidReg = IdeReadPortB (PciIo, IdeRegisters->CylinderLsb);
2620 LBAHighReg = IdeReadPortB (PciIo, IdeRegisters->CylinderMsb);
2621
2622 //
2623 // Refer to ATA/ATAPI 4 Spec, section 9.1
2624 //
2625 if ((SectorCountReg == 0x1) && (LBALowReg == 0x1) && (LBAMidReg == 0x0) && (LBAHighReg == 0x0)) {
2626 DeviceType = EfiIdeHarddisk;
2627 } else if ((LBAMidReg == 0x14) && (LBAHighReg == 0xeb)) {
2628 DeviceType = EfiIdeCdrom;
2629 } else {
2630 continue;
2631 }
2632
2633 //
2634 // Send IDENTIFY cmd to the device to test if it is really attached.
2635 //
2636 if (DeviceType == EfiIdeHarddisk) {
2637 Status = AtaIdentify (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
2638 //
2639 // if identifying ata device is failure, then try to send identify packet cmd.
2640 //
2641 if (EFI_ERROR (Status)) {
2642 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED));
2643
2644 DeviceType = EfiIdeCdrom;
2645 Status = AtaIdentifyPacket (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
2646 }
2647 } else {
2648 Status = AtaIdentifyPacket (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
2649 //
2650 // if identifying atapi device is failure, then try to send identify cmd.
2651 //
2652 if (EFI_ERROR (Status)) {
2653 DeviceType = EfiIdeHarddisk;
2654 Status = AtaIdentify (Instance, IdeChannel, IdeDevice, &Buffer, NULL);
2655 }
2656 }
2657
2658 if (EFI_ERROR (Status)) {
2659 //
2660 // No device is found at this port
2661 //
2662 continue;
2663 }
2664
2665 DEBUG ((EFI_D_INFO, "[%a] channel [%a] [%a] device\n",
2666 (IdeChannel == 1) ? "secondary" : "primary ", (IdeDevice == 1) ? "slave " : "master",
2667 DeviceType == EfiIdeCdrom ? "cdrom " : "harddisk"));
2668 //
2669 // If the device is a hard disk, then try to enable S.M.A.R.T feature
2670 //
2671 if (DeviceType == EfiIdeHarddisk) {
2672 IdeAtaSmartSupport (
2673 Instance,
2674 IdeChannel,
2675 IdeDevice,
2676 &Buffer,
2677 NULL
2678 );
2679 }
2680
2681 //
2682 // Submit identify data to IDE controller init driver
2683 //
2684 IdeInit->SubmitData (IdeInit, IdeChannel, IdeDevice, &Buffer);
2685
2686 //
2687 // Now start to config ide device parameter and transfer mode.
2688 //
2689 Status = IdeInit->CalculateMode (
2690 IdeInit,
2691 IdeChannel,
2692 IdeDevice,
2693 &SupportedModes
2694 );
2695 if (EFI_ERROR (Status)) {
2696 DEBUG ((EFI_D_ERROR, "Calculate Mode Fail, Status = %r\n", Status));
2697 continue;
2698 }
2699
2700 //
2701 // Set best supported PIO mode on this IDE device
2702 //
2703 if (SupportedModes->PioMode.Mode <= EfiAtaPioMode2) {
2704 TransferMode.ModeCategory = EFI_ATA_MODE_DEFAULT_PIO;
2705 } else {
2706 TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;
2707 }
2708
2709 TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);
2710
2711 if (SupportedModes->ExtModeCount == 0){
2712 Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);
2713
2714 if (EFI_ERROR (Status)) {
2715 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
2716 continue;
2717 }
2718 }
2719
2720 //
2721 // Set supported DMA mode on this IDE device. Note that UDMA & MDMA cann't
2722 // be set together. Only one DMA mode can be set to a device. If setting
2723 // DMA mode operation fails, we can continue moving on because we only use
2724 // PIO mode at boot time. DMA modes are used by certain kind of OS booting
2725 //
2726 if (SupportedModes->UdmaMode.Valid) {
2727 TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;
2728 TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);
2729 Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);
2730
2731 if (EFI_ERROR (Status)) {
2732 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
2733 continue;
2734 }
2735 } else if (SupportedModes->MultiWordDmaMode.Valid) {
2736 TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;
2737 TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
2738 Status = SetDeviceTransferMode (Instance, IdeChannel, IdeDevice, &TransferMode, NULL);
2739
2740 if (EFI_ERROR (Status)) {
2741 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
2742 continue;
2743 }
2744 }
2745
2746 //
2747 // Set Parameters for the device:
2748 // 1) Init
2749 // 2) Establish the block count for READ/WRITE MULTIPLE (EXT) command
2750 //
2751 if (DeviceType == EfiIdeHarddisk) {
2752 //
2753 // Init driver parameters
2754 //
2755 DriveParameters.Sector = (UINT8) ((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->sectors_per_track;
2756 DriveParameters.Heads = (UINT8) (((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->heads - 1);
2757 DriveParameters.MultipleSector = (UINT8) ((ATA5_IDENTIFY_DATA *)(&Buffer.AtaData))->multi_sector_cmd_max_sct_cnt;
2758
2759 Status = SetDriveParameters (Instance, IdeChannel, IdeDevice, &DriveParameters, NULL);
2760 }
2761
2762 //
2763 // Set IDE controller Timing Blocks in the PCI Configuration Space
2764 //
2765 IdeInit->SetTiming (IdeInit, IdeChannel, IdeDevice, SupportedModes);
2766
2767 //
2768 // IDE controller and IDE device timing is configured successfully.
2769 // Now insert the device into device list.
2770 //
2771 Status = CreateNewDeviceInfo (Instance, IdeChannel, IdeDevice, DeviceType, &Buffer);
2772 if (EFI_ERROR (Status)) {
2773 continue;
2774 }
2775
2776 if (DeviceType == EfiIdeHarddisk) {
2777 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));
2778 }
2779 }
2780 return EFI_SUCCESS;
2781 }
2782
2783
2784 /**
2785 Initialize ATA host controller at IDE mode.
2786
2787 The function is designed to initialize ATA host controller.
2788
2789 @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
2790
2791 **/
2792 EFI_STATUS
2793 EFIAPI
2794 IdeModeInitialization (
2795 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance
2796 )
2797 {
2798 EFI_STATUS Status;
2799 EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
2800 EFI_PCI_IO_PROTOCOL *PciIo;
2801 UINT8 Channel;
2802 UINT8 IdeChannel;
2803 BOOLEAN ChannelEnabled;
2804 UINT8 MaxDevices;
2805
2806 IdeInit = Instance->IdeControllerInit;
2807 PciIo = Instance->PciIo;
2808 Channel = IdeInit->ChannelCount;
2809
2810 //
2811 // Obtain IDE IO port registers' base addresses
2812 //
2813 Status = GetIdeRegisterIoAddr (PciIo, Instance->IdeRegisters);
2814 if (EFI_ERROR (Status)) {
2815 goto ErrorExit;
2816 }
2817
2818 for (IdeChannel = 0; IdeChannel < Channel; IdeChannel++) {
2819 IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, IdeChannel);
2820
2821 //
2822 // now obtain channel information fron IdeControllerInit protocol.
2823 //
2824 Status = IdeInit->GetChannelInfo (
2825 IdeInit,
2826 IdeChannel,
2827 &ChannelEnabled,
2828 &MaxDevices
2829 );
2830 if (EFI_ERROR (Status)) {
2831 DEBUG ((EFI_D_ERROR, "[GetChannel, Status=%x]", Status));
2832 continue;
2833 }
2834
2835 if (!ChannelEnabled) {
2836 continue;
2837 }
2838
2839 ASSERT (MaxDevices <= 2);
2840 //
2841 // Now inform the IDE Controller Init Module.
2842 //
2843 IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelReset, IdeChannel);
2844
2845 //
2846 // No reset channel function implemented.
2847 //
2848 IdeInit->NotifyPhase (IdeInit, EfiIdeAfterChannelReset, IdeChannel);
2849
2850 //
2851 // Now inform the IDE Controller Init Module.
2852 //
2853 IdeInit->NotifyPhase (IdeInit, EfiIdeBusBeforeDevicePresenceDetection, IdeChannel);
2854
2855 //
2856 // Detect all attached ATA devices and set the transfer mode for each device.
2857 //
2858 DetectAndConfigIdeDevice (Instance, IdeChannel);
2859 }
2860
2861 //
2862 // All configurations done! Notify IdeController to do post initialization
2863 // work such as saving IDE controller PCI settings for S3 resume
2864 //
2865 IdeInit->NotifyPhase (IdeInit, EfiIdeBusPhaseMaximum, 0);
2866
2867 ErrorExit:
2868 return Status;
2869 }
2870
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