MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h

   1 /** @file
   2
   3   This file contains the definination for host controller register operation routines.
   4
   5 Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef _EFI_EHCI_REG_H_
  11 #define _EFI_EHCI_REG_H_
  12
  13 //
  14 // EHCI register offset
  15 //
  16
  17 //
  18 // Capability register offset
  19 //
  20 #define EHC_CAPLENGTH_OFFSET  0      // Capability register length offset
  21 #define EHC_HCSPARAMS_OFFSET  0x04   // Structural Parameters 04-07h
  22 #define EHC_HCCPARAMS_OFFSET  0x08   // Capability parameters offset
  23
  24 //
  25 // Capability register bit definition
  26 //
  27 #define HCSP_NPORTS  0x0F            // Number of root hub port
  28 #define HCSP_PPC     0x10            // Port Power Control
  29 #define HCCP_64BIT   0x01            // 64-bit addressing capability
  30
  31 //
  32 // Operational register offset
  33 //
  34 #define EHC_USBCMD_OFFSET       0x0  // USB command register offset
  35 #define EHC_USBSTS_OFFSET       0x04 // Statue register offset
  36 #define EHC_USBINTR_OFFSET      0x08 // USB interrutp offset
  37 #define EHC_FRINDEX_OFFSET      0x0C // Frame index offset
  38 #define EHC_CTRLDSSEG_OFFSET    0x10 // Control data structure segment offset
  39 #define EHC_FRAME_BASE_OFFSET   0x14 // Frame list base address offset
  40 #define EHC_ASYNC_HEAD_OFFSET   0x18 // Next asynchronous list address offset
  41 #define EHC_CONFIG_FLAG_OFFSET  0x40 // Configure flag register offset
  42 #define EHC_PORT_STAT_OFFSET    0x44 // Port status/control offset
  43
  44 #define EHC_FRAME_LEN  1024
  45
  46 //
  47 // Register bit definition
  48 //
  49 #define CONFIGFLAG_ROUTE_EHC  0x01   // Route port to EHC
  50
  51 #define USBCMD_RUN            0x01     // Run/stop
  52 #define USBCMD_RESET          0x02     // Start the host controller reset
  53 #define USBCMD_ENABLE_PERIOD  0x10     // Enable periodic schedule
  54 #define USBCMD_ENABLE_ASYNC   0x20     // Enable asynchronous schedule
  55 #define USBCMD_IAAD           0x40     // Interrupt on async advance doorbell
  56
  57 #define USBSTS_IAA             0x20    // Interrupt on async advance
  58 #define USBSTS_PERIOD_ENABLED  0x4000  // Periodic schedule status
  59 #define USBSTS_ASYNC_ENABLED   0x8000  // Asynchronous schedule status
  60 #define USBSTS_HALT            0x1000  // Host controller halted
  61 #define USBSTS_SYS_ERROR       0x10    // Host system error
  62 #define USBSTS_INTACK_MASK     0x003F  // Mask for the interrupt ACK, the WC
  63                                        // (write clean) bits in USBSTS register
  64
  65 #define PORTSC_CONN            0x01    // Current Connect Status
  66 #define PORTSC_CONN_CHANGE     0x02    // Connect Status Change
  67 #define PORTSC_ENABLED         0x04    // Port Enable / Disable
  68 #define PORTSC_ENABLE_CHANGE   0x08    // Port Enable / Disable Change
  69 #define PORTSC_OVERCUR         0x10    // Over current Active
  70 #define PORTSC_OVERCUR_CHANGE  0x20    // Over current Change
  71 #define PORSTSC_RESUME         0x40    // Force Port Resume
  72 #define PORTSC_SUSPEND         0x80    // Port Suspend State
  73 #define PORTSC_RESET           0x100   // Port Reset
  74 #define PORTSC_LINESTATE_K     0x400   // Line Status K-state
  75 #define PORTSC_LINESTATE_J     0x800   // Line Status J-state
  76 #define PORTSC_POWER           0x1000  // Port Power
  77 #define PORTSC_OWNER           0x2000  // Port Owner
  78 #define PORTSC_CHANGE_MASK     0x2A    // Mask of the port change bits,
  79                                        // they are WC (write clean)
  80 //
  81 // PCI Configuration Registers
  82 //
  83 #define EHC_BAR_INDEX  0               // how many bytes away from USB_BASE to 0x10
  84
  85 //
  86 // Debug port capability id
  87 //
  88 #define EHC_DEBUG_PORT_CAP_ID  0x0A
  89
  90 #define EHC_LINK_TERMINATED(Link)  (((Link) & 0x01) != 0)
  91
  92 #define EHC_ADDR(High, QhHw32)   \
  93         ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
  94
  95 #define EHCI_IS_DATAIN(EndpointAddr)  EHC_BIT_IS_SET((EndpointAddr), 0x80)
  96
  97 //
  98 // Structure to map the hardware port states to the
  99 // UEFI's port states.
 100 //
 101 typedef struct {
 102   UINT16    HwState;
 103   UINT16    UefiState;
 104 } USB_PORT_STATE_MAP;
 105
 106 //
 107 // Ehci Data and Ctrl Structures
 108 //
 109 #pragma pack(1)
 110 typedef struct {
 111   UINT8    ProgInterface;
 112   UINT8    SubClassCode;
 113   UINT8    BaseCode;
 114 } USB_CLASSC;
 115 #pragma pack()
 116
 117 /**
 118   Read EHCI capability register.
 119
 120   @param  Ehc     The EHCI device.
 121   @param  Offset  Capability register address.
 122
 123   @return The register content.
 124
 125 **/
 126 UINT32
 127 EhcReadCapRegister (
 128   IN  USB2_HC_DEV  *Ehc,
 129   IN  UINT32       Offset
 130   );
 131
 132 /**
 133   Check whether the host controller has an in-use debug port.
 134
 135   @param[in] Ehc         The Enhanced Host Controller to query.
 136
 137   @param[in] PortNumber  If PortNumber is not NULL, then query whether
 138                          PortNumber is an in-use debug port on Ehc. (PortNumber
 139                          is taken in UEFI notation, i.e., zero-based.)
 140                          Otherwise, query whether Ehc has any in-use debug
 141                          port.
 142
 143   @retval TRUE   PortNumber is an in-use debug port on Ehc (if PortNumber is
 144                  not NULL), or some port on Ehc is an in-use debug port
 145                  (otherwise).
 146
 147   @retval FALSE  PortNumber is not an in-use debug port on Ehc (if PortNumber
 148                  is not NULL), or no port on Ehc is an in-use debug port
 149                  (otherwise).
 150 **/
 151 BOOLEAN
 152 EhcIsDebugPortInUse (
 153   IN CONST USB2_HC_DEV  *Ehc,
 154   IN CONST UINT8        *PortNumber OPTIONAL
 155   );
 156
 157 /**
 158   Read EHCI Operation register.
 159
 160   @param  Ehc      The EHCI device.
 161   @param  Offset   The operation register offset.
 162
 163   @return The register content.
 164
 165 **/
 166 UINT32
 167 EhcReadOpReg (
 168   IN  USB2_HC_DEV  *Ehc,
 169   IN  UINT32       Offset
 170   );
 171
 172 /**
 173   Write  the data to the EHCI operation register.
 174
 175   @param  Ehc      The EHCI device.
 176   @param  Offset   EHCI operation register offset.
 177   @param  Data     The data to write.
 178
 179 **/
 180 VOID
 181 EhcWriteOpReg (
 182   IN USB2_HC_DEV  *Ehc,
 183   IN UINT32       Offset,
 184   IN UINT32       Data
 185   );
 186
 187 /**
 188   Set one bit of the operational register while keeping other bits.
 189
 190   @param  Ehc          The EHCI device.
 191   @param  Offset       The offset of the operational register.
 192   @param  Bit          The bit mask of the register to set.
 193
 194 **/
 195 VOID
 196 EhcSetOpRegBit (
 197   IN USB2_HC_DEV  *Ehc,
 198   IN UINT32       Offset,
 199   IN UINT32       Bit
 200   );
 201
 202 /**
 203   Clear one bit of the operational register while keeping other bits.
 204
 205   @param  Ehc          The EHCI device.
 206   @param  Offset       The offset of the operational register.
 207   @param  Bit          The bit mask of the register to clear.
 208
 209 **/
 210 VOID
 211 EhcClearOpRegBit (
 212   IN USB2_HC_DEV  *Ehc,
 213   IN UINT32       Offset,
 214   IN UINT32       Bit
 215   );
 216
 217 /**
 218   Add support for UEFI Over Legacy (UoL) feature, stop
 219   the legacy USB SMI support.
 220
 221   @param  Ehc      The EHCI device.
 222
 223 **/
 224 VOID
 225 EhcClearLegacySupport (
 226   IN USB2_HC_DEV  *Ehc
 227   );
 228
 229 /**
 230   Set door bell and wait it to be ACKed by host controller.
 231   This function is used to synchronize with the hardware.
 232
 233   @param  Ehc          The EHCI device.
 234   @param  Timeout      The time to wait before abort (in millisecond, ms).
 235
 236   @retval EFI_SUCCESS  Synchronized with the hardware.
 237   @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.
 238
 239 **/
 240 EFI_STATUS
 241 EhcSetAndWaitDoorBell (
 242   IN  USB2_HC_DEV  *Ehc,
 243   IN  UINT32       Timeout
 244   );
 245
 246 /**
 247   Clear all the interrutp status bits, these bits are Write-Clean.
 248
 249   @param  Ehc      The EHCI device.
 250
 251 **/
 252 VOID
 253 EhcAckAllInterrupt (
 254   IN  USB2_HC_DEV  *Ehc
 255   );
 256
 257 /**
 258   Whether Ehc is halted.
 259
 260   @param  Ehc     The EHCI device.
 261
 262   @retval TRUE    The controller is halted.
 263   @retval FALSE   It isn't halted.
 264
 265 **/
 266 BOOLEAN
 267 EhcIsHalt (
 268   IN USB2_HC_DEV  *Ehc
 269   );
 270
 271 /**
 272   Whether system error occurred.
 273
 274   @param  Ehc      The EHCI device.
 275
 276   @retval TRUE     System error happened.
 277   @retval FALSE    No system error.
 278
 279 **/
 280 BOOLEAN
 281 EhcIsSysError (
 282   IN USB2_HC_DEV  *Ehc
 283   );
 284
 285 /**
 286   Reset the host controller.
 287
 288   @param  Ehc          The EHCI device.
 289   @param  Timeout      Time to wait before abort (in millisecond, ms).
 290
 291   @retval EFI_SUCCESS  The host controller is reset.
 292   @return Others       Failed to reset the host.
 293
 294 **/
 295 EFI_STATUS
 296 EhcResetHC (
 297   IN USB2_HC_DEV  *Ehc,
 298   IN UINT32       Timeout
 299   );
 300
 301 /**
 302   Halt the host controller.
 303
 304   @param  Ehc          The EHCI device.
 305   @param  Timeout      Time to wait before abort.
 306
 307   @return EFI_SUCCESS  The EHCI is halt.
 308   @return EFI_TIMEOUT  Failed to halt the controller before Timeout.
 309
 310 **/
 311 EFI_STATUS
 312 EhcHaltHC (
 313   IN USB2_HC_DEV  *Ehc,
 314   IN UINT32       Timeout
 315   );
 316
 317 /**
 318   Set the EHCI to run.
 319
 320   @param  Ehc          The EHCI device.
 321   @param  Timeout      Time to wait before abort.
 322
 323   @return EFI_SUCCESS  The EHCI is running.
 324   @return Others       Failed to set the EHCI to run.
 325
 326 **/
 327 EFI_STATUS
 328 EhcRunHC (
 329   IN USB2_HC_DEV  *Ehc,
 330   IN UINT32       Timeout
 331   );
 332
 333 /**
 334   Initialize the HC hardware.
 335   EHCI spec lists the five things to do to initialize the hardware:
 336   1. Program CTRLDSSEGMENT
 337   2. Set USBINTR to enable interrupts
 338   3. Set periodic list base
 339   4. Set USBCMD, interrupt threshold, frame list size etc
 340   5. Write 1 to CONFIGFLAG to route all ports to EHCI
 341
 342   @param  Ehc          The EHCI device.
 343
 344   @return EFI_SUCCESS  The EHCI has come out of halt state.
 345   @return EFI_TIMEOUT  Time out happened.
 346
 347 **/
 348 EFI_STATUS
 349 EhcInitHC (
 350   IN USB2_HC_DEV  *Ehc
 351   );
 352
 353 #endif