MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h

   1 /** @file
   2
   3   This file contains the definination for host controller register operation routines.
   4
   5 Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _EFI_EHCI_REG_H_
  17 #define _EFI_EHCI_REG_H_
  18
  19 //
  20 // EHCI register offset
  21 //
  22
  23
  24 //
  25 // Capability register offset
  26 //
  27 #define EHC_CAPLENGTH_OFFSET    0    // Capability register length offset
  28 #define EHC_HCSPARAMS_OFFSET    0x04 // Structural Parameters 04-07h
  29 #define EHC_HCCPARAMS_OFFSET    0x08 // Capability parameters offset
  30
  31 //
  32 // Capability register bit definition
  33 //
  34 #define HCSP_NPORTS             0x0F // Number of root hub port
  35 #define HCSP_PPC                0x10 // Port Power Control
  36 #define HCCP_64BIT              0x01 // 64-bit addressing capability
  37
  38 //
  39 // Operational register offset
  40 //
  41 #define EHC_USBCMD_OFFSET       0x0  // USB command register offset
  42 #define EHC_USBSTS_OFFSET       0x04 // Statue register offset
  43 #define EHC_USBINTR_OFFSET      0x08 // USB interrutp offset
  44 #define EHC_FRINDEX_OFFSET      0x0C // Frame index offset
  45 #define EHC_CTRLDSSEG_OFFSET    0x10 // Control data structure segment offset
  46 #define EHC_FRAME_BASE_OFFSET   0x14 // Frame list base address offset
  47 #define EHC_ASYNC_HEAD_OFFSET   0x18 // Next asynchronous list address offset
  48 #define EHC_CONFIG_FLAG_OFFSET  0x40 // Configure flag register offset
  49 #define EHC_PORT_STAT_OFFSET    0x44 // Port status/control offset
  50
  51 #define EHC_FRAME_LEN           1024
  52
  53 //
  54 // Register bit definition
  55 //
  56 #define CONFIGFLAG_ROUTE_EHC    0x01 // Route port to EHC
  57
  58 #define USBCMD_RUN              0x01   // Run/stop
  59 #define USBCMD_RESET            0x02   // Start the host controller reset
  60 #define USBCMD_ENABLE_PERIOD    0x10   // Enable periodic schedule
  61 #define USBCMD_ENABLE_ASYNC     0x20   // Enable asynchronous schedule
  62 #define USBCMD_IAAD             0x40   // Interrupt on async advance doorbell
  63
  64 #define USBSTS_IAA              0x20   // Interrupt on async advance
  65 #define USBSTS_PERIOD_ENABLED   0x4000 // Periodic schedule status
  66 #define USBSTS_ASYNC_ENABLED    0x8000 // Asynchronous schedule status
  67 #define USBSTS_HALT             0x1000 // Host controller halted
  68 #define USBSTS_SYS_ERROR        0x10   // Host system error
  69 #define USBSTS_INTACK_MASK      0x003F // Mask for the interrupt ACK, the WC
  70                                        // (write clean) bits in USBSTS register
  71
  72 #define PORTSC_CONN             0x01   // Current Connect Status
  73 #define PORTSC_CONN_CHANGE      0x02   // Connect Status Change
  74 #define PORTSC_ENABLED          0x04   // Port Enable / Disable
  75 #define PORTSC_ENABLE_CHANGE    0x08   // Port Enable / Disable Change
  76 #define PORTSC_OVERCUR          0x10   // Over current Active
  77 #define PORTSC_OVERCUR_CHANGE   0x20   // Over current Change
  78 #define PORSTSC_RESUME          0x40   // Force Port Resume
  79 #define PORTSC_SUSPEND          0x80   // Port Suspend State
  80 #define PORTSC_RESET            0x100  // Port Reset
  81 #define PORTSC_LINESTATE_K      0x400  // Line Status K-state
  82 #define PORTSC_LINESTATE_J      0x800  // Line Status J-state
  83 #define PORTSC_POWER            0x1000 // Port Power
  84 #define PORTSC_OWNER            0x2000 // Port Owner
  85 #define PORTSC_CHANGE_MASK      0x2A   // Mask of the port change bits,
  86                                        // they are WC (write clean)
  87 //
  88 // PCI Configuration Registers
  89 //
  90 #define EHC_BAR_INDEX           0      // how many bytes away from USB_BASE to 0x10
  91
  92 #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
  93
  94 #define EHC_ADDR(High, QhHw32)   \
  95         ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
  96
  97 #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
  98
  99 //
 100 // Structure to map the hardware port states to the
 101 // UEFI's port states.
 102 //
 103 typedef struct {
 104   UINT16                  HwState;
 105   UINT16                  UefiState;
 106 } USB_PORT_STATE_MAP;
 107
 108 //
 109 // Ehci Data and Ctrl Structures
 110 //
 111 #pragma pack(1)
 112 typedef struct {
 113   UINT8                   ProgInterface;
 114   UINT8                   SubClassCode;
 115   UINT8                   BaseCode;
 116 } USB_CLASSC;
 117 #pragma pack()
 118
 119 /**
 120   Read EHCI capability register.
 121
 122   @param  Ehc     The EHCI device.
 123   @param  Offset  Capability register address.
 124
 125   @return The register content.
 126
 127 **/
 128 UINT32
 129 EhcReadCapRegister (
 130   IN  USB2_HC_DEV         *Ehc,
 131   IN  UINT32              Offset
 132   );
 133
 134
 135 /**
 136   Read EHCI Operation register.
 137
 138   @param  Ehc      The EHCI device.
 139   @param  Offset   The operation register offset.
 140
 141   @return The register content.
 142
 143 **/
 144 UINT32
 145 EhcReadOpReg (
 146   IN  USB2_HC_DEV         *Ehc,
 147   IN  UINT32              Offset
 148   );
 149
 150
 151 /**
 152   Write  the data to the EHCI operation register.
 153
 154   @param  Ehc      The EHCI device.
 155   @param  Offset   EHCI operation register offset.
 156   @param  Data     The data to write.
 157
 158 **/
 159 VOID
 160 EhcWriteOpReg (
 161   IN USB2_HC_DEV          *Ehc,
 162   IN UINT32               Offset,
 163   IN UINT32               Data
 164   );
 165
 166 /**
 167   Set one bit of the operational register while keeping other bits.
 168
 169   @param  Ehc          The EHCI device.
 170   @param  Offset       The offset of the operational register.
 171   @param  Bit          The bit mask of the register to set.
 172
 173 **/
 174 VOID
 175 EhcSetOpRegBit (
 176   IN USB2_HC_DEV          *Ehc,
 177   IN UINT32               Offset,
 178   IN UINT32               Bit
 179   );
 180
 181 /**
 182   Clear one bit of the operational register while keeping other bits.
 183
 184   @param  Ehc          The EHCI device.
 185   @param  Offset       The offset of the operational register.
 186   @param  Bit          The bit mask of the register to clear.
 187
 188 **/
 189 VOID
 190 EhcClearOpRegBit (
 191   IN USB2_HC_DEV          *Ehc,
 192   IN UINT32               Offset,
 193   IN UINT32               Bit
 194   );
 195
 196 /**
 197   Add support for UEFI Over Legacy (UoL) feature, stop
 198   the legacy USB SMI support.
 199
 200   @param  Ehc      The EHCI device.
 201
 202 **/
 203 VOID
 204 EhcClearLegacySupport (
 205   IN USB2_HC_DEV          *Ehc
 206   );
 207
 208
 209
 210 /**
 211   Set door bell and wait it to be ACKed by host controller.
 212   This function is used to synchronize with the hardware.
 213
 214   @param  Ehc          The EHCI device.
 215   @param  Timeout      The time to wait before abort (in millisecond, ms).
 216
 217   @retval EFI_SUCCESS  Synchronized with the hardware.
 218   @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.
 219
 220 **/
 221 EFI_STATUS
 222 EhcSetAndWaitDoorBell (
 223   IN  USB2_HC_DEV         *Ehc,
 224   IN  UINT32               Timeout
 225   );
 226
 227
 228 /**
 229   Clear all the interrutp status bits, these bits are Write-Clean.
 230
 231   @param  Ehc      The EHCI device.
 232
 233 **/
 234 VOID
 235 EhcAckAllInterrupt (
 236   IN  USB2_HC_DEV         *Ehc
 237   );
 238
 239
 240
 241 /**
 242   Whether Ehc is halted.
 243
 244   @param  Ehc     The EHCI device.
 245
 246   @retval TRUE    The controller is halted.
 247   @retval FALSE   It isn't halted.
 248
 249 **/
 250 BOOLEAN
 251 EhcIsHalt (
 252   IN USB2_HC_DEV          *Ehc
 253   );
 254
 255
 256 /**
 257   Whether system error occurred.
 258
 259   @param  Ehc      The EHCI device.
 260
 261   @retval TRUE     System error happened.
 262   @retval FALSE    No system error.
 263
 264 **/
 265 BOOLEAN
 266 EhcIsSysError (
 267   IN USB2_HC_DEV          *Ehc
 268   );
 269
 270
 271 /**
 272   Reset the host controller.
 273
 274   @param  Ehc          The EHCI device.
 275   @param  Timeout      Time to wait before abort (in millisecond, ms).
 276
 277   @retval EFI_SUCCESS  The host controller is reset.
 278   @return Others       Failed to reset the host.
 279
 280 **/
 281 EFI_STATUS
 282 EhcResetHC (
 283   IN USB2_HC_DEV          *Ehc,
 284   IN UINT32               Timeout
 285   );
 286
 287
 288 /**
 289   Halt the host controller.
 290
 291   @param  Ehc          The EHCI device.
 292   @param  Timeout      Time to wait before abort.
 293
 294   @return EFI_SUCCESS  The EHCI is halt.
 295   @return EFI_TIMEOUT  Failed to halt the controller before Timeout.
 296
 297 **/
 298 EFI_STATUS
 299 EhcHaltHC (
 300   IN USB2_HC_DEV         *Ehc,
 301   IN UINT32              Timeout
 302   );
 303
 304
 305 /**
 306   Set the EHCI to run.
 307
 308   @param  Ehc          The EHCI device.
 309   @param  Timeout      Time to wait before abort.
 310
 311   @return EFI_SUCCESS  The EHCI is running.
 312   @return Others       Failed to set the EHCI to run.
 313
 314 **/
 315 EFI_STATUS
 316 EhcRunHC (
 317   IN USB2_HC_DEV          *Ehc,
 318   IN UINT32               Timeout
 319   );
 320
 321
 322
 323 /**
 324   Initialize the HC hardware.
 325   EHCI spec lists the five things to do to initialize the hardware:
 326   1. Program CTRLDSSEGMENT
 327   2. Set USBINTR to enable interrupts
 328   3. Set periodic list base
 329   4. Set USBCMD, interrupt threshold, frame list size etc
 330   5. Write 1 to CONFIGFLAG to route all ports to EHCI
 331
 332   @param  Ehc          The EHCI device.
 333
 334   @return EFI_SUCCESS  The EHCI has come out of halt state.
 335   @return EFI_TIMEOUT  Time out happened.
 336
 337 **/
 338 EFI_STATUS
 339 EhcInitHC (
 340   IN USB2_HC_DEV          *Ehc
 341   );
 342
 343 #endif