MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h

   1 /** @file
   2
   3   This file contains the definination for host controller register operation routines.
   4
   5 Copyright (c) 2007 - 2009, Intel Corporation
   6 All rights reserved. This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _EFI_EHCI_REG_H_
  17 #define _EFI_EHCI_REG_H_
  18
  19
  20 typedef enum {
  21   //
  22   // Capability register offset
  23   //
  24   EHC_CAPLENGTH_OFFSET    = 0,    // Capability register length offset
  25   EHC_HCSPARAMS_OFFSET    = 0x04, // Structural Parameters 04-07h
  26   EHC_HCCPARAMS_OFFSET    = 0x08, // Capability parameters offset
  27
  28   //
  29   // Capability register bit definition
  30   //
  31   HCSP_NPORTS             = 0x0F, // Number of root hub port
  32   HCCP_64BIT              = 0x01, // 64-bit addressing capability
  33
  34   //
  35   // Operational register offset
  36   //
  37   EHC_USBCMD_OFFSET       = 0x0,  // USB command register offset
  38   EHC_USBSTS_OFFSET       = 0x04, // Statue register offset
  39   EHC_USBINTR_OFFSET      = 0x08, // USB interrutp offset
  40   EHC_FRINDEX_OFFSET      = 0x0C, // Frame index offset
  41   EHC_CTRLDSSEG_OFFSET    = 0x10, // Control data structure segment offset
  42   EHC_FRAME_BASE_OFFSET   = 0x14, // Frame list base address offset
  43   EHC_ASYNC_HEAD_OFFSET   = 0x18, // Next asynchronous list address offset
  44   EHC_CONFIG_FLAG_OFFSET  = 0x40, // Configure flag register offset
  45   EHC_PORT_STAT_OFFSET    = 0x44, // Port status/control offset
  46
  47   EHC_FRAME_LEN           = 1024,
  48
  49   //
  50   // Register bit definition
  51   //
  52   CONFIGFLAG_ROUTE_EHC    = 0x01, // Route port to EHC
  53
  54   USBCMD_RUN              = 0x01,   // Run/stop
  55   USBCMD_RESET            = 0x02,   // Start the host controller reset
  56   USBCMD_ENABLE_PERIOD    = 0x10,   // Enable periodic schedule
  57   USBCMD_ENABLE_ASYNC     = 0x20,   // Enable asynchronous schedule
  58   USBCMD_IAAD             = 0x40,   // Interrupt on async advance doorbell
  59
  60   USBSTS_IAA              = 0x20,   // Interrupt on async advance
  61   USBSTS_PERIOD_ENABLED   = 0x4000, // Periodic schedule status
  62   USBSTS_ASYNC_ENABLED    = 0x8000, // Asynchronous schedule status
  63   USBSTS_HALT             = 0x1000, // Host controller halted
  64   USBSTS_SYS_ERROR        = 0x10,   // Host system error
  65   USBSTS_INTACK_MASK      = 0x003F, // Mask for the interrupt ACK, the WC
  66                                     // (write clean) bits in USBSTS register
  67
  68   PORTSC_CONN             = 0x01,   // Current Connect Status
  69   PORTSC_CONN_CHANGE      = 0x02,   // Connect Status Change
  70   PORTSC_ENABLED          = 0x04,   // Port Enable / Disable
  71   PORTSC_ENABLE_CHANGE    = 0x08,   // Port Enable / Disable Change
  72   PORTSC_OVERCUR          = 0x10,   // Over current Active
  73   PORTSC_OVERCUR_CHANGE   = 0x20,   // Over current Change
  74   PORSTSC_RESUME          = 0x40,   // Force Port Resume
  75   PORTSC_SUSPEND          = 0x80,   // Port Suspend State
  76   PORTSC_RESET            = 0x100,  // Port Reset
  77   PORTSC_LINESTATE_K      = 0x400,  // Line Status K-state
  78   PORTSC_LINESTATE_J      = 0x800,  // Line Status J-state
  79   PORTSC_POWER            = 0x1000, // Port Power
  80   PORTSC_OWNER            = 0x2000, // Port Owner
  81   PORTSC_CHANGE_MASK      = 0x2A,   // Mask of the port change bits,
  82                                     // they are WC (write clean)
  83   //
  84   // PCI Configuration Registers
  85   //
  86   EHC_BAR_INDEX           = 0 /* how many bytes away from USB_BASE to 0x10 */
  87 }EHCI_REGISTER_OFFSET;
  88
  89 #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0)
  90
  91 #define EHC_ADDR(High, QhHw32)   \
  92         ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0)))
  93
  94 #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80)
  95
  96 //
  97 // Structure to map the hardware port states to the
  98 // UEFI's port states.
  99 //
 100 typedef struct {
 101   UINT16                  HwState;
 102   UINT16                  UefiState;
 103 } USB_PORT_STATE_MAP;
 104
 105 //
 106 // Ehci Data and Ctrl Structures
 107 //
 108 #pragma pack(1)
 109 typedef struct {
 110   UINT8                   PI;
 111   UINT8                   SubClassCode;
 112   UINT8                   BaseCode;
 113 } USB_CLASSC;
 114 #pragma pack()
 115
 116 /**
 117   Read EHCI capability register.
 118
 119   @param  Ehc     The EHCI device.
 120   @param  Offset  Capability register address.
 121
 122   @return The register content.
 123
 124 **/
 125 UINT32
 126 EhcReadCapRegister (
 127   IN  USB2_HC_DEV         *Ehc,
 128   IN  UINT32              Offset
 129   );
 130
 131
 132 /**
 133   Read EHCI Operation register.
 134
 135   @param  Ehc      The EHCI device.
 136   @param  Offset   The operation register offset.
 137
 138   @return The register content.
 139
 140 **/
 141 UINT32
 142 EhcReadOpReg (
 143   IN  USB2_HC_DEV         *Ehc,
 144   IN  UINT32              Offset
 145   );
 146
 147
 148 /**
 149   Write  the data to the EHCI operation register.
 150
 151   @param  Ehc      The EHCI device.
 152   @param  Offset   EHCI operation register offset.
 153   @param  Data     The data to write.
 154
 155 **/
 156 VOID
 157 EhcWriteOpReg (
 158   IN USB2_HC_DEV          *Ehc,
 159   IN UINT32               Offset,
 160   IN UINT32               Data
 161   );
 162
 163
 164 /**
 165   Add support for UEFI Over Legacy (UoL) feature, stop
 166   the legacy USB SMI support.
 167
 168   @param  Ehc      The EHCI device.
 169
 170 **/
 171 VOID
 172 EhcClearLegacySupport (
 173   IN USB2_HC_DEV          *Ehc
 174   );
 175
 176
 177
 178 /**
 179   Set door bell and wait it to be ACKed by host controller.
 180   This function is used to synchronize with the hardware.
 181
 182   @param  Ehc          The EHCI device.
 183   @param  Timeout      The time to wait before abort (in millisecond, ms).
 184
 185   @retval EFI_SUCCESS  Synchronized with the hardware.
 186   @retval EFI_TIMEOUT  Time out happened while waiting door bell to set.
 187
 188 **/
 189 EFI_STATUS
 190 EhcSetAndWaitDoorBell (
 191   IN  USB2_HC_DEV         *Ehc,
 192   IN  UINT32               Timeout
 193   );
 194
 195
 196 /**
 197   Clear all the interrutp status bits, these bits are Write-Clean.
 198
 199   @param  Ehc      The EHCI device.
 200
 201 **/
 202 VOID
 203 EhcAckAllInterrupt (
 204   IN  USB2_HC_DEV         *Ehc
 205   );
 206
 207
 208
 209 /**
 210   Whether Ehc is halted.
 211
 212   @param  Ehc     The EHCI device.
 213
 214   @retval TRUE    The controller is halted.
 215   @retval FALSE   It isn't halted.
 216
 217 **/
 218 BOOLEAN
 219 EhcIsHalt (
 220   IN USB2_HC_DEV          *Ehc
 221   );
 222
 223
 224 /**
 225   Whether system error occurred.
 226
 227   @param  Ehc      The EHCI device.
 228
 229   @retval TRUE     System error happened.
 230   @retval FALSE    No system error.
 231
 232 **/
 233 BOOLEAN
 234 EhcIsSysError (
 235   IN USB2_HC_DEV          *Ehc
 236   );
 237
 238
 239 /**
 240   Reset the host controller.
 241
 242   @param  Ehc          The EHCI device.
 243   @param  Timeout      Time to wait before abort (in millisecond, ms).
 244
 245   @retval EFI_SUCCESS  The host controller is reset.
 246   @return Others       Failed to reset the host.
 247
 248 **/
 249 EFI_STATUS
 250 EhcResetHC (
 251   IN USB2_HC_DEV          *Ehc,
 252   IN UINT32               Timeout
 253   );
 254
 255
 256 /**
 257   Halt the host controller.
 258
 259   @param  Ehc          The EHCI device.
 260   @param  Timeout      Time to wait before abort.
 261
 262   @return EFI_SUCCESS  The EHCI is halt.
 263   @return EFI_TIMEOUT  Failed to halt the controller before Timeout.
 264
 265 **/
 266 EFI_STATUS
 267 EhcHaltHC (
 268   IN USB2_HC_DEV         *Ehc,
 269   IN UINT32              Timeout
 270   );
 271
 272
 273 /**
 274   Set the EHCI to run.
 275
 276   @param  Ehc          The EHCI device.
 277   @param  Timeout      Time to wait before abort.
 278
 279   @return EFI_SUCCESS  The EHCI is running.
 280   @return Others       Failed to set the EHCI to run.
 281
 282 **/
 283 EFI_STATUS
 284 EhcRunHC (
 285   IN USB2_HC_DEV          *Ehc,
 286   IN UINT32               Timeout
 287   );
 288
 289
 290
 291 /**
 292   Initialize the HC hardware.
 293   EHCI spec lists the five things to do to initialize the hardware:
 294   1. Program CTRLDSSEGMENT
 295   2. Set USBINTR to enable interrupts
 296   3. Set periodic list base
 297   4. Set USBCMD, interrupt threshold, frame list size etc
 298   5. Write 1 to CONFIGFLAG to route all ports to EHCI
 299
 300   @param  Ehc          The EHCI device.
 301
 302   @return EFI_SUCCESS  The EHCI has come out of halt state.
 303   @return EFI_TIMEOUT  Time out happened.
 304
 305 **/
 306 EFI_STATUS
 307 EhcInitHC (
 308   IN USB2_HC_DEV          *Ehc
 309   );
 310
 311 #endif