]> git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
projects / mirror_edk2.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
MdeModulePkg/NvmExpressDxe: Expose EFI_NVM_EXPRESS_PASS_THRU protocol
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / NvmExpressDxe / NvmExpressHci.c
1 /** @file
2 NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows
3 NVM Express specification.
4
5 Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include "NvmExpress.h"
17
18 /**
19 Read Nvm Express controller capability register.
20
21 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
22 @param Cap The buffer used to store capability register content.
23
24 @return EFI_SUCCESS Successfully read the controller capability register content.
25 @return EFI_DEVICE_ERROR Fail to read the controller capability register.
26
27 **/
28 EFI_STATUS
29 ReadNvmeControllerCapabilities (
30 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
31 IN NVME_CAP *Cap
32 )
33 {
34 EFI_PCI_IO_PROTOCOL *PciIo;
35 EFI_STATUS Status;
36 UINT64 Data;
37
38 PciIo = Private->PciIo;
39 Status = PciIo->Mem.Read (
40 PciIo,
41 EfiPciIoWidthUint32,
42 NVME_BAR,
43 NVME_CAP_OFFSET,
44 2,
45 &Data
46 );
47
48 if (EFI_ERROR(Status)) {
49 return Status;
50 }
51
52 WriteUnaligned64 ((UINT64*)Cap, Data);
53 return EFI_SUCCESS;
54 }
55
56 /**
57 Read Nvm Express controller configuration register.
58
59 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
60 @param Cc The buffer used to store configuration register content.
61
62 @return EFI_SUCCESS Successfully read the controller configuration register content.
63 @return EFI_DEVICE_ERROR Fail to read the controller configuration register.
64
65 **/
66 EFI_STATUS
67 ReadNvmeControllerConfiguration (
68 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
69 IN NVME_CC *Cc
70 )
71 {
72 EFI_PCI_IO_PROTOCOL *PciIo;
73 EFI_STATUS Status;
74 UINT32 Data;
75
76 PciIo = Private->PciIo;
77 Status = PciIo->Mem.Read (
78 PciIo,
79 EfiPciIoWidthUint32,
80 NVME_BAR,
81 NVME_CC_OFFSET,
82 1,
83 &Data
84 );
85
86 if (EFI_ERROR(Status)) {
87 return Status;
88 }
89
90 WriteUnaligned32 ((UINT32*)Cc, Data);
91 return EFI_SUCCESS;
92 }
93
94 /**
95 Write Nvm Express controller configuration register.
96
97 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
98 @param Cc The buffer used to store the content to be written into configuration register.
99
100 @return EFI_SUCCESS Successfully write data into the controller configuration register.
101 @return EFI_DEVICE_ERROR Fail to write data into the controller configuration register.
102
103 **/
104 EFI_STATUS
105 WriteNvmeControllerConfiguration (
106 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
107 IN NVME_CC *Cc
108 )
109 {
110 EFI_PCI_IO_PROTOCOL *PciIo;
111 EFI_STATUS Status;
112 UINT32 Data;
113
114 PciIo = Private->PciIo;
115 Data = ReadUnaligned32 ((UINT32*)Cc);
116 Status = PciIo->Mem.Write (
117 PciIo,
118 EfiPciIoWidthUint32,
119 NVME_BAR,
120 NVME_CC_OFFSET,
121 1,
122 &Data
123 );
124
125 if (EFI_ERROR(Status)) {
126 return Status;
127 }
128
129 DEBUG ((EFI_D_INFO, "Cc.En: %d\n", Cc->En));
130 DEBUG ((EFI_D_INFO, "Cc.Css: %d\n", Cc->Css));
131 DEBUG ((EFI_D_INFO, "Cc.Mps: %d\n", Cc->Mps));
132 DEBUG ((EFI_D_INFO, "Cc.Ams: %d\n", Cc->Ams));
133 DEBUG ((EFI_D_INFO, "Cc.Shn: %d\n", Cc->Shn));
134 DEBUG ((EFI_D_INFO, "Cc.Iosqes: %d\n", Cc->Iosqes));
135 DEBUG ((EFI_D_INFO, "Cc.Iocqes: %d\n", Cc->Iocqes));
136
137 return EFI_SUCCESS;
138 }
139
140 /**
141 Read Nvm Express controller status register.
142
143 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
144 @param Csts The buffer used to store status register content.
145
146 @return EFI_SUCCESS Successfully read the controller status register content.
147 @return EFI_DEVICE_ERROR Fail to read the controller status register.
148
149 **/
150 EFI_STATUS
151 ReadNvmeControllerStatus (
152 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
153 IN NVME_CSTS *Csts
154 )
155 {
156 EFI_PCI_IO_PROTOCOL *PciIo;
157 EFI_STATUS Status;
158 UINT32 Data;
159
160 PciIo = Private->PciIo;
161 Status = PciIo->Mem.Read (
162 PciIo,
163 EfiPciIoWidthUint32,
164 NVME_BAR,
165 NVME_CSTS_OFFSET,
166 1,
167 &Data
168 );
169
170 if (EFI_ERROR(Status)) {
171 return Status;
172 }
173
174 WriteUnaligned32 ((UINT32*)Csts, Data);
175 return EFI_SUCCESS;
176 }
177
178 /**
179 Read Nvm Express admin queue attributes register.
180
181 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
182 @param Aqa The buffer used to store admin queue attributes register content.
183
184 @return EFI_SUCCESS Successfully read the admin queue attributes register content.
185 @return EFI_DEVICE_ERROR Fail to read the admin queue attributes register.
186
187 **/
188 EFI_STATUS
189 ReadNvmeAdminQueueAttributes (
190 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
191 IN NVME_AQA *Aqa
192 )
193 {
194 EFI_PCI_IO_PROTOCOL *PciIo;
195 EFI_STATUS Status;
196 UINT32 Data;
197
198 PciIo = Private->PciIo;
199 Status = PciIo->Mem.Read (
200 PciIo,
201 EfiPciIoWidthUint32,
202 NVME_BAR,
203 NVME_AQA_OFFSET,
204 1,
205 &Data
206 );
207
208 if (EFI_ERROR(Status)) {
209 return Status;
210 }
211
212 WriteUnaligned32 ((UINT32*)Aqa, Data);
213 return EFI_SUCCESS;
214 }
215
216 /**
217 Write Nvm Express admin queue attributes register.
218
219 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
220 @param Aqa The buffer used to store the content to be written into admin queue attributes register.
221
222 @return EFI_SUCCESS Successfully write data into the admin queue attributes register.
223 @return EFI_DEVICE_ERROR Fail to write data into the admin queue attributes register.
224
225 **/
226 EFI_STATUS
227 WriteNvmeAdminQueueAttributes (
228 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
229 IN NVME_AQA *Aqa
230 )
231 {
232 EFI_PCI_IO_PROTOCOL *PciIo;
233 EFI_STATUS Status;
234 UINT32 Data;
235
236 PciIo = Private->PciIo;
237 Data = ReadUnaligned32 ((UINT32*)Aqa);
238 Status = PciIo->Mem.Write (
239 PciIo,
240 EfiPciIoWidthUint32,
241 NVME_BAR,
242 NVME_AQA_OFFSET,
243 1,
244 &Data
245 );
246
247 if (EFI_ERROR(Status)) {
248 return Status;
249 }
250
251 DEBUG ((EFI_D_INFO, "Aqa.Asqs: %d\n", Aqa->Asqs));
252 DEBUG ((EFI_D_INFO, "Aqa.Acqs: %d\n", Aqa->Acqs));
253
254 return EFI_SUCCESS;
255 }
256
257 /**
258 Read Nvm Express admin submission queue base address register.
259
260 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
261 @param Asq The buffer used to store admin submission queue base address register content.
262
263 @return EFI_SUCCESS Successfully read the admin submission queue base address register content.
264 @return EFI_DEVICE_ERROR Fail to read the admin submission queue base address register.
265
266 **/
267 EFI_STATUS
268 ReadNvmeAdminSubmissionQueueBaseAddress (
269 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
270 IN NVME_ASQ *Asq
271 )
272 {
273 EFI_PCI_IO_PROTOCOL *PciIo;
274 EFI_STATUS Status;
275 UINT64 Data;
276
277 PciIo = Private->PciIo;
278 Status = PciIo->Mem.Read (
279 PciIo,
280 EfiPciIoWidthUint32,
281 NVME_BAR,
282 NVME_ASQ_OFFSET,
283 2,
284 &Data
285 );
286
287 if (EFI_ERROR(Status)) {
288 return Status;
289 }
290
291 WriteUnaligned64 ((UINT64*)Asq, Data);
292 return EFI_SUCCESS;
293 }
294
295 /**
296 Write Nvm Express admin submission queue base address register.
297
298 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
299 @param Asq The buffer used to store the content to be written into admin submission queue base address register.
300
301 @return EFI_SUCCESS Successfully write data into the admin submission queue base address register.
302 @return EFI_DEVICE_ERROR Fail to write data into the admin submission queue base address register.
303
304 **/
305 EFI_STATUS
306 WriteNvmeAdminSubmissionQueueBaseAddress (
307 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
308 IN NVME_ASQ *Asq
309 )
310 {
311 EFI_PCI_IO_PROTOCOL *PciIo;
312 EFI_STATUS Status;
313 UINT64 Data;
314
315 PciIo = Private->PciIo;
316 Data = ReadUnaligned64 ((UINT64*)Asq);
317
318 Status = PciIo->Mem.Write (
319 PciIo,
320 EfiPciIoWidthUint32,
321 NVME_BAR,
322 NVME_ASQ_OFFSET,
323 2,
324 &Data
325 );
326
327 if (EFI_ERROR(Status)) {
328 return Status;
329 }
330
331 DEBUG ((EFI_D_INFO, "Asq.Asqb: %lx\n", Asq->Asqb));
332
333 return EFI_SUCCESS;
334 }
335
336 /**
337 Read Nvm Express admin completion queue base address register.
338
339 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
340 @param Acq The buffer used to store admin completion queue base address register content.
341
342 @return EFI_SUCCESS Successfully read the admin completion queue base address register content.
343 @return EFI_DEVICE_ERROR Fail to read the admin completion queue base address register.
344
345 **/
346 EFI_STATUS
347 ReadNvmeAdminCompletionQueueBaseAddress (
348 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
349 IN NVME_ACQ *Acq
350 )
351 {
352 EFI_PCI_IO_PROTOCOL *PciIo;
353 EFI_STATUS Status;
354 UINT64 Data;
355
356 PciIo = Private->PciIo;
357
358 Status = PciIo->Mem.Read (
359 PciIo,
360 EfiPciIoWidthUint32,
361 NVME_BAR,
362 NVME_ACQ_OFFSET,
363 2,
364 &Data
365 );
366
367 if (EFI_ERROR(Status)) {
368 return Status;
369 }
370
371 WriteUnaligned64 ((UINT64*)Acq, Data);
372 return EFI_SUCCESS;
373 }
374
375 /**
376 Write Nvm Express admin completion queue base address register.
377
378 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
379 @param Acq The buffer used to store the content to be written into admin completion queue base address register.
380
381 @return EFI_SUCCESS Successfully write data into the admin completion queue base address register.
382 @return EFI_DEVICE_ERROR Fail to write data into the admin completion queue base address register.
383
384 **/
385 EFI_STATUS
386 WriteNvmeAdminCompletionQueueBaseAddress (
387 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
388 IN NVME_ACQ *Acq
389 )
390 {
391 EFI_PCI_IO_PROTOCOL *PciIo;
392 EFI_STATUS Status;
393 UINT64 Data;
394
395 PciIo = Private->PciIo;
396 Data = ReadUnaligned64 ((UINT64*)Acq);
397
398 Status = PciIo->Mem.Write (
399 PciIo,
400 EfiPciIoWidthUint32,
401 NVME_BAR,
402 NVME_ACQ_OFFSET,
403 2,
404 &Data
405 );
406
407 if (EFI_ERROR(Status)) {
408 return Status;
409 }
410
411 DEBUG ((EFI_D_INFO, "Acq.Acqb: %lxh\n", Acq->Acqb));
412
413 return EFI_SUCCESS;
414 }
415
416 /**
417 Disable the Nvm Express controller.
418
419 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
420
421 @return EFI_SUCCESS Successfully disable the controller.
422 @return EFI_DEVICE_ERROR Fail to disable the controller.
423
424 **/
425 EFI_STATUS
426 NvmeDisableController (
427 IN NVME_CONTROLLER_PRIVATE_DATA *Private
428 )
429 {
430 NVME_CC Cc;
431 NVME_CSTS Csts;
432 EFI_STATUS Status;
433 UINT32 Index;
434 UINT8 Timeout;
435
436 //
437 // Read Controller Configuration Register.
438 //
439 Status = ReadNvmeControllerConfiguration (Private, &Cc);
440 if (EFI_ERROR(Status)) {
441 return Status;
442 }
443
444 Cc.En = 0;
445
446 //
447 // Disable the controller.
448 //
449 Status = WriteNvmeControllerConfiguration (Private, &Cc);
450
451 if (EFI_ERROR(Status)) {
452 return Status;
453 }
454
455 //
456 // Cap.To specifies max delay time in 500ms increments for Csts.Rdy to transition from 1 to 0 after
457 // Cc.Enable transition from 1 to 0. Loop produces a 1 millisecond delay per itteration, up to 500 * Cap.To.
458 //
459 if (Private->Cap.To == 0) {
460 Timeout = 1;
461 } else {
462 Timeout = Private->Cap.To;
463 }
464
465 for(Index = (Timeout * 500); Index != 0; --Index) {
466 gBS->Stall(1000);
467
468 //
469 // Check if the controller is initialized
470 //
471 Status = ReadNvmeControllerStatus (Private, &Csts);
472
473 if (EFI_ERROR(Status)) {
474 return Status;
475 }
476
477 if (Csts.Rdy == 0) {
478 break;
479 }
480 }
481
482 if (Index == 0) {
483 Status = EFI_DEVICE_ERROR;
484 }
485
486 DEBUG ((EFI_D_INFO, "NVMe controller is disabled with status [%r].\n", Status));
487 return Status;
488 }
489
490 /**
491 Enable the Nvm Express controller.
492
493 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
494
495 @return EFI_SUCCESS Successfully enable the controller.
496 @return EFI_DEVICE_ERROR Fail to enable the controller.
497 @return EFI_TIMEOUT Fail to enable the controller in given time slot.
498
499 **/
500 EFI_STATUS
501 NvmeEnableController (
502 IN NVME_CONTROLLER_PRIVATE_DATA *Private
503 )
504 {
505 NVME_CC Cc;
506 NVME_CSTS Csts;
507 EFI_STATUS Status;
508 UINT32 Index;
509 UINT8 Timeout;
510
511 //
512 // Enable the controller.
513 // CC.AMS, CC.MPS and CC.CSS are all set to 0.
514 //
515 ZeroMem (&Cc, sizeof (NVME_CC));
516 Cc.En = 1;
517 Status = WriteNvmeControllerConfiguration (Private, &Cc);
518
519 if (EFI_ERROR(Status)) {
520 return Status;
521 }
522
523 //
524 // Cap.To specifies max delay time in 500ms increments for Csts.Rdy to set after
525 // Cc.Enable. Loop produces a 1 millisecond delay per itteration, up to 500 * Cap.To.
526 //
527 if (Private->Cap.To == 0) {
528 Timeout = 1;
529 } else {
530 Timeout = Private->Cap.To;
531 }
532
533 for(Index = (Timeout * 500); Index != 0; --Index) {
534 gBS->Stall(1000);
535
536 //
537 // Check if the controller is initialized
538 //
539 Status = ReadNvmeControllerStatus (Private, &Csts);
540
541 if (EFI_ERROR(Status)) {
542 return Status;
543 }
544
545 if (Csts.Rdy) {
546 break;
547 }
548 }
549
550 if (Index == 0) {
551 Status = EFI_TIMEOUT;
552 }
553
554 DEBUG ((EFI_D_INFO, "NVMe controller is enabled with status [%r].\n", Status));
555 return Status;
556 }
557
558 /**
559 Get identify controller data.
560
561 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
562 @param Buffer The buffer used to store the identify controller data.
563
564 @return EFI_SUCCESS Successfully get the identify controller data.
565 @return EFI_DEVICE_ERROR Fail to get the identify controller data.
566
567 **/
568 EFI_STATUS
569 NvmeIdentifyController (
570 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
571 IN VOID *Buffer
572 )
573 {
574 EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
575 EFI_NVM_EXPRESS_COMMAND Command;
576 EFI_NVM_EXPRESS_COMPLETION Completion;
577 EFI_STATUS Status;
578
579 ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
580 ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
581 ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
582
583 Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_OPC;
584 //
585 // According to Nvm Express 1.1 spec Figure 38, When not used, the field shall be cleared to 0h.
586 // For the Identify command, the Namespace Identifier is only used for the Namespace data structure.
587 //
588 Command.Nsid = 0;
589
590 CommandPacket.NvmeCmd = &Command;
591 CommandPacket.NvmeCompletion = &Completion;
592 CommandPacket.TransferBuffer = Buffer;
593 CommandPacket.TransferLength = sizeof (NVME_ADMIN_CONTROLLER_DATA);
594 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
595 CommandPacket.QueueType = NVME_ADMIN_QUEUE;
596 //
597 // Set bit 0 (Cns bit) to 1 to identify a controller
598 //
599 Command.Cdw10 = 1;
600 Command.Flags = CDW10_VALID;
601
602 Status = Private->Passthru.PassThru (
603 &Private->Passthru,
604 NVME_CONTROLLER_ID,
605 &CommandPacket,
606 NULL
607 );
608
609 return Status;
610 }
611
612 /**
613 Get specified identify namespace data.
614
615 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
616 @param NamespaceId The specified namespace identifier.
617 @param Buffer The buffer used to store the identify namespace data.
618
619 @return EFI_SUCCESS Successfully get the identify namespace data.
620 @return EFI_DEVICE_ERROR Fail to get the identify namespace data.
621
622 **/
623 EFI_STATUS
624 NvmeIdentifyNamespace (
625 IN NVME_CONTROLLER_PRIVATE_DATA *Private,
626 IN UINT32 NamespaceId,
627 IN VOID *Buffer
628 )
629 {
630 EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
631 EFI_NVM_EXPRESS_COMMAND Command;
632 EFI_NVM_EXPRESS_COMPLETION Completion;
633 EFI_STATUS Status;
634
635 ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
636 ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
637 ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
638
639 CommandPacket.NvmeCmd = &Command;
640 CommandPacket.NvmeCompletion = &Completion;
641
642 Command.Cdw0.Opcode = NVME_ADMIN_IDENTIFY_OPC;
643 Command.Nsid = NamespaceId;
644 CommandPacket.TransferBuffer = Buffer;
645 CommandPacket.TransferLength = sizeof (NVME_ADMIN_NAMESPACE_DATA);
646 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
647 CommandPacket.QueueType = NVME_ADMIN_QUEUE;
648 //
649 // Set bit 0 (Cns bit) to 1 to identify a namespace
650 //
651 CommandPacket.NvmeCmd->Cdw10 = 0;
652 CommandPacket.NvmeCmd->Flags = CDW10_VALID;
653
654 Status = Private->Passthru.PassThru (
655 &Private->Passthru,
656 NamespaceId,
657 &CommandPacket,
658 NULL
659 );
660
661 return Status;
662 }
663
664 /**
665 Create io completion queue.
666
667 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
668
669 @return EFI_SUCCESS Successfully create io completion queue.
670 @return EFI_DEVICE_ERROR Fail to create io completion queue.
671
672 **/
673 EFI_STATUS
674 NvmeCreateIoCompletionQueue (
675 IN NVME_CONTROLLER_PRIVATE_DATA *Private
676 )
677 {
678 EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
679 EFI_NVM_EXPRESS_COMMAND Command;
680 EFI_NVM_EXPRESS_COMPLETION Completion;
681 EFI_STATUS Status;
682 NVME_ADMIN_CRIOCQ CrIoCq;
683
684 ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
685 ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
686 ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
687 ZeroMem (&CrIoCq, sizeof(NVME_ADMIN_CRIOCQ));
688
689 CommandPacket.NvmeCmd = &Command;
690 CommandPacket.NvmeCompletion = &Completion;
691
692 Command.Cdw0.Opcode = NVME_ADMIN_CRIOCQ_OPC;
693 CommandPacket.TransferBuffer = Private->CqBufferPciAddr[1];
694 CommandPacket.TransferLength = EFI_PAGE_SIZE;
695 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
696 CommandPacket.QueueType = NVME_ADMIN_QUEUE;
697
698 CrIoCq.Qid = NVME_IO_QUEUE;
699 CrIoCq.Qsize = NVME_CCQ_SIZE;
700 CrIoCq.Pc = 1;
701 CopyMem (&CommandPacket.NvmeCmd->Cdw10, &CrIoCq, sizeof (NVME_ADMIN_CRIOCQ));
702 CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID;
703
704 Status = Private->Passthru.PassThru (
705 &Private->Passthru,
706 0,
707 &CommandPacket,
708 NULL
709 );
710
711 return Status;
712 }
713
714 /**
715 Create io submission queue.
716
717 @param Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
718
719 @return EFI_SUCCESS Successfully create io submission queue.
720 @return EFI_DEVICE_ERROR Fail to create io submission queue.
721
722 **/
723 EFI_STATUS
724 NvmeCreateIoSubmissionQueue (
725 IN NVME_CONTROLLER_PRIVATE_DATA *Private
726 )
727 {
728 EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET CommandPacket;
729 EFI_NVM_EXPRESS_COMMAND Command;
730 EFI_NVM_EXPRESS_COMPLETION Completion;
731 EFI_STATUS Status;
732 NVME_ADMIN_CRIOSQ CrIoSq;
733
734 ZeroMem (&CommandPacket, sizeof(EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET));
735 ZeroMem (&Command, sizeof(EFI_NVM_EXPRESS_COMMAND));
736 ZeroMem (&Completion, sizeof(EFI_NVM_EXPRESS_COMPLETION));
737 ZeroMem (&CrIoSq, sizeof(NVME_ADMIN_CRIOSQ));
738
739 CommandPacket.NvmeCmd = &Command;
740 CommandPacket.NvmeCompletion = &Completion;
741
742 Command.Cdw0.Opcode = NVME_ADMIN_CRIOSQ_OPC;
743 CommandPacket.TransferBuffer = Private->SqBufferPciAddr[1];
744 CommandPacket.TransferLength = EFI_PAGE_SIZE;
745 CommandPacket.CommandTimeout = NVME_GENERIC_TIMEOUT;
746 CommandPacket.QueueType = NVME_ADMIN_QUEUE;
747
748 CrIoSq.Qid = NVME_IO_QUEUE;
749 CrIoSq.Qsize = NVME_CSQ_SIZE;
750 CrIoSq.Pc = 1;
751 CrIoSq.Cqid = NVME_IO_QUEUE;
752 CrIoSq.Qprio = 0;
753 CopyMem (&CommandPacket.NvmeCmd->Cdw10, &CrIoSq, sizeof (NVME_ADMIN_CRIOSQ));
754 CommandPacket.NvmeCmd->Flags = CDW10_VALID | CDW11_VALID;
755
756 Status = Private->Passthru.PassThru (
757 &Private->Passthru,
758 0,
759 &CommandPacket,
760 NULL
761 );
762
763 return Status;
764 }
765
766 /**
767 Initialize the Nvm Express controller.
768
769 @param[in] Private The pointer to the NVME_CONTROLLER_PRIVATE_DATA data structure.
770
771 @retval EFI_SUCCESS The NVM Express Controller is initialized successfully.
772 @retval Others A device error occurred while initializing the controller.
773
774 **/
775 EFI_STATUS
776 NvmeControllerInit (
777 IN NVME_CONTROLLER_PRIVATE_DATA *Private
778 )
779 {
780 EFI_STATUS Status;
781 EFI_PCI_IO_PROTOCOL *PciIo;
782 UINT64 Supports;
783 NVME_AQA Aqa;
784 NVME_ASQ Asq;
785 NVME_ACQ Acq;
786
787 //
788 // Save original PCI attributes and enable this controller.
789 //
790 PciIo = Private->PciIo;
791 Status = PciIo->Attributes (
792 PciIo,
793 EfiPciIoAttributeOperationGet,
794 0,
795 &Private->PciAttributes
796 );
797
798 if (EFI_ERROR (Status)) {
799 return Status;
800 }
801
802 Status = PciIo->Attributes (
803 PciIo,
804 EfiPciIoAttributeOperationSupported,
805 0,
806 &Supports
807 );
808
809 if (!EFI_ERROR (Status)) {
810 Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
811 Status = PciIo->Attributes (
812 PciIo,
813 EfiPciIoAttributeOperationEnable,
814 Supports,
815 NULL
816 );
817 }
818
819 if (EFI_ERROR (Status)) {
820 DEBUG ((EFI_D_INFO, "NvmeControllerInit: failed to enable controller\n"));
821 return Status;
822 }
823
824 //
825 // Read the Controller Capabilities register and verify that the NVM command set is supported
826 //
827 Status = ReadNvmeControllerCapabilities (Private, &Private->Cap);
828 if (EFI_ERROR (Status)) {
829 return Status;
830 }
831
832 if (Private->Cap.Css != 0x01) {
833 DEBUG ((EFI_D_INFO, "NvmeControllerInit: the controller doesn't support NVMe command set\n"));
834 return EFI_UNSUPPORTED;
835 }
836
837 //
838 // Currently the driver only supports 4k page size.
839 //
840 ASSERT ((Private->Cap.Mpsmin + 12) <= EFI_PAGE_SHIFT);
841
842 Private->Cid[0] = 0;
843 Private->Cid[1] = 0;
844
845 Status = NvmeDisableController (Private);
846
847 if (EFI_ERROR(Status)) {
848 return Status;
849 }
850
851 //
852 // set number of entries admin submission & completion queues.
853 //
854 Aqa.Asqs = NVME_ASQ_SIZE;
855 Aqa.Rsvd1 = 0;
856 Aqa.Acqs = NVME_ACQ_SIZE;
857 Aqa.Rsvd2 = 0;
858
859 //
860 // Address of admin submission queue.
861 //
862 Asq.Rsvd1 = 0;
863 Asq.Asqb = (UINT64)(UINTN)(Private->BufferPciAddr) >> 12;
864
865 //
866 // Address of admin completion queue.
867 //
868 Acq.Rsvd1 = 0;
869 Acq.Acqb = (UINT64)(UINTN)(Private->BufferPciAddr + EFI_PAGE_SIZE) >> 12;
870
871 //
872 // Address of I/O submission & completion queue.
873 //
874 Private->SqBuffer[0] = (NVME_SQ *)(UINTN)(Private->Buffer);
875 Private->SqBufferPciAddr[0] = (NVME_SQ *)(UINTN)(Private->BufferPciAddr);
876 Private->CqBuffer[0] = (NVME_CQ *)(UINTN)(Private->Buffer + 1 * EFI_PAGE_SIZE);
877 Private->CqBufferPciAddr[0] = (NVME_CQ *)(UINTN)(Private->BufferPciAddr + 1 * EFI_PAGE_SIZE);
878 Private->SqBuffer[1] = (NVME_SQ *)(UINTN)(Private->Buffer + 2 * EFI_PAGE_SIZE);
879 Private->SqBufferPciAddr[1] = (NVME_SQ *)(UINTN)(Private->BufferPciAddr + 2 * EFI_PAGE_SIZE);
880 Private->CqBuffer[1] = (NVME_CQ *)(UINTN)(Private->Buffer + 3 * EFI_PAGE_SIZE);
881 Private->CqBufferPciAddr[1] = (NVME_CQ *)(UINTN)(Private->BufferPciAddr + 3 * EFI_PAGE_SIZE);
882
883 DEBUG ((EFI_D_INFO, "Private->Buffer = [%016X]\n", (UINT64)(UINTN)Private->Buffer));
884 DEBUG ((EFI_D_INFO, "Admin Submission Queue size (Aqa.Asqs) = [%08X]\n", Aqa.Asqs));
885 DEBUG ((EFI_D_INFO, "Admin Completion Queue size (Aqa.Acqs) = [%08X]\n", Aqa.Acqs));
886 DEBUG ((EFI_D_INFO, "Admin Submission Queue (SqBuffer[0]) = [%016X]\n", Private->SqBuffer[0]));
887 DEBUG ((EFI_D_INFO, "Admin Completion Queue (CqBuffer[0]) = [%016X]\n", Private->CqBuffer[0]));
888 DEBUG ((EFI_D_INFO, "I/O Submission Queue (SqBuffer[1]) = [%016X]\n", Private->SqBuffer[1]));
889 DEBUG ((EFI_D_INFO, "I/O Completion Queue (CqBuffer[1]) = [%016X]\n", Private->CqBuffer[1]));
890
891 //
892 // Program admin queue attributes.
893 //
894 Status = WriteNvmeAdminQueueAttributes (Private, &Aqa);
895
896 if (EFI_ERROR(Status)) {
897 return Status;
898 }
899
900 //
901 // Program admin submission queue address.
902 //
903 Status = WriteNvmeAdminSubmissionQueueBaseAddress (Private, &Asq);
904
905 if (EFI_ERROR(Status)) {
906 return Status;
907 }
908
909 //
910 // Program admin completion queue address.
911 //
912 Status = WriteNvmeAdminCompletionQueueBaseAddress (Private, &Acq);
913
914 if (EFI_ERROR(Status)) {
915 return Status;
916 }
917
918 Status = NvmeEnableController (Private);
919 if (EFI_ERROR(Status)) {
920 return Status;
921 }
922
923 //
924 // Allocate buffer for Identify Controller data
925 //
926 Private->ControllerData = (NVME_ADMIN_CONTROLLER_DATA *)AllocateZeroPool (sizeof(NVME_ADMIN_CONTROLLER_DATA));
927
928 if (Private->ControllerData == NULL) {
929 return EFI_OUT_OF_RESOURCES;
930 }
931
932 //
933 // Get current Identify Controller Data
934 //
935 Status = NvmeIdentifyController (Private, Private->ControllerData);
936
937 if (EFI_ERROR(Status)) {
938 FreePool(Private->ControllerData);
939 Private->ControllerData = NULL;
940 return EFI_NOT_FOUND;
941 }
942
943 //
944 // Dump NvmExpress Identify Controller Data
945 //
946 Private->ControllerData->Sn[19] = 0;
947 Private->ControllerData->Mn[39] = 0;
948 DEBUG ((EFI_D_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
949 DEBUG ((EFI_D_INFO, " PCI VID : 0x%x\n", Private->ControllerData->Vid));
950 DEBUG ((EFI_D_INFO, " PCI SSVID : 0x%x\n", Private->ControllerData->Ssvid));
951 DEBUG ((EFI_D_INFO, " SN : %a\n", (CHAR8 *)(Private->ControllerData->Sn)));
952 DEBUG ((EFI_D_INFO, " MN : %a\n", (CHAR8 *)(Private->ControllerData->Mn)));
953 DEBUG ((EFI_D_INFO, " FR : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));
954 DEBUG ((EFI_D_INFO, " RAB : 0x%x\n", Private->ControllerData->Rab));
955 DEBUG ((EFI_D_INFO, " IEEE : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oui));
956 DEBUG ((EFI_D_INFO, " AERL : 0x%x\n", Private->ControllerData->Aerl));
957 DEBUG ((EFI_D_INFO, " SQES : 0x%x\n", Private->ControllerData->Sqes));
958 DEBUG ((EFI_D_INFO, " CQES : 0x%x\n", Private->ControllerData->Cqes));
959 DEBUG ((EFI_D_INFO, " NN : 0x%x\n", Private->ControllerData->Nn));
960
961 //
962 // Create one I/O completion queue.
963 //
964 Status = NvmeCreateIoCompletionQueue (Private);
965 if (EFI_ERROR(Status)) {
966 return Status;
967 }
968
969 //
970 // Create one I/O Submission queue.
971 //
972 Status = NvmeCreateIoSubmissionQueue (Private);
973 if (EFI_ERROR(Status)) {
974 return Status;
975 }
976
977 return Status;
978 }
979
EFI Development Kit II mirror for PVE