MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.h

   1 /** @file
   2   The NvmExpressPei driver is used to manage non-volatile memory subsystem
   3   which follows NVM Express specification at PEI phase.
   4
   5   Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions
   9   of the BSD License which accompanies this distribution.  The
  10   full text of the license may be found at
  11   http://opensource.org/licenses/bsd-license.php
  12
  13   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16 **/
  17
  18 #ifndef _NVM_EXPRESS_PEI_H_
  19 #define _NVM_EXPRESS_PEI_H_
  20
  21 #include <PiPei.h>
  22
  23 #include <IndustryStandard/Nvme.h>
  24
  25 #include <Ppi/NvmExpressHostController.h>
  26 #include <Ppi/BlockIo.h>
  27 #include <Ppi/BlockIo2.h>
  28 #include <Ppi/IoMmu.h>
  29 #include <Ppi/EndOfPeiPhase.h>
  30
  31 #include <Library/DebugLib.h>
  32 #include <Library/PeiServicesLib.h>
  33 #include <Library/MemoryAllocationLib.h>
  34 #include <Library/BaseMemoryLib.h>
  35 #include <Library/IoLib.h>
  36 #include <Library/TimerLib.h>
  37
  38 //
  39 // Structure forward declarations
  40 //
  41 typedef struct _PEI_NVME_NAMESPACE_INFO           PEI_NVME_NAMESPACE_INFO;
  42 typedef struct _PEI_NVME_CONTROLLER_PRIVATE_DATA  PEI_NVME_CONTROLLER_PRIVATE_DATA;
  43
  44 #include "NvmExpressPeiHci.h"
  45 #include "NvmExpressPeiPassThru.h"
  46 #include "NvmExpressPeiBlockIo.h"
  47
  48 //
  49 // NVME PEI driver implementation related definitions
  50 //
  51 #define NVME_MAX_QUEUES                               2     // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
  52 #define NVME_ASQ_SIZE                                 1     // Number of admin submission queue entries, which is 0-based
  53 #define NVME_ACQ_SIZE                                 1     // Number of admin completion queue entries, which is 0-based
  54 #define NVME_CSQ_SIZE                                 63    // Number of I/O submission queue entries, which is 0-based
  55 #define NVME_CCQ_SIZE                                 63    // Number of I/O completion queue entries, which is 0-based
  56 #define NVME_PRP_SIZE                                 (8)   // Pages of PRP list
  57
  58 #define NVME_MEM_MAX_PAGES                                           \
  59   (                                                                  \
  60   1                                         /* ASQ */             +  \
  61   1                                         /* ACQ */             +  \
  62   1                                         /* SQs */             +  \
  63   1                                         /* CQs */             +  \
  64   NVME_PRP_SIZE)                            /* PRPs */
  65
  66 #define NVME_ADMIN_QUEUE                              0x00
  67 #define NVME_IO_QUEUE                                 0x01
  68 #define NVME_GENERIC_TIMEOUT                          5000000   // Generic PassThru command timeout value, in us unit
  69 #define NVME_POLL_INTERVAL                            100       // Poll interval for PassThru command, in us unit
  70
  71 //
  72 // Nvme namespace data structure.
  73 //
  74 struct _PEI_NVME_NAMESPACE_INFO {
  75   UINT32                                    NamespaceId;
  76   UINT64                                    NamespaceUuid;
  77   EFI_PEI_BLOCK_IO2_MEDIA                   Media;
  78
  79   PEI_NVME_CONTROLLER_PRIVATE_DATA          *Controller;
  80 };
  81
  82 //
  83 // Unique signature for private data structure.
  84 //
  85 #define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE    SIGNATURE_32 ('N','V','P','C')
  86
  87 //
  88 // Nvme controller private data structure.
  89 //
  90 struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {
  91   UINT32                                    Signature;
  92   UINTN                                     MmioBase;
  93   EFI_PEI_RECOVERY_BLOCK_IO_PPI             BlkIoPpi;
  94   EFI_PEI_RECOVERY_BLOCK_IO2_PPI            BlkIo2Ppi;
  95   EFI_PEI_PPI_DESCRIPTOR                    BlkIoPpiList;
  96   EFI_PEI_PPI_DESCRIPTOR                    BlkIo2PpiList;
  97   EFI_PEI_NOTIFY_DESCRIPTOR                 EndOfPeiNotifyList;
  98
  99   //
 100   // Pointer to identify controller data
 101   //
 102   NVME_ADMIN_CONTROLLER_DATA                *ControllerData;
 103
 104   //
 105   // (4 + NVME_PRP_SIZE) x 4kB aligned buffers will be carved out of this buffer
 106   // 1st 4kB boundary is the start of the admin submission queue
 107   // 2nd 4kB boundary is the start of the admin completion queue
 108   // 3rd 4kB boundary is the start of I/O submission queue
 109   // 4th 4kB boundary is the start of I/O completion queue
 110   // 5th 4kB boundary is the start of PRP list buffers
 111   //
 112   VOID                                      *Buffer;
 113   VOID                                      *BufferMapping;
 114
 115   //
 116   // Pointers to 4kB aligned submission & completion queues
 117   //
 118   NVME_SQ                                   *SqBuffer[NVME_MAX_QUEUES];
 119   NVME_CQ                                   *CqBuffer[NVME_MAX_QUEUES];
 120
 121   //
 122   // Submission and completion queue indices
 123   //
 124   NVME_SQTDBL                               SqTdbl[NVME_MAX_QUEUES];
 125   NVME_CQHDBL                               CqHdbl[NVME_MAX_QUEUES];
 126
 127   UINT8                                     Pt[NVME_MAX_QUEUES];
 128   UINT16                                    Cid[NVME_MAX_QUEUES];
 129
 130   //
 131   // Nvme controller capabilities
 132   //
 133   NVME_CAP                                  Cap;
 134
 135   //
 136   // Namespaces information on the controller
 137   //
 138   UINT32                                    ActiveNamespaceNum;
 139   PEI_NVME_NAMESPACE_INFO                   *NamespaceInfo;
 140 };
 141
 142 #define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a)     \
 143   CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIoPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
 144 #define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a)    \
 145   CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
 146 #define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a)    \
 147   CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
 148
 149
 150 /**
 151   Initialize IOMMU.
 152 **/
 153 VOID
 154 IoMmuInit (
 155   VOID
 156   );
 157
 158 /**
 159   Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
 160   OperationBusMasterCommonBuffer64 mapping.
 161
 162   @param  Pages                 The number of pages to allocate.
 163   @param  HostAddress           A pointer to store the base system memory address of the
 164                                 allocated range.
 165   @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to
 166                                 access the hosts HostAddress.
 167   @param  Mapping               A resulting value to pass to Unmap().
 168
 169   @retval EFI_SUCCESS           The requested memory pages were allocated.
 170   @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
 171                                 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
 172   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 173   @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
 174
 175 **/
 176 EFI_STATUS
 177 IoMmuAllocateBuffer (
 178   IN UINTN                  Pages,
 179   OUT VOID                  **HostAddress,
 180   OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,
 181   OUT VOID                  **Mapping
 182   );
 183
 184 /**
 185   Frees memory that was allocated with AllocateBuffer().
 186
 187   @param  Pages                 The number of pages to free.
 188   @param  HostAddress           The base system memory address of the allocated range.
 189   @param  Mapping               The mapping value returned from Map().
 190
 191   @retval EFI_SUCCESS           The requested memory pages were freed.
 192   @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
 193                                 was not allocated with AllocateBuffer().
 194
 195 **/
 196 EFI_STATUS
 197 IoMmuFreeBuffer (
 198   IN UINTN                  Pages,
 199   IN VOID                   *HostAddress,
 200   IN VOID                   *Mapping
 201   );
 202
 203 /**
 204   Provides the controller-specific addresses required to access system memory from a
 205   DMA bus master.
 206
 207   @param  Operation             Indicates if the bus master is going to read or write to system memory.
 208   @param  HostAddress           The system memory address to map to the PCI controller.
 209   @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes
 210                                 that were mapped.
 211   @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to
 212                                 access the hosts HostAddress.
 213   @param  Mapping               A resulting value to pass to Unmap().
 214
 215   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
 216   @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
 217   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 218   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 219   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
 220
 221 **/
 222 EFI_STATUS
 223 IoMmuMap (
 224   IN  EDKII_IOMMU_OPERATION Operation,
 225   IN VOID                   *HostAddress,
 226   IN  OUT UINTN             *NumberOfBytes,
 227   OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,
 228   OUT VOID                  **Mapping
 229   );
 230
 231 /**
 232   Completes the Map() operation and releases any corresponding resources.
 233
 234   @param  Mapping               The mapping value returned from Map().
 235
 236   @retval EFI_SUCCESS           The range was unmapped.
 237   @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
 238   @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.
 239 **/
 240 EFI_STATUS
 241 IoMmuUnmap (
 242   IN VOID                  *Mapping
 243   );
 244
 245 /**
 246   One notified function to cleanup the allocated resources at the end of PEI.
 247
 248   @param[in] PeiServices         Pointer to PEI Services Table.
 249   @param[in] NotifyDescriptor    Pointer to the descriptor for the Notification
 250                                  event that caused this function to execute.
 251   @param[in] Ppi                 Pointer to the PPI data associated with this function.
 252
 253   @retval     EFI_SUCCESS  The function completes successfully
 254
 255 **/
 256 EFI_STATUS
 257 EFIAPI
 258 NvmePeimEndOfPei (
 259   IN EFI_PEI_SERVICES           **PeiServices,
 260   IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
 261   IN VOID                       *Ppi
 262   );
 263
 264 #endif