2 The NvmExpressPei driver is used to manage non-volatile memory subsystem
3 which follows NVM Express specification at PEI phase.
5 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions
9 of the BSD License which accompanies this distribution. The
10 full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #ifndef _NVM_EXPRESS_PEI_H_
19 #define _NVM_EXPRESS_PEI_H_
23 #include <IndustryStandard/Nvme.h>
25 #include <Ppi/NvmExpressHostController.h>
26 #include <Ppi/BlockIo.h>
27 #include <Ppi/BlockIo2.h>
28 #include <Ppi/IoMmu.h>
29 #include <Ppi/EndOfPeiPhase.h>
31 #include <Library/DebugLib.h>
32 #include <Library/PeiServicesLib.h>
33 #include <Library/MemoryAllocationLib.h>
34 #include <Library/BaseMemoryLib.h>
35 #include <Library/IoLib.h>
36 #include <Library/PciLib.h>
37 #include <Library/TimerLib.h>
40 // Structure forward declarations
42 typedef struct _PEI_NVME_NAMESPACE_INFO PEI_NVME_NAMESPACE_INFO
;
43 typedef struct _PEI_NVME_CONTROLLER_PRIVATE_DATA PEI_NVME_CONTROLLER_PRIVATE_DATA
;
45 #include "NvmExpressPeiHci.h"
46 #include "NvmExpressPeiPassThru.h"
47 #include "NvmExpressPeiBlockIo.h"
50 // NVME PEI driver implementation related definitions
52 #define NVME_MAX_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
53 #define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
54 #define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
55 #define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based
56 #define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based
57 #define NVME_PRP_SIZE (8) // Pages of PRP list
59 #define NVME_MEM_MAX_PAGES \
65 NVME_PRP_SIZE) /* PRPs */
67 #define NVME_ADMIN_QUEUE 0x00
68 #define NVME_IO_QUEUE 0x01
69 #define NVME_GENERIC_TIMEOUT 5000000 // Generic PassThru command timeout value, in us unit
70 #define NVME_POLL_INTERVAL 100 // Poll interval for PassThru command, in us unit
73 // Nvme namespace data structure.
75 struct _PEI_NVME_NAMESPACE_INFO
{
78 EFI_PEI_BLOCK_IO2_MEDIA Media
;
80 PEI_NVME_CONTROLLER_PRIVATE_DATA
*Controller
;
84 // Unique signature for private data structure.
86 #define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','P','C')
89 // Nvme controller private data structure.
91 struct _PEI_NVME_CONTROLLER_PRIVATE_DATA
{
94 EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi
;
95 EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi
;
96 EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList
;
97 EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList
;
98 EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList
;
101 // Pointer to identify controller data
103 NVME_ADMIN_CONTROLLER_DATA
*ControllerData
;
106 // (4 + NVME_PRP_SIZE) x 4kB aligned buffers will be carved out of this buffer
107 // 1st 4kB boundary is the start of the admin submission queue
108 // 2nd 4kB boundary is the start of the admin completion queue
109 // 3rd 4kB boundary is the start of I/O submission queue
110 // 4th 4kB boundary is the start of I/O completion queue
111 // 5th 4kB boundary is the start of PRP list buffers
117 // Pointers to 4kB aligned submission & completion queues
119 NVME_SQ
*SqBuffer
[NVME_MAX_QUEUES
];
120 NVME_CQ
*CqBuffer
[NVME_MAX_QUEUES
];
123 // Submission and completion queue indices
125 NVME_SQTDBL SqTdbl
[NVME_MAX_QUEUES
];
126 NVME_CQHDBL CqHdbl
[NVME_MAX_QUEUES
];
128 UINT8 Pt
[NVME_MAX_QUEUES
];
129 UINT16 Cid
[NVME_MAX_QUEUES
];
132 // Nvme controller capabilities
137 // Namespaces information on the controller
139 UINT32 ActiveNamespaceNum
;
140 PEI_NVME_NAMESPACE_INFO
*NamespaceInfo
;
143 #define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a) \
144 CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIoPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
145 #define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a) \
146 CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
147 #define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a) \
148 CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
160 Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
161 OperationBusMasterCommonBuffer64 mapping.
163 @param Pages The number of pages to allocate.
164 @param HostAddress A pointer to store the base system memory address of the
166 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
167 access the hosts HostAddress.
168 @param Mapping A resulting value to pass to Unmap().
170 @retval EFI_SUCCESS The requested memory pages were allocated.
171 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
172 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
173 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
174 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
178 IoMmuAllocateBuffer (
180 OUT VOID
**HostAddress
,
181 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
186 Frees memory that was allocated with AllocateBuffer().
188 @param Pages The number of pages to free.
189 @param HostAddress The base system memory address of the allocated range.
190 @param Mapping The mapping value returned from Map().
192 @retval EFI_SUCCESS The requested memory pages were freed.
193 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
194 was not allocated with AllocateBuffer().
200 IN VOID
*HostAddress
,
205 Provides the controller-specific addresses required to access system memory from a
208 @param Operation Indicates if the bus master is going to read or write to system memory.
209 @param HostAddress The system memory address to map to the PCI controller.
210 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
212 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
213 access the hosts HostAddress.
214 @param Mapping A resulting value to pass to Unmap().
216 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
217 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
218 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
219 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
220 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
225 IN EDKII_IOMMU_OPERATION Operation
,
226 IN VOID
*HostAddress
,
227 IN OUT UINTN
*NumberOfBytes
,
228 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
233 Completes the Map() operation and releases any corresponding resources.
235 @param Mapping The mapping value returned from Map().
237 @retval EFI_SUCCESS The range was unmapped.
238 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
239 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
247 One notified function to cleanup the allocated resources at the end of PEI.
249 @param[in] PeiServices Pointer to PEI Services Table.
250 @param[in] NotifyDescriptor Pointer to the descriptor for the Notification
251 event that caused this function to execute.
252 @param[in] Ppi Pointer to the PPI data associated with this function.
254 @retval EFI_SUCCESS The function completes successfully
260 IN EFI_PEI_SERVICES
**PeiServices
,
261 IN EFI_PEI_NOTIFY_DESCRIPTOR
*NotifyDescriptor
,