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MdeModulePkg/NvmExpressPei: Add the NVME device PEI BlockIo support
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1 /** @file
2 The NvmExpressPei driver is used to manage non-volatile memory subsystem
3 which follows NVM Express specification at PEI phase.
4
5 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
6
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions
9 of the BSD License which accompanies this distribution. The
10 full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #ifndef _NVM_EXPRESS_PEI_H_
19 #define _NVM_EXPRESS_PEI_H_
20
21 #include <PiPei.h>
22
23 #include <IndustryStandard/Nvme.h>
24
25 #include <Ppi/NvmExpressHostController.h>
26 #include <Ppi/BlockIo.h>
27 #include <Ppi/BlockIo2.h>
28 #include <Ppi/IoMmu.h>
29 #include <Ppi/EndOfPeiPhase.h>
30
31 #include <Library/DebugLib.h>
32 #include <Library/PeiServicesLib.h>
33 #include <Library/MemoryAllocationLib.h>
34 #include <Library/BaseMemoryLib.h>
35 #include <Library/IoLib.h>
36 #include <Library/PciLib.h>
37 #include <Library/TimerLib.h>
38
39 //
40 // Structure forward declarations
41 //
42 typedef struct _PEI_NVME_NAMESPACE_INFO PEI_NVME_NAMESPACE_INFO;
43 typedef struct _PEI_NVME_CONTROLLER_PRIVATE_DATA PEI_NVME_CONTROLLER_PRIVATE_DATA;
44
45 #include "NvmExpressPeiHci.h"
46 #include "NvmExpressPeiPassThru.h"
47 #include "NvmExpressPeiBlockIo.h"
48
49 //
50 // NVME PEI driver implementation related definitions
51 //
52 #define NVME_MAX_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
53 #define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
54 #define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
55 #define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based
56 #define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based
57 #define NVME_PRP_SIZE (8) // Pages of PRP list
58
59 #define NVME_MEM_MAX_PAGES \
60 ( \
61 1 /* ASQ */ + \
62 1 /* ACQ */ + \
63 1 /* SQs */ + \
64 1 /* CQs */ + \
65 NVME_PRP_SIZE) /* PRPs */
66
67 #define NVME_ADMIN_QUEUE 0x00
68 #define NVME_IO_QUEUE 0x01
69 #define NVME_GENERIC_TIMEOUT 5000000 // Generic PassThru command timeout value, in us unit
70 #define NVME_POLL_INTERVAL 100 // Poll interval for PassThru command, in us unit
71
72 //
73 // Nvme namespace data structure.
74 //
75 struct _PEI_NVME_NAMESPACE_INFO {
76 UINT32 NamespaceId;
77 UINT64 NamespaceUuid;
78 EFI_PEI_BLOCK_IO2_MEDIA Media;
79
80 PEI_NVME_CONTROLLER_PRIVATE_DATA *Controller;
81 };
82
83 //
84 // Unique signature for private data structure.
85 //
86 #define NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('N','V','P','C')
87
88 //
89 // Nvme controller private data structure.
90 //
91 struct _PEI_NVME_CONTROLLER_PRIVATE_DATA {
92 UINT32 Signature;
93 UINTN MmioBase;
94 EFI_PEI_RECOVERY_BLOCK_IO_PPI BlkIoPpi;
95 EFI_PEI_RECOVERY_BLOCK_IO2_PPI BlkIo2Ppi;
96 EFI_PEI_PPI_DESCRIPTOR BlkIoPpiList;
97 EFI_PEI_PPI_DESCRIPTOR BlkIo2PpiList;
98 EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
99
100 //
101 // Pointer to identify controller data
102 //
103 NVME_ADMIN_CONTROLLER_DATA *ControllerData;
104
105 //
106 // (4 + NVME_PRP_SIZE) x 4kB aligned buffers will be carved out of this buffer
107 // 1st 4kB boundary is the start of the admin submission queue
108 // 2nd 4kB boundary is the start of the admin completion queue
109 // 3rd 4kB boundary is the start of I/O submission queue
110 // 4th 4kB boundary is the start of I/O completion queue
111 // 5th 4kB boundary is the start of PRP list buffers
112 //
113 VOID *Buffer;
114 VOID *BufferMapping;
115
116 //
117 // Pointers to 4kB aligned submission & completion queues
118 //
119 NVME_SQ *SqBuffer[NVME_MAX_QUEUES];
120 NVME_CQ *CqBuffer[NVME_MAX_QUEUES];
121
122 //
123 // Submission and completion queue indices
124 //
125 NVME_SQTDBL SqTdbl[NVME_MAX_QUEUES];
126 NVME_CQHDBL CqHdbl[NVME_MAX_QUEUES];
127
128 UINT8 Pt[NVME_MAX_QUEUES];
129 UINT16 Cid[NVME_MAX_QUEUES];
130
131 //
132 // Nvme controller capabilities
133 //
134 NVME_CAP Cap;
135
136 //
137 // Namespaces information on the controller
138 //
139 UINT32 ActiveNamespaceNum;
140 PEI_NVME_NAMESPACE_INFO *NamespaceInfo;
141 };
142
143 #define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a) \
144 CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIoPpi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
145 #define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a) \
146 CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
147 #define GET_NVME_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a) \
148 CR (a, PEI_NVME_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, NVME_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
149
150
151 /**
152 Initialize IOMMU.
153 **/
154 VOID
155 IoMmuInit (
156 VOID
157 );
158
159 /**
160 Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
161 OperationBusMasterCommonBuffer64 mapping.
162
163 @param Pages The number of pages to allocate.
164 @param HostAddress A pointer to store the base system memory address of the
165 allocated range.
166 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
167 access the hosts HostAddress.
168 @param Mapping A resulting value to pass to Unmap().
169
170 @retval EFI_SUCCESS The requested memory pages were allocated.
171 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
172 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
173 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
174 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
175
176 **/
177 EFI_STATUS
178 IoMmuAllocateBuffer (
179 IN UINTN Pages,
180 OUT VOID **HostAddress,
181 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
182 OUT VOID **Mapping
183 );
184
185 /**
186 Frees memory that was allocated with AllocateBuffer().
187
188 @param Pages The number of pages to free.
189 @param HostAddress The base system memory address of the allocated range.
190 @param Mapping The mapping value returned from Map().
191
192 @retval EFI_SUCCESS The requested memory pages were freed.
193 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
194 was not allocated with AllocateBuffer().
195
196 **/
197 EFI_STATUS
198 IoMmuFreeBuffer (
199 IN UINTN Pages,
200 IN VOID *HostAddress,
201 IN VOID *Mapping
202 );
203
204 /**
205 Provides the controller-specific addresses required to access system memory from a
206 DMA bus master.
207
208 @param Operation Indicates if the bus master is going to read or write to system memory.
209 @param HostAddress The system memory address to map to the PCI controller.
210 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
211 that were mapped.
212 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
213 access the hosts HostAddress.
214 @param Mapping A resulting value to pass to Unmap().
215
216 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
217 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
218 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
219 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
220 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
221
222 **/
223 EFI_STATUS
224 IoMmuMap (
225 IN EDKII_IOMMU_OPERATION Operation,
226 IN VOID *HostAddress,
227 IN OUT UINTN *NumberOfBytes,
228 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
229 OUT VOID **Mapping
230 );
231
232 /**
233 Completes the Map() operation and releases any corresponding resources.
234
235 @param Mapping The mapping value returned from Map().
236
237 @retval EFI_SUCCESS The range was unmapped.
238 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
239 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
240 **/
241 EFI_STATUS
242 IoMmuUnmap (
243 IN VOID *Mapping
244 );
245
246 /**
247 One notified function to cleanup the allocated resources at the end of PEI.
248
249 @param[in] PeiServices Pointer to PEI Services Table.
250 @param[in] NotifyDescriptor Pointer to the descriptor for the Notification
251 event that caused this function to execute.
252 @param[in] Ppi Pointer to the PPI data associated with this function.
253
254 @retval EFI_SUCCESS The function completes successfully
255
256 **/
257 EFI_STATUS
258 EFIAPI
259 NvmePeimEndOfPei (
260 IN EFI_PEI_SERVICES **PeiServices,
261 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
262 IN VOID *Ppi
263 );
264
265 #endif