MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPeiHci.h

   1 /** @file
   2   The NvmExpressPei driver is used to manage non-volatile memory subsystem
   3   which follows NVM Express specification at PEI phase.
   4
   5   Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions
   9   of the BSD License which accompanies this distribution.  The
  10   full text of the license may be found at
  11   http://opensource.org/licenses/bsd-license.php
  12
  13   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16 **/
  17
  18 #ifndef _NVM_EXPRESS_PEI_HCI_H_
  19 #define _NVM_EXPRESS_PEI_HCI_H_
  20
  21 //
  22 // NVME host controller registers operation definitions
  23 //
  24 #define NVME_GET_CAP(Private, Cap)             NvmeMmioRead  (Cap, Private->MmioBase + NVME_CAP_OFFSET, sizeof (NVME_CAP))
  25 #define NVME_GET_CC(Private, Cc)               NvmeMmioRead  (Cc, Private->MmioBase + NVME_CC_OFFSET, sizeof (NVME_CC))
  26 #define NVME_SET_CC(Private, Cc)               NvmeMmioWrite (Private->MmioBase + NVME_CC_OFFSET, Cc, sizeof (NVME_CC))
  27 #define NVME_GET_CSTS(Private, Csts)           NvmeMmioRead  (Csts, Private->MmioBase + NVME_CSTS_OFFSET, sizeof (NVME_CSTS))
  28 #define NVME_GET_AQA(Private, Aqa)             NvmeMmioRead  (Aqa, Private->MmioBase + NVME_AQA_OFFSET, sizeof (NVME_AQA))
  29 #define NVME_SET_AQA(Private, Aqa)             NvmeMmioWrite (Private->MmioBase + NVME_AQA_OFFSET, Aqa, sizeof (NVME_AQA))
  30 #define NVME_GET_ASQ(Private, Asq)             NvmeMmioRead  (Asq, Private->MmioBase + NVME_ASQ_OFFSET, sizeof (NVME_ASQ))
  31 #define NVME_SET_ASQ(Private, Asq)             NvmeMmioWrite (Private->MmioBase + NVME_ASQ_OFFSET, Asq, sizeof (NVME_ASQ))
  32 #define NVME_GET_ACQ(Private, Acq)             NvmeMmioRead  (Acq, Private->MmioBase + NVME_ACQ_OFFSET, sizeof (NVME_ACQ))
  33 #define NVME_SET_ACQ(Private, Acq)             NvmeMmioWrite (Private->MmioBase + NVME_ACQ_OFFSET, Acq, sizeof (NVME_ACQ))
  34 #define NVME_GET_VER(Private, Ver)             NvmeMmioRead  (Ver, Private->MmioBase + NVME_VER_OFFSET, sizeof (NVME_VER))
  35 #define NVME_SET_SQTDBL(Private, Qid, Sqtdbl)  NvmeMmioWrite (Private->MmioBase + NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd), Sqtdbl, sizeof (NVME_SQTDBL))
  36 #define NVME_SET_CQHDBL(Private, Qid, Cqhdbl)  NvmeMmioWrite (Private->MmioBase + NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd), Cqhdbl, sizeof (NVME_CQHDBL))
  37
  38 //
  39 // Base memory address enum types
  40 //
  41 enum {
  42   BASEMEM_ASQ,
  43   BASEMEM_ACQ,
  44   BASEMEM_SQ,
  45   BASEMEM_CQ,
  46   BASEMEM_PRP,
  47   MAX_BASEMEM_COUNT
  48 };
  49
  50 //
  51 // All of base memories are 4K(0x1000) alignment
  52 //
  53 #define ALIGN(v, a)                          (UINTN)((((v) - 1) | ((a) - 1)) + 1)
  54 #define NVME_MEM_BASE(Private)               ((UINTN)(Private->Buffer))
  55 #define NVME_ASQ_BASE(Private)               (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ASQ))                                * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
  56 #define NVME_ACQ_BASE(Private)               (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_ACQ))                                * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
  57 #define NVME_SQ_BASE(Private, Index)         (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_SQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
  58 #define NVME_CQ_BASE(Private, Index)         (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_CQ) + ((Index)*(NVME_MAX_QUEUES-1))) * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
  59 #define NVME_PRP_BASE(Private)               (ALIGN (NVME_MEM_BASE(Private) + ((NvmeBaseMemPageOffset (BASEMEM_PRP))                                * EFI_PAGE_SIZE), EFI_PAGE_SIZE))
  60
  61
  62 /**
  63   Transfer MMIO Data to memory.
  64
  65   @param[in,out] MemBuffer    Destination: Memory address.
  66   @param[in] MmioAddr         Source: MMIO address.
  67   @param[in] Size             Size for read.
  68
  69   @retval EFI_SUCCESS         MMIO read sucessfully.
  70
  71 **/
  72 EFI_STATUS
  73 NvmeMmioRead (
  74   IN OUT VOID *MemBuffer,
  75   IN     UINTN MmioAddr,
  76   IN     UINTN Size
  77   );
  78
  79 /**
  80   Transfer memory data to MMIO.
  81
  82   @param[in,out] MmioAddr    Destination: MMIO address.
  83   @param[in] MemBuffer       Source: Memory address.
  84   @param[in] Size            Size for write.
  85
  86   @retval EFI_SUCCESS        MMIO write sucessfully.
  87
  88 **/
  89 EFI_STATUS
  90 NvmeMmioWrite (
  91   IN OUT UINTN MmioAddr,
  92   IN     VOID *MemBuffer,
  93   IN     UINTN Size
  94   );
  95
  96 /**
  97   Get the page offset for specific NVME based memory.
  98
  99   @param[in] BaseMemIndex    The Index of BaseMem (0-based).
 100
 101   @retval - The page count for specific BaseMem Index
 102
 103 **/
 104 UINT32
 105 NvmeBaseMemPageOffset (
 106   IN UINTN              BaseMemIndex
 107   );
 108
 109 /**
 110   Initialize the Nvm Express controller.
 111
 112   @param[in] Private     The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
 113
 114   @retval EFI_SUCCESS    The NVM Express Controller is initialized successfully.
 115   @retval Others         A device error occurred while initializing the controller.
 116
 117 **/
 118 EFI_STATUS
 119 NvmeControllerInit (
 120   IN PEI_NVME_CONTROLLER_PRIVATE_DATA    *Private
 121   );
 122
 123 /**
 124   Get specified identify namespace data.
 125
 126   @param[in] Private        The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
 127   @param[in] NamespaceId    The specified namespace identifier.
 128   @param[in] Buffer         The buffer used to store the identify namespace data.
 129
 130   @return EFI_SUCCESS         Successfully get the identify namespace data.
 131   @return EFI_DEVICE_ERROR    Fail to get the identify namespace data.
 132
 133 **/
 134 EFI_STATUS
 135 NvmeIdentifyNamespace (
 136   IN PEI_NVME_CONTROLLER_PRIVATE_DATA    *Private,
 137   IN UINT32                              NamespaceId,
 138   IN VOID                                *Buffer
 139   );
 140
 141 /**
 142   Free the DMA resources allocated by an NVME controller.
 143
 144   @param[in] Private     The pointer to the PEI_NVME_CONTROLLER_PRIVATE_DATA data structure.
 145
 146 **/
 147 VOID
 148 NvmeFreeDmaResource (
 149   IN PEI_NVME_CONTROLLER_PRIVATE_DATA    *Private
 150   );
 151
 152 #endif