MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h

   1 /** @file
   2   Header files and data structures needed by PCI Bus module.
   3
   4 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15
  16 #ifndef _EFI_PCI_BUS_H_
  17 #define _EFI_PCI_BUS_H_
  18
  19 #include <PiDxe.h>
  20
  21 #include <Protocol/LoadedImage.h>
  22 #include <Protocol/PciHostBridgeResourceAllocation.h>
  23 #include <Protocol/PciIo.h>
  24 #include <Protocol/LoadFile2.h>
  25 #include <Protocol/PciRootBridgeIo.h>
  26 #include <Protocol/PciHotPlugRequest.h>
  27 #include <Protocol/DevicePath.h>
  28 #include <Protocol/PciPlatform.h>
  29 #include <Protocol/PciHotPlugInit.h>
  30 #include <Protocol/Decompress.h>
  31 #include <Protocol/BusSpecificDriverOverride.h>
  32 #include <Protocol/IncompatiblePciDeviceSupport.h>
  33 #include <Protocol/PciOverride.h>
  34 #include <Protocol/PciEnumerationComplete.h>
  35 #include <Protocol/IoMmu.h>
  36
  37 #include <Library/DebugLib.h>
  38 #include <Library/UefiDriverEntryPoint.h>
  39 #include <Library/BaseLib.h>
  40 #include <Library/UefiLib.h>
  41 #include <Library/BaseMemoryLib.h>
  42 #include <Library/ReportStatusCodeLib.h>
  43 #include <Library/MemoryAllocationLib.h>
  44 #include <Library/UefiBootServicesTableLib.h>
  45 #include <Library/DevicePathLib.h>
  46 #include <Library/PcdLib.h>
  47
  48 #include <IndustryStandard/Pci.h>
  49 #include <IndustryStandard/PeImage.h>
  50 #include <IndustryStandard/Acpi.h>
  51
  52 typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;
  53 typedef struct _PCI_BAR                    PCI_BAR;
  54
  55 #define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
  56 #define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)
  57
  58 #define     EFI_PCI_IOV_POLICY_ARI           0x0001
  59 #define     EFI_PCI_IOV_POLICY_SRIOV         0x0002
  60 #define     EFI_PCI_IOV_POLICY_MRIOV         0x0004
  61
  62 typedef enum {
  63   PciBarTypeUnknown = 0,
  64   PciBarTypeIo16,
  65   PciBarTypeIo32,
  66   PciBarTypeMem32,
  67   PciBarTypePMem32,
  68   PciBarTypeMem64,
  69   PciBarTypePMem64,
  70   PciBarTypeIo,
  71   PciBarTypeMem,
  72   PciBarTypeMaxType
  73 } PCI_BAR_TYPE;
  74
  75 #include "ComponentName.h"
  76 #include "PciIo.h"
  77 #include "PciCommand.h"
  78 #include "PciDeviceSupport.h"
  79 #include "PciEnumerator.h"
  80 #include "PciEnumeratorSupport.h"
  81 #include "PciDriverOverride.h"
  82 #include "PciRomTable.h"
  83 #include "PciOptionRomSupport.h"
  84 #include "PciPowerManagement.h"
  85 #include "PciHotPlugSupport.h"
  86 #include "PciLib.h"
  87
  88 #define VGABASE1  0x3B0
  89 #define VGALIMIT1 0x3BB
  90
  91 #define VGABASE2  0x3C0
  92 #define VGALIMIT2 0x3DF
  93
  94 #define ISABASE   0x100
  95 #define ISALIMIT  0x3FF
  96
  97 //
  98 // PCI BAR parameters
  99 //
 100 struct _PCI_BAR {
 101   UINT64        BaseAddress;
 102   UINT64        Length;
 103   UINT64        Alignment;
 104   PCI_BAR_TYPE  BarType;
 105   BOOLEAN       BarTypeFixed;
 106   UINT16        Offset;
 107 };
 108
 109 //
 110 // defined in PCI Card Specification, 8.0
 111 //
 112 #define PCI_CARD_MEMORY_BASE_0                0x1C
 113 #define PCI_CARD_MEMORY_LIMIT_0               0x20
 114 #define PCI_CARD_MEMORY_BASE_1                0x24
 115 #define PCI_CARD_MEMORY_LIMIT_1               0x28
 116 #define PCI_CARD_IO_BASE_0_LOWER              0x2C
 117 #define PCI_CARD_IO_BASE_0_UPPER              0x2E
 118 #define PCI_CARD_IO_LIMIT_0_LOWER             0x30
 119 #define PCI_CARD_IO_LIMIT_0_UPPER             0x32
 120 #define PCI_CARD_IO_BASE_1_LOWER              0x34
 121 #define PCI_CARD_IO_BASE_1_UPPER              0x36
 122 #define PCI_CARD_IO_LIMIT_1_LOWER             0x38
 123 #define PCI_CARD_IO_LIMIT_1_UPPER             0x3A
 124 #define PCI_CARD_BRIDGE_CONTROL               0x3E
 125
 126 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
 127 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
 128
 129 #define RB_IO_RANGE                           1
 130 #define RB_MEM32_RANGE                        2
 131 #define RB_PMEM32_RANGE                       3
 132 #define RB_MEM64_RANGE                        4
 133 #define RB_PMEM64_RANGE                       5
 134
 135 #define PPB_BAR_0                             0
 136 #define PPB_BAR_1                             1
 137 #define PPB_IO_RANGE                          2
 138 #define PPB_MEM32_RANGE                       3
 139 #define PPB_PMEM32_RANGE                      4
 140 #define PPB_PMEM64_RANGE                      5
 141 #define PPB_MEM64_RANGE                       0xFF
 142
 143 #define P2C_BAR_0                             0
 144 #define P2C_MEM_1                             1
 145 #define P2C_MEM_2                             2
 146 #define P2C_IO_1                              3
 147 #define P2C_IO_2                              4
 148
 149 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 150 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 151 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 152 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 153 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 154 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 155 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 156
 157 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 158
 159 //
 160 // Define option for attribute
 161 //
 162 #define EFI_SET_SUPPORTS    0
 163 #define EFI_SET_ATTRIBUTES  1
 164
 165 #define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')
 166
 167 struct _PCI_IO_DEVICE {
 168   UINT32                                    Signature;
 169   EFI_HANDLE                                Handle;
 170   EFI_PCI_IO_PROTOCOL                       PciIo;
 171   LIST_ENTRY                                Link;
 172
 173   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 174   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 175   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 176   EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;
 177
 178   //
 179   // PCI configuration space header type
 180   //
 181   PCI_TYPE00                                Pci;
 182
 183   //
 184   // Bus number, Device number, Function number
 185   //
 186   UINT8                                     BusNumber;
 187   UINT8                                     DeviceNumber;
 188   UINT8                                     FunctionNumber;
 189
 190   //
 191   // BAR for this PCI Device
 192   //
 193   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 194
 195   //
 196   // The bridge device this pci device is subject to
 197   //
 198   PCI_IO_DEVICE                             *Parent;
 199
 200   //
 201   // A linked list for children Pci Device if it is bridge device
 202   //
 203   LIST_ENTRY                                ChildList;
 204
 205   //
 206   // TRUE if the PCI bus driver creates the handle for this PCI device
 207   //
 208   BOOLEAN                                   Registered;
 209
 210   //
 211   // TRUE if the PCI bus driver successfully allocates the resource required by
 212   // this PCI device
 213   //
 214   BOOLEAN                                   Allocated;
 215
 216   //
 217   // The attribute this PCI device currently set
 218   //
 219   UINT64                                    Attributes;
 220
 221   //
 222   // The attributes this PCI device actually supports
 223   //
 224   UINT64                                    Supports;
 225
 226   //
 227   // The resource decode the bridge supports
 228   //
 229   UINT32                                    Decodes;
 230
 231   //
 232   // TRUE if the ROM image is from the PCI Option ROM BAR
 233   //
 234   BOOLEAN                                   EmbeddedRom;
 235
 236   //
 237   // The OptionRom Size
 238   //
 239   UINT64                                    RomSize;
 240
 241   //
 242   // TRUE if all OpROM (in device or in platform specific position) have been processed
 243   //
 244   BOOLEAN                                   AllOpRomProcessed;
 245
 246   //
 247   // TRUE if there is any EFI driver in the OptionRom
 248   //
 249   BOOLEAN                                   BusOverride;
 250
 251   //
 252   // A list tracking reserved resource on a bridge device
 253   //
 254   LIST_ENTRY                                ReservedResourceList;
 255
 256   //
 257   // A list tracking image handle of platform specific overriding driver
 258   //
 259   LIST_ENTRY                                OptionRomDriverList;
 260
 261   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 262   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 263
 264   //
 265   // Bus number ranges for a PCI Root Bridge device
 266   //
 267   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *BusNumberRanges;
 268
 269   BOOLEAN                                   IsPciExp;
 270   //
 271   // For SR-IOV
 272   //
 273   UINT8                                     PciExpressCapabilityOffset;
 274   UINT32                                    AriCapabilityOffset;
 275   UINT32                                    SrIovCapabilityOffset;
 276   UINT32                                    MrIovCapabilityOffset;
 277   PCI_BAR                                   VfPciBar[PCI_MAX_BAR];
 278   UINT32                                    SystemPageSize;
 279   UINT16                                    InitialVFs;
 280   UINT16                                    ReservedBusNum;
 281   //
 282   // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
 283   // but some chipsets support non-standard I/O window alignments less than 4K.
 284   // This field is used to support this case.
 285   //
 286   UINT16                                    BridgeIoAlignment;
 287 };
 288
 289 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 290   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 291
 292 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 293   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 294
 295 #define PCI_IO_DEVICE_FROM_LINK(a) \
 296   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 297
 298 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
 299   CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
 300
 301
 302
 303 //
 304 // Global Variables
 305 //
 306 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
 307 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 308 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 309 extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
 310 extern BOOLEAN                                      gFullEnumeration;
 311 extern UINTN                                        gPciHostBridgeNumber;
 312 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 313 extern UINT64                                       gAllOne;
 314 extern UINT64                                       gAllZero;
 315 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 316 extern EFI_PCI_OVERRIDE_PROTOCOL                    *gPciOverrideProtocol;
 317 extern BOOLEAN                                      mReserveIsaAliases;
 318 extern BOOLEAN                                      mReserveVgaAliases;
 319
 320 /**
 321   Macro that checks whether device is a GFX device.
 322
 323   @param  _p      Specified device.
 324
 325   @retval TRUE    Device is a GFX device.
 326   @retval FALSE   Device is not a GFX device.
 327
 328 **/
 329 #define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
 330
 331 /**
 332   Test to see if this driver supports ControllerHandle. Any ControllerHandle
 333   than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
 334
 335   @param  This                Protocol instance pointer.
 336   @param  Controller          Handle of device to test.
 337   @param  RemainingDevicePath Optional parameter use to pick a specific child
 338                               device to start.
 339
 340   @retval EFI_SUCCESS         This driver supports this device.
 341   @retval EFI_ALREADY_STARTED This driver is already running on this device.
 342   @retval other               This driver does not support this device.
 343
 344 **/
 345 EFI_STATUS
 346 EFIAPI
 347 PciBusDriverBindingSupported (
 348   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 349   IN EFI_HANDLE                     Controller,
 350   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 351   );
 352
 353 /**
 354   Start this driver on ControllerHandle and enumerate Pci bus and start
 355   all device under PCI bus.
 356
 357   @param  This                 Protocol instance pointer.
 358   @param  Controller           Handle of device to bind driver to.
 359   @param  RemainingDevicePath  Optional parameter use to pick a specific child
 360                                device to start.
 361
 362   @retval EFI_SUCCESS          This driver is added to ControllerHandle.
 363   @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.
 364   @retval other                This driver does not support this device.
 365
 366 **/
 367 EFI_STATUS
 368 EFIAPI
 369 PciBusDriverBindingStart (
 370   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 371   IN EFI_HANDLE                     Controller,
 372   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 373   );
 374
 375 /**
 376   Stop this driver on ControllerHandle. Support stopping any child handles
 377   created by this driver.
 378
 379   @param  This              Protocol instance pointer.
 380   @param  Controller        Handle of device to stop driver on.
 381   @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of
 382                             children is zero stop the entire bus driver.
 383   @param  ChildHandleBuffer List of Child Handles to Stop.
 384
 385   @retval EFI_SUCCESS       This driver is removed ControllerHandle.
 386   @retval other             This driver was not removed from this device.
 387
 388 **/
 389 EFI_STATUS
 390 EFIAPI
 391 PciBusDriverBindingStop (
 392   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 393   IN  EFI_HANDLE                    Controller,
 394   IN  UINTN                         NumberOfChildren,
 395   IN  EFI_HANDLE                    *ChildHandleBuffer
 396   );
 397
 398 #endif