MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h

   1 /** @file
   2   Header files and data structures needed by PCI Bus module.
   3
   4 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
   5 SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9
  10 #ifndef _EFI_PCI_BUS_H_
  11 #define _EFI_PCI_BUS_H_
  12
  13 #include <PiDxe.h>
  14
  15 #include <Protocol/LoadedImage.h>
  16 #include <Protocol/PciHostBridgeResourceAllocation.h>
  17 #include <Protocol/PciIo.h>
  18 #include <Protocol/LoadFile2.h>
  19 #include <Protocol/PciRootBridgeIo.h>
  20 #include <Protocol/PciHotPlugRequest.h>
  21 #include <Protocol/DevicePath.h>
  22 #include <Protocol/PciPlatform.h>
  23 #include <Protocol/PciHotPlugInit.h>
  24 #include <Protocol/Decompress.h>
  25 #include <Protocol/BusSpecificDriverOverride.h>
  26 #include <Protocol/IncompatiblePciDeviceSupport.h>
  27 #include <Protocol/PciOverride.h>
  28 #include <Protocol/PciEnumerationComplete.h>
  29 #include <Protocol/IoMmu.h>
  30
  31 #include <Library/DebugLib.h>
  32 #include <Library/UefiDriverEntryPoint.h>
  33 #include <Library/BaseLib.h>
  34 #include <Library/UefiLib.h>
  35 #include <Library/BaseMemoryLib.h>
  36 #include <Library/ReportStatusCodeLib.h>
  37 #include <Library/MemoryAllocationLib.h>
  38 #include <Library/UefiBootServicesTableLib.h>
  39 #include <Library/DevicePathLib.h>
  40 #include <Library/PcdLib.h>
  41
  42 #include <IndustryStandard/Pci.h>
  43 #include <IndustryStandard/PeImage.h>
  44 #include <IndustryStandard/Acpi.h>
  45
  46 typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;
  47 typedef struct _PCI_BAR                    PCI_BAR;
  48
  49 #define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
  50 #define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)
  51
  52 #define     EFI_PCI_IOV_POLICY_ARI           0x0001
  53 #define     EFI_PCI_IOV_POLICY_SRIOV         0x0002
  54 #define     EFI_PCI_IOV_POLICY_MRIOV         0x0004
  55
  56 typedef enum {
  57   PciBarTypeUnknown = 0,
  58   PciBarTypeIo16,
  59   PciBarTypeIo32,
  60   PciBarTypeMem32,
  61   PciBarTypePMem32,
  62   PciBarTypeMem64,
  63   PciBarTypePMem64,
  64   PciBarTypeOpRom,
  65   PciBarTypeIo,
  66   PciBarTypeMem,
  67   PciBarTypeMaxType
  68 } PCI_BAR_TYPE;
  69
  70 #include "ComponentName.h"
  71 #include "PciIo.h"
  72 #include "PciCommand.h"
  73 #include "PciDeviceSupport.h"
  74 #include "PciEnumerator.h"
  75 #include "PciEnumeratorSupport.h"
  76 #include "PciDriverOverride.h"
  77 #include "PciRomTable.h"
  78 #include "PciOptionRomSupport.h"
  79 #include "PciPowerManagement.h"
  80 #include "PciHotPlugSupport.h"
  81 #include "PciLib.h"
  82
  83 #define VGABASE1  0x3B0
  84 #define VGALIMIT1 0x3BB
  85
  86 #define VGABASE2  0x3C0
  87 #define VGALIMIT2 0x3DF
  88
  89 #define ISABASE   0x100
  90 #define ISALIMIT  0x3FF
  91
  92 //
  93 // PCI BAR parameters
  94 //
  95 struct _PCI_BAR {
  96   UINT64        BaseAddress;
  97   UINT64        Length;
  98   UINT64        Alignment;
  99   PCI_BAR_TYPE  BarType;
 100   BOOLEAN       BarTypeFixed;
 101   UINT16        Offset;
 102 };
 103
 104 //
 105 // defined in PCI Card Specification, 8.0
 106 //
 107 #define PCI_CARD_MEMORY_BASE_0                0x1C
 108 #define PCI_CARD_MEMORY_LIMIT_0               0x20
 109 #define PCI_CARD_MEMORY_BASE_1                0x24
 110 #define PCI_CARD_MEMORY_LIMIT_1               0x28
 111 #define PCI_CARD_IO_BASE_0_LOWER              0x2C
 112 #define PCI_CARD_IO_BASE_0_UPPER              0x2E
 113 #define PCI_CARD_IO_LIMIT_0_LOWER             0x30
 114 #define PCI_CARD_IO_LIMIT_0_UPPER             0x32
 115 #define PCI_CARD_IO_BASE_1_LOWER              0x34
 116 #define PCI_CARD_IO_BASE_1_UPPER              0x36
 117 #define PCI_CARD_IO_LIMIT_1_LOWER             0x38
 118 #define PCI_CARD_IO_LIMIT_1_UPPER             0x3A
 119 #define PCI_CARD_BRIDGE_CONTROL               0x3E
 120
 121 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
 122 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
 123
 124 #define RB_IO_RANGE                           1
 125 #define RB_MEM32_RANGE                        2
 126 #define RB_PMEM32_RANGE                       3
 127 #define RB_MEM64_RANGE                        4
 128 #define RB_PMEM64_RANGE                       5
 129
 130 #define PPB_BAR_0                             0
 131 #define PPB_BAR_1                             1
 132 #define PPB_IO_RANGE                          2
 133 #define PPB_MEM32_RANGE                       3
 134 #define PPB_PMEM32_RANGE                      4
 135 #define PPB_PMEM64_RANGE                      5
 136 #define PPB_MEM64_RANGE                       0xFF
 137
 138 #define P2C_BAR_0                             0
 139 #define P2C_MEM_1                             1
 140 #define P2C_MEM_2                             2
 141 #define P2C_IO_1                              3
 142 #define P2C_IO_2                              4
 143
 144 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 145 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 146 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 147 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 148 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 149 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 150 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 151
 152 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 153
 154 //
 155 // Define option for attribute
 156 //
 157 #define EFI_SET_SUPPORTS    0
 158 #define EFI_SET_ATTRIBUTES  1
 159
 160 #define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')
 161
 162 struct _PCI_IO_DEVICE {
 163   UINT32                                    Signature;
 164   EFI_HANDLE                                Handle;
 165   EFI_PCI_IO_PROTOCOL                       PciIo;
 166   LIST_ENTRY                                Link;
 167
 168   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 169   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 170   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 171   EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;
 172
 173   //
 174   // PCI configuration space header type
 175   //
 176   PCI_TYPE00                                Pci;
 177
 178   //
 179   // Bus number, Device number, Function number
 180   //
 181   UINT8                                     BusNumber;
 182   UINT8                                     DeviceNumber;
 183   UINT8                                     FunctionNumber;
 184
 185   //
 186   // BAR for this PCI Device
 187   //
 188   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 189
 190   //
 191   // The bridge device this pci device is subject to
 192   //
 193   PCI_IO_DEVICE                             *Parent;
 194
 195   //
 196   // A linked list for children Pci Device if it is bridge device
 197   //
 198   LIST_ENTRY                                ChildList;
 199
 200   //
 201   // TRUE if the PCI bus driver creates the handle for this PCI device
 202   //
 203   BOOLEAN                                   Registered;
 204
 205   //
 206   // TRUE if the PCI bus driver successfully allocates the resource required by
 207   // this PCI device
 208   //
 209   BOOLEAN                                   Allocated;
 210
 211   //
 212   // The attribute this PCI device currently set
 213   //
 214   UINT64                                    Attributes;
 215
 216   //
 217   // The attributes this PCI device actually supports
 218   //
 219   UINT64                                    Supports;
 220
 221   //
 222   // The resource decode the bridge supports
 223   //
 224   UINT32                                    Decodes;
 225
 226   //
 227   // TRUE if the ROM image is from the PCI Option ROM BAR
 228   //
 229   BOOLEAN                                   EmbeddedRom;
 230
 231   //
 232   // The OptionRom Size
 233   //
 234   UINT32                                    RomSize;
 235
 236   //
 237   // TRUE if all OpROM (in device or in platform specific position) have been processed
 238   //
 239   BOOLEAN                                   AllOpRomProcessed;
 240
 241   //
 242   // TRUE if there is any EFI driver in the OptionRom
 243   //
 244   BOOLEAN                                   BusOverride;
 245
 246   //
 247   // A list tracking reserved resource on a bridge device
 248   //
 249   LIST_ENTRY                                ReservedResourceList;
 250
 251   //
 252   // A list tracking image handle of platform specific overriding driver
 253   //
 254   LIST_ENTRY                                OptionRomDriverList;
 255
 256   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 257   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 258
 259   //
 260   // Bus number ranges for a PCI Root Bridge device
 261   //
 262   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *BusNumberRanges;
 263
 264   BOOLEAN                                   IsPciExp;
 265   //
 266   // For SR-IOV
 267   //
 268   UINT8                                     PciExpressCapabilityOffset;
 269   UINT32                                    AriCapabilityOffset;
 270   UINT32                                    SrIovCapabilityOffset;
 271   UINT32                                    MrIovCapabilityOffset;
 272   PCI_BAR                                   VfPciBar[PCI_MAX_BAR];
 273   UINT32                                    SystemPageSize;
 274   UINT16                                    InitialVFs;
 275   UINT16                                    ReservedBusNum;
 276   //
 277   // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
 278   // but some chipsets support non-standard I/O window alignments less than 4K.
 279   // This field is used to support this case.
 280   //
 281   UINT16                                    BridgeIoAlignment;
 282 };
 283
 284 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 285   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 286
 287 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 288   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 289
 290 #define PCI_IO_DEVICE_FROM_LINK(a) \
 291   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 292
 293 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
 294   CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
 295
 296
 297
 298 //
 299 // Global Variables
 300 //
 301 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
 302 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 303 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 304 extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
 305 extern BOOLEAN                                      gFullEnumeration;
 306 extern UINTN                                        gPciHostBridgeNumber;
 307 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 308 extern UINT64                                       gAllOne;
 309 extern UINT64                                       gAllZero;
 310 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 311 extern EFI_PCI_OVERRIDE_PROTOCOL                    *gPciOverrideProtocol;
 312 extern BOOLEAN                                      mReserveIsaAliases;
 313 extern BOOLEAN                                      mReserveVgaAliases;
 314
 315 /**
 316   Macro that checks whether device is a GFX device.
 317
 318   @param  _p      Specified device.
 319
 320   @retval TRUE    Device is a GFX device.
 321   @retval FALSE   Device is not a GFX device.
 322
 323 **/
 324 #define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
 325
 326 /**
 327   Test to see if this driver supports ControllerHandle. Any ControllerHandle
 328   than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
 329
 330   @param  This                Protocol instance pointer.
 331   @param  Controller          Handle of device to test.
 332   @param  RemainingDevicePath Optional parameter use to pick a specific child
 333                               device to start.
 334
 335   @retval EFI_SUCCESS         This driver supports this device.
 336   @retval EFI_ALREADY_STARTED This driver is already running on this device.
 337   @retval other               This driver does not support this device.
 338
 339 **/
 340 EFI_STATUS
 341 EFIAPI
 342 PciBusDriverBindingSupported (
 343   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 344   IN EFI_HANDLE                     Controller,
 345   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 346   );
 347
 348 /**
 349   Start this driver on ControllerHandle and enumerate Pci bus and start
 350   all device under PCI bus.
 351
 352   @param  This                 Protocol instance pointer.
 353   @param  Controller           Handle of device to bind driver to.
 354   @param  RemainingDevicePath  Optional parameter use to pick a specific child
 355                                device to start.
 356
 357   @retval EFI_SUCCESS          This driver is added to ControllerHandle.
 358   @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.
 359   @retval other                This driver does not support this device.
 360
 361 **/
 362 EFI_STATUS
 363 EFIAPI
 364 PciBusDriverBindingStart (
 365   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 366   IN EFI_HANDLE                     Controller,
 367   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 368   );
 369
 370 /**
 371   Stop this driver on ControllerHandle. Support stopping any child handles
 372   created by this driver.
 373
 374   @param  This              Protocol instance pointer.
 375   @param  Controller        Handle of device to stop driver on.
 376   @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of
 377                             children is zero stop the entire bus driver.
 378   @param  ChildHandleBuffer List of Child Handles to Stop.
 379
 380   @retval EFI_SUCCESS       This driver is removed ControllerHandle.
 381   @retval other             This driver was not removed from this device.
 382
 383 **/
 384 EFI_STATUS
 385 EFIAPI
 386 PciBusDriverBindingStop (
 387   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 388   IN  EFI_HANDLE                    Controller,
 389   IN  UINTN                         NumberOfChildren,
 390   IN  EFI_HANDLE                    *ChildHandleBuffer
 391   );
 392
 393 #endif