MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h

   1 /** @file
   2   Header files and data structures needed by PCI Bus module.
   3
   4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15
  16 #ifndef _EFI_PCI_BUS_H_
  17 #define _EFI_PCI_BUS_H_
  18
  19 #include <PiDxe.h>
  20
  21 #include <Protocol/LoadedImage.h>
  22 #include <Protocol/PciHostBridgeResourceAllocation.h>
  23 #include <Protocol/PciIo.h>
  24 #include <Protocol/LoadFile2.h>
  25 #include <Protocol/PciRootBridgeIo.h>
  26 #include <Protocol/PciHotPlugRequest.h>
  27 #include <Protocol/DevicePath.h>
  28 #include <Protocol/PciPlatform.h>
  29 #include <Protocol/PciHotPlugInit.h>
  30 #include <Protocol/Decompress.h>
  31 #include <Protocol/BusSpecificDriverOverride.h>
  32 #include <Protocol/IncompatiblePciDeviceSupport.h>
  33 #include <Protocol/PciOverride.h>
  34 #include <Protocol/PciEnumerationComplete.h>
  35
  36 #include <Library/DebugLib.h>
  37 #include <Library/UefiDriverEntryPoint.h>
  38 #include <Library/BaseLib.h>
  39 #include <Library/UefiLib.h>
  40 #include <Library/BaseMemoryLib.h>
  41 #include <Library/ReportStatusCodeLib.h>
  42 #include <Library/MemoryAllocationLib.h>
  43 #include <Library/UefiBootServicesTableLib.h>
  44 #include <Library/DevicePathLib.h>
  45 #include <Library/PcdLib.h>
  46 #include <Library/PeCoffLib.h>
  47
  48 #include <IndustryStandard/Pci.h>
  49 #include <IndustryStandard/PeImage.h>
  50 #include <IndustryStandard/Acpi.h>
  51
  52 typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;
  53 typedef struct _PCI_BAR                    PCI_BAR;
  54
  55 #define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
  56 #define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)
  57
  58 #define     EFI_PCI_IOV_POLICY_ARI           0x0001
  59 #define     EFI_PCI_IOV_POLICY_SRIOV         0x0002
  60 #define     EFI_PCI_IOV_POLICY_MRIOV         0x0004
  61
  62 typedef enum {
  63   PciBarTypeUnknown = 0,
  64   PciBarTypeIo16,
  65   PciBarTypeIo32,
  66   PciBarTypeMem32,
  67   PciBarTypePMem32,
  68   PciBarTypeMem64,
  69   PciBarTypePMem64,
  70   PciBarTypeIo,
  71   PciBarTypeMem,
  72   PciBarTypeMaxType
  73 } PCI_BAR_TYPE;
  74
  75 #include "ComponentName.h"
  76 #include "PciIo.h"
  77 #include "PciCommand.h"
  78 #include "PciDeviceSupport.h"
  79 #include "PciEnumerator.h"
  80 #include "PciEnumeratorSupport.h"
  81 #include "PciDriverOverride.h"
  82 #include "PciRomTable.h"
  83 #include "PciOptionRomSupport.h"
  84 #include "PciPowerManagement.h"
  85 #include "PciHotPlugSupport.h"
  86 #include "PciLib.h"
  87
  88 #define VGABASE1  0x3B0
  89 #define VGALIMIT1 0x3BB
  90
  91 #define VGABASE2  0x3C0
  92 #define VGALIMIT2 0x3DF
  93
  94 #define ISABASE   0x100
  95 #define ISALIMIT  0x3FF
  96
  97 //
  98 // PCI BAR parameters
  99 //
 100 struct _PCI_BAR {
 101   UINT64        BaseAddress;
 102   UINT64        Length;
 103   UINT64        Alignment;
 104   PCI_BAR_TYPE  BarType;
 105   UINT16        Offset;
 106 };
 107
 108 //
 109 // defined in PCI Card Specification, 8.0
 110 //
 111 #define PCI_CARD_MEMORY_BASE_0                0x1C
 112 #define PCI_CARD_MEMORY_LIMIT_0               0x20
 113 #define PCI_CARD_MEMORY_BASE_1                0x24
 114 #define PCI_CARD_MEMORY_LIMIT_1               0x28
 115 #define PCI_CARD_IO_BASE_0_LOWER              0x2C
 116 #define PCI_CARD_IO_BASE_0_UPPER              0x2E
 117 #define PCI_CARD_IO_LIMIT_0_LOWER             0x30
 118 #define PCI_CARD_IO_LIMIT_0_UPPER             0x32
 119 #define PCI_CARD_IO_BASE_1_LOWER              0x34
 120 #define PCI_CARD_IO_BASE_1_UPPER              0x36
 121 #define PCI_CARD_IO_LIMIT_1_LOWER             0x38
 122 #define PCI_CARD_IO_LIMIT_1_UPPER             0x3A
 123 #define PCI_CARD_BRIDGE_CONTROL               0x3E
 124
 125 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
 126 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
 127
 128 #define RB_IO_RANGE                           1
 129 #define RB_MEM32_RANGE                        2
 130 #define RB_PMEM32_RANGE                       3
 131 #define RB_MEM64_RANGE                        4
 132 #define RB_PMEM64_RANGE                       5
 133
 134 #define PPB_BAR_0                             0
 135 #define PPB_BAR_1                             1
 136 #define PPB_IO_RANGE                          2
 137 #define PPB_MEM32_RANGE                       3
 138 #define PPB_PMEM32_RANGE                      4
 139 #define PPB_PMEM64_RANGE                      5
 140 #define PPB_MEM64_RANGE                       0xFF
 141
 142 #define P2C_BAR_0                             0
 143 #define P2C_MEM_1                             1
 144 #define P2C_MEM_2                             2
 145 #define P2C_IO_1                              3
 146 #define P2C_IO_2                              4
 147
 148 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 149 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 150 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 151 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 152 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 153 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 154 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 155
 156 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 157
 158 //
 159 // Define option for attribute
 160 //
 161 #define EFI_SET_SUPPORTS    0
 162 #define EFI_SET_ATTRIBUTES  1
 163
 164 #define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')
 165
 166 struct _PCI_IO_DEVICE {
 167   UINT32                                    Signature;
 168   EFI_HANDLE                                Handle;
 169   EFI_PCI_IO_PROTOCOL                       PciIo;
 170   LIST_ENTRY                                Link;
 171
 172   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 173   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 174   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 175   EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;
 176
 177   //
 178   // PCI configuration space header type
 179   //
 180   PCI_TYPE00                                Pci;
 181
 182   //
 183   // Bus number, Device number, Function number
 184   //
 185   UINT8                                     BusNumber;
 186   UINT8                                     DeviceNumber;
 187   UINT8                                     FunctionNumber;
 188
 189   //
 190   // BAR for this PCI Device
 191   //
 192   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 193
 194   //
 195   // The bridge device this pci device is subject to
 196   //
 197   PCI_IO_DEVICE                             *Parent;
 198
 199   //
 200   // A linked list for children Pci Device if it is bridge device
 201   //
 202   LIST_ENTRY                                ChildList;
 203
 204   //
 205   // TURE if the PCI bus driver creates the handle for this PCI device
 206   //
 207   BOOLEAN                                   Registered;
 208
 209   //
 210   // TRUE if the PCI bus driver successfully allocates the resource required by
 211   // this PCI device
 212   //
 213   BOOLEAN                                   Allocated;
 214
 215   //
 216   // The attribute this PCI device currently set
 217   //
 218   UINT64                                    Attributes;
 219
 220   //
 221   // The attributes this PCI device actually supports
 222   //
 223   UINT64                                    Supports;
 224
 225   //
 226   // The resource decode the bridge supports
 227   //
 228   UINT32                                    Decodes;
 229
 230   //
 231   // TRUE if the ROM image is from the PCI Option ROM BAR
 232   //
 233   BOOLEAN                                   EmbeddedRom;
 234
 235   //
 236   // The OptionRom Size
 237   //
 238   UINT64                                    RomSize;
 239
 240   //
 241   // The OptionRom Size
 242   //
 243   UINT64                                    RomBase;
 244
 245   //
 246   // TRUE if all OpROM (in device or in platform specific position) have been processed
 247   //
 248   BOOLEAN                                   AllOpRomProcessed;
 249
 250   //
 251   // TRUE if there is any EFI driver in the OptionRom
 252   //
 253   BOOLEAN                                   BusOverride;
 254
 255   //
 256   // A list tracking reserved resource on a bridge device
 257   //
 258   LIST_ENTRY                                ReservedResourceList;
 259
 260   //
 261   // A list tracking image handle of platform specific overriding driver
 262   //
 263   LIST_ENTRY                                OptionRomDriverList;
 264
 265   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 266   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 267
 268   //
 269   // Bus number ranges for a PCI Root Bridge device
 270   //
 271   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *BusNumberRanges;
 272
 273   BOOLEAN                                   IsPciExp;
 274   //
 275   // For SR-IOV
 276   //
 277   UINT8                                     PciExpressCapabilityOffset;
 278   UINT32                                    AriCapabilityOffset;
 279   UINT32                                    SrIovCapabilityOffset;
 280   UINT32                                    MrIovCapabilityOffset;
 281   PCI_BAR                                   VfPciBar[PCI_MAX_BAR];
 282   UINT32                                    SystemPageSize;
 283   UINT16                                    InitialVFs;
 284   UINT16                                    ReservedBusNum;
 285   //
 286   // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
 287   // but some chipsets support non-stardard I/O window aligments less than 4K.
 288   // This field is used to support this case.
 289   //
 290   UINT16                                    BridgeIoAlignment;
 291 };
 292
 293 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 294   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 295
 296 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 297   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 298
 299 #define PCI_IO_DEVICE_FROM_LINK(a) \
 300   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 301
 302 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
 303   CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
 304
 305
 306
 307 //
 308 // Global Variables
 309 //
 310 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gIncompatiblePciDeviceSupport;
 311 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 312 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 313 extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
 314 extern BOOLEAN                                      gFullEnumeration;
 315 extern UINTN                                        gPciHostBridgeNumber;
 316 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 317 extern UINT64                                       gAllOne;
 318 extern UINT64                                       gAllZero;
 319 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 320 extern EFI_PCI_OVERRIDE_PROTOCOL                    *gPciOverrideProtocol;
 321 extern BOOLEAN                                      mReserveIsaAliases;
 322 extern BOOLEAN                                      mReserveVgaAliases;
 323
 324 /**
 325   Macro that checks whether device is a GFX device.
 326
 327   @param  _p      Specified device.
 328
 329   @retval TRUE    Device is a a GFX device.
 330   @retval FALSE   Device is not a a GFX device.
 331
 332 **/
 333 #define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
 334
 335 /**
 336   Test to see if this driver supports ControllerHandle. Any ControllerHandle
 337   than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
 338
 339   @param  This                Protocol instance pointer.
 340   @param  Controller          Handle of device to test.
 341   @param  RemainingDevicePath Optional parameter use to pick a specific child.
 342                               device to start.
 343
 344   @retval EFI_SUCCESS         This driver supports this device.
 345   @retval EFI_ALREADY_STARTED This driver is already running on this device.
 346   @retval other               This driver does not support this device.
 347
 348 **/
 349 EFI_STATUS
 350 EFIAPI
 351 PciBusDriverBindingSupported (
 352   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 353   IN EFI_HANDLE                     Controller,
 354   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 355   );
 356
 357 /**
 358   Start this driver on ControllerHandle and enumerate Pci bus and start
 359   all device under PCI bus.
 360
 361   @param  This                 Protocol instance pointer.
 362   @param  Controller           Handle of device to bind driver to.
 363   @param  RemainingDevicePath  Optional parameter use to pick a specific child.
 364                                device to start.
 365
 366   @retval EFI_SUCCESS          This driver is added to ControllerHandle.
 367   @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.
 368   @retval other                This driver does not support this device.
 369
 370 **/
 371 EFI_STATUS
 372 EFIAPI
 373 PciBusDriverBindingStart (
 374   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 375   IN EFI_HANDLE                     Controller,
 376   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 377   );
 378
 379 /**
 380   Stop this driver on ControllerHandle. Support stoping any child handles
 381   created by this driver.
 382
 383   @param  This              Protocol instance pointer.
 384   @param  Controller        Handle of device to stop driver on.
 385   @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of
 386                             children is zero stop the entire bus driver.
 387   @param  ChildHandleBuffer List of Child Handles to Stop.
 388
 389   @retval EFI_SUCCESS       This driver is removed ControllerHandle.
 390   @retval other             This driver was not removed from this device.
 391
 392 **/
 393 EFI_STATUS
 394 EFIAPI
 395 PciBusDriverBindingStop (
 396   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 397   IN  EFI_HANDLE                    Controller,
 398   IN  UINTN                         NumberOfChildren,
 399   IN  EFI_HANDLE                    *ChildHandleBuffer
 400   );
 401
 402 #endif