MdeModulePkg/Bus/Pci/PciBusDxe/PciCommand.h

   1 /** @file
   2   PCI command register operations supporting functions declaration for PCI Bus module.
   3
   4 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
   5 SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9
  10 #ifndef _EFI_PCI_COMMAND_H_
  11 #define _EFI_PCI_COMMAND_H_
  12
  13 //
  14 // The PCI Command register bits owned by PCI Bus driver.
  15 //
  16 // They should be cleared at the beginning. The other registers
  17 // are owned by chipset, we should not touch them.
  18 //
  19 #define EFI_PCI_COMMAND_BITS_OWNED                          ( \
  20                 EFI_PCI_COMMAND_IO_SPACE                    | \
  21                 EFI_PCI_COMMAND_MEMORY_SPACE                | \
  22                 EFI_PCI_COMMAND_BUS_MASTER                  | \
  23                 EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE | \
  24                 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP           | \
  25                 EFI_PCI_COMMAND_FAST_BACK_TO_BACK             \
  26                 )
  27
  28 //
  29 // The PCI Bridge Control register bits owned by PCI Bus driver.
  30 //
  31 // They should be cleared at the beginning. The other registers
  32 // are owned by chipset, we should not touch them.
  33 //
  34 #define EFI_PCI_BRIDGE_CONTROL_BITS_OWNED                   ( \
  35                 EFI_PCI_BRIDGE_CONTROL_ISA                  | \
  36                 EFI_PCI_BRIDGE_CONTROL_VGA                  | \
  37                 EFI_PCI_BRIDGE_CONTROL_VGA_16               | \
  38                 EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK      \
  39                 )
  40
  41 //
  42 // The PCCard Bridge Control register bits owned by PCI Bus driver.
  43 //
  44 // They should be cleared at the beginning. The other registers
  45 // are owned by chipset, we should not touch them.
  46 //
  47 #define EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED                ( \
  48                 EFI_PCI_BRIDGE_CONTROL_ISA                  | \
  49                 EFI_PCI_BRIDGE_CONTROL_VGA                  | \
  50                 EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK      \
  51                 )
  52
  53
  54 #define EFI_GET_REGISTER      1
  55 #define EFI_SET_REGISTER      2
  56 #define EFI_ENABLE_REGISTER   3
  57 #define EFI_DISABLE_REGISTER  4
  58
  59 /**
  60   Operate the PCI register via PciIo function interface.
  61
  62   @param PciIoDevice    Pointer to instance of PCI_IO_DEVICE.
  63   @param Command        Operator command.
  64   @param Offset         The address within the PCI configuration space for the PCI controller.
  65   @param Operation      Type of Operation.
  66   @param PtrCommand     Return buffer holding old PCI command, if operation is not EFI_SET_REGISTER.
  67
  68   @return Status of PciIo operation.
  69
  70 **/
  71 EFI_STATUS
  72 PciOperateRegister (
  73   IN  PCI_IO_DEVICE *PciIoDevice,
  74   IN  UINT16        Command,
  75   IN  UINT8         Offset,
  76   IN  UINT8         Operation,
  77   OUT UINT16        *PtrCommand
  78   );
  79
  80 /**
  81   Check the capability supporting by given device.
  82
  83   @param PciIoDevice   Pointer to instance of PCI_IO_DEVICE.
  84
  85   @retval TRUE         Capability supported.
  86   @retval FALSE        Capability not supported.
  87
  88 **/
  89 BOOLEAN
  90 PciCapabilitySupport (
  91   IN PCI_IO_DEVICE  *PciIoDevice
  92   );
  93
  94 /**
  95   Locate capability register block per capability ID.
  96
  97   @param PciIoDevice       A pointer to the PCI_IO_DEVICE.
  98   @param CapId             The capability ID.
  99   @param Offset            A pointer to the offset returned.
 100   @param NextRegBlock      A pointer to the next block returned.
 101
 102   @retval EFI_SUCCESS      Successfully located capability register block.
 103   @retval EFI_UNSUPPORTED  Pci device does not support capability.
 104   @retval EFI_NOT_FOUND    Pci device support but can not find register block.
 105
 106 **/
 107 EFI_STATUS
 108 LocateCapabilityRegBlock (
 109   IN PCI_IO_DEVICE  *PciIoDevice,
 110   IN UINT8          CapId,
 111   IN OUT UINT8      *Offset,
 112   OUT UINT8         *NextRegBlock OPTIONAL
 113   );
 114
 115 /**
 116   Locate PciExpress capability register block per capability ID.
 117
 118   @param PciIoDevice       A pointer to the PCI_IO_DEVICE.
 119   @param CapId             The capability ID.
 120   @param Offset            A pointer to the offset returned.
 121   @param NextRegBlock      A pointer to the next block returned.
 122
 123   @retval EFI_SUCCESS      Successfully located capability register block.
 124   @retval EFI_UNSUPPORTED  Pci device does not support capability.
 125   @retval EFI_NOT_FOUND    Pci device support but can not find register block.
 126
 127 **/
 128 EFI_STATUS
 129 LocatePciExpressCapabilityRegBlock (
 130   IN     PCI_IO_DEVICE *PciIoDevice,
 131   IN     UINT16        CapId,
 132   IN OUT UINT32        *Offset,
 133      OUT UINT32        *NextRegBlock OPTIONAL
 134   );
 135
 136 /**
 137   Macro that reads command register.
 138
 139   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 140   @param b[out]           Pointer to the 16-bit value read from command register.
 141
 142   @return status of PciIo operation
 143
 144 **/
 145 #define PCI_READ_COMMAND_REGISTER(a,b) \
 146         PciOperateRegister (a, 0, PCI_COMMAND_OFFSET, EFI_GET_REGISTER, b)
 147
 148 /**
 149   Macro that writes command register.
 150
 151   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 152   @param b[in]            The 16-bit value written into command register.
 153
 154   @return status of PciIo operation
 155
 156 **/
 157 #define PCI_SET_COMMAND_REGISTER(a,b) \
 158         PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_SET_REGISTER, NULL)
 159
 160 /**
 161   Macro that enables command register.
 162
 163   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 164   @param b[in]            The enabled value written into command register.
 165
 166   @return status of PciIo operation
 167
 168 **/
 169 #define PCI_ENABLE_COMMAND_REGISTER(a,b) \
 170         PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_ENABLE_REGISTER, NULL)
 171
 172 /**
 173   Macro that disables command register.
 174
 175   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 176   @param b[in]            The disabled value written into command register.
 177
 178   @return status of PciIo operation
 179
 180 **/
 181 #define PCI_DISABLE_COMMAND_REGISTER(a,b) \
 182         PciOperateRegister (a, b, PCI_COMMAND_OFFSET, EFI_DISABLE_REGISTER, NULL)
 183
 184 /**
 185   Macro that reads PCI bridge control register.
 186
 187   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 188   @param b[out]           The 16-bit value read from control register.
 189
 190   @return status of PciIo operation
 191
 192 **/
 193 #define PCI_READ_BRIDGE_CONTROL_REGISTER(a,b) \
 194         PciOperateRegister (a, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_GET_REGISTER, b)
 195
 196 /**
 197   Macro that writes PCI bridge control register.
 198
 199   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 200   @param b[in]            The 16-bit value written into control register.
 201
 202   @return status of PciIo operation
 203
 204 **/
 205 #define PCI_SET_BRIDGE_CONTROL_REGISTER(a,b) \
 206         PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_SET_REGISTER, NULL)
 207
 208 /**
 209   Macro that enables PCI bridge control register.
 210
 211   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 212   @param b[in]            The enabled value written into command register.
 213
 214   @return status of PciIo operation
 215
 216 **/
 217 #define PCI_ENABLE_BRIDGE_CONTROL_REGISTER(a,b) \
 218         PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_ENABLE_REGISTER, NULL)
 219
 220 /**
 221  Macro that disables PCI bridge control register.
 222
 223   @param a[in]            Pointer to instance of PCI_IO_DEVICE.
 224   @param b[in]            The disabled value written into command register.
 225
 226   @return status of PciIo operation
 227
 228 **/
 229 #define PCI_DISABLE_BRIDGE_CONTROL_REGISTER(a,b) \
 230         PciOperateRegister (a, b, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_DISABLE_REGISTER, NULL)
 231
 232 #endif