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[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciEnumerator.c
1 /** @file
2 PCI eunmeration implementation on entire PCI bus system for PCI Bus module.
3
4 Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "PciBus.h"
16
17 /**
18 This routine is used to enumerate entire pci bus system
19 in a given platform.
20
21 @param Controller Parent controller handle.
22
23 @retval EFI_SUCCESS PCI enumeration finished successfully.
24 @retval other Some error occurred when enumerating the pci bus system.
25
26 **/
27 EFI_STATUS
28 PciEnumerator (
29 IN EFI_HANDLE Controller
30 )
31 {
32 EFI_HANDLE Handle;
33 EFI_HANDLE HostBridgeHandle;
34 EFI_STATUS Status;
35 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;
36 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
37
38 //
39 // If PCI bus has already done the full enumeration, never do it again
40 //
41 if (!gFullEnumeration) {
42 return PciEnumeratorLight (Controller);
43 }
44
45 //
46 // Get the rootbridge Io protocol to find the host bridge handle
47 //
48 Status = gBS->OpenProtocol (
49 Controller,
50 &gEfiPciRootBridgeIoProtocolGuid,
51 (VOID **) &PciRootBridgeIo,
52 gPciBusDriverBinding.DriverBindingHandle,
53 Controller,
54 EFI_OPEN_PROTOCOL_GET_PROTOCOL
55 );
56
57 if (EFI_ERROR (Status)) {
58 return Status;
59 }
60
61 //
62 // Get the host bridge handle
63 //
64 HostBridgeHandle = PciRootBridgeIo->ParentHandle;
65
66 //
67 // Get the pci host bridge resource allocation protocol
68 //
69 Status = gBS->OpenProtocol (
70 HostBridgeHandle,
71 &gEfiPciHostBridgeResourceAllocationProtocolGuid,
72 (VOID **) &PciResAlloc,
73 gPciBusDriverBinding.DriverBindingHandle,
74 Controller,
75 EFI_OPEN_PROTOCOL_GET_PROTOCOL
76 );
77
78 if (EFI_ERROR (Status)) {
79 return Status;
80 }
81
82 //
83 // Notify the pci bus enumeration is about to begin
84 //
85 NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginEnumeration);
86
87 //
88 // Start the bus allocation phase
89 //
90 Status = PciHostBridgeEnumerator (PciResAlloc);
91
92 if (EFI_ERROR (Status)) {
93 return Status;
94 }
95
96 //
97 // Submit the resource request
98 //
99 Status = PciHostBridgeResourceAllocator (PciResAlloc);
100
101 if (EFI_ERROR (Status)) {
102 return Status;
103 }
104
105 //
106 // Notify the pci bus enumeration is about to complete
107 //
108 NotifyPhase (PciResAlloc, EfiPciHostBridgeEndEnumeration);
109
110 //
111 // Process P2C
112 //
113 Status = PciHostBridgeP2CProcess (PciResAlloc);
114
115 if (EFI_ERROR (Status)) {
116 return Status;
117 }
118
119 //
120 // Process attributes for devices on this host bridge
121 //
122 Status = PciHostBridgeDeviceAttribute (PciResAlloc);
123 if (EFI_ERROR (Status)) {
124 return Status;
125 }
126
127 gFullEnumeration = FALSE;
128
129 Handle = NULL;
130 Status = gBS->InstallProtocolInterface (
131 &Handle,
132 &gEfiPciEnumerationCompleteProtocolGuid,
133 EFI_NATIVE_INTERFACE,
134 NULL
135 );
136 if (EFI_ERROR (Status)) {
137 return Status;
138 }
139
140 return EFI_SUCCESS;
141 }
142
143 /**
144 Enumerate PCI root bridge.
145
146 @param PciResAlloc Pointer to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
147 @param RootBridgeDev Instance of root bridge device.
148
149 @retval EFI_SUCCESS Successfully enumerated root bridge.
150 @retval other Failed to enumerate root bridge.
151
152 **/
153 EFI_STATUS
154 PciRootBridgeEnumerator (
155 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
156 IN PCI_IO_DEVICE *RootBridgeDev
157 )
158 {
159 EFI_STATUS Status;
160 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;
161 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration1;
162 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration2;
163 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration3;
164 UINT8 SubBusNumber;
165 UINT8 StartBusNumber;
166 UINT8 PaddedBusRange;
167 EFI_HANDLE RootBridgeHandle;
168 UINT8 Desc;
169 UINT64 AddrLen;
170 UINT64 AddrRangeMin;
171
172 SubBusNumber = 0;
173 StartBusNumber = 0;
174 PaddedBusRange = 0;
175
176 //
177 // Get the root bridge handle
178 //
179 RootBridgeHandle = RootBridgeDev->Handle;
180
181 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
182 EFI_PROGRESS_CODE,
183 EFI_IO_BUS_PCI | EFI_IOB_PCI_BUS_ENUM,
184 RootBridgeDev->DevicePath
185 );
186
187 //
188 // Get the Bus information
189 //
190 Status = PciResAlloc->StartBusEnumeration (
191 PciResAlloc,
192 RootBridgeHandle,
193 (VOID **) &Configuration
194 );
195
196 if (EFI_ERROR (Status)) {
197 return Status;
198 }
199
200 if (Configuration == NULL || Configuration->Desc == ACPI_END_TAG_DESCRIPTOR) {
201 return EFI_INVALID_PARAMETER;
202 }
203 RootBridgeDev->BusNumberRanges = Configuration;
204
205 //
206 // Sort the descriptors in ascending order
207 //
208 for (Configuration1 = Configuration; Configuration1->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration1++) {
209 Configuration2 = Configuration1;
210 for (Configuration3 = Configuration1 + 1; Configuration3->Desc != ACPI_END_TAG_DESCRIPTOR; Configuration3++) {
211 if (Configuration2->AddrRangeMin > Configuration3->AddrRangeMin) {
212 Configuration2 = Configuration3;
213 }
214 }
215 //
216 // All other fields other than AddrRangeMin and AddrLen are ignored in a descriptor,
217 // so only need to swap these two fields.
218 //
219 if (Configuration2 != Configuration1) {
220 AddrRangeMin = Configuration1->AddrRangeMin;
221 Configuration1->AddrRangeMin = Configuration2->AddrRangeMin;
222 Configuration2->AddrRangeMin = AddrRangeMin;
223
224 AddrLen = Configuration1->AddrLen;
225 Configuration1->AddrLen = Configuration2->AddrLen;
226 Configuration2->AddrLen = AddrLen;
227 }
228 }
229
230 //
231 // Get the bus number to start with
232 //
233 StartBusNumber = (UINT8) (Configuration->AddrRangeMin);
234
235 //
236 // Initialize the subordinate bus number
237 //
238 SubBusNumber = StartBusNumber;
239
240 //
241 // Reset all assigned PCI bus number
242 //
243 ResetAllPpbBusNumber (
244 RootBridgeDev,
245 StartBusNumber
246 );
247
248 //
249 // Assign bus number
250 //
251 Status = PciScanBus (
252 RootBridgeDev,
253 StartBusNumber,
254 &SubBusNumber,
255 &PaddedBusRange
256 );
257
258 if (EFI_ERROR (Status)) {
259 return Status;
260 }
261
262
263 //
264 // Assign max bus number scanned
265 //
266
267 Status = PciAllocateBusNumber (RootBridgeDev, SubBusNumber, PaddedBusRange, &SubBusNumber);
268 if (EFI_ERROR (Status)) {
269 return Status;
270 }
271
272 //
273 // Find the bus range which contains the higest bus number, then returns the number of buses
274 // that should be decoded.
275 //
276 while (Configuration->AddrRangeMin + Configuration->AddrLen - 1 < SubBusNumber) {
277 Configuration++;
278 }
279 AddrLen = Configuration->AddrLen;
280 Configuration->AddrLen = SubBusNumber - Configuration->AddrRangeMin + 1;
281
282 //
283 // Save the Desc field of the next descriptor. Mark the next descriptor as an END descriptor.
284 //
285 Configuration++;
286 Desc = Configuration->Desc;
287 Configuration->Desc = ACPI_END_TAG_DESCRIPTOR;
288
289 //
290 // Set bus number
291 //
292 Status = PciResAlloc->SetBusNumbers (
293 PciResAlloc,
294 RootBridgeHandle,
295 RootBridgeDev->BusNumberRanges
296 );
297
298 //
299 // Restore changed fields
300 //
301 Configuration->Desc = Desc;
302 (Configuration - 1)->AddrLen = AddrLen;
303
304 return Status;
305 }
306
307 /**
308 This routine is used to process all PCI devices' Option Rom
309 on a certain root bridge.
310
311 @param Bridge Given parent's root bridge.
312 @param RomBase Base address of ROM driver loaded from.
313 @param MaxLength Maximum rom size.
314
315 **/
316 VOID
317 ProcessOptionRom (
318 IN PCI_IO_DEVICE *Bridge,
319 IN UINT64 RomBase,
320 IN UINT64 MaxLength
321 )
322 {
323 LIST_ENTRY *CurrentLink;
324 PCI_IO_DEVICE *Temp;
325
326 //
327 // Go through bridges to reach all devices
328 //
329 CurrentLink = Bridge->ChildList.ForwardLink;
330 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
331 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
332 if (!IsListEmpty (&Temp->ChildList)) {
333
334 //
335 // Go further to process the option rom under this bridge
336 //
337 ProcessOptionRom (Temp, RomBase, MaxLength);
338 }
339
340 if (Temp->RomSize != 0 && Temp->RomSize <= MaxLength) {
341
342 //
343 // Load and process the option rom
344 //
345 LoadOpRomImage (Temp, RomBase);
346 }
347
348 CurrentLink = CurrentLink->ForwardLink;
349 }
350 }
351
352 /**
353 This routine is used to assign bus number to the given PCI bus system
354
355 @param Bridge Parent root bridge instance.
356 @param StartBusNumber Number of beginning.
357 @param SubBusNumber The number of sub bus.
358
359 @retval EFI_SUCCESS Successfully assigned bus number.
360 @retval EFI_DEVICE_ERROR Failed to assign bus number.
361
362 **/
363 EFI_STATUS
364 PciAssignBusNumber (
365 IN PCI_IO_DEVICE *Bridge,
366 IN UINT8 StartBusNumber,
367 OUT UINT8 *SubBusNumber
368 )
369 {
370 EFI_STATUS Status;
371 PCI_TYPE00 Pci;
372 UINT8 Device;
373 UINT8 Func;
374 UINT64 Address;
375 UINTN SecondBus;
376 UINT16 Register;
377 UINT8 Register8;
378 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
379
380 PciRootBridgeIo = Bridge->PciRootBridgeIo;
381
382 SecondBus = 0;
383 Register = 0;
384
385 *SubBusNumber = StartBusNumber;
386
387 //
388 // First check to see whether the parent is ppb
389 //
390 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
391 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
392
393 //
394 // Check to see whether a pci device is present
395 //
396 Status = PciDevicePresent (
397 PciRootBridgeIo,
398 &Pci,
399 StartBusNumber,
400 Device,
401 Func
402 );
403
404 if (!EFI_ERROR (Status) &&
405 (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci))) {
406
407 //
408 // Reserved one bus for cardbus bridge
409 //
410 Status = PciAllocateBusNumber (Bridge, *SubBusNumber, 1, SubBusNumber);
411 if (EFI_ERROR (Status)) {
412 return Status;
413 }
414 SecondBus = *SubBusNumber;
415
416 Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);
417
418 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x18);
419
420 Status = PciRootBridgeIo->Pci.Write (
421 PciRootBridgeIo,
422 EfiPciWidthUint16,
423 Address,
424 1,
425 &Register
426 );
427
428 //
429 // Initialize SubBusNumber to SecondBus
430 //
431 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
432 Status = PciRootBridgeIo->Pci.Write (
433 PciRootBridgeIo,
434 EfiPciWidthUint8,
435 Address,
436 1,
437 SubBusNumber
438 );
439 //
440 // If it is PPB, resursively search down this bridge
441 //
442 if (IS_PCI_BRIDGE (&Pci)) {
443
444 Register8 = 0xFF;
445 Status = PciRootBridgeIo->Pci.Write (
446 PciRootBridgeIo,
447 EfiPciWidthUint8,
448 Address,
449 1,
450 &Register8
451 );
452
453 Status = PciAssignBusNumber (
454 Bridge,
455 (UINT8) (SecondBus),
456 SubBusNumber
457 );
458
459 if (EFI_ERROR (Status)) {
460 return EFI_DEVICE_ERROR;
461 }
462 }
463
464 //
465 // Set the current maximum bus number under the PPB
466 //
467 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0x1A);
468
469 Status = PciRootBridgeIo->Pci.Write (
470 PciRootBridgeIo,
471 EfiPciWidthUint8,
472 Address,
473 1,
474 SubBusNumber
475 );
476
477 }
478
479 if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
480
481 //
482 // Skip sub functions, this is not a multi function device
483 //
484 Func = PCI_MAX_FUNC;
485 }
486 }
487 }
488
489 return EFI_SUCCESS;
490 }
491
492 /**
493 This routine is used to determine the root bridge attribute by interfacing
494 the host bridge resource allocation protocol.
495
496 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
497 @param RootBridgeDev Root bridge instance
498
499 @retval EFI_SUCCESS Successfully got root bridge's attribute.
500 @retval other Failed to get attribute.
501
502 **/
503 EFI_STATUS
504 DetermineRootBridgeAttributes (
505 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
506 IN PCI_IO_DEVICE *RootBridgeDev
507 )
508 {
509 UINT64 Attributes;
510 EFI_STATUS Status;
511 EFI_HANDLE RootBridgeHandle;
512
513 Attributes = 0;
514 RootBridgeHandle = RootBridgeDev->Handle;
515
516 //
517 // Get root bridge attribute by calling into pci host bridge resource allocation protocol
518 //
519 Status = PciResAlloc->GetAllocAttributes (
520 PciResAlloc,
521 RootBridgeHandle,
522 &Attributes
523 );
524
525 if (EFI_ERROR (Status)) {
526 return Status;
527 }
528
529 //
530 // Here is the point where PCI bus driver calls HOST bridge allocation protocol
531 // Currently we hardcoded for ea815
532 //
533 if ((Attributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {
534 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED;
535 }
536
537 if ((Attributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) != 0) {
538 RootBridgeDev->Decodes |= EFI_BRIDGE_MEM64_DECODE_SUPPORTED;
539 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED;
540 }
541
542 RootBridgeDev->Decodes |= EFI_BRIDGE_MEM32_DECODE_SUPPORTED;
543 RootBridgeDev->Decodes |= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED;
544 RootBridgeDev->Decodes |= EFI_BRIDGE_IO16_DECODE_SUPPORTED;
545
546 return EFI_SUCCESS;
547 }
548
549 /**
550 Get Max Option Rom size on specified bridge.
551
552 @param Bridge Given bridge device instance.
553
554 @return Max size of option rom needed.
555
556 **/
557 UINT64
558 GetMaxOptionRomSize (
559 IN PCI_IO_DEVICE *Bridge
560 )
561 {
562 LIST_ENTRY *CurrentLink;
563 PCI_IO_DEVICE *Temp;
564 UINT64 MaxOptionRomSize;
565 UINT64 TempOptionRomSize;
566
567 MaxOptionRomSize = 0;
568
569 //
570 // Go through bridges to reach all devices
571 //
572 CurrentLink = Bridge->ChildList.ForwardLink;
573 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
574 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
575 if (!IsListEmpty (&Temp->ChildList)) {
576
577 //
578 // Get max option rom size under this bridge
579 //
580 TempOptionRomSize = GetMaxOptionRomSize (Temp);
581
582 //
583 // Compare with the option rom size of the bridge
584 // Get the larger one
585 //
586 if (Temp->RomSize > TempOptionRomSize) {
587 TempOptionRomSize = Temp->RomSize;
588 }
589
590 } else {
591
592 //
593 // For devices get the rom size directly
594 //
595 TempOptionRomSize = Temp->RomSize;
596 }
597
598 //
599 // Get the largest rom size on this bridge
600 //
601 if (TempOptionRomSize > MaxOptionRomSize) {
602 MaxOptionRomSize = TempOptionRomSize;
603 }
604
605 CurrentLink = CurrentLink->ForwardLink;
606 }
607
608 return MaxOptionRomSize;
609 }
610
611 /**
612 Process attributes of devices on this host bridge
613
614 @param PciResAlloc Protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
615
616 @retval EFI_SUCCESS Successfully process attribute.
617 @retval EFI_NOT_FOUND Can not find the specific root bridge device.
618 @retval other Failed to determine the root bridge device's attribute.
619
620 **/
621 EFI_STATUS
622 PciHostBridgeDeviceAttribute (
623 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
624 )
625 {
626 EFI_HANDLE RootBridgeHandle;
627 PCI_IO_DEVICE *RootBridgeDev;
628 EFI_STATUS Status;
629
630 RootBridgeHandle = NULL;
631
632 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
633
634 //
635 // Get RootBridg Device by handle
636 //
637 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
638
639 if (RootBridgeDev == NULL) {
640 return EFI_NOT_FOUND;
641 }
642
643 //
644 // Set the attributes for devcies behind the Root Bridge
645 //
646 Status = DetermineDeviceAttribute (RootBridgeDev);
647 if (EFI_ERROR (Status)) {
648 return Status;
649 }
650
651 }
652
653 return EFI_SUCCESS;
654 }
655
656 /**
657 Get resource allocation status from the ACPI resource descriptor.
658
659 @param AcpiConfig Point to Acpi configuration table.
660 @param IoResStatus Return the status of I/O resource.
661 @param Mem32ResStatus Return the status of 32-bit Memory resource.
662 @param PMem32ResStatus Return the status of 32-bit Prefetchable Memory resource.
663 @param Mem64ResStatus Return the status of 64-bit Memory resource.
664 @param PMem64ResStatus Return the status of 64-bit Prefetchable Memory resource.
665
666 **/
667 VOID
668 GetResourceAllocationStatus (
669 VOID *AcpiConfig,
670 OUT UINT64 *IoResStatus,
671 OUT UINT64 *Mem32ResStatus,
672 OUT UINT64 *PMem32ResStatus,
673 OUT UINT64 *Mem64ResStatus,
674 OUT UINT64 *PMem64ResStatus
675 )
676 {
677 UINT8 *Temp;
678 UINT64 ResStatus;
679 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ACPIAddressDesc;
680
681 Temp = (UINT8 *) AcpiConfig;
682
683 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
684
685 ACPIAddressDesc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;
686 ResStatus = ACPIAddressDesc->AddrTranslationOffset;
687
688 switch (ACPIAddressDesc->ResType) {
689 case 0:
690 if (ACPIAddressDesc->AddrSpaceGranularity == 32) {
691 if (ACPIAddressDesc->SpecificFlag == 0x06) {
692 //
693 // Pmem32
694 //
695 *PMem32ResStatus = ResStatus;
696 } else {
697 //
698 // Mem32
699 //
700 *Mem32ResStatus = ResStatus;
701 }
702 }
703
704 if (ACPIAddressDesc->AddrSpaceGranularity == 64) {
705 if (ACPIAddressDesc->SpecificFlag == 0x06) {
706 //
707 // PMem64
708 //
709 *PMem64ResStatus = ResStatus;
710 } else {
711 //
712 // Mem64
713 //
714 *Mem64ResStatus = ResStatus;
715 }
716 }
717
718 break;
719
720 case 1:
721 //
722 // Io
723 //
724 *IoResStatus = ResStatus;
725 break;
726
727 default:
728 break;
729 }
730
731 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
732 }
733 }
734
735 /**
736 Remove a PCI device from device pool and mark its bar.
737
738 @param PciDevice Instance of Pci device.
739
740 @retval EFI_SUCCESS Successfully remove the PCI device.
741 @retval EFI_ABORTED Pci device is a root bridge or a PCI-PCI bridge.
742
743 **/
744 EFI_STATUS
745 RejectPciDevice (
746 IN PCI_IO_DEVICE *PciDevice
747 )
748 {
749 PCI_IO_DEVICE *Bridge;
750 PCI_IO_DEVICE *Temp;
751 LIST_ENTRY *CurrentLink;
752
753 //
754 // Remove the padding resource from a bridge
755 //
756 if ( IS_PCI_BRIDGE(&PciDevice->Pci) &&
757 PciDevice->ResourcePaddingDescriptors != NULL ) {
758 FreePool (PciDevice->ResourcePaddingDescriptors);
759 PciDevice->ResourcePaddingDescriptors = NULL;
760 return EFI_SUCCESS;
761 }
762
763 //
764 // Skip RB and PPB
765 //
766 if (IS_PCI_BRIDGE (&PciDevice->Pci) || (PciDevice->Parent == NULL)) {
767 return EFI_ABORTED;
768 }
769
770 if (IS_CARDBUS_BRIDGE (&PciDevice->Pci)) {
771 //
772 // Get the root bridge device
773 //
774 Bridge = PciDevice;
775 while (Bridge->Parent != NULL) {
776 Bridge = Bridge->Parent;
777 }
778
779 RemoveAllPciDeviceOnBridge (Bridge->Handle, PciDevice);
780
781 //
782 // Mark its bar
783 //
784 InitializeP2C (PciDevice);
785 }
786
787 //
788 // Remove the device
789 //
790 Bridge = PciDevice->Parent;
791 CurrentLink = Bridge->ChildList.ForwardLink;
792 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
793 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
794 if (Temp == PciDevice) {
795 InitializePciDevice (Temp);
796 RemoveEntryList (CurrentLink);
797 return EFI_SUCCESS;
798 }
799
800 CurrentLink = CurrentLink->ForwardLink;
801 }
802
803 return EFI_ABORTED;
804 }
805
806 /**
807 Determine whethter a PCI device can be rejected.
808
809 @param PciResNode Pointer to Pci resource node instance.
810
811 @retval TRUE The PCI device can be rejected.
812 @retval TRUE The PCI device cannot be rejected.
813
814 **/
815 BOOLEAN
816 IsRejectiveDevice (
817 IN PCI_RESOURCE_NODE *PciResNode
818 )
819 {
820 PCI_IO_DEVICE *Temp;
821
822 Temp = PciResNode->PciDev;
823
824 //
825 // Ensure the device is present
826 //
827 if (Temp == NULL) {
828 return FALSE;
829 }
830
831 //
832 // PPB and RB should go ahead
833 //
834 if (IS_PCI_BRIDGE (&Temp->Pci) || (Temp->Parent == NULL)) {
835 return TRUE;
836 }
837
838 //
839 // Skip device on Bus0
840 //
841 if ((Temp->Parent != NULL) && (Temp->BusNumber == 0)) {
842 return FALSE;
843 }
844
845 //
846 // Skip VGA
847 //
848 if (IS_PCI_VGA (&Temp->Pci)) {
849 return FALSE;
850 }
851
852 return TRUE;
853 }
854
855 /**
856 Compare two resource nodes and get the larger resource consumer.
857
858 @param PciResNode1 resource node 1 want to be compared
859 @param PciResNode2 resource node 2 want to be compared
860
861 @return Larger resource node.
862
863 **/
864 PCI_RESOURCE_NODE *
865 GetLargerConsumerDevice (
866 IN PCI_RESOURCE_NODE *PciResNode1,
867 IN PCI_RESOURCE_NODE *PciResNode2
868 )
869 {
870 if (PciResNode2 == NULL) {
871 return PciResNode1;
872 }
873
874 if ((IS_PCI_BRIDGE(&(PciResNode2->PciDev->Pci)) || (PciResNode2->PciDev->Parent == NULL)) \
875 && (PciResNode2->ResourceUsage != PciResUsagePadding) )
876 {
877 return PciResNode1;
878 }
879
880 if (PciResNode1 == NULL) {
881 return PciResNode2;
882 }
883
884 if ((PciResNode1->Length) > (PciResNode2->Length)) {
885 return PciResNode1;
886 }
887
888 return PciResNode2;
889 }
890
891
892 /**
893 Get the max resource consumer in the host resource pool.
894
895 @param ResPool Pointer to resource pool node.
896
897 @return The max resource consumer in the host resource pool.
898
899 **/
900 PCI_RESOURCE_NODE *
901 GetMaxResourceConsumerDevice (
902 IN PCI_RESOURCE_NODE *ResPool
903 )
904 {
905 PCI_RESOURCE_NODE *Temp;
906 LIST_ENTRY *CurrentLink;
907 PCI_RESOURCE_NODE *PciResNode;
908 PCI_RESOURCE_NODE *PPBResNode;
909
910 PciResNode = NULL;
911
912 CurrentLink = ResPool->ChildList.ForwardLink;
913 while (CurrentLink != NULL && CurrentLink != &ResPool->ChildList) {
914
915 Temp = RESOURCE_NODE_FROM_LINK (CurrentLink);
916
917 if (!IsRejectiveDevice (Temp)) {
918 CurrentLink = CurrentLink->ForwardLink;
919 continue;
920 }
921
922 if ((IS_PCI_BRIDGE (&(Temp->PciDev->Pci)) || (Temp->PciDev->Parent == NULL)) \
923 && (Temp->ResourceUsage != PciResUsagePadding))
924 {
925 PPBResNode = GetMaxResourceConsumerDevice (Temp);
926 PciResNode = GetLargerConsumerDevice (PciResNode, PPBResNode);
927 } else {
928 PciResNode = GetLargerConsumerDevice (PciResNode, Temp);
929 }
930
931 CurrentLink = CurrentLink->ForwardLink;
932 }
933
934 return PciResNode;
935 }
936
937 /**
938 Adjust host bridge allocation so as to reduce resource requirement
939
940 @param IoPool Pointer to instance of I/O resource Node.
941 @param Mem32Pool Pointer to instance of 32-bit memory resource Node.
942 @param PMem32Pool Pointer to instance of 32-bit Prefetchable memory resource node.
943 @param Mem64Pool Pointer to instance of 64-bit memory resource node.
944 @param PMem64Pool Pointer to instance of 64-bit Prefetchable memory resource node.
945 @param IoResStatus Status of I/O resource Node.
946 @param Mem32ResStatus Status of 32-bit memory resource Node.
947 @param PMem32ResStatus Status of 32-bit Prefetchable memory resource node.
948 @param Mem64ResStatus Status of 64-bit memory resource node.
949 @param PMem64ResStatus Status of 64-bit Prefetchable memory resource node.
950
951 @retval EFI_SUCCESS Successfully adjusted resoruce on host bridge.
952 @retval EFI_ABORTED Host bridge hasn't this resource type or no resource be adjusted.
953
954 **/
955 EFI_STATUS
956 PciHostBridgeAdjustAllocation (
957 IN PCI_RESOURCE_NODE *IoPool,
958 IN PCI_RESOURCE_NODE *Mem32Pool,
959 IN PCI_RESOURCE_NODE *PMem32Pool,
960 IN PCI_RESOURCE_NODE *Mem64Pool,
961 IN PCI_RESOURCE_NODE *PMem64Pool,
962 IN UINT64 IoResStatus,
963 IN UINT64 Mem32ResStatus,
964 IN UINT64 PMem32ResStatus,
965 IN UINT64 Mem64ResStatus,
966 IN UINT64 PMem64ResStatus
967 )
968 {
969 BOOLEAN AllocationAjusted;
970 PCI_RESOURCE_NODE *PciResNode;
971 PCI_RESOURCE_NODE *ResPool[5];
972 PCI_IO_DEVICE *RemovedPciDev[5];
973 UINT64 ResStatus[5];
974 UINTN RemovedPciDevNum;
975 UINTN DevIndex;
976 UINTN ResType;
977 EFI_STATUS Status;
978 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;
979
980 PciResNode = NULL;
981 ZeroMem (RemovedPciDev, 5 * sizeof (PCI_IO_DEVICE *));
982 RemovedPciDevNum = 0;
983
984 ResPool[0] = IoPool;
985 ResPool[1] = Mem32Pool;
986 ResPool[2] = PMem32Pool;
987 ResPool[3] = Mem64Pool;
988 ResPool[4] = PMem64Pool;
989
990 ResStatus[0] = IoResStatus;
991 ResStatus[1] = Mem32ResStatus;
992 ResStatus[2] = PMem32ResStatus;
993 ResStatus[3] = Mem64ResStatus;
994 ResStatus[4] = PMem64ResStatus;
995
996 AllocationAjusted = FALSE;
997
998 for (ResType = 0; ResType < 5; ResType++) {
999
1000 if (ResStatus[ResType] == EFI_RESOURCE_SATISFIED) {
1001 continue;
1002 }
1003
1004 if (ResStatus[ResType] == EFI_RESOURCE_NOT_SATISFIED) {
1005 //
1006 // Host bridge hasn't this resource type
1007 //
1008 return EFI_ABORTED;
1009 }
1010
1011 //
1012 // Hostbridge hasn't enough resource
1013 //
1014 PciResNode = GetMaxResourceConsumerDevice (ResPool[ResType]);
1015 if (PciResNode == NULL) {
1016 continue;
1017 }
1018
1019 //
1020 // Check if the device has been removed before
1021 //
1022 for (DevIndex = 0; DevIndex < RemovedPciDevNum; DevIndex++) {
1023 if (PciResNode->PciDev == RemovedPciDev[DevIndex]) {
1024 break;
1025 }
1026 }
1027
1028 if (DevIndex != RemovedPciDevNum) {
1029 continue;
1030 }
1031
1032 //
1033 // Remove the device if it isn't in the array
1034 //
1035 Status = RejectPciDevice (PciResNode->PciDev);
1036 if (Status == EFI_SUCCESS) {
1037 DEBUG ((
1038 EFI_D_ERROR,
1039 "PciBus: [%02x|%02x|%02x] was rejected due to resource confliction.\n",
1040 PciResNode->PciDev->BusNumber, PciResNode->PciDev->DeviceNumber, PciResNode->PciDev->FunctionNumber
1041 ));
1042
1043 //
1044 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code
1045 //
1046 //
1047 // Have no way to get ReqRes, AllocRes & Bar here
1048 //
1049 ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));
1050 AllocFailExtendedData.DevicePathSize = (UINT16) sizeof (EFI_DEVICE_PATH_PROTOCOL);
1051 AllocFailExtendedData.DevicePath = (UINT8 *) PciResNode->PciDev->DevicePath;
1052 AllocFailExtendedData.Bar = PciResNode->Bar;
1053
1054 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
1055 EFI_PROGRESS_CODE,
1056 EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,
1057 (VOID *) &AllocFailExtendedData,
1058 sizeof (AllocFailExtendedData)
1059 );
1060
1061 //
1062 // Add it to the array and indicate at least a device has been rejected
1063 //
1064 RemovedPciDev[RemovedPciDevNum++] = PciResNode->PciDev;
1065 AllocationAjusted = TRUE;
1066 }
1067 }
1068 //
1069 // End for
1070 //
1071
1072 if (AllocationAjusted) {
1073 return EFI_SUCCESS;
1074 } else {
1075 return EFI_ABORTED;
1076 }
1077 }
1078
1079 /**
1080 Summary requests for all resource type, and contruct ACPI resource
1081 requestor instance.
1082
1083 @param Bridge detecting bridge
1084 @param IoNode Pointer to instance of I/O resource Node
1085 @param Mem32Node Pointer to instance of 32-bit memory resource Node
1086 @param PMem32Node Pointer to instance of 32-bit Pmemory resource node
1087 @param Mem64Node Pointer to instance of 64-bit memory resource node
1088 @param PMem64Node Pointer to instance of 64-bit Pmemory resource node
1089 @param Config Output buffer holding new constructed APCI resource requestor
1090
1091 @retval EFI_SUCCESS Successfully constructed ACPI resource.
1092 @retval EFI_OUT_OF_RESOURCES No memory availabe.
1093
1094 **/
1095 EFI_STATUS
1096 ConstructAcpiResourceRequestor (
1097 IN PCI_IO_DEVICE *Bridge,
1098 IN PCI_RESOURCE_NODE *IoNode,
1099 IN PCI_RESOURCE_NODE *Mem32Node,
1100 IN PCI_RESOURCE_NODE *PMem32Node,
1101 IN PCI_RESOURCE_NODE *Mem64Node,
1102 IN PCI_RESOURCE_NODE *PMem64Node,
1103 OUT VOID **Config
1104 )
1105 {
1106 UINT8 NumConfig;
1107 UINT8 Aperture;
1108 UINT8 *Configuration;
1109 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1110 EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
1111
1112 NumConfig = 0;
1113 Aperture = 0;
1114
1115 *Config = NULL;
1116
1117 //
1118 // if there is io request, add to the io aperture
1119 //
1120 if (ResourceRequestExisted (IoNode)) {
1121 NumConfig++;
1122 Aperture |= 0x01;
1123 }
1124
1125 //
1126 // if there is mem32 request, add to the mem32 aperture
1127 //
1128 if (ResourceRequestExisted (Mem32Node)) {
1129 NumConfig++;
1130 Aperture |= 0x02;
1131 }
1132
1133 //
1134 // if there is pmem32 request, add to the pmem32 aperture
1135 //
1136 if (ResourceRequestExisted (PMem32Node)) {
1137 NumConfig++;
1138 Aperture |= 0x04;
1139 }
1140
1141 //
1142 // if there is mem64 request, add to the mem64 aperture
1143 //
1144 if (ResourceRequestExisted (Mem64Node)) {
1145 NumConfig++;
1146 Aperture |= 0x08;
1147 }
1148
1149 //
1150 // if there is pmem64 request, add to the pmem64 aperture
1151 //
1152 if (ResourceRequestExisted (PMem64Node)) {
1153 NumConfig++;
1154 Aperture |= 0x10;
1155 }
1156
1157 if (NumConfig != 0) {
1158
1159 //
1160 // If there is at least one type of resource request,
1161 // allocate a acpi resource node
1162 //
1163 Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
1164 if (Configuration == NULL) {
1165 return EFI_OUT_OF_RESOURCES;
1166 }
1167
1168 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
1169
1170 //
1171 // Deal with io aperture
1172 //
1173 if ((Aperture & 0x01) != 0) {
1174 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1175 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1176 //
1177 // Io
1178 //
1179 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
1180 //
1181 // non ISA range
1182 //
1183 Ptr->SpecificFlag = 1;
1184 Ptr->AddrLen = IoNode->Length;
1185 Ptr->AddrRangeMax = IoNode->Alignment;
1186
1187 Ptr++;
1188 }
1189 //
1190 // Deal with mem32 aperture
1191 //
1192 if ((Aperture & 0x02) != 0) {
1193 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1194 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1195 //
1196 // Mem
1197 //
1198 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1199 //
1200 // Nonprefechable
1201 //
1202 Ptr->SpecificFlag = 0;
1203 //
1204 // 32 bit
1205 //
1206 Ptr->AddrSpaceGranularity = 32;
1207 Ptr->AddrLen = Mem32Node->Length;
1208 Ptr->AddrRangeMax = Mem32Node->Alignment;
1209
1210 Ptr++;
1211 }
1212
1213 //
1214 // Deal with Pmem32 aperture
1215 //
1216 if ((Aperture & 0x04) != 0) {
1217 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1218 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1219 //
1220 // Mem
1221 //
1222 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1223 //
1224 // prefechable
1225 //
1226 Ptr->SpecificFlag = 0x6;
1227 //
1228 // 32 bit
1229 //
1230 Ptr->AddrSpaceGranularity = 32;
1231 Ptr->AddrLen = PMem32Node->Length;
1232 Ptr->AddrRangeMax = PMem32Node->Alignment;
1233
1234 Ptr++;
1235 }
1236 //
1237 // Deal with mem64 aperture
1238 //
1239 if ((Aperture & 0x08) != 0) {
1240 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1241 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1242 //
1243 // Mem
1244 //
1245 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1246 //
1247 // nonprefechable
1248 //
1249 Ptr->SpecificFlag = 0;
1250 //
1251 // 64 bit
1252 //
1253 Ptr->AddrSpaceGranularity = 64;
1254 Ptr->AddrLen = Mem64Node->Length;
1255 Ptr->AddrRangeMax = Mem64Node->Alignment;
1256
1257 Ptr++;
1258 }
1259 //
1260 // Deal with Pmem64 aperture
1261 //
1262 if ((Aperture & 0x10) != 0) {
1263 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1264 Ptr->Len = (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3);
1265 //
1266 // Mem
1267 //
1268 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1269 //
1270 // prefechable
1271 //
1272 Ptr->SpecificFlag = 0x06;
1273 //
1274 // 64 bit
1275 //
1276 Ptr->AddrSpaceGranularity = 64;
1277 Ptr->AddrLen = PMem64Node->Length;
1278 Ptr->AddrRangeMax = PMem64Node->Alignment;
1279
1280 Ptr++;
1281 }
1282
1283 //
1284 // put the checksum
1285 //
1286 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) Ptr;
1287
1288 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
1289 PtrEnd->Checksum = 0;
1290
1291 } else {
1292
1293 //
1294 // If there is no resource request
1295 //
1296 Configuration = AllocateZeroPool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
1297 if (Configuration == NULL) {
1298 return EFI_OUT_OF_RESOURCES;
1299 }
1300
1301 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (Configuration);
1302 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1303
1304 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) (Ptr + 1);
1305 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
1306 PtrEnd->Checksum = 0;
1307 }
1308
1309 *Config = Configuration;
1310
1311 return EFI_SUCCESS;
1312 }
1313
1314 /**
1315 Get resource base from an acpi configuration descriptor.
1316
1317 @param Config An acpi configuration descriptor.
1318 @param IoBase Output of I/O resource base address.
1319 @param Mem32Base Output of 32-bit memory base address.
1320 @param PMem32Base Output of 32-bit prefetchable memory base address.
1321 @param Mem64Base Output of 64-bit memory base address.
1322 @param PMem64Base Output of 64-bit prefetchable memory base address.
1323
1324 **/
1325 VOID
1326 GetResourceBase (
1327 IN VOID *Config,
1328 OUT UINT64 *IoBase,
1329 OUT UINT64 *Mem32Base,
1330 OUT UINT64 *PMem32Base,
1331 OUT UINT64 *Mem64Base,
1332 OUT UINT64 *PMem64Base
1333 )
1334 {
1335 UINT8 *Temp;
1336 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1337 UINT64 ResStatus;
1338
1339 ASSERT (Config != NULL);
1340
1341 *IoBase = 0xFFFFFFFFFFFFFFFFULL;
1342 *Mem32Base = 0xFFFFFFFFFFFFFFFFULL;
1343 *PMem32Base = 0xFFFFFFFFFFFFFFFFULL;
1344 *Mem64Base = 0xFFFFFFFFFFFFFFFFULL;
1345 *PMem64Base = 0xFFFFFFFFFFFFFFFFULL;
1346
1347 Temp = (UINT8 *) Config;
1348
1349 while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
1350
1351 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;
1352 ResStatus = Ptr->AddrTranslationOffset;
1353
1354 if (ResStatus == EFI_RESOURCE_SATISFIED) {
1355
1356 switch (Ptr->ResType) {
1357
1358 //
1359 // Memory type aperture
1360 //
1361 case 0:
1362
1363 //
1364 // Check to see the granularity
1365 //
1366 if (Ptr->AddrSpaceGranularity == 32) {
1367 if ((Ptr->SpecificFlag & 0x06) != 0) {
1368 *PMem32Base = Ptr->AddrRangeMin;
1369 } else {
1370 *Mem32Base = Ptr->AddrRangeMin;
1371 }
1372 }
1373
1374 if (Ptr->AddrSpaceGranularity == 64) {
1375 if ((Ptr->SpecificFlag & 0x06) != 0) {
1376 *PMem64Base = Ptr->AddrRangeMin;
1377 } else {
1378 *Mem64Base = Ptr->AddrRangeMin;
1379 }
1380 }
1381 break;
1382
1383 case 1:
1384
1385 //
1386 // Io type aperture
1387 //
1388 *IoBase = Ptr->AddrRangeMin;
1389 break;
1390
1391 default:
1392 break;
1393
1394 }
1395 //
1396 // End switch
1397 //
1398 }
1399 //
1400 // End for
1401 //
1402 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
1403 }
1404 }
1405
1406 /**
1407 Enumerate pci bridge, allocate resource and determine attribute
1408 for devices on this bridge.
1409
1410 @param BridgeDev Pointer to instance of bridge device.
1411
1412 @retval EFI_SUCCESS Successfully enumerated PCI bridge.
1413 @retval other Failed to enumerate.
1414
1415 **/
1416 EFI_STATUS
1417 PciBridgeEnumerator (
1418 IN PCI_IO_DEVICE *BridgeDev
1419 )
1420 {
1421 UINT8 SubBusNumber;
1422 UINT8 StartBusNumber;
1423 EFI_PCI_IO_PROTOCOL *PciIo;
1424 EFI_STATUS Status;
1425
1426 SubBusNumber = 0;
1427 StartBusNumber = 0;
1428 PciIo = &(BridgeDev->PciIo);
1429 Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x19, 1, &StartBusNumber);
1430
1431 if (EFI_ERROR (Status)) {
1432 return Status;
1433 }
1434
1435 Status = PciAssignBusNumber (
1436 BridgeDev,
1437 StartBusNumber,
1438 &SubBusNumber
1439 );
1440
1441 if (EFI_ERROR (Status)) {
1442 return Status;
1443 }
1444
1445 Status = PciPciDeviceInfoCollector (BridgeDev, StartBusNumber);
1446
1447 if (EFI_ERROR (Status)) {
1448 return Status;
1449 }
1450
1451 Status = PciBridgeResourceAllocator (BridgeDev);
1452
1453 if (EFI_ERROR (Status)) {
1454 return Status;
1455 }
1456
1457 Status = DetermineDeviceAttribute (BridgeDev);
1458
1459 if (EFI_ERROR (Status)) {
1460 return Status;
1461 }
1462
1463 return EFI_SUCCESS;
1464
1465 }
1466
1467 /**
1468 Allocate all kinds of resource for PCI bridge.
1469
1470 @param Bridge Pointer to bridge instance.
1471
1472 @retval EFI_SUCCESS Successfully allocated resource for PCI bridge.
1473 @retval other Failed to allocate resource for bridge.
1474
1475 **/
1476 EFI_STATUS
1477 PciBridgeResourceAllocator (
1478 IN PCI_IO_DEVICE *Bridge
1479 )
1480 {
1481 PCI_RESOURCE_NODE *IoBridge;
1482 PCI_RESOURCE_NODE *Mem32Bridge;
1483 PCI_RESOURCE_NODE *PMem32Bridge;
1484 PCI_RESOURCE_NODE *Mem64Bridge;
1485 PCI_RESOURCE_NODE *PMem64Bridge;
1486 UINT64 IoBase;
1487 UINT64 Mem32Base;
1488 UINT64 PMem32Base;
1489 UINT64 Mem64Base;
1490 UINT64 PMem64Base;
1491 EFI_STATUS Status;
1492
1493 IoBridge = CreateResourceNode (
1494 Bridge,
1495 0,
1496 Bridge->BridgeIoAlignment,
1497 0,
1498 PciBarTypeIo16,
1499 PciResUsageTypical
1500 );
1501
1502 Mem32Bridge = CreateResourceNode (
1503 Bridge,
1504 0,
1505 0xFFFFF,
1506 0,
1507 PciBarTypeMem32,
1508 PciResUsageTypical
1509 );
1510
1511 PMem32Bridge = CreateResourceNode (
1512 Bridge,
1513 0,
1514 0xFFFFF,
1515 0,
1516 PciBarTypePMem32,
1517 PciResUsageTypical
1518 );
1519
1520 Mem64Bridge = CreateResourceNode (
1521 Bridge,
1522 0,
1523 0xFFFFF,
1524 0,
1525 PciBarTypeMem64,
1526 PciResUsageTypical
1527 );
1528
1529 PMem64Bridge = CreateResourceNode (
1530 Bridge,
1531 0,
1532 0xFFFFF,
1533 0,
1534 PciBarTypePMem64,
1535 PciResUsageTypical
1536 );
1537
1538 //
1539 // Create resourcemap by going through all the devices subject to this root bridge
1540 //
1541 CreateResourceMap (
1542 Bridge,
1543 IoBridge,
1544 Mem32Bridge,
1545 PMem32Bridge,
1546 Mem64Bridge,
1547 PMem64Bridge
1548 );
1549
1550 Status = GetResourceBaseFromBridge (
1551 Bridge,
1552 &IoBase,
1553 &Mem32Base,
1554 &PMem32Base,
1555 &Mem64Base,
1556 &PMem64Base
1557 );
1558
1559 if (EFI_ERROR (Status)) {
1560 return Status;
1561 }
1562
1563 //
1564 // Program IO resources
1565 //
1566 ProgramResource (
1567 IoBase,
1568 IoBridge
1569 );
1570
1571 //
1572 // Program Mem32 resources
1573 //
1574 ProgramResource (
1575 Mem32Base,
1576 Mem32Bridge
1577 );
1578
1579 //
1580 // Program PMem32 resources
1581 //
1582 ProgramResource (
1583 PMem32Base,
1584 PMem32Bridge
1585 );
1586
1587 //
1588 // Program Mem64 resources
1589 //
1590 ProgramResource (
1591 Mem64Base,
1592 Mem64Bridge
1593 );
1594
1595 //
1596 // Program PMem64 resources
1597 //
1598 ProgramResource (
1599 PMem64Base,
1600 PMem64Bridge
1601 );
1602
1603 DestroyResourceTree (IoBridge);
1604 DestroyResourceTree (Mem32Bridge);
1605 DestroyResourceTree (PMem32Bridge);
1606 DestroyResourceTree (PMem64Bridge);
1607 DestroyResourceTree (Mem64Bridge);
1608
1609 gBS->FreePool (IoBridge);
1610 gBS->FreePool (Mem32Bridge);
1611 gBS->FreePool (PMem32Bridge);
1612 gBS->FreePool (PMem64Bridge);
1613 gBS->FreePool (Mem64Bridge);
1614
1615 return EFI_SUCCESS;
1616 }
1617
1618 /**
1619 Get resource base address for a pci bridge device.
1620
1621 @param Bridge Given Pci driver instance.
1622 @param IoBase Output for base address of I/O type resource.
1623 @param Mem32Base Output for base address of 32-bit memory type resource.
1624 @param PMem32Base Ooutput for base address of 32-bit Pmemory type resource.
1625 @param Mem64Base Output for base address of 64-bit memory type resource.
1626 @param PMem64Base Output for base address of 64-bit Pmemory type resource.
1627
1628 @retval EFI_SUCCESS Successfully got resource base address.
1629 @retval EFI_OUT_OF_RESOURCES PCI bridge is not available.
1630
1631 **/
1632 EFI_STATUS
1633 GetResourceBaseFromBridge (
1634 IN PCI_IO_DEVICE *Bridge,
1635 OUT UINT64 *IoBase,
1636 OUT UINT64 *Mem32Base,
1637 OUT UINT64 *PMem32Base,
1638 OUT UINT64 *Mem64Base,
1639 OUT UINT64 *PMem64Base
1640 )
1641 {
1642 if (!Bridge->Allocated) {
1643 return EFI_OUT_OF_RESOURCES;
1644 }
1645
1646 *IoBase = gAllOne;
1647 *Mem32Base = gAllOne;
1648 *PMem32Base = gAllOne;
1649 *Mem64Base = gAllOne;
1650 *PMem64Base = gAllOne;
1651
1652 if (IS_PCI_BRIDGE (&Bridge->Pci)) {
1653
1654 if (Bridge->PciBar[PPB_IO_RANGE].Length > 0) {
1655 *IoBase = Bridge->PciBar[PPB_IO_RANGE].BaseAddress;
1656 }
1657
1658 if (Bridge->PciBar[PPB_MEM32_RANGE].Length > 0) {
1659 *Mem32Base = Bridge->PciBar[PPB_MEM32_RANGE].BaseAddress;
1660 }
1661
1662 if (Bridge->PciBar[PPB_PMEM32_RANGE].Length > 0) {
1663 *PMem32Base = Bridge->PciBar[PPB_PMEM32_RANGE].BaseAddress;
1664 }
1665
1666 if (Bridge->PciBar[PPB_PMEM64_RANGE].Length > 0) {
1667 *PMem64Base = Bridge->PciBar[PPB_PMEM64_RANGE].BaseAddress;
1668 } else {
1669 *PMem64Base = gAllOne;
1670 }
1671
1672 }
1673
1674 if (IS_CARDBUS_BRIDGE (&Bridge->Pci)) {
1675 if (Bridge->PciBar[P2C_IO_1].Length > 0) {
1676 *IoBase = Bridge->PciBar[P2C_IO_1].BaseAddress;
1677 } else {
1678 if (Bridge->PciBar[P2C_IO_2].Length > 0) {
1679 *IoBase = Bridge->PciBar[P2C_IO_2].BaseAddress;
1680 }
1681 }
1682
1683 if (Bridge->PciBar[P2C_MEM_1].Length > 0) {
1684 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypePMem32) {
1685 *PMem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;
1686 }
1687
1688 if (Bridge->PciBar[P2C_MEM_1].BarType == PciBarTypeMem32) {
1689 *Mem32Base = Bridge->PciBar[P2C_MEM_1].BaseAddress;
1690 }
1691 }
1692
1693 if (Bridge->PciBar[P2C_MEM_2].Length > 0) {
1694 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypePMem32) {
1695 *PMem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;
1696 }
1697
1698 if (Bridge->PciBar[P2C_MEM_2].BarType == PciBarTypeMem32) {
1699 *Mem32Base = Bridge->PciBar[P2C_MEM_2].BaseAddress;
1700 }
1701 }
1702 }
1703
1704 return EFI_SUCCESS;
1705 }
1706
1707 /**
1708 These are the notifications from the PCI bus driver that it is about to enter a certain
1709 phase of the PCI enumeration process.
1710
1711 This member function can be used to notify the host bridge driver to perform specific actions,
1712 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
1713 Eight notification points are defined at this time. See belows:
1714 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
1715 structures. The PCI enumerator should issue this notification
1716 before starting a fresh enumeration process. Enumeration cannot
1717 be restarted after sending any other notification such as
1718 EfiPciHostBridgeBeginBusAllocation.
1719 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
1720 required here. This notification can be used to perform any
1721 chipset-specific programming.
1722 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
1723 specific action is required here. This notification can be used to
1724 perform any chipset-specific programming.
1725 EfiPciHostBridgeBeginResourceAllocation
1726 The resource allocation phase is about to begin. No specific
1727 action is required here. This notification can be used to perform
1728 any chipset-specific programming.
1729 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
1730 root bridges. These resource settings are returned on the next call to
1731 GetProposedResources(). Before calling NotifyPhase() with a Phase of
1732 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
1733 for gathering I/O and memory requests for
1734 all the PCI root bridges and submitting these requests using
1735 SubmitResources(). This function pads the resource amount
1736 to suit the root bridge hardware, takes care of dependencies between
1737 the PCI root bridges, and calls the Global Coherency Domain (GCD)
1738 with the allocation request. In the case of padding, the allocated range
1739 could be bigger than what was requested.
1740 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
1741 resources (proposed resources) for all the PCI root bridges. After the
1742 hardware is programmed, reassigning resources will not be supported.
1743 The bus settings are not affected.
1744 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
1745 root bridges and resets the I/O and memory apertures to their initial
1746 state. The bus settings are not affected. If the request to allocate
1747 resources fails, the PCI enumerator can use this notification to
1748 deallocate previous resources, adjust the requests, and retry
1749 allocation.
1750 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
1751 required here. This notification can be used to perform any chipsetspecific
1752 programming.
1753
1754 @param[in] PciResAlloc The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
1755 @param[in] Phase The phase during enumeration
1756
1757 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
1758 is valid for a Phase of EfiPciHostBridgeAllocateResources if
1759 SubmitResources() has not been called for one or more
1760 PCI root bridges before this call
1761 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
1762 for a Phase of EfiPciHostBridgeSetResources.
1763 @retval EFI_INVALID_PARAMETER Invalid phase parameter
1764 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1765 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
1766 previously submitted resource requests cannot be fulfilled or
1767 were only partially fulfilled.
1768 @retval EFI_SUCCESS The notification was accepted without any errors.
1769
1770 **/
1771 EFI_STATUS
1772 NotifyPhase (
1773 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc,
1774 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
1775 )
1776 {
1777 EFI_HANDLE HostBridgeHandle;
1778 EFI_HANDLE RootBridgeHandle;
1779 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
1780 EFI_STATUS Status;
1781
1782 HostBridgeHandle = NULL;
1783 RootBridgeHandle = NULL;
1784 if (gPciPlatformProtocol != NULL) {
1785 //
1786 // Get Host Bridge Handle.
1787 //
1788 PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);
1789
1790 //
1791 // Get the rootbridge Io protocol to find the host bridge handle
1792 //
1793 Status = gBS->HandleProtocol (
1794 RootBridgeHandle,
1795 &gEfiPciRootBridgeIoProtocolGuid,
1796 (VOID **) &PciRootBridgeIo
1797 );
1798
1799 if (EFI_ERROR (Status)) {
1800 return EFI_NOT_FOUND;
1801 }
1802
1803 HostBridgeHandle = PciRootBridgeIo->ParentHandle;
1804
1805 //
1806 // Call PlatformPci::PlatformNotify() if the protocol is present.
1807 //
1808 gPciPlatformProtocol->PlatformNotify (
1809 gPciPlatformProtocol,
1810 HostBridgeHandle,
1811 Phase,
1812 ChipsetEntry
1813 );
1814 } else if (gPciOverrideProtocol != NULL){
1815 //
1816 // Get Host Bridge Handle.
1817 //
1818 PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle);
1819
1820 //
1821 // Get the rootbridge Io protocol to find the host bridge handle
1822 //
1823 Status = gBS->HandleProtocol (
1824 RootBridgeHandle,
1825 &gEfiPciRootBridgeIoProtocolGuid,
1826 (VOID **) &PciRootBridgeIo
1827 );
1828
1829 if (EFI_ERROR (Status)) {
1830 return EFI_NOT_FOUND;
1831 }
1832
1833 HostBridgeHandle = PciRootBridgeIo->ParentHandle;
1834
1835 //
1836 // Call PlatformPci::PhaseNotify() if the protocol is present.
1837 //
1838 gPciOverrideProtocol->PlatformNotify (
1839 gPciOverrideProtocol,
1840 HostBridgeHandle,
1841 Phase,
1842 ChipsetEntry
1843 );
1844 }
1845
1846 Status = PciResAlloc->NotifyPhase (
1847 PciResAlloc,
1848 Phase
1849 );
1850
1851 if (gPciPlatformProtocol != NULL) {
1852 //
1853 // Call PlatformPci::PlatformNotify() if the protocol is present.
1854 //
1855 gPciPlatformProtocol->PlatformNotify (
1856 gPciPlatformProtocol,
1857 HostBridgeHandle,
1858 Phase,
1859 ChipsetExit
1860 );
1861
1862 } else if (gPciOverrideProtocol != NULL) {
1863 //
1864 // Call PlatformPci::PhaseNotify() if the protocol is present.
1865 //
1866 gPciOverrideProtocol->PlatformNotify (
1867 gPciOverrideProtocol,
1868 HostBridgeHandle,
1869 Phase,
1870 ChipsetExit
1871 );
1872 }
1873
1874 return Status;
1875 }
1876
1877 /**
1878 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
1879 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
1880 PCI controllers before enumeration.
1881
1882 This function is called during the PCI enumeration process. No specific action is expected from this
1883 member function. It allows the host bridge driver to preinitialize individual PCI controllers before
1884 enumeration.
1885
1886 @param Bridge Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1887 @param Bus The bus number of the pci device.
1888 @param Device The device number of the pci device.
1889 @param Func The function number of the pci device.
1890 @param Phase The phase of the PCI device enumeration.
1891
1892 @retval EFI_SUCCESS The requested parameters were returned.
1893 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1894 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
1895 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
1896 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
1897 not enumerate this device, including its child devices if it is a PCI-to-PCI
1898 bridge.
1899
1900 **/
1901 EFI_STATUS
1902 PreprocessController (
1903 IN PCI_IO_DEVICE *Bridge,
1904 IN UINT8 Bus,
1905 IN UINT8 Device,
1906 IN UINT8 Func,
1907 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
1908 )
1909 {
1910 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress;
1911 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc;
1912 EFI_HANDLE RootBridgeHandle;
1913 EFI_HANDLE HostBridgeHandle;
1914 EFI_STATUS Status;
1915
1916 //
1917 // Get the host bridge handle
1918 //
1919 HostBridgeHandle = Bridge->PciRootBridgeIo->ParentHandle;
1920
1921 //
1922 // Get the pci host bridge resource allocation protocol
1923 //
1924 Status = gBS->OpenProtocol (
1925 HostBridgeHandle,
1926 &gEfiPciHostBridgeResourceAllocationProtocolGuid,
1927 (VOID **) &PciResAlloc,
1928 NULL,
1929 NULL,
1930 EFI_OPEN_PROTOCOL_GET_PROTOCOL
1931 );
1932
1933 if (EFI_ERROR (Status)) {
1934 return EFI_UNSUPPORTED;
1935 }
1936
1937 //
1938 // Get Root Brige Handle
1939 //
1940 while (Bridge->Parent != NULL) {
1941 Bridge = Bridge->Parent;
1942 }
1943
1944 RootBridgeHandle = Bridge->Handle;
1945
1946 RootBridgePciAddress.Register = 0;
1947 RootBridgePciAddress.Function = Func;
1948 RootBridgePciAddress.Device = Device;
1949 RootBridgePciAddress.Bus = Bus;
1950 RootBridgePciAddress.ExtendedRegister = 0;
1951
1952 if (gPciPlatformProtocol != NULL) {
1953 //
1954 // Call PlatformPci::PrepController() if the protocol is present.
1955 //
1956 gPciPlatformProtocol->PlatformPrepController (
1957 gPciPlatformProtocol,
1958 HostBridgeHandle,
1959 RootBridgeHandle,
1960 RootBridgePciAddress,
1961 Phase,
1962 ChipsetEntry
1963 );
1964 } else if (gPciOverrideProtocol != NULL) {
1965 //
1966 // Call PlatformPci::PrepController() if the protocol is present.
1967 //
1968 gPciOverrideProtocol->PlatformPrepController (
1969 gPciOverrideProtocol,
1970 HostBridgeHandle,
1971 RootBridgeHandle,
1972 RootBridgePciAddress,
1973 Phase,
1974 ChipsetEntry
1975 );
1976 }
1977
1978 Status = PciResAlloc->PreprocessController (
1979 PciResAlloc,
1980 RootBridgeHandle,
1981 RootBridgePciAddress,
1982 Phase
1983 );
1984
1985 if (gPciPlatformProtocol != NULL) {
1986 //
1987 // Call PlatformPci::PrepController() if the protocol is present.
1988 //
1989 gPciPlatformProtocol->PlatformPrepController (
1990 gPciPlatformProtocol,
1991 HostBridgeHandle,
1992 RootBridgeHandle,
1993 RootBridgePciAddress,
1994 Phase,
1995 ChipsetExit
1996 );
1997 } else if (gPciOverrideProtocol != NULL) {
1998 //
1999 // Call PlatformPci::PrepController() if the protocol is present.
2000 //
2001 gPciOverrideProtocol->PlatformPrepController (
2002 gPciOverrideProtocol,
2003 HostBridgeHandle,
2004 RootBridgeHandle,
2005 RootBridgePciAddress,
2006 Phase,
2007 ChipsetExit
2008 );
2009 }
2010
2011 return EFI_SUCCESS;
2012 }
2013
2014 /**
2015 This function allows the PCI bus driver to be notified to act as requested when a hot-plug event has
2016 happened on the hot-plug controller. Currently, the operations include add operation and remove operation..
2017
2018 @param This A pointer to the hot plug request protocol.
2019 @param Operation The operation the PCI bus driver is requested to make.
2020 @param Controller The handle of the hot-plug controller.
2021 @param RemainingDevicePath The remaining device path for the PCI-like hot-plug device.
2022 @param NumberOfChildren The number of child handles.
2023 For a add operation, it is an output parameter.
2024 For a remove operation, it's an input parameter.
2025 @param ChildHandleBuffer The buffer which contains the child handles.
2026
2027 @retval EFI_INVALID_PARAMETER Operation is not a legal value.
2028 Controller is NULL or not a valid handle.
2029 NumberOfChildren is NULL.
2030 ChildHandleBuffer is NULL while Operation is add.
2031 @retval EFI_OUT_OF_RESOURCES There are no enough resources to start the devices.
2032 @retval EFI_NOT_FOUND Can not find bridge according to controller handle.
2033 @retval EFI_SUCCESS The handles for the specified device have been created or destroyed
2034 as requested, and for an add operation, the new handles are
2035 returned in ChildHandleBuffer.
2036 **/
2037 EFI_STATUS
2038 EFIAPI
2039 PciHotPlugRequestNotify (
2040 IN EFI_PCI_HOTPLUG_REQUEST_PROTOCOL * This,
2041 IN EFI_PCI_HOTPLUG_OPERATION Operation,
2042 IN EFI_HANDLE Controller,
2043 IN EFI_DEVICE_PATH_PROTOCOL * RemainingDevicePath OPTIONAL,
2044 IN OUT UINT8 *NumberOfChildren,
2045 IN OUT EFI_HANDLE * ChildHandleBuffer
2046 )
2047 {
2048 PCI_IO_DEVICE *Bridge;
2049 PCI_IO_DEVICE *Temp;
2050 EFI_PCI_IO_PROTOCOL *PciIo;
2051 UINTN Index;
2052 EFI_HANDLE RootBridgeHandle;
2053 EFI_STATUS Status;
2054
2055 //
2056 // Check input parameter validity
2057 //
2058 if ((Controller == NULL) || (NumberOfChildren == NULL)){
2059 return EFI_INVALID_PARAMETER;
2060 }
2061
2062 if ((Operation != EfiPciHotPlugRequestAdd) && (Operation != EfiPciHotplugRequestRemove)) {
2063 return EFI_INVALID_PARAMETER;
2064 }
2065
2066 if (Operation == EfiPciHotPlugRequestAdd){
2067 if (ChildHandleBuffer == NULL) {
2068 return EFI_INVALID_PARAMETER;
2069 }
2070 } else if ((Operation == EfiPciHotplugRequestRemove) && (*NumberOfChildren != 0)) {
2071 if (ChildHandleBuffer == NULL) {
2072 return EFI_INVALID_PARAMETER;
2073 }
2074 }
2075
2076 Status = gBS->OpenProtocol (
2077 Controller,
2078 &gEfiPciIoProtocolGuid,
2079 (VOID **) &PciIo,
2080 gPciBusDriverBinding.DriverBindingHandle,
2081 Controller,
2082 EFI_OPEN_PROTOCOL_GET_PROTOCOL
2083 );
2084
2085 if (EFI_ERROR (Status)) {
2086 return EFI_NOT_FOUND;
2087 }
2088
2089 Bridge = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);
2090
2091 //
2092 // Get root bridge handle
2093 //
2094 Temp = Bridge;
2095 while (Temp->Parent != NULL) {
2096 Temp = Temp->Parent;
2097 }
2098
2099 RootBridgeHandle = Temp->Handle;
2100
2101 if (Operation == EfiPciHotPlugRequestAdd) {
2102 //
2103 // Report Status Code to indicate hot plug happens
2104 //
2105 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
2106 EFI_PROGRESS_CODE,
2107 (EFI_IO_BUS_PCI | EFI_IOB_PC_HOTPLUG),
2108 Temp->DevicePath
2109 );
2110
2111 if (NumberOfChildren != NULL) {
2112 *NumberOfChildren = 0;
2113 }
2114
2115 if (IsListEmpty (&Bridge->ChildList)) {
2116
2117 Status = PciBridgeEnumerator (Bridge);
2118
2119 if (EFI_ERROR (Status)) {
2120 return Status;
2121 }
2122 }
2123
2124 Status = StartPciDevicesOnBridge (
2125 RootBridgeHandle,
2126 Bridge,
2127 RemainingDevicePath,
2128 NumberOfChildren,
2129 ChildHandleBuffer
2130 );
2131
2132 return Status;
2133 }
2134
2135 if (Operation == EfiPciHotplugRequestRemove) {
2136
2137 if (*NumberOfChildren == 0) {
2138 //
2139 // Remove all devices on the bridge
2140 //
2141 RemoveAllPciDeviceOnBridge (RootBridgeHandle, Bridge);
2142 return EFI_SUCCESS;
2143
2144 }
2145
2146 for (Index = 0; Index < *NumberOfChildren; Index++) {
2147 //
2148 // De register all the pci device
2149 //
2150 Status = DeRegisterPciDevice (RootBridgeHandle, ChildHandleBuffer[Index]);
2151
2152 if (EFI_ERROR (Status)) {
2153 return Status;
2154 }
2155
2156 }
2157 //
2158 // End for
2159 //
2160 return EFI_SUCCESS;
2161 }
2162
2163 return EFI_SUCCESS;
2164 }
2165
2166 /**
2167 Search hostbridge according to given handle
2168
2169 @param RootBridgeHandle Host bridge handle.
2170
2171 @retval TRUE Found host bridge handle.
2172 @retval FALSE Not found hot bridge handle.
2173
2174 **/
2175 BOOLEAN
2176 SearchHostBridgeHandle (
2177 IN EFI_HANDLE RootBridgeHandle
2178 )
2179 {
2180 EFI_HANDLE HostBridgeHandle;
2181 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
2182 UINTN Index;
2183 EFI_STATUS Status;
2184
2185 //
2186 // Get the rootbridge Io protocol to find the host bridge handle
2187 //
2188 Status = gBS->OpenProtocol (
2189 RootBridgeHandle,
2190 &gEfiPciRootBridgeIoProtocolGuid,
2191 (VOID **) &PciRootBridgeIo,
2192 gPciBusDriverBinding.DriverBindingHandle,
2193 RootBridgeHandle,
2194 EFI_OPEN_PROTOCOL_GET_PROTOCOL
2195 );
2196
2197 if (EFI_ERROR (Status)) {
2198 return FALSE;
2199 }
2200
2201 HostBridgeHandle = PciRootBridgeIo->ParentHandle;
2202 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {
2203 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {
2204 return TRUE;
2205 }
2206 }
2207
2208 return FALSE;
2209 }
2210
2211 /**
2212 Add host bridge handle to global variable for enumerating.
2213
2214 @param HostBridgeHandle Host bridge handle.
2215
2216 @retval EFI_SUCCESS Successfully added host bridge.
2217 @retval EFI_ABORTED Host bridge is NULL, or given host bridge
2218 has been in host bridge list.
2219
2220 **/
2221 EFI_STATUS
2222 AddHostBridgeEnumerator (
2223 IN EFI_HANDLE HostBridgeHandle
2224 )
2225 {
2226 UINTN Index;
2227
2228 if (HostBridgeHandle == NULL) {
2229 return EFI_ABORTED;
2230 }
2231
2232 for (Index = 0; Index < gPciHostBridgeNumber; Index++) {
2233 if (HostBridgeHandle == gPciHostBrigeHandles[Index]) {
2234 return EFI_ABORTED;
2235 }
2236 }
2237
2238 if (Index < PCI_MAX_HOST_BRIDGE_NUM) {
2239 gPciHostBrigeHandles[Index] = HostBridgeHandle;
2240 gPciHostBridgeNumber++;
2241 }
2242
2243 return EFI_SUCCESS;
2244 }
2245
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