2 PCI emumeration support functions implementation for PCI Bus module.
4 Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
12 extern CHAR16
*mBarTypeStr
[];
13 extern EDKII_DEVICE_SECURITY_PROTOCOL
*mDeviceSecurityProtocol
;
15 #define OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
16 #define EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
17 #define SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
18 #define DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
21 This routine is used to check whether the pci device is present.
23 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
24 @param Pci Output buffer for PCI device configuration space.
25 @param Bus PCI bus NO.
26 @param Device PCI device NO.
27 @param Func PCI Func NO.
29 @retval EFI_NOT_FOUND PCI device not present.
30 @retval EFI_SUCCESS PCI device is found.
35 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
,
46 // Create PCI address map in terms of Bus, Device and Func
48 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
51 // Read the Vendor ID register
53 Status
= PciRootBridgeIo
->Pci
.Read (
61 if (!EFI_ERROR (Status
) && ((Pci
->Hdr
).VendorId
!= 0xffff)) {
63 // Read the entire config header for the device
65 Status
= PciRootBridgeIo
->Pci
.Read (
69 sizeof (PCI_TYPE00
) / sizeof (UINT32
),
80 Collect all the resource information under this root bridge.
82 A database that records all the information about pci device subject to this
83 root bridge will then be created.
85 @param Bridge Parent bridge instance.
86 @param StartBusNumber Bus number of beginning.
88 @retval EFI_SUCCESS PCI device is found.
89 @retval other Some error occurred when reading PCI bridge information.
93 PciPciDeviceInfoCollector (
94 IN PCI_IO_DEVICE
*Bridge
,
95 IN UINT8 StartBusNumber
103 PCI_IO_DEVICE
*PciIoDevice
;
104 EFI_PCI_IO_PROTOCOL
*PciIo
;
106 Status
= EFI_SUCCESS
;
109 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
110 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
112 // Check to see whether PCI device is present
114 Status
= PciDevicePresent (
115 Bridge
->PciRootBridgeIo
,
117 (UINT8
)StartBusNumber
,
122 if (EFI_ERROR (Status
) && (Func
== 0)) {
124 // go to next device if there is no Function 0
129 if (!EFI_ERROR (Status
)) {
131 // Call back to host bridge function
133 PreprocessController (Bridge
, (UINT8
)StartBusNumber
, Device
, Func
, EfiPciBeforeResourceCollection
);
136 // Collect all the information about the PCI device discovered
138 Status
= PciSearchDevice (
141 (UINT8
)StartBusNumber
,
148 // Recursively scan PCI busses on the other side of PCI-PCI bridges
151 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
) || IS_CARDBUS_BRIDGE (&Pci
))) {
153 // If it is PPB, we need to get the secondary bus to continue the enumeration
155 PciIo
= &(PciIoDevice
->PciIo
);
157 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
, 1, &SecBus
);
159 if (EFI_ERROR (Status
)) {
164 // Ensure secondary bus number is greater than the primary bus number to avoid
165 // any potential dead loop when PcdPciDisableBusEnumeration is set to TRUE
167 if (SecBus
<= StartBusNumber
) {
172 // Get resource padding for PPB
174 GetResourcePaddingPpb (PciIoDevice
);
177 // Deep enumerate the next level bus
179 Status
= PciPciDeviceInfoCollector (
185 if ((Func
== 0) && !IS_PCI_MULTI_FUNC (&Pci
)) {
187 // Skip sub functions, this is not a multi function device
199 Search required device and create PCI device instance.
201 @param Bridge Parent bridge instance.
202 @param Pci Input PCI device information block.
203 @param Bus PCI bus NO.
204 @param Device PCI device NO.
205 @param Func PCI func NO.
206 @param PciDevice Output of searched PCI device instance.
208 @retval EFI_SUCCESS Successfully created PCI device instance.
209 @retval EFI_OUT_OF_RESOURCES Cannot get PCI device information.
214 IN PCI_IO_DEVICE
*Bridge
,
219 OUT PCI_IO_DEVICE
**PciDevice
222 PCI_IO_DEVICE
*PciIoDevice
;
228 "PciBus: Discovered %s @ [%02x|%02x|%02x]\n",
229 IS_PCI_BRIDGE (Pci
) ? L
"PPB" :
230 IS_CARDBUS_BRIDGE (Pci
) ? L
"P2C" :
237 if (!IS_PCI_BRIDGE (Pci
)) {
238 if (IS_CARDBUS_BRIDGE (Pci
)) {
239 PciIoDevice
= GatherP2CInfo (
246 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
247 InitializeP2C (PciIoDevice
);
251 // Create private data for Pci Device
253 PciIoDevice
= GatherDeviceInfo (
263 // Create private data for PPB
265 PciIoDevice
= GatherPpbInfo (
274 // Special initialization for PPB including making the PPB quiet
276 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
277 InitializePpb (PciIoDevice
);
281 if (PciIoDevice
== NULL
) {
282 return EFI_OUT_OF_RESOURCES
;
286 // Update the bar information for this PCI device so as to support some specific device
288 UpdatePciInfo (PciIoDevice
);
290 if (PciIoDevice
->DevicePath
== NULL
) {
291 return EFI_OUT_OF_RESOURCES
;
295 // Detect this function has option rom
297 if (gFullEnumeration
) {
298 if (!IS_CARDBUS_BRIDGE (Pci
)) {
299 GetOpRomInfo (PciIoDevice
);
302 ResetPowerManagementFeature (PciIoDevice
);
306 // Insert it into a global tree for future reference
308 InsertPciDevice (Bridge
, PciIoDevice
);
311 // Determine PCI device attributes
314 if (PciDevice
!= NULL
) {
315 *PciDevice
= PciIoDevice
;
322 Dump the PPB padding resource information.
324 @param PciIoDevice PCI IO instance.
325 @param ResourceType The desired resource type to dump.
326 PciBarTypeUnknown means to dump all types of resources.
329 DumpPpbPaddingResource (
330 IN PCI_IO_DEVICE
*PciIoDevice
,
331 IN PCI_BAR_TYPE ResourceType
334 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptor
;
337 if (PciIoDevice
->ResourcePaddingDescriptors
== NULL
) {
341 if ((ResourceType
== PciBarTypeIo16
) || (ResourceType
== PciBarTypeIo32
)) {
342 ResourceType
= PciBarTypeIo
;
345 for (Descriptor
= PciIoDevice
->ResourcePaddingDescriptors
; Descriptor
->Desc
!= ACPI_END_TAG_DESCRIPTOR
; Descriptor
++) {
346 Type
= PciBarTypeUnknown
;
347 if ((Descriptor
->Desc
== ACPI_ADDRESS_SPACE_DESCRIPTOR
) && (Descriptor
->ResType
== ACPI_ADDRESS_SPACE_TYPE_IO
)) {
349 } else if ((Descriptor
->Desc
== ACPI_ADDRESS_SPACE_DESCRIPTOR
) && (Descriptor
->ResType
== ACPI_ADDRESS_SPACE_TYPE_MEM
)) {
350 if (Descriptor
->AddrSpaceGranularity
== 32) {
354 if (Descriptor
->SpecificFlag
== EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
) {
355 Type
= PciBarTypePMem32
;
361 if (Descriptor
->SpecificFlag
== 0) {
362 Type
= PciBarTypeMem32
;
366 if (Descriptor
->AddrSpaceGranularity
== 64) {
370 if (Descriptor
->SpecificFlag
== EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
) {
371 Type
= PciBarTypePMem64
;
377 if (Descriptor
->SpecificFlag
== 0) {
378 Type
= PciBarTypeMem64
;
383 if ((Type
!= PciBarTypeUnknown
) && ((ResourceType
== PciBarTypeUnknown
) || (ResourceType
== Type
))) {
386 " Padding: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx\n",
388 Descriptor
->AddrRangeMax
,
396 Dump the PCI BAR information.
398 @param PciIoDevice PCI IO instance.
402 IN PCI_IO_DEVICE
*PciIoDevice
407 for (Index
= 0; Index
< PCI_MAX_BAR
; Index
++) {
408 if (PciIoDevice
->PciBar
[Index
].BarType
== PciBarTypeUnknown
) {
414 " BAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
416 mBarTypeStr
[MIN (PciIoDevice
->PciBar
[Index
].BarType
, PciBarTypeMaxType
)],
417 PciIoDevice
->PciBar
[Index
].Alignment
,
418 PciIoDevice
->PciBar
[Index
].Length
,
419 PciIoDevice
->PciBar
[Index
].Offset
423 for (Index
= 0; Index
< PCI_MAX_BAR
; Index
++) {
424 if ((PciIoDevice
->VfPciBar
[Index
].BarType
== PciBarTypeUnknown
) && (PciIoDevice
->VfPciBar
[Index
].Length
== 0)) {
430 " VFBAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
432 mBarTypeStr
[MIN (PciIoDevice
->VfPciBar
[Index
].BarType
, PciBarTypeMaxType
)],
433 PciIoDevice
->VfPciBar
[Index
].Alignment
,
434 PciIoDevice
->VfPciBar
[Index
].Length
,
435 PciIoDevice
->VfPciBar
[Index
].Offset
439 DEBUG ((DEBUG_INFO
, "\n"));
443 Create PCI device instance for PCI device.
445 @param Bridge Parent bridge instance.
446 @param Pci Input PCI device information block.
447 @param Bus PCI device Bus NO.
448 @param Device PCI device Device NO.
449 @param Func PCI device's func NO.
451 @return Created PCI device instance.
456 IN PCI_IO_DEVICE
*Bridge
,
465 PCI_IO_DEVICE
*PciIoDevice
;
467 PciIoDevice
= CreatePciIoDevice (
475 if (PciIoDevice
== NULL
) {
480 // If it is a full enumeration, disconnect the device in advance
482 if (gFullEnumeration
) {
483 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
487 // Start to parse the bars
489 for (Offset
= 0x10, BarIndex
= 0; Offset
<= 0x24 && BarIndex
< PCI_MAX_BAR
; BarIndex
++) {
490 Offset
= PciParseBar (PciIoDevice
, Offset
, BarIndex
);
494 // Parse the SR-IOV VF bars
496 if (PcdGetBool (PcdSrIovSupport
) && (PciIoDevice
->SrIovCapabilityOffset
!= 0)) {
497 for (Offset
= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0
, BarIndex
= 0;
498 Offset
<= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5
;
501 ASSERT (BarIndex
< PCI_MAX_BAR
);
502 Offset
= PciIovParseVfBar (PciIoDevice
, Offset
, BarIndex
);
507 DumpPciBars (PciIoDevice
);
513 Create PCI device instance for PCI-PCI bridge.
515 @param Bridge Parent bridge instance.
516 @param Pci Input PCI device information block.
517 @param Bus PCI device Bus NO.
518 @param Device PCI device Device NO.
519 @param Func PCI device's func NO.
521 @return Created PCI device instance.
526 IN PCI_IO_DEVICE
*Bridge
,
533 PCI_IO_DEVICE
*PciIoDevice
;
536 EFI_PCI_IO_PROTOCOL
*PciIo
;
538 UINT32 PMemBaseLimit
;
539 UINT16 PrefetchableMemoryBase
;
540 UINT16 PrefetchableMemoryLimit
;
542 PciIoDevice
= CreatePciIoDevice (
550 if (PciIoDevice
== NULL
) {
554 if (gFullEnumeration
) {
555 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
558 // Initialize the bridge control register
560 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED
);
564 // PPB can have two BARs
566 if (PciParseBar (PciIoDevice
, 0x10, PPB_BAR_0
) == 0x14) {
570 PciParseBar (PciIoDevice
, 0x14, PPB_BAR_1
);
573 PciIo
= &PciIoDevice
->PciIo
;
576 // Test whether it support 32 decode or not
578 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
579 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
580 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
581 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
584 if ((Value
& 0x01) != 0) {
585 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
587 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO16_DECODE_SUPPORTED
;
592 // if PcdPciBridgeIoAlignmentProbe is TRUE, PCI bus driver probes
593 // PCI bridge supporting non-standard I/O window alignment less than 4K.
596 PciIoDevice
->BridgeIoAlignment
= 0xFFF;
597 if (FeaturePcdGet (PcdPciBridgeIoAlignmentProbe
)) {
599 // Check any bits of bit 3-1 of I/O Base Register are writable.
600 // if so, it is assumed non-standard I/O window alignment is supported by this bridge.
601 // Per spec, bit 3-1 of I/O Base Register are reserved bits, so its content can't be assumed.
603 Value
= (UINT8
)(Temp
^ (BIT3
| BIT2
| BIT1
));
604 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
605 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
606 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
607 Value
= (UINT8
)((Value
^ Temp
) & (BIT3
| BIT2
| BIT1
));
610 PciIoDevice
->BridgeIoAlignment
= 0x7FF;
613 PciIoDevice
->BridgeIoAlignment
= 0x3FF;
615 case BIT3
| BIT2
| BIT1
:
616 PciIoDevice
->BridgeIoAlignment
= 0x1FF;
621 Status
= BarExisted (
629 // Test if it supports 64 memory or not
631 // The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory Limit
633 // 0 - the bridge supports only 32 bit addresses.
634 // 1 - the bridge supports 64-bit addresses.
636 PrefetchableMemoryBase
= (UINT16
)(PMemBaseLimit
& 0xffff);
637 PrefetchableMemoryLimit
= (UINT16
)(PMemBaseLimit
>> 16);
638 if (!EFI_ERROR (Status
) &&
639 ((PrefetchableMemoryBase
& 0x000f) == 0x0001) &&
640 ((PrefetchableMemoryLimit
& 0x000f) == 0x0001))
642 Status
= BarExisted (
649 if (!EFI_ERROR (Status
)) {
650 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
651 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED
;
653 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
658 // Memory 32 code is required for ppb
660 PciIoDevice
->Decodes
|= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
;
662 GetResourcePaddingPpb (PciIoDevice
);
665 DumpPpbPaddingResource (PciIoDevice
, PciBarTypeUnknown
);
666 DumpPciBars (PciIoDevice
);
673 Create PCI device instance for PCI Card bridge device.
675 @param Bridge Parent bridge instance.
676 @param Pci Input PCI device information block.
677 @param Bus PCI device Bus NO.
678 @param Device PCI device Device NO.
679 @param Func PCI device's func NO.
681 @return Created PCI device instance.
686 IN PCI_IO_DEVICE
*Bridge
,
693 PCI_IO_DEVICE
*PciIoDevice
;
695 PciIoDevice
= CreatePciIoDevice (
703 if (PciIoDevice
== NULL
) {
707 if (gFullEnumeration
) {
708 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
711 // Initialize the bridge control register
713 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED
);
717 // P2C only has one bar that is in 0x10
719 PciParseBar (PciIoDevice
, 0x10, P2C_BAR_0
);
722 // Read PciBar information from the bar register
724 GetBackPcCardBar (PciIoDevice
);
725 PciIoDevice
->Decodes
= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
|
726 EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
|
727 EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
730 DumpPciBars (PciIoDevice
);
737 Create device path for pci device.
739 @param ParentDevicePath Parent bridge's path.
740 @param PciIoDevice Pci device instance.
742 @return Device path protocol instance for specific pci device.
745 EFI_DEVICE_PATH_PROTOCOL
*
746 CreatePciDevicePath (
747 IN EFI_DEVICE_PATH_PROTOCOL
*ParentDevicePath
,
748 IN PCI_IO_DEVICE
*PciIoDevice
751 PCI_DEVICE_PATH PciNode
;
754 // Create PCI device path
756 PciNode
.Header
.Type
= HARDWARE_DEVICE_PATH
;
757 PciNode
.Header
.SubType
= HW_PCI_DP
;
758 SetDevicePathNodeLength (&PciNode
.Header
, sizeof (PciNode
));
760 PciNode
.Device
= PciIoDevice
->DeviceNumber
;
761 PciNode
.Function
= PciIoDevice
->FunctionNumber
;
762 PciIoDevice
->DevicePath
= AppendDevicePathNode (ParentDevicePath
, &PciNode
.Header
);
764 return PciIoDevice
->DevicePath
;
768 Check whether the PCI IOV VF bar is existed or not.
770 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
771 @param Offset The offset.
772 @param BarLengthValue The bar length value returned.
773 @param OriginalBarValue The original bar value returned.
775 @retval EFI_NOT_FOUND The bar doesn't exist.
776 @retval EFI_SUCCESS The bar exist.
781 IN PCI_IO_DEVICE
*PciIoDevice
,
783 OUT UINT32
*BarLengthValue
,
784 OUT UINT32
*OriginalBarValue
787 EFI_PCI_IO_PROTOCOL
*PciIo
;
788 UINT32 OriginalValue
;
793 // Ensure it is called properly
795 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
796 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
797 return EFI_NOT_FOUND
;
800 PciIo
= &PciIoDevice
->PciIo
;
803 // Preserve the original value
806 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
809 // Raise TPL to high level to disable timer interrupt while the BAR is probed
811 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
813 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &gAllOne
);
814 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &Value
);
817 // Write back the original value
819 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
822 // Restore TPL to its original level
824 gBS
->RestoreTPL (OldTpl
);
826 if (BarLengthValue
!= NULL
) {
827 *BarLengthValue
= Value
;
830 if (OriginalBarValue
!= NULL
) {
831 *OriginalBarValue
= OriginalValue
;
835 return EFI_NOT_FOUND
;
842 Check whether the bar is existed or not.
844 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
845 @param Offset The offset.
846 @param BarLengthValue The bar length value returned.
847 @param OriginalBarValue The original bar value returned.
849 @retval EFI_NOT_FOUND The bar doesn't exist.
850 @retval EFI_SUCCESS The bar exist.
855 IN PCI_IO_DEVICE
*PciIoDevice
,
857 OUT UINT32
*BarLengthValue
,
858 OUT UINT32
*OriginalBarValue
861 EFI_PCI_IO_PROTOCOL
*PciIo
;
862 UINT32 OriginalValue
;
866 PciIo
= &PciIoDevice
->PciIo
;
869 // Preserve the original value
871 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
)Offset
, 1, &OriginalValue
);
874 // Raise TPL to high level to disable timer interrupt while the BAR is probed
876 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
878 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
)Offset
, 1, &gAllOne
);
879 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
)Offset
, 1, &Value
);
882 // Write back the original value
884 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
)Offset
, 1, &OriginalValue
);
887 // Restore TPL to its original level
889 gBS
->RestoreTPL (OldTpl
);
891 if (BarLengthValue
!= NULL
) {
892 *BarLengthValue
= Value
;
895 if (OriginalBarValue
!= NULL
) {
896 *OriginalBarValue
= OriginalValue
;
900 return EFI_NOT_FOUND
;
907 Test whether the device can support given attributes.
909 @param PciIoDevice Pci device instance.
910 @param Command Input command register value, and
911 returned supported register value.
912 @param BridgeControl Input bridge control value for PPB or P2C, and
913 returned supported bridge control value.
914 @param OldCommand Returned and stored old command register offset.
915 @param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.
919 PciTestSupportedAttribute (
920 IN PCI_IO_DEVICE
*PciIoDevice
,
921 IN OUT UINT16
*Command
,
922 IN OUT UINT16
*BridgeControl
,
923 OUT UINT16
*OldCommand
,
924 OUT UINT16
*OldBridgeControl
931 // Preserve the original value
933 PCI_READ_COMMAND_REGISTER (PciIoDevice
, OldCommand
);
936 // Raise TPL to high level to disable timer interrupt while the BAR is probed
938 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
939 CommandValue
= *Command
| *OldCommand
;
941 PCI_SET_COMMAND_REGISTER (PciIoDevice
, CommandValue
);
942 PCI_READ_COMMAND_REGISTER (PciIoDevice
, &CommandValue
);
944 *Command
= *Command
& CommandValue
;
946 // Write back the original value
948 PCI_SET_COMMAND_REGISTER (PciIoDevice
, *OldCommand
);
951 // Restore TPL to its original level
953 gBS
->RestoreTPL (OldTpl
);
955 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
957 // Preserve the original value
959 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, OldBridgeControl
);
962 // Raise TPL to high level to disable timer interrupt while the BAR is probed
964 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
966 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *BridgeControl
);
967 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, BridgeControl
);
970 // Write back the original value
972 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *OldBridgeControl
);
975 // Restore TPL to its original level
977 gBS
->RestoreTPL (OldTpl
);
979 *OldBridgeControl
= 0;
985 Set the supported or current attributes of a PCI device.
987 @param PciIoDevice Structure pointer for PCI device.
988 @param Command Command register value.
989 @param BridgeControl Bridge control value for PPB or P2C.
990 @param Option Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.
994 PciSetDeviceAttribute (
995 IN PCI_IO_DEVICE
*PciIoDevice
,
997 IN UINT16 BridgeControl
,
1005 if ((Command
& EFI_PCI_COMMAND_IO_SPACE
) != 0) {
1006 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IO
;
1009 if ((Command
& EFI_PCI_COMMAND_MEMORY_SPACE
) != 0) {
1010 Attributes
|= EFI_PCI_IO_ATTRIBUTE_MEMORY
;
1013 if ((Command
& EFI_PCI_COMMAND_BUS_MASTER
) != 0) {
1014 Attributes
|= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
;
1017 if ((Command
& EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
) != 0) {
1018 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
1021 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_ISA
) != 0) {
1022 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_IO
;
1025 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA
) != 0) {
1026 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO
;
1027 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
1028 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
1031 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA_16
) != 0) {
1032 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
;
1033 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
;
1036 if (Option
== EFI_SET_SUPPORTS
) {
1037 Attributes
|= (UINT64
)(EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE
|
1038 EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED
|
1039 EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE
|
1040 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
1041 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
1042 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1044 if (IS_PCI_LPC (&PciIoDevice
->Pci
)) {
1045 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO
;
1046 Attributes
|= (mReserveIsaAliases
? (UINT64
)EFI_PCI_IO_ATTRIBUTE_ISA_IO
: \
1047 (UINT64
)EFI_PCI_IO_ATTRIBUTE_ISA_IO_16
);
1050 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
1052 // For bridge, it should support IDE attributes
1054 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
1055 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
1057 if (mReserveVgaAliases
) {
1058 Attributes
&= ~(UINT64
)(EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
| \
1059 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
);
1061 Attributes
&= ~(UINT64
)(EFI_PCI_IO_ATTRIBUTE_VGA_IO
| \
1062 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
);
1065 if (IS_PCI_IDE (&PciIoDevice
->Pci
)) {
1066 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
1067 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
1070 if (IS_PCI_VGA (&PciIoDevice
->Pci
)) {
1071 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
1072 Attributes
|= (mReserveVgaAliases
? (UINT64
)EFI_PCI_IO_ATTRIBUTE_VGA_IO
: \
1073 (UINT64
)EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
);
1077 PciIoDevice
->Supports
= Attributes
;
1078 PciIoDevice
->Supports
&= ((PciIoDevice
->Parent
->Supports
) | \
1079 EFI_PCI_IO_ATTRIBUTE_IO
| EFI_PCI_IO_ATTRIBUTE_MEMORY
| \
1080 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
);
1083 // When this attribute is clear, the RomImage and RomSize fields in the PCI IO were
1084 // initialized based on the PCI option ROM found through the ROM BAR of the PCI controller.
1085 // When this attribute is set, the PCI option ROM described by the RomImage and RomSize
1086 // fields is not from the the ROM BAR of the PCI controller.
1088 if (!PciIoDevice
->EmbeddedRom
) {
1089 Attributes
|= EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
;
1092 PciIoDevice
->Attributes
= Attributes
;
1097 Determine if the device can support Fast Back to Back attribute.
1099 @param PciIoDevice Pci device instance.
1100 @param StatusIndex Status register value.
1102 @retval EFI_SUCCESS This device support Fast Back to Back attribute.
1103 @retval EFI_UNSUPPORTED This device doesn't support Fast Back to Back attribute.
1107 GetFastBackToBackSupport (
1108 IN PCI_IO_DEVICE
*PciIoDevice
,
1109 IN UINT8 StatusIndex
1112 EFI_PCI_IO_PROTOCOL
*PciIo
;
1114 UINT32 StatusRegister
;
1117 // Read the status register
1119 PciIo
= &PciIoDevice
->PciIo
;
1120 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint16
, StatusIndex
, 1, &StatusRegister
);
1121 if (EFI_ERROR (Status
)) {
1122 return EFI_UNSUPPORTED
;
1126 // Check the Fast B2B bit
1128 if ((StatusRegister
& EFI_PCI_FAST_BACK_TO_BACK_CAPABLE
) != 0) {
1131 return EFI_UNSUPPORTED
;
1136 Process the option ROM for all the children of the specified parent PCI device.
1137 It can only be used after the first full Option ROM process.
1139 @param PciIoDevice Pci device instance.
1143 ProcessOptionRomLight (
1144 IN PCI_IO_DEVICE
*PciIoDevice
1147 PCI_IO_DEVICE
*Temp
;
1148 LIST_ENTRY
*CurrentLink
;
1151 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1153 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1154 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1155 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1157 if (!IsListEmpty (&Temp
->ChildList
)) {
1158 ProcessOptionRomLight (Temp
);
1161 Temp
->AllOpRomProcessed
= PciRomGetImageMapping (Temp
);
1163 CurrentLink
= CurrentLink
->ForwardLink
;
1168 Determine the related attributes of all devices under a Root Bridge.
1170 @param PciIoDevice PCI device instance.
1174 DetermineDeviceAttribute (
1175 IN PCI_IO_DEVICE
*PciIoDevice
1179 UINT16 BridgeControl
;
1181 UINT16 OldBridgeControl
;
1182 BOOLEAN FastB2BSupport
;
1183 PCI_IO_DEVICE
*Temp
;
1184 LIST_ENTRY
*CurrentLink
;
1188 // For Root Bridge, just copy it by RootBridgeIo protocol
1189 // so as to keep consistent with the actual attribute
1191 if (PciIoDevice
->Parent
== NULL
) {
1192 Status
= PciIoDevice
->PciRootBridgeIo
->GetAttributes (
1193 PciIoDevice
->PciRootBridgeIo
,
1194 &PciIoDevice
->Supports
,
1195 &PciIoDevice
->Attributes
1197 if (EFI_ERROR (Status
)) {
1202 // Assume the PCI Root Bridge supports DAC
1204 PciIoDevice
->Supports
|= (UINT64
)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
1205 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
1206 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1209 // Set the attributes to be checked for common PCI devices and PPB or P2C
1210 // Since some devices only support part of them, it is better to set the
1211 // attribute according to its command or bridge control register
1213 Command
= EFI_PCI_COMMAND_IO_SPACE
|
1214 EFI_PCI_COMMAND_MEMORY_SPACE
|
1215 EFI_PCI_COMMAND_BUS_MASTER
|
1216 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
;
1218 BridgeControl
= EFI_PCI_BRIDGE_CONTROL_ISA
| EFI_PCI_BRIDGE_CONTROL_VGA
| EFI_PCI_BRIDGE_CONTROL_VGA_16
;
1221 // Test whether the device can support attributes above
1223 PciTestSupportedAttribute (PciIoDevice
, &Command
, &BridgeControl
, &OldCommand
, &OldBridgeControl
);
1226 // Set the supported attributes for specified PCI device
1228 PciSetDeviceAttribute (PciIoDevice
, Command
, BridgeControl
, EFI_SET_SUPPORTS
);
1231 // Set the current attributes for specified PCI device
1233 PciSetDeviceAttribute (PciIoDevice
, OldCommand
, OldBridgeControl
, EFI_SET_ATTRIBUTES
);
1236 // Enable other PCI supported attributes but not defined in PCI_IO_PROTOCOL
1237 // For PCI Express devices, Memory Write and Invalidate is hardwired to 0b so only enable it for PCI devices.
1238 if (!PciIoDevice
->IsPciExp
) {
1239 PCI_ENABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE
);
1243 FastB2BSupport
= TRUE
;
1246 // P2C can not support FB2B on the secondary side
1248 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
1249 FastB2BSupport
= FALSE
;
1253 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1255 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1256 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1257 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1258 Status
= DetermineDeviceAttribute (Temp
);
1259 if (EFI_ERROR (Status
)) {
1264 // Detect Fast Back to Back support for the device under the bridge
1266 Status
= GetFastBackToBackSupport (Temp
, PCI_PRIMARY_STATUS_OFFSET
);
1267 if (FastB2BSupport
&& EFI_ERROR (Status
)) {
1268 FastB2BSupport
= FALSE
;
1271 CurrentLink
= CurrentLink
->ForwardLink
;
1275 // Set or clear Fast Back to Back bit for the whole bridge
1277 if (!IsListEmpty (&PciIoDevice
->ChildList
)) {
1278 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
1279 Status
= GetFastBackToBackSupport (PciIoDevice
, PCI_BRIDGE_STATUS_REGISTER_OFFSET
);
1281 if (EFI_ERROR (Status
) || (!FastB2BSupport
)) {
1282 FastB2BSupport
= FALSE
;
1283 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1285 PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1289 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1290 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1291 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1292 if (FastB2BSupport
) {
1293 PCI_ENABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1295 PCI_DISABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1298 CurrentLink
= CurrentLink
->ForwardLink
;
1303 // End for IsListEmpty
1309 This routine is used to update the bar information for those incompatible PCI device.
1311 @param PciIoDevice Input Pci device instance. Output Pci device instance with updated
1314 @retval EFI_SUCCESS Successfully updated bar information.
1315 @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.
1320 IN OUT PCI_IO_DEVICE
*PciIoDevice
1326 VOID
*Configuration
;
1327 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1329 Configuration
= NULL
;
1330 Status
= EFI_SUCCESS
;
1332 if (gIncompatiblePciDeviceSupport
== NULL
) {
1334 // It can only be supported after the Incompatible PCI Device
1335 // Support Protocol has been installed
1337 Status
= gBS
->LocateProtocol (
1338 &gEfiIncompatiblePciDeviceSupportProtocolGuid
,
1340 (VOID
**)&gIncompatiblePciDeviceSupport
1344 if (Status
== EFI_SUCCESS
) {
1346 // Check whether the device belongs to incompatible devices from protocol or not
1347 // If it is , then get its special requirement in the ACPI table
1349 Status
= gIncompatiblePciDeviceSupport
->CheckDevice (
1350 gIncompatiblePciDeviceSupport
,
1351 PciIoDevice
->Pci
.Hdr
.VendorId
,
1352 PciIoDevice
->Pci
.Hdr
.DeviceId
,
1353 PciIoDevice
->Pci
.Hdr
.RevisionID
,
1354 PciIoDevice
->Pci
.Device
.SubsystemVendorID
,
1355 PciIoDevice
->Pci
.Device
.SubsystemID
,
1360 if (EFI_ERROR (Status
) || (Configuration
== NULL
)) {
1361 return EFI_UNSUPPORTED
;
1365 // Update PCI device information from the ACPI table
1367 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*)Configuration
;
1369 while (Ptr
->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
1370 if (Ptr
->Desc
!= ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
1372 // The format is not support
1377 for (BarIndex
= 0; BarIndex
< PCI_MAX_BAR
; BarIndex
++) {
1378 if ((Ptr
->AddrTranslationOffset
!= MAX_UINT64
) &&
1379 (Ptr
->AddrTranslationOffset
!= MAX_UINT8
) &&
1380 (Ptr
->AddrTranslationOffset
!= BarIndex
)
1384 // Skip updating when AddrTranslationOffset is not MAX_UINT64 or MAX_UINT8 (wide match).
1385 // Skip updating when current BarIndex doesn't equal to AddrTranslationOffset.
1386 // Comparing against MAX_UINT8 is to keep backward compatibility.
1392 switch (Ptr
->ResType
) {
1393 case ACPI_ADDRESS_SPACE_TYPE_MEM
:
1396 // Make sure the bar is memory type
1398 if (CheckBarType (PciIoDevice
, (UINT8
)BarIndex
, PciBarTypeMem
)) {
1402 // Ignored if granularity is 0.
1403 // Ignored if PCI BAR is I/O or 32-bit memory.
1404 // If PCI BAR is 64-bit memory and granularity is 32, then
1405 // the PCI BAR resource is allocated below 4GB.
1406 // If PCI BAR is 64-bit memory and granularity is 64, then
1407 // the PCI BAR resource is allocated above 4GB.
1409 if (PciIoDevice
->PciBar
[BarIndex
].BarType
== PciBarTypeMem64
) {
1410 switch (Ptr
->AddrSpaceGranularity
) {
1412 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1414 PciIoDevice
->PciBar
[BarIndex
].BarTypeFixed
= TRUE
;
1421 if (PciIoDevice
->PciBar
[BarIndex
].BarType
== PciBarTypePMem64
) {
1422 switch (Ptr
->AddrSpaceGranularity
) {
1424 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1426 PciIoDevice
->PciBar
[BarIndex
].BarTypeFixed
= TRUE
;
1436 case ACPI_ADDRESS_SPACE_TYPE_IO
:
1439 // Make sure the bar is IO type
1441 if (CheckBarType (PciIoDevice
, (UINT8
)BarIndex
, PciBarTypeIo
)) {
1450 // Update the new alignment for the device
1452 SetNewAlign (&(PciIoDevice
->PciBar
[BarIndex
].Alignment
), Ptr
->AddrRangeMax
);
1455 // Update the new length for the device
1457 if (Ptr
->AddrLen
!= 0) {
1458 PciIoDevice
->PciBar
[BarIndex
].Length
= Ptr
->AddrLen
;
1466 FreePool (Configuration
);
1472 This routine will update the alignment with the new alignment.
1473 Compare with OLD_ALIGN/EVEN_ALIGN/SQUAD_ALIGN/DQUAD_ALIGN is to keep
1474 backward compatibility.
1476 @param Alignment Input Old alignment. Output updated alignment.
1477 @param NewAlignment New alignment.
1482 IN OUT UINT64
*Alignment
,
1483 IN UINT64 NewAlignment
1486 UINT64 OldAlignment
;
1490 // The new alignment is the same as the original,
1493 if ((NewAlignment
== 0) || (NewAlignment
== OLD_ALIGN
)) {
1498 // Check the validity of the parameter
1500 if ((NewAlignment
!= EVEN_ALIGN
) &&
1501 (NewAlignment
!= SQUAD_ALIGN
) &&
1502 (NewAlignment
!= DQUAD_ALIGN
))
1504 *Alignment
= NewAlignment
;
1508 OldAlignment
= (*Alignment
) + 1;
1512 // Get the first non-zero hex value of the length
1514 while ((OldAlignment
& 0x0F) == 0x00) {
1515 OldAlignment
= RShiftU64 (OldAlignment
, 4);
1520 // Adjust the alignment to even, quad or double quad boundary
1522 if (NewAlignment
== EVEN_ALIGN
) {
1523 if ((OldAlignment
& 0x01) != 0) {
1524 OldAlignment
= OldAlignment
+ 2 - (OldAlignment
& 0x01);
1526 } else if (NewAlignment
== SQUAD_ALIGN
) {
1527 if ((OldAlignment
& 0x03) != 0) {
1528 OldAlignment
= OldAlignment
+ 4 - (OldAlignment
& 0x03);
1530 } else if (NewAlignment
== DQUAD_ALIGN
) {
1531 if ((OldAlignment
& 0x07) != 0) {
1532 OldAlignment
= OldAlignment
+ 8 - (OldAlignment
& 0x07);
1537 // Update the old value
1539 NewAlignment
= LShiftU64 (OldAlignment
, ShiftBit
) - 1;
1540 *Alignment
= NewAlignment
;
1546 Parse PCI IOV VF bar information and fill them into PCI device instance.
1548 @param PciIoDevice Pci device instance.
1549 @param Offset Bar offset.
1550 @param BarIndex Bar index.
1552 @return Next bar offset.
1557 IN PCI_IO_DEVICE
*PciIoDevice
,
1563 UINT32 OriginalValue
;
1568 // Ensure it is called properly
1570 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
1571 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
1578 Status
= VfBarExisted (
1585 if (EFI_ERROR (Status
)) {
1586 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1587 PciIoDevice
->VfPciBar
[BarIndex
].Length
= 0;
1588 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1591 // Scan all the BARs anyway
1593 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
)Offset
;
1597 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
)Offset
;
1598 if ((Value
& 0x01) != 0) {
1600 // Device I/Os. Impossible
1607 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1609 switch (Value
& 0x07) {
1611 // memory space; anywhere in 32 bit address space
1614 if ((Value
& 0x08) != 0) {
1615 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1617 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1620 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1621 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1626 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1630 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1631 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1637 // memory space; anywhere in 64 bit address space
1640 if ((Value
& 0x08) != 0) {
1641 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1643 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1647 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1648 // is regarded as an extension for the first bar. As a result
1649 // the sizing will be conducted on combined 64 bit value
1650 // Here just store the masked first 32bit value for future size
1653 PciIoDevice
->VfPciBar
[BarIndex
].Length
= Value
& Mask
;
1654 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1656 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1657 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1661 // Increment the offset to point to next DWORD
1665 Status
= VfBarExisted (
1672 if (EFI_ERROR (Status
)) {
1673 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1678 // Fix the length to support some special 64 bit BAR
1680 Value
|= ((UINT32
)-1 << HighBitSet32 (Value
));
1683 // Calculate the size of 64bit bar
1685 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
)OriginalValue
, 32);
1687 PciIoDevice
->VfPciBar
[BarIndex
].Length
= PciIoDevice
->VfPciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
)Value
, 32);
1688 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(PciIoDevice
->VfPciBar
[BarIndex
].Length
)) + 1;
1689 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1694 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1698 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1699 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1708 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1709 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1710 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1712 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1713 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1721 // Check the length again so as to keep compatible with some special bars
1723 if (PciIoDevice
->VfPciBar
[BarIndex
].Length
== 0) {
1724 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1725 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1726 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1730 // Increment number of bar
1736 Parse PCI bar information and fill them into PCI device instance.
1738 @param PciIoDevice Pci device instance.
1739 @param Offset Bar offset.
1740 @param BarIndex Bar index.
1742 @return Next bar offset.
1747 IN PCI_IO_DEVICE
*PciIoDevice
,
1753 UINT32 OriginalValue
;
1760 Status
= BarExisted (
1767 if (EFI_ERROR (Status
)) {
1768 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1769 PciIoDevice
->PciBar
[BarIndex
].Length
= 0;
1770 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1773 // Some devices don't fully comply to PCI spec 2.2. So be to scan all the BARs anyway
1775 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
)Offset
;
1779 PciIoDevice
->PciBar
[BarIndex
].BarTypeFixed
= FALSE
;
1780 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
)Offset
;
1781 if ((Value
& 0x01) != 0) {
1787 if ((Value
& 0xFFFF0000) != 0) {
1791 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo32
;
1792 PciIoDevice
->PciBar
[BarIndex
].Length
= ((~(Value
& Mask
)) + 1);
1793 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1798 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo16
;
1799 PciIoDevice
->PciBar
[BarIndex
].Length
= 0x0000FFFF & ((~(Value
& Mask
)) + 1);
1800 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1804 // Workaround. Some platforms implement IO bar with 0 length
1805 // Need to treat it as no-bar
1807 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1808 PciIoDevice
->PciBar
[BarIndex
].BarType
= (PCI_BAR_TYPE
)0;
1811 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1815 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1817 switch (Value
& 0x07) {
1819 // memory space; anywhere in 32 bit address space
1822 if ((Value
& 0x08) != 0) {
1823 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1825 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1828 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1829 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1831 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1833 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1835 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1841 // memory space; anywhere in 64 bit address space
1844 if ((Value
& 0x08) != 0) {
1845 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1847 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1851 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1852 // is regarded as an extension for the first bar. As a result
1853 // the sizing will be conducted on combined 64 bit value
1854 // Here just store the masked first 32bit value for future size
1857 PciIoDevice
->PciBar
[BarIndex
].Length
= Value
& Mask
;
1858 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1861 // Increment the offset to point to next DWORD
1865 Status
= BarExisted (
1872 if (EFI_ERROR (Status
)) {
1874 // the high 32 bit does not claim any BAR, we need to re-check the low 32 bit BAR again
1876 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1878 // some device implement MMIO bar with 0 length, need to treat it as no-bar
1880 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1886 // Fix the length to support some special 64 bit BAR
1889 DEBUG ((DEBUG_INFO
, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
1892 Value
|= ((UINT32
)(-1) << HighBitSet32 (Value
));
1896 // Calculate the size of 64bit bar
1898 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
)OriginalValue
, 32);
1900 PciIoDevice
->PciBar
[BarIndex
].Length
= PciIoDevice
->PciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
)Value
, 32);
1901 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(PciIoDevice
->PciBar
[BarIndex
].Length
)) + 1;
1902 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1904 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1906 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1908 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1917 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1918 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1919 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1921 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1923 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1925 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1933 // Check the length again so as to keep compatible with some special bars
1935 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1936 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1937 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1938 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1942 // Increment number of bar
1948 This routine is used to initialize the bar of a PCI device.
1950 @param PciIoDevice Pci device instance.
1952 @note It can be called typically when a device is going to be rejected.
1956 InitializePciDevice (
1957 IN PCI_IO_DEVICE
*PciIoDevice
1960 EFI_PCI_IO_PROTOCOL
*PciIo
;
1963 PciIo
= &(PciIoDevice
->PciIo
);
1966 // Put all the resource apertures
1967 // Resource base is set to all ones so as to indicate its resource
1968 // has not been allocated
1970 for (Offset
= 0x10; Offset
<= 0x24; Offset
+= sizeof (UINT32
)) {
1971 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, Offset
, 1, &gAllOne
);
1976 This routine is used to initialize the bar of a PCI-PCI Bridge device.
1978 @param PciIoDevice PCI-PCI bridge device instance.
1983 IN PCI_IO_DEVICE
*PciIoDevice
1986 EFI_PCI_IO_PROTOCOL
*PciIo
;
1988 PciIo
= &(PciIoDevice
->PciIo
);
1991 // Put all the resource apertures including IO16
1992 // Io32, pMem32, pMem64 to quiescent state
1993 // Resource base all ones, Resource limit all zeros
1995 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
1996 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1D, 1, &gAllZero
);
1998 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x20, 1, &gAllOne
);
1999 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x22, 1, &gAllZero
);
2001 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x24, 1, &gAllOne
);
2002 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x26, 1, &gAllZero
);
2004 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllOne
);
2005 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2C, 1, &gAllZero
);
2008 // Don't support use io32 as for now
2010 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x30, 1, &gAllOne
);
2011 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x32, 1, &gAllZero
);
2014 // Force Interrupt line to zero for cards that come up randomly
2016 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
2020 This routine is used to initialize the bar of a PCI Card Bridge device.
2022 @param PciIoDevice PCI Card bridge device.
2027 IN PCI_IO_DEVICE
*PciIoDevice
2030 EFI_PCI_IO_PROTOCOL
*PciIo
;
2032 PciIo
= &(PciIoDevice
->PciIo
);
2035 // Put all the resource apertures including IO16
2036 // Io32, pMem32, pMem64 to quiescent state(
2037 // Resource base all ones, Resource limit all zeros
2039 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x1c, 1, &gAllOne
);
2040 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x20, 1, &gAllZero
);
2042 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x24, 1, &gAllOne
);
2043 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllZero
);
2045 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2c, 1, &gAllOne
);
2046 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x30, 1, &gAllZero
);
2048 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x34, 1, &gAllOne
);
2049 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x38, 1, &gAllZero
);
2052 // Force Interrupt line to zero for cards that come up randomly
2054 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
2058 Authenticate the PCI device by using DeviceSecurityProtocol.
2060 @param PciIoDevice PCI device.
2062 @retval EFI_SUCCESS The device passes the authentication.
2063 @return not EFI_SUCCESS The device failes the authentication or
2064 unexpected error happen during authentication.
2067 AuthenticatePciDevice (
2068 IN PCI_IO_DEVICE
*PciIoDevice
2071 EDKII_DEVICE_IDENTIFIER DeviceIdentifier
;
2074 if (mDeviceSecurityProtocol
!= NULL
) {
2076 // Prepare the parameter
2078 DeviceIdentifier
.Version
= EDKII_DEVICE_IDENTIFIER_REVISION
;
2079 CopyGuid (&DeviceIdentifier
.DeviceType
, &gEdkiiDeviceIdentifierTypePciGuid
);
2080 DeviceIdentifier
.DeviceHandle
= NULL
;
2081 Status
= gBS
->InstallMultipleProtocolInterfaces (
2082 &DeviceIdentifier
.DeviceHandle
,
2083 &gEfiDevicePathProtocolGuid
,
2084 PciIoDevice
->DevicePath
,
2085 &gEdkiiDeviceIdentifierTypePciGuid
,
2086 &PciIoDevice
->PciIo
,
2089 if (EFI_ERROR (Status
)) {
2094 // Do DeviceAuthentication
2096 Status
= mDeviceSecurityProtocol
->DeviceAuthenticate (mDeviceSecurityProtocol
, &DeviceIdentifier
);
2098 // Always uninstall, because they are only for Authentication.
2099 // No need to check return Status.
2101 gBS
->UninstallMultipleProtocolInterfaces (
2102 DeviceIdentifier
.DeviceHandle
,
2103 &gEfiDevicePathProtocolGuid
,
2104 PciIoDevice
->DevicePath
,
2105 &gEdkiiDeviceIdentifierTypePciGuid
,
2106 &PciIoDevice
->PciIo
,
2113 // Device Security Protocol is not found, just return success
2119 Checks if PCI device is Root Bridge.
2121 @param PciIoDevice Instance of PCI device
2123 @retval TRUE Device is Root Bridge
2124 @retval FALSE Device is not Root Bridge
2129 IN PCI_IO_DEVICE
*PciIoDevice
2132 if (PciIoDevice
->Parent
== NULL
) {
2140 Create and initialize general PCI I/O device instance for
2141 PCI device/bridge device/hotplug bridge device.
2143 @param Bridge Parent bridge instance.
2144 @param Pci Input Pci information block.
2145 @param Bus Device Bus NO.
2146 @param Device Device device NO.
2147 @param Func Device func NO.
2149 @return Instance of PCI device. NULL means no instance created.
2154 IN PCI_IO_DEVICE
*Bridge
,
2161 PCI_IO_DEVICE
*PciIoDevice
;
2162 EFI_PCI_IO_PROTOCOL
*PciIo
;
2165 PciIoDevice
= AllocateZeroPool (sizeof (PCI_IO_DEVICE
));
2166 if (PciIoDevice
== NULL
) {
2170 PciIoDevice
->Signature
= PCI_IO_DEVICE_SIGNATURE
;
2171 PciIoDevice
->Handle
= NULL
;
2172 PciIoDevice
->PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
2173 PciIoDevice
->DevicePath
= NULL
;
2174 PciIoDevice
->BusNumber
= Bus
;
2175 PciIoDevice
->DeviceNumber
= Device
;
2176 PciIoDevice
->FunctionNumber
= Func
;
2177 PciIoDevice
->Decodes
= 0;
2179 if (gFullEnumeration
) {
2180 PciIoDevice
->Allocated
= FALSE
;
2182 PciIoDevice
->Allocated
= TRUE
;
2185 PciIoDevice
->Registered
= FALSE
;
2186 PciIoDevice
->Attributes
= 0;
2187 PciIoDevice
->Supports
= 0;
2188 PciIoDevice
->BusOverride
= FALSE
;
2189 PciIoDevice
->AllOpRomProcessed
= FALSE
;
2191 PciIoDevice
->IsPciExp
= FALSE
;
2193 CopyMem (&(PciIoDevice
->Pci
), Pci
, sizeof (PCI_TYPE01
));
2196 // Initialize the PCI I/O instance structure
2198 InitializePciIoInstance (PciIoDevice
);
2199 InitializePciDriverOverrideInstance (PciIoDevice
);
2200 InitializePciLoadFile2 (PciIoDevice
);
2201 PciIo
= &PciIoDevice
->PciIo
;
2204 // Create a device path for this PCI device and store it into its private data
2206 CreatePciDevicePath (
2212 // Detect if PCI Express Device
2214 PciIoDevice
->PciExpressCapabilityOffset
= 0;
2215 Status
= LocateCapabilityRegBlock (
2217 EFI_PCI_CAPABILITY_ID_PCIEXP
,
2218 &PciIoDevice
->PciExpressCapabilityOffset
,
2221 if (!EFI_ERROR (Status
)) {
2222 PciIoDevice
->IsPciExp
= TRUE
;
2226 // Now we can do the authentication check for the device.
2228 Status
= AuthenticatePciDevice (PciIoDevice
);
2230 // If authentication fails, skip this device.
2232 if (EFI_ERROR (Status
)) {
2233 if (PciIoDevice
->DevicePath
!= NULL
) {
2234 FreePool (PciIoDevice
->DevicePath
);
2237 FreePool (PciIoDevice
);
2242 // Check if device's parent is not Root Bridge
2244 if (PcdGetBool (PcdAriSupport
) && !IsRootBridge (Bridge
)) {
2246 // Check if the device is an ARI device.
2248 Status
= LocatePciExpressCapabilityRegBlock (
2250 EFI_PCIE_CAPABILITY_ID_ARI
,
2251 &PciIoDevice
->AriCapabilityOffset
,
2254 if (!EFI_ERROR (Status
)) {
2256 // We need to enable ARI feature before calculate BusReservation,
2257 // because FirstVFOffset and VFStride may change after that.
2259 EFI_PCI_IO_PROTOCOL
*ParentPciIo
;
2263 // Check if its parent supports ARI forwarding.
2265 ParentPciIo
= &Bridge
->PciIo
;
2266 ParentPciIo
->Pci
.Read (
2268 EfiPciIoWidthUint32
,
2269 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET
,
2273 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING
) != 0) {
2275 // ARI forward support in bridge, so enable it.
2277 ParentPciIo
->Pci
.Read (
2279 EfiPciIoWidthUint32
,
2280 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2284 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
) == 0) {
2285 Data32
|= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
;
2286 ParentPciIo
->Pci
.Write (
2288 EfiPciIoWidthUint32
,
2289 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2295 " ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",
2297 Bridge
->DeviceNumber
,
2298 Bridge
->FunctionNumber
2303 DEBUG ((DEBUG_INFO
, " ARI: CapOffset = 0x%x\n", PciIoDevice
->AriCapabilityOffset
));
2308 // Initialization for SR-IOV
2311 if (PcdGetBool (PcdSrIovSupport
)) {
2312 Status
= LocatePciExpressCapabilityRegBlock (
2314 EFI_PCIE_CAPABILITY_ID_SRIOV
,
2315 &PciIoDevice
->SrIovCapabilityOffset
,
2318 if (!EFI_ERROR (Status
)) {
2319 UINT32 SupportedPageSize
;
2321 UINT16 FirstVFOffset
;
2327 // If the SR-IOV device is an ARI device, then Set ARI Capable Hierarchy for the device.
2329 if (PcdGetBool (PcdAriSupport
) && (PciIoDevice
->AriCapabilityOffset
!= 0)) {
2332 EfiPciIoWidthUint16
,
2333 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2337 Data16
|= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY
;
2340 EfiPciIoWidthUint16
,
2341 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2348 // Calculate SystemPageSize
2353 EfiPciIoWidthUint32
,
2354 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE
,
2358 PciIoDevice
->SystemPageSize
= (PcdGet32 (PcdSrIovSystemPageSize
) & SupportedPageSize
);
2359 ASSERT (PciIoDevice
->SystemPageSize
!= 0);
2363 EfiPciIoWidthUint32
,
2364 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE
,
2366 &PciIoDevice
->SystemPageSize
2369 // Adjust SystemPageSize for Alignment usage later
2371 PciIoDevice
->SystemPageSize
<<= 12;
2374 // Calculate BusReservation for PCI IOV
2378 // Read First FirstVFOffset, InitialVFs, and VFStride
2382 EfiPciIoWidthUint16
,
2383 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF
,
2389 EfiPciIoWidthUint16
,
2390 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS
,
2392 &PciIoDevice
->InitialVFs
2396 EfiPciIoWidthUint16
,
2397 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE
,
2404 PFRid
= EFI_PCI_RID (Bus
, Device
, Func
);
2405 LastVF
= PFRid
+ FirstVFOffset
+ (PciIoDevice
->InitialVFs
- 1) * VFStride
;
2408 // Calculate ReservedBusNum for this PF
2410 PciIoDevice
->ReservedBusNum
= (UINT16
)(EFI_PCI_BUS_OF_RID (LastVF
) - Bus
+ 1);
2414 " SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x; FirstVFOffset = 0x%x;\n",
2416 PciIoDevice
->SystemPageSize
>> 12,
2421 " InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",
2422 PciIoDevice
->InitialVFs
,
2423 PciIoDevice
->ReservedBusNum
,
2424 PciIoDevice
->SrIovCapabilityOffset
2429 if (PcdGetBool (PcdMrIovSupport
)) {
2430 Status
= LocatePciExpressCapabilityRegBlock (
2432 EFI_PCIE_CAPABILITY_ID_MRIOV
,
2433 &PciIoDevice
->MrIovCapabilityOffset
,
2436 if (!EFI_ERROR (Status
)) {
2437 DEBUG ((DEBUG_INFO
, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice
->MrIovCapabilityOffset
));
2441 PciIoDevice
->ResizableBarOffset
= 0;
2442 if (PcdGetBool (PcdPcieResizableBarSupport
)) {
2443 Status
= LocatePciExpressCapabilityRegBlock (
2445 PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID
,
2446 &PciIoDevice
->ResizableBarOffset
,
2449 if (!EFI_ERROR (Status
)) {
2450 PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl
;
2452 Offset
= PciIoDevice
->ResizableBarOffset
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
)
2453 + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY
),
2458 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL
),
2459 &ResizableBarControl
2461 PciIoDevice
->ResizableBarNumber
= ResizableBarControl
.Bits
.ResizableBarNumber
;
2462 PciProgramResizableBar (PciIoDevice
, PciResizableBarMax
);
2467 // Initialize the reserved resource list
2469 InitializeListHead (&PciIoDevice
->ReservedResourceList
);
2472 // Initialize the driver list
2474 InitializeListHead (&PciIoDevice
->OptionRomDriverList
);
2477 // Initialize the child list
2479 InitializeListHead (&PciIoDevice
->ChildList
);
2485 This routine is used to enumerate entire pci bus system
2486 in a given platform.
2488 It is only called on the second start on the same Root Bridge.
2490 @param Controller Parent bridge handler.
2492 @retval EFI_SUCCESS PCI enumeration finished successfully.
2493 @retval other Some error occurred when enumerating the pci bus system.
2497 PciEnumeratorLight (
2498 IN EFI_HANDLE Controller
2502 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2503 PCI_IO_DEVICE
*RootBridgeDev
;
2506 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2509 MaxBus
= PCI_MAX_BUS
;
2513 // If this root bridge has been already enumerated, then return successfully
2515 if (GetRootBridgeByHandle (Controller
) != NULL
) {
2520 // Open pci root bridge io protocol
2522 Status
= gBS
->OpenProtocol (
2524 &gEfiPciRootBridgeIoProtocolGuid
,
2525 (VOID
**)&PciRootBridgeIo
,
2526 gPciBusDriverBinding
.DriverBindingHandle
,
2528 EFI_OPEN_PROTOCOL_BY_DRIVER
2530 if (EFI_ERROR (Status
) && (Status
!= EFI_ALREADY_STARTED
)) {
2534 Status
= PciRootBridgeIo
->Configuration (PciRootBridgeIo
, (VOID
**)&Descriptors
);
2536 if (EFI_ERROR (Status
)) {
2540 while (PciGetBusRange (&Descriptors
, &MinBus
, &MaxBus
, NULL
) == EFI_SUCCESS
) {
2542 // Create a device node for root bridge device with a NULL host bridge controller handle
2544 RootBridgeDev
= CreateRootBridge (Controller
);
2546 if (RootBridgeDev
== NULL
) {
2552 // Record the root bridge-io protocol
2554 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2556 Status
= PciPciDeviceInfoCollector (
2561 if (!EFI_ERROR (Status
)) {
2563 // Remove those PCI devices which are rejected when full enumeration
2565 RemoveRejectedPciDevices (RootBridgeDev
->Handle
, RootBridgeDev
);
2568 // Process option rom light
2570 ProcessOptionRomLight (RootBridgeDev
);
2573 // Determine attributes for all devices under this root bridge
2575 DetermineDeviceAttribute (RootBridgeDev
);
2578 // If successfully, insert the node into device pool
2580 InsertRootBridge (RootBridgeDev
);
2583 // If unsuccessfully, destroy the entire node
2585 DestroyRootBridge (RootBridgeDev
);
2595 Get bus range from PCI resource descriptor list.
2597 @param Descriptors A pointer to the address space descriptor.
2598 @param MinBus The min bus returned.
2599 @param MaxBus The max bus returned.
2600 @param BusRange The bus range returned.
2602 @retval EFI_SUCCESS Successfully got bus range.
2603 @retval EFI_NOT_FOUND Can not find the specific bus.
2608 IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
2611 OUT UINT16
*BusRange
2614 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
2615 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
2616 if (MinBus
!= NULL
) {
2617 *MinBus
= (UINT16
)(*Descriptors
)->AddrRangeMin
;
2620 if (MaxBus
!= NULL
) {
2621 *MaxBus
= (UINT16
)(*Descriptors
)->AddrRangeMax
;
2624 if (BusRange
!= NULL
) {
2625 *BusRange
= (UINT16
)(*Descriptors
)->AddrLen
;
2634 return EFI_NOT_FOUND
;
2638 This routine can be used to start the root bridge.
2640 @param RootBridgeDev Pci device instance.
2642 @retval EFI_SUCCESS This device started.
2643 @retval other Failed to get PCI Root Bridge I/O protocol.
2647 StartManagingRootBridge (
2648 IN PCI_IO_DEVICE
*RootBridgeDev
2651 EFI_HANDLE RootBridgeHandle
;
2653 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2656 // Get the root bridge handle
2658 RootBridgeHandle
= RootBridgeDev
->Handle
;
2659 PciRootBridgeIo
= NULL
;
2662 // Get the pci root bridge io protocol
2664 Status
= gBS
->OpenProtocol (
2666 &gEfiPciRootBridgeIoProtocolGuid
,
2667 (VOID
**)&PciRootBridgeIo
,
2668 gPciBusDriverBinding
.DriverBindingHandle
,
2670 EFI_OPEN_PROTOCOL_BY_DRIVER
2673 if (EFI_ERROR (Status
) && (Status
!= EFI_ALREADY_STARTED
)) {
2678 // Store the PciRootBridgeIo protocol into root bridge private data
2680 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2686 This routine can be used to check whether a PCI device should be rejected when light enumeration.
2688 @param PciIoDevice Pci device instance.
2690 @retval TRUE This device should be rejected.
2691 @retval FALSE This device shouldn't be rejected.
2695 IsPciDeviceRejected (
2696 IN PCI_IO_DEVICE
*PciIoDevice
2706 // PPB should be skip!
2708 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
2712 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
2714 // Only test base registers for P2C
2716 for (BarOffset
= 0x1C; BarOffset
<= 0x38; BarOffset
+= 2 * sizeof (UINT32
)) {
2717 Mask
= (BarOffset
< 0x2C) ? 0xFFFFF000 : 0xFFFFFFFC;
2718 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2719 if (EFI_ERROR (Status
)) {
2723 TestValue
= TestValue
& Mask
;
2724 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2726 // The bar isn't programed, so it should be rejected
2735 for (BarOffset
= 0x14; BarOffset
<= 0x24; BarOffset
+= sizeof (UINT32
)) {
2739 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2740 if (EFI_ERROR (Status
)) {
2744 if ((TestValue
& 0x01) != 0) {
2749 TestValue
= TestValue
& Mask
;
2750 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2758 TestValue
= TestValue
& Mask
;
2760 if ((TestValue
& 0x07) == 0x04) {
2764 BarOffset
+= sizeof (UINT32
);
2765 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2767 // Test its high 32-Bit BAR
2769 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2770 if (TestValue
== OldValue
) {
2778 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2789 Reset all bus number from specific bridge.
2791 @param Bridge Parent specific bridge.
2792 @param StartBusNumber Start bus number.
2796 ResetAllPpbBusNumber (
2797 IN PCI_IO_DEVICE
*Bridge
,
2798 IN UINT8 StartBusNumber
2808 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2810 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
2812 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2813 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2815 // Check to see whether a pci device is present
2817 Status
= PciDevicePresent (
2825 if (EFI_ERROR (Status
) && (Func
== 0)) {
2827 // go to next device if there is no Function 0
2832 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
))) {
2834 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x18);
2835 Status
= PciRootBridgeIo
->Pci
.Read (
2842 SecondaryBus
= (UINT8
)(Register
>> 8);
2844 if (SecondaryBus
!= 0) {
2845 ResetAllPpbBusNumber (Bridge
, SecondaryBus
);
2849 // Reset register 18h, 19h, 1Ah on PCI Bridge
2851 Register
&= 0xFF000000;
2852 Status
= PciRootBridgeIo
->Pci
.Write (
2861 if ((Func
== 0) && !IS_PCI_MULTI_FUNC (&Pci
)) {
2863 // Skip sub functions, this is not a multi function device
2865 Func
= PCI_MAX_FUNC
;