2 PCI emumeration support functions implementation for PCI Bus module.
4 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 This routine is used to check whether the pci device is present.
20 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
21 @param Pci Output buffer for PCI device configuration space.
22 @param Bus PCI bus NO.
23 @param Device PCI device NO.
24 @param Func PCI Func NO.
26 @retval EFI_NOT_FOUND PCI device not present.
27 @retval EFI_SUCCESS PCI device is found.
32 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
,
43 // Create PCI address map in terms of Bus, Device and Func
45 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
48 // Read the Vendor ID register
50 Status
= PciRootBridgeIo
->Pci
.Read (
58 if (!EFI_ERROR (Status
) && (Pci
->Hdr
).VendorId
!= 0xffff) {
60 // Read the entire config header for the device
62 Status
= PciRootBridgeIo
->Pci
.Read (
66 sizeof (PCI_TYPE00
) / sizeof (UINT32
),
77 Collect all the resource information under this root bridge.
79 A database that records all the information about pci device subject to this
80 root bridge will then be created.
82 @param Bridge Parent bridge instance.
83 @param StartBusNumber Bus number of begining.
85 @retval EFI_SUCCESS PCI device is found.
86 @retval other Some error occurred when reading PCI bridge information.
90 PciPciDeviceInfoCollector (
91 IN PCI_IO_DEVICE
*Bridge
,
92 IN UINT8 StartBusNumber
100 PCI_IO_DEVICE
*PciIoDevice
;
101 EFI_PCI_IO_PROTOCOL
*PciIo
;
103 Status
= EFI_SUCCESS
;
106 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
108 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
111 // Check to see whether PCI device is present
113 Status
= PciDevicePresent (
114 Bridge
->PciRootBridgeIo
,
116 (UINT8
) StartBusNumber
,
120 if (!EFI_ERROR (Status
)) {
123 // Call back to host bridge function
125 PreprocessController (Bridge
, (UINT8
) StartBusNumber
, Device
, Func
, EfiPciBeforeResourceCollection
);
128 // Collect all the information about the PCI device discovered
130 Status
= PciSearchDevice (
133 (UINT8
) StartBusNumber
,
140 // Recursively scan PCI busses on the other side of PCI-PCI bridges
143 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
) || IS_CARDBUS_BRIDGE (&Pci
))) {
146 // If it is PPB, we need to get the secondary bus to continue the enumeration
148 PciIo
= &(PciIoDevice
->PciIo
);
150 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
, 1, &SecBus
);
152 if (EFI_ERROR (Status
)) {
157 // Get resource padding for PPB
159 GetResourcePaddingPpb (PciIoDevice
);
162 // Deep enumerate the next level bus
164 Status
= PciPciDeviceInfoCollector (
171 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
174 // Skip sub functions, this is not a multi function device
187 Seach required device and create PCI device instance.
189 @param Bridge Parent bridge instance.
190 @param Pci Input PCI device information block.
191 @param Bus PCI bus NO.
192 @param Device PCI device NO.
193 @param Func PCI func NO.
194 @param PciDevice Output of searched PCI device instance.
196 @retval EFI_SUCCESS Successfully created PCI device instance.
197 @retval EFI_OUT_OF_RESOURCES Cannot get PCI device information.
202 IN PCI_IO_DEVICE
*Bridge
,
207 OUT PCI_IO_DEVICE
**PciDevice
210 PCI_IO_DEVICE
*PciIoDevice
;
214 if (!IS_PCI_BRIDGE (Pci
)) {
216 if (IS_CARDBUS_BRIDGE (Pci
)) {
217 PciIoDevice
= GatherP2CInfo (
224 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
225 InitializeP2C (PciIoDevice
);
230 // Create private data for Pci Device
232 PciIoDevice
= GatherDeviceInfo (
245 // Create private data for PPB
247 PciIoDevice
= GatherPpbInfo (
256 // Special initialization for PPB including making the PPB quiet
258 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
259 InitializePpb (PciIoDevice
);
263 if (PciIoDevice
== NULL
) {
264 return EFI_OUT_OF_RESOURCES
;
268 // Update the bar information for this PCI device so as to support some specific device
270 UpdatePciInfo (PciIoDevice
);
272 if (PciIoDevice
->DevicePath
== NULL
) {
273 return EFI_OUT_OF_RESOURCES
;
277 // Detect this function has option rom
279 if (gFullEnumeration
) {
281 if (!IS_CARDBUS_BRIDGE (Pci
)) {
283 GetOpRomInfo (PciIoDevice
);
287 ResetPowerManagementFeature (PciIoDevice
);
292 // Insert it into a global tree for future reference
294 InsertPciDevice (Bridge
, PciIoDevice
);
297 // Determine PCI device attributes
300 if (PciDevice
!= NULL
) {
301 *PciDevice
= PciIoDevice
;
308 Create PCI device instance for PCI device.
310 @param Bridge Parent bridge instance.
311 @param Pci Input PCI device information block.
312 @param Bus PCI device Bus NO.
313 @param Device PCI device Device NO.
314 @param Func PCI device's func NO.
316 @return Created PCI device instance.
321 IN PCI_IO_DEVICE
*Bridge
,
330 PCI_IO_DEVICE
*PciIoDevice
;
332 PciIoDevice
= CreatePciIoDevice (
340 if (PciIoDevice
== NULL
) {
345 // Create a device path for this PCI device and store it into its private data
347 CreatePciDevicePath (
353 // If it is a full enumeration, disconnect the device in advance
355 if (gFullEnumeration
) {
357 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
362 // Start to parse the bars
364 for (Offset
= 0x10, BarIndex
= 0; Offset
<= 0x24 && BarIndex
< PCI_MAX_BAR
; BarIndex
++) {
365 Offset
= PciParseBar (PciIoDevice
, Offset
, BarIndex
);
369 // Parse the SR-IOV VF bars
371 if (PcdGetBool (PcdSrIovSupport
) && PciIoDevice
->SrIovCapabilityOffset
!= 0) {
372 for (Offset
= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0
, BarIndex
= 0;
373 Offset
<= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5
;
376 ASSERT (BarIndex
< PCI_MAX_BAR
);
377 Offset
= PciIovParseVfBar (PciIoDevice
, Offset
, BarIndex
);
384 Create PCI device instance for PCI-PCI bridge.
386 @param Bridge Parent bridge instance.
387 @param Pci Input PCI device information block.
388 @param Bus PCI device Bus NO.
389 @param Device PCI device Device NO.
390 @param Func PCI device's func NO.
392 @return Created PCI device instance.
397 IN PCI_IO_DEVICE
*Bridge
,
404 PCI_IO_DEVICE
*PciIoDevice
;
407 EFI_PCI_IO_PROTOCOL
*PciIo
;
410 PciIoDevice
= CreatePciIoDevice (
418 if (PciIoDevice
== NULL
) {
423 // Create a device path for this PCI device and store it into its private data
425 CreatePciDevicePath (
430 if (gFullEnumeration
) {
431 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
434 // Initalize the bridge control register
436 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED
);
441 // PPB can have two BARs
443 if (PciParseBar (PciIoDevice
, 0x10, PPB_BAR_0
) == 0x14) {
447 PciParseBar (PciIoDevice
, 0x14, PPB_BAR_1
);
450 PciIo
= &PciIoDevice
->PciIo
;
453 // Test whether it support 32 decode or not
455 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
456 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
457 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
458 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
461 if ((Value
& 0x01) != 0) {
462 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
464 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO16_DECODE_SUPPORTED
;
469 // if PcdPciBridgeIoAlignmentProbe is TRUE, PCI bus driver probes
470 // PCI bridge supporting non-stardard I/O window alignment less than 4K.
473 PciIoDevice
->BridgeIoAlignment
= 0xFFF;
474 if (FeaturePcdGet (PcdPciBridgeIoAlignmentProbe
)) {
476 // Check any bits of bit 3-1 of I/O Base Register are writable.
477 // if so, it is assumed non-stardard I/O window alignment is supported by this bridge.
478 // Per spec, bit 3-1 of I/O Base Register are reserved bits, so its content can't be assumed.
480 Value
= (UINT8
)(Temp
^ (BIT3
| BIT2
| BIT1
));
481 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
482 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
483 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
484 Value
= (UINT8
)((Value
^ Temp
) & (BIT3
| BIT2
| BIT1
));
487 PciIoDevice
->BridgeIoAlignment
= 0x7FF;
490 PciIoDevice
->BridgeIoAlignment
= 0x3FF;
492 case BIT3
| BIT2
| BIT1
:
493 PciIoDevice
->BridgeIoAlignment
= 0x1FF;
498 Status
= BarExisted (
506 // Test if it supports 64 memory or not
508 if (!EFI_ERROR (Status
)) {
510 Status
= BarExisted (
517 if (!EFI_ERROR (Status
)) {
518 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
519 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED
;
521 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
526 // Memory 32 code is required for ppb
528 PciIoDevice
->Decodes
|= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
;
530 GetResourcePaddingPpb (PciIoDevice
);
537 Create PCI device instance for PCI Card bridge device.
539 @param Bridge Parent bridge instance.
540 @param Pci Input PCI device information block.
541 @param Bus PCI device Bus NO.
542 @param Device PCI device Device NO.
543 @param Func PCI device's func NO.
545 @return Created PCI device instance.
550 IN PCI_IO_DEVICE
*Bridge
,
557 PCI_IO_DEVICE
*PciIoDevice
;
559 PciIoDevice
= CreatePciIoDevice (
567 if (PciIoDevice
== NULL
) {
572 // Create a device path for this PCI device and store it into its private data
574 CreatePciDevicePath (
579 if (gFullEnumeration
) {
580 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
583 // Initalize the bridge control register
585 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED
);
589 // P2C only has one bar that is in 0x10
591 PciParseBar (PciIoDevice
, 0x10, P2C_BAR_0
);
594 // Read PciBar information from the bar register
596 GetBackPcCardBar (PciIoDevice
);
597 PciIoDevice
->Decodes
= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
|
598 EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
|
599 EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
605 Create device path for pci deivce.
607 @param ParentDevicePath Parent bridge's path.
608 @param PciIoDevice Pci device instance.
610 @return Device path protocol instance for specific pci device.
613 EFI_DEVICE_PATH_PROTOCOL
*
614 CreatePciDevicePath (
615 IN EFI_DEVICE_PATH_PROTOCOL
*ParentDevicePath
,
616 IN PCI_IO_DEVICE
*PciIoDevice
620 PCI_DEVICE_PATH PciNode
;
623 // Create PCI device path
625 PciNode
.Header
.Type
= HARDWARE_DEVICE_PATH
;
626 PciNode
.Header
.SubType
= HW_PCI_DP
;
627 SetDevicePathNodeLength (&PciNode
.Header
, sizeof (PciNode
));
629 PciNode
.Device
= PciIoDevice
->DeviceNumber
;
630 PciNode
.Function
= PciIoDevice
->FunctionNumber
;
631 PciIoDevice
->DevicePath
= AppendDevicePathNode (ParentDevicePath
, &PciNode
.Header
);
633 return PciIoDevice
->DevicePath
;
637 Check whether the PCI IOV VF bar is existed or not.
639 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
640 @param Offset The offset.
641 @param BarLengthValue The bar length value returned.
642 @param OriginalBarValue The original bar value returned.
644 @retval EFI_NOT_FOUND The bar doesn't exist.
645 @retval EFI_SUCCESS The bar exist.
650 IN PCI_IO_DEVICE
*PciIoDevice
,
652 OUT UINT32
*BarLengthValue
,
653 OUT UINT32
*OriginalBarValue
656 EFI_PCI_IO_PROTOCOL
*PciIo
;
657 UINT32 OriginalValue
;
662 // Ensure it is called properly
664 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
665 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
666 return EFI_NOT_FOUND
;
669 PciIo
= &PciIoDevice
->PciIo
;
672 // Preserve the original value
675 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
678 // Raise TPL to high level to disable timer interrupt while the BAR is probed
680 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
682 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &gAllOne
);
683 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &Value
);
686 // Write back the original value
688 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
691 // Restore TPL to its original level
693 gBS
->RestoreTPL (OldTpl
);
695 if (BarLengthValue
!= NULL
) {
696 *BarLengthValue
= Value
;
699 if (OriginalBarValue
!= NULL
) {
700 *OriginalBarValue
= OriginalValue
;
704 return EFI_NOT_FOUND
;
711 Check whether the bar is existed or not.
713 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
714 @param Offset The offset.
715 @param BarLengthValue The bar length value returned.
716 @param OriginalBarValue The original bar value returned.
718 @retval EFI_NOT_FOUND The bar doesn't exist.
719 @retval EFI_SUCCESS The bar exist.
724 IN PCI_IO_DEVICE
*PciIoDevice
,
726 OUT UINT32
*BarLengthValue
,
727 OUT UINT32
*OriginalBarValue
730 EFI_PCI_IO_PROTOCOL
*PciIo
;
731 UINT32 OriginalValue
;
735 PciIo
= &PciIoDevice
->PciIo
;
738 // Preserve the original value
740 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
743 // Raise TPL to high level to disable timer interrupt while the BAR is probed
745 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
747 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &gAllOne
);
748 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &Value
);
751 // Write back the original value
753 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
756 // Restore TPL to its original level
758 gBS
->RestoreTPL (OldTpl
);
760 if (BarLengthValue
!= NULL
) {
761 *BarLengthValue
= Value
;
764 if (OriginalBarValue
!= NULL
) {
765 *OriginalBarValue
= OriginalValue
;
769 return EFI_NOT_FOUND
;
776 Test whether the device can support given attributes.
778 @param PciIoDevice Pci device instance.
779 @param Command Input command register value, and
780 returned supported register value.
781 @param BridgeControl Inout bridge control value for PPB or P2C, and
782 returned supported bridge control value.
783 @param OldCommand Returned and stored old command register offset.
784 @param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.
788 PciTestSupportedAttribute (
789 IN PCI_IO_DEVICE
*PciIoDevice
,
790 IN OUT UINT16
*Command
,
791 IN OUT UINT16
*BridgeControl
,
792 OUT UINT16
*OldCommand
,
793 OUT UINT16
*OldBridgeControl
799 // Preserve the original value
801 PCI_READ_COMMAND_REGISTER (PciIoDevice
, OldCommand
);
804 // Raise TPL to high level to disable timer interrupt while the BAR is probed
806 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
808 PCI_SET_COMMAND_REGISTER (PciIoDevice
, *Command
);
809 PCI_READ_COMMAND_REGISTER (PciIoDevice
, Command
);
812 // Write back the original value
814 PCI_SET_COMMAND_REGISTER (PciIoDevice
, *OldCommand
);
817 // Restore TPL to its original level
819 gBS
->RestoreTPL (OldTpl
);
821 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
824 // Preserve the original value
826 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, OldBridgeControl
);
829 // Raise TPL to high level to disable timer interrupt while the BAR is probed
831 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
833 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *BridgeControl
);
834 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, BridgeControl
);
837 // Write back the original value
839 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *OldBridgeControl
);
842 // Restore TPL to its original level
844 gBS
->RestoreTPL (OldTpl
);
847 *OldBridgeControl
= 0;
853 Set the supported or current attributes of a PCI device.
855 @param PciIoDevice Structure pointer for PCI device.
856 @param Command Command register value.
857 @param BridgeControl Bridge control value for PPB or P2C.
858 @param Option Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.
862 PciSetDeviceAttribute (
863 IN PCI_IO_DEVICE
*PciIoDevice
,
865 IN UINT16 BridgeControl
,
873 if ((Command
& EFI_PCI_COMMAND_IO_SPACE
) != 0) {
874 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IO
;
877 if ((Command
& EFI_PCI_COMMAND_MEMORY_SPACE
) != 0) {
878 Attributes
|= EFI_PCI_IO_ATTRIBUTE_MEMORY
;
881 if ((Command
& EFI_PCI_COMMAND_BUS_MASTER
) != 0) {
882 Attributes
|= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
;
885 if ((Command
& EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
) != 0) {
886 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
889 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_ISA
) != 0) {
890 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_IO
;
893 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA
) != 0) {
894 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO
;
895 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
896 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
899 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA_16
) != 0) {
900 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
;
901 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
;
904 if (Option
== EFI_SET_SUPPORTS
) {
906 Attributes
|= EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE
|
907 EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED
|
908 EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE
|
909 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
910 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
911 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
;
913 if ((Attributes
& EFI_PCI_IO_ATTRIBUTE_IO
) != 0) {
914 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO
;
915 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_IO
;
918 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
920 // For bridge, it should support IDE attributes
922 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
923 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
926 if (IS_PCI_IDE (&PciIoDevice
->Pci
)) {
927 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
928 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
931 if (IS_PCI_VGA (&PciIoDevice
->Pci
)) {
932 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
933 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO
;
937 PciIoDevice
->Supports
= Attributes
;
938 PciIoDevice
->Supports
&= ( (PciIoDevice
->Parent
->Supports
) | \
939 EFI_PCI_IO_ATTRIBUTE_IO
| EFI_PCI_IO_ATTRIBUTE_MEMORY
| \
940 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
);
943 PciIoDevice
->Attributes
= Attributes
;
948 Determine if the device can support Fast Back to Back attribute.
950 @param PciIoDevice Pci device instance.
951 @param StatusIndex Status register value.
953 @retval EFI_SUCCESS This device support Fast Back to Back attribute.
954 @retval EFI_UNSUPPORTED This device doesn't support Fast Back to Back attribute.
958 GetFastBackToBackSupport (
959 IN PCI_IO_DEVICE
*PciIoDevice
,
963 EFI_PCI_IO_PROTOCOL
*PciIo
;
965 UINT32 StatusRegister
;
968 // Read the status register
970 PciIo
= &PciIoDevice
->PciIo
;
971 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint16
, StatusIndex
, 1, &StatusRegister
);
972 if (EFI_ERROR (Status
)) {
973 return EFI_UNSUPPORTED
;
977 // Check the Fast B2B bit
979 if ((StatusRegister
& EFI_PCI_FAST_BACK_TO_BACK_CAPABLE
) != 0) {
982 return EFI_UNSUPPORTED
;
987 Process the option ROM for all the children of the specified parent PCI device.
988 It can only be used after the first full Option ROM process.
990 @param PciIoDevice Pci device instance.
994 ProcessOptionRomLight (
995 IN PCI_IO_DEVICE
*PciIoDevice
999 LIST_ENTRY
*CurrentLink
;
1002 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1004 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1005 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1007 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1009 if (!IsListEmpty (&Temp
->ChildList
)) {
1010 ProcessOptionRomLight (Temp
);
1013 PciRomGetImageMapping (Temp
);
1016 // The OpRom has already been processed in the first round
1018 Temp
->AllOpRomProcessed
= TRUE
;
1020 CurrentLink
= CurrentLink
->ForwardLink
;
1025 Determine the related attributes of all devices under a Root Bridge.
1027 @param PciIoDevice PCI device instance.
1031 DetermineDeviceAttribute (
1032 IN PCI_IO_DEVICE
*PciIoDevice
1036 UINT16 BridgeControl
;
1038 UINT16 OldBridgeControl
;
1039 BOOLEAN FastB2BSupport
;
1040 PCI_IO_DEVICE
*Temp
;
1041 LIST_ENTRY
*CurrentLink
;
1045 // For Root Bridge, just copy it by RootBridgeIo proctocol
1046 // so as to keep consistent with the actual attribute
1048 if (PciIoDevice
->Parent
== NULL
) {
1049 Status
= PciIoDevice
->PciRootBridgeIo
->GetAttributes (
1050 PciIoDevice
->PciRootBridgeIo
,
1051 &PciIoDevice
->Supports
,
1052 &PciIoDevice
->Attributes
1054 if (EFI_ERROR (Status
)) {
1060 // Set the attributes to be checked for common PCI devices and PPB or P2C
1061 // Since some devices only support part of them, it is better to set the
1062 // attribute according to its command or bridge control register
1064 Command
= EFI_PCI_COMMAND_IO_SPACE
|
1065 EFI_PCI_COMMAND_MEMORY_SPACE
|
1066 EFI_PCI_COMMAND_BUS_MASTER
|
1067 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
;
1069 BridgeControl
= EFI_PCI_BRIDGE_CONTROL_ISA
| EFI_PCI_BRIDGE_CONTROL_VGA
| EFI_PCI_BRIDGE_CONTROL_VGA_16
;
1072 // Test whether the device can support attributes above
1074 PciTestSupportedAttribute (PciIoDevice
, &Command
, &BridgeControl
, &OldCommand
, &OldBridgeControl
);
1077 // Set the supported attributes for specified PCI device
1079 PciSetDeviceAttribute (PciIoDevice
, Command
, BridgeControl
, EFI_SET_SUPPORTS
);
1082 // Set the current attributes for specified PCI device
1084 PciSetDeviceAttribute (PciIoDevice
, OldCommand
, OldBridgeControl
, EFI_SET_ATTRIBUTES
);
1087 // Enable other supported attributes but not defined in PCI_IO_PROTOCOL
1089 PCI_ENABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE
);
1092 FastB2BSupport
= TRUE
;
1095 // P2C can not support FB2B on the secondary side
1097 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
1098 FastB2BSupport
= FALSE
;
1102 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1104 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1105 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1107 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1108 Status
= DetermineDeviceAttribute (Temp
);
1109 if (EFI_ERROR (Status
)) {
1113 // Detect Fast Bact to Bact support for the device under the bridge
1115 Status
= GetFastBackToBackSupport (Temp
, PCI_PRIMARY_STATUS_OFFSET
);
1116 if (FastB2BSupport
&& EFI_ERROR (Status
)) {
1117 FastB2BSupport
= FALSE
;
1120 CurrentLink
= CurrentLink
->ForwardLink
;
1123 // Set or clear Fast Back to Back bit for the whole bridge
1125 if (!IsListEmpty (&PciIoDevice
->ChildList
)) {
1127 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
1129 Status
= GetFastBackToBackSupport (PciIoDevice
, PCI_BRIDGE_STATUS_REGISTER_OFFSET
);
1131 if (EFI_ERROR (Status
) || (!FastB2BSupport
)) {
1132 FastB2BSupport
= FALSE
;
1133 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1135 PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1139 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1140 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1141 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1142 if (FastB2BSupport
) {
1143 PCI_ENABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1145 PCI_DISABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1148 CurrentLink
= CurrentLink
->ForwardLink
;
1152 // End for IsListEmpty
1158 This routine is used to update the bar information for those incompatible PCI device.
1160 @param PciIoDevice Input Pci device instance. Output Pci device instance with updated
1163 @retval EFI_SUCCESS Successfully updated bar information.
1164 @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.
1169 IN OUT PCI_IO_DEVICE
*PciIoDevice
1176 VOID
*Configuration
;
1177 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1179 Configuration
= NULL
;
1180 Status
= EFI_SUCCESS
;
1182 if (gEfiIncompatiblePciDeviceSupport
== NULL
) {
1184 // It can only be supported after the Incompatible PCI Device
1185 // Support Protocol has been installed
1187 Status
= gBS
->LocateProtocol (
1188 &gEfiIncompatiblePciDeviceSupportProtocolGuid
,
1190 (VOID
**) &gEfiIncompatiblePciDeviceSupport
1193 if (Status
== EFI_SUCCESS
) {
1195 // Check whether the device belongs to incompatible devices from protocol or not
1196 // If it is , then get its special requirement in the ACPI table
1198 Status
= gEfiIncompatiblePciDeviceSupport
->CheckDevice (
1199 gEfiIncompatiblePciDeviceSupport
,
1200 PciIoDevice
->Pci
.Hdr
.VendorId
,
1201 PciIoDevice
->Pci
.Hdr
.DeviceId
,
1202 PciIoDevice
->Pci
.Hdr
.RevisionID
,
1203 PciIoDevice
->Pci
.Device
.SubsystemVendorID
,
1204 PciIoDevice
->Pci
.Device
.SubsystemID
,
1210 if (EFI_ERROR (Status
) || Configuration
== NULL
) {
1211 return EFI_UNSUPPORTED
;
1215 // Update PCI device information from the ACPI table
1217 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Configuration
;
1219 while (Ptr
->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
1221 if (Ptr
->Desc
!= ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
1223 // The format is not support
1228 BarIndex
= (UINTN
) Ptr
->AddrTranslationOffset
;
1229 BarEndIndex
= BarIndex
;
1232 // Update all the bars in the device
1234 if (BarIndex
== PCI_BAR_ALL
) {
1236 BarEndIndex
= PCI_MAX_BAR
- 1;
1239 if (BarIndex
> PCI_MAX_BAR
) {
1244 for (; BarIndex
<= BarEndIndex
; BarIndex
++) {
1246 switch (Ptr
->ResType
) {
1247 case ACPI_ADDRESS_SPACE_TYPE_MEM
:
1250 // Make sure the bar is memory type
1252 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeMem
)) {
1257 case ACPI_ADDRESS_SPACE_TYPE_IO
:
1260 // Make sure the bar is IO type
1262 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeIo
)) {
1271 // Update the new alignment for the device
1273 SetNewAlign (&(PciIoDevice
->PciBar
[BarIndex
].Alignment
), Ptr
->AddrRangeMax
);
1276 // Update the new length for the device
1278 if (Ptr
->AddrLen
!= PCI_BAR_NOCHANGE
) {
1279 PciIoDevice
->PciBar
[BarIndex
].Length
= Ptr
->AddrLen
;
1287 FreePool (Configuration
);
1293 This routine will update the alignment with the new alignment.
1295 @param Alignment Input Old alignment. Output updated alignment.
1296 @param NewAlignment New alignment.
1301 IN OUT UINT64
*Alignment
,
1302 IN UINT64 NewAlignment
1305 UINT64 OldAlignment
;
1309 // The new alignment is the same as the original,
1312 if (NewAlignment
== PCI_BAR_OLD_ALIGN
) {
1316 // Check the validity of the parameter
1318 if (NewAlignment
!= PCI_BAR_EVEN_ALIGN
&&
1319 NewAlignment
!= PCI_BAR_SQUAD_ALIGN
&&
1320 NewAlignment
!= PCI_BAR_DQUAD_ALIGN
) {
1321 *Alignment
= NewAlignment
;
1325 OldAlignment
= (*Alignment
) + 1;
1329 // Get the first non-zero hex value of the length
1331 while ((OldAlignment
& 0x0F) == 0x00) {
1332 OldAlignment
= RShiftU64 (OldAlignment
, 4);
1337 // Adjust the alignment to even, quad or double quad boundary
1339 if (NewAlignment
== PCI_BAR_EVEN_ALIGN
) {
1340 if ((OldAlignment
& 0x01) != 0) {
1341 OldAlignment
= OldAlignment
+ 2 - (OldAlignment
& 0x01);
1343 } else if (NewAlignment
== PCI_BAR_SQUAD_ALIGN
) {
1344 if ((OldAlignment
& 0x03) != 0) {
1345 OldAlignment
= OldAlignment
+ 4 - (OldAlignment
& 0x03);
1347 } else if (NewAlignment
== PCI_BAR_DQUAD_ALIGN
) {
1348 if ((OldAlignment
& 0x07) != 0) {
1349 OldAlignment
= OldAlignment
+ 8 - (OldAlignment
& 0x07);
1354 // Update the old value
1356 NewAlignment
= LShiftU64 (OldAlignment
, ShiftBit
) - 1;
1357 *Alignment
= NewAlignment
;
1363 Parse PCI IOV VF bar information and fill them into PCI device instance.
1365 @param PciIoDevice Pci device instance.
1366 @param Offset Bar offset.
1367 @param BarIndex Bar index.
1369 @return Next bar offset.
1374 IN PCI_IO_DEVICE
*PciIoDevice
,
1380 UINT32 OriginalValue
;
1387 // Ensure it is called properly
1389 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
1390 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
1397 Status
= VfBarExisted (
1404 if (EFI_ERROR (Status
)) {
1405 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1406 PciIoDevice
->VfPciBar
[BarIndex
].Length
= 0;
1407 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1410 // Scan all the BARs anyway
1412 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
) Offset
;
1416 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
) Offset
;
1417 if ((Value
& 0x01) != 0) {
1419 // Device I/Os. Impossible
1428 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1430 switch (Value
& 0x07) {
1433 //memory space; anywhere in 32 bit address space
1436 if ((Value
& 0x08) != 0) {
1437 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1439 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1442 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1443 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1448 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1452 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1453 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1459 // memory space; anywhere in 64 bit address space
1462 if ((Value
& 0x08) != 0) {
1463 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1465 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1469 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1470 // is regarded as an extension for the first bar. As a result
1471 // the sizing will be conducted on combined 64 bit value
1472 // Here just store the masked first 32bit value for future size
1475 PciIoDevice
->VfPciBar
[BarIndex
].Length
= Value
& Mask
;
1476 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1478 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1479 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1483 // Increment the offset to point to next DWORD
1487 Status
= VfBarExisted (
1494 if (EFI_ERROR (Status
)) {
1499 // Fix the length to support some spefic 64 bit BAR
1503 for (Data
= Value
; Data
!= 0; Data
>>= 1) {
1506 Value
|= ((UINT32
)(-1) << Index
);
1509 // Calculate the size of 64bit bar
1511 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
) OriginalValue
, 32);
1513 PciIoDevice
->VfPciBar
[BarIndex
].Length
= PciIoDevice
->VfPciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
) Value
, 32);
1514 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(PciIoDevice
->VfPciBar
[BarIndex
].Length
)) + 1;
1515 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1520 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1524 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1525 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1534 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1535 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1536 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1538 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1539 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1547 // Check the length again so as to keep compatible with some special bars
1549 if (PciIoDevice
->VfPciBar
[BarIndex
].Length
== 0) {
1550 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1551 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1552 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1556 // Increment number of bar
1562 Parse PCI bar information and fill them into PCI device instance.
1564 @param PciIoDevice Pci device instance.
1565 @param Offset Bar offset.
1566 @param BarIndex Bar index.
1568 @return Next bar offset.
1573 IN PCI_IO_DEVICE
*PciIoDevice
,
1579 UINT32 OriginalValue
;
1588 Status
= BarExisted (
1595 if (EFI_ERROR (Status
)) {
1596 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1597 PciIoDevice
->PciBar
[BarIndex
].Length
= 0;
1598 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1601 // Some devices don't fully comply to PCI spec 2.2. So be to scan all the BARs anyway
1603 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1607 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1608 if ((Value
& 0x01) != 0) {
1614 if ((Value
& 0xFFFF0000) != 0) {
1618 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo32
;
1619 PciIoDevice
->PciBar
[BarIndex
].Length
= ((~(Value
& Mask
)) + 1);
1620 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1626 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo16
;
1627 PciIoDevice
->PciBar
[BarIndex
].Length
= 0x0000FFFF & ((~(Value
& Mask
)) + 1);
1628 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1632 // Workaround. Some platforms inplement IO bar with 0 length
1633 // Need to treat it as no-bar
1635 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1636 PciIoDevice
->PciBar
[BarIndex
].BarType
= (PCI_BAR_TYPE
) 0;
1639 PciIoDevice
->PciBar
[BarIndex
].Prefetchable
= FALSE
;
1640 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1646 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1648 switch (Value
& 0x07) {
1651 //memory space; anywhere in 32 bit address space
1654 if ((Value
& 0x08) != 0) {
1655 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1657 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1660 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1661 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1663 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1665 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1667 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1672 // memory space; anywhere in 64 bit address space
1675 if ((Value
& 0x08) != 0) {
1676 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1678 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1682 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1683 // is regarded as an extension for the first bar. As a result
1684 // the sizing will be conducted on combined 64 bit value
1685 // Here just store the masked first 32bit value for future size
1688 PciIoDevice
->PciBar
[BarIndex
].Length
= Value
& Mask
;
1689 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1692 // Increment the offset to point to next DWORD
1696 Status
= BarExisted (
1703 if (EFI_ERROR (Status
)) {
1705 // the high 32 bit does not claim any BAR, we need to re-check the low 32 bit BAR again
1707 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1709 // some device implement MMIO bar with 0 length, need to treat it as no-bar
1711 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1717 // Fix the length to support some spefic 64 bit BAR
1721 for (Data
= Value
; Data
!= 0; Data
>>= 1) {
1724 Value
|= ((UINT32
)(-1) << Index
);
1727 // Calculate the size of 64bit bar
1729 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
) OriginalValue
, 32);
1731 PciIoDevice
->PciBar
[BarIndex
].Length
= PciIoDevice
->PciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
) Value
, 32);
1732 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(PciIoDevice
->PciBar
[BarIndex
].Length
)) + 1;
1733 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1735 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1737 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1739 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1748 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1749 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1750 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1752 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1754 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1756 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1763 // Check the length again so as to keep compatible with some special bars
1765 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1766 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1767 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1768 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1772 // Increment number of bar
1778 This routine is used to initialize the bar of a PCI device.
1780 @param PciIoDevice Pci device instance.
1782 @note It can be called typically when a device is going to be rejected.
1786 InitializePciDevice (
1787 IN PCI_IO_DEVICE
*PciIoDevice
1790 EFI_PCI_IO_PROTOCOL
*PciIo
;
1793 PciIo
= &(PciIoDevice
->PciIo
);
1796 // Put all the resource apertures
1797 // Resource base is set to all ones so as to indicate its resource
1798 // has not been alloacted
1800 for (Offset
= 0x10; Offset
<= 0x24; Offset
+= sizeof (UINT32
)) {
1801 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, Offset
, 1, &gAllOne
);
1806 This routine is used to initialize the bar of a PCI-PCI Bridge device.
1808 @param PciIoDevice PCI-PCI bridge device instance.
1813 IN PCI_IO_DEVICE
*PciIoDevice
1816 EFI_PCI_IO_PROTOCOL
*PciIo
;
1818 PciIo
= &(PciIoDevice
->PciIo
);
1821 // Put all the resource apertures including IO16
1822 // Io32, pMem32, pMem64 to quiescent state
1823 // Resource base all ones, Resource limit all zeros
1825 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
1826 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1D, 1, &gAllZero
);
1828 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x20, 1, &gAllOne
);
1829 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x22, 1, &gAllZero
);
1831 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x24, 1, &gAllOne
);
1832 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x26, 1, &gAllZero
);
1834 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllOne
);
1835 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2C, 1, &gAllZero
);
1838 // Don't support use io32 as for now
1840 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x30, 1, &gAllOne
);
1841 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x32, 1, &gAllZero
);
1844 // Force Interrupt line to zero for cards that come up randomly
1846 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
1850 This routine is used to initialize the bar of a PCI Card Bridge device.
1852 @param PciIoDevice PCI Card bridge device.
1857 IN PCI_IO_DEVICE
*PciIoDevice
1860 EFI_PCI_IO_PROTOCOL
*PciIo
;
1862 PciIo
= &(PciIoDevice
->PciIo
);
1865 // Put all the resource apertures including IO16
1866 // Io32, pMem32, pMem64 to quiescent state(
1867 // Resource base all ones, Resource limit all zeros
1869 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x1c, 1, &gAllOne
);
1870 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x20, 1, &gAllZero
);
1872 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x24, 1, &gAllOne
);
1873 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllZero
);
1875 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2c, 1, &gAllOne
);
1876 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x30, 1, &gAllZero
);
1878 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x34, 1, &gAllOne
);
1879 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x38, 1, &gAllZero
);
1882 // Force Interrupt line to zero for cards that come up randomly
1884 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
1888 Create and initiliaze general PCI I/O device instance for
1889 PCI device/bridge device/hotplug bridge device.
1891 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1892 @param Pci Input Pci information block.
1893 @param Bus Device Bus NO.
1894 @param Device Device device NO.
1895 @param Func Device func NO.
1897 @return Instance of PCI device. NULL means no instance created.
1902 IN PCI_IO_DEVICE
*Bridge
,
1909 PCI_IO_DEVICE
*PciIoDevice
;
1910 EFI_PCI_IO_PROTOCOL
*PciIo
;
1913 PciIoDevice
= AllocateZeroPool (sizeof (PCI_IO_DEVICE
));
1914 if (PciIoDevice
== NULL
) {
1918 PciIoDevice
->Signature
= PCI_IO_DEVICE_SIGNATURE
;
1919 PciIoDevice
->Handle
= NULL
;
1920 PciIoDevice
->PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
1921 PciIoDevice
->DevicePath
= NULL
;
1922 PciIoDevice
->BusNumber
= Bus
;
1923 PciIoDevice
->DeviceNumber
= Device
;
1924 PciIoDevice
->FunctionNumber
= Func
;
1925 PciIoDevice
->Decodes
= 0;
1927 if (gFullEnumeration
) {
1928 PciIoDevice
->Allocated
= FALSE
;
1930 PciIoDevice
->Allocated
= TRUE
;
1933 PciIoDevice
->Registered
= FALSE
;
1934 PciIoDevice
->Attributes
= 0;
1935 PciIoDevice
->Supports
= 0;
1936 PciIoDevice
->BusOverride
= FALSE
;
1937 PciIoDevice
->AllOpRomProcessed
= FALSE
;
1939 PciIoDevice
->IsPciExp
= FALSE
;
1941 CopyMem (&(PciIoDevice
->Pci
), Pci
, sizeof (PCI_TYPE01
));
1944 // Initialize the PCI I/O instance structure
1946 InitializePciIoInstance (PciIoDevice
);
1947 InitializePciDriverOverrideInstance (PciIoDevice
);
1948 InitializePciLoadFile2 (PciIoDevice
);
1949 PciIo
= &PciIoDevice
->PciIo
;
1952 // Detect if PCI Express Device
1954 PciIoDevice
->PciExpressCapabilityOffset
= 0;
1955 Status
= LocateCapabilityRegBlock (
1957 EFI_PCI_CAPABILITY_ID_PCIEXP
,
1958 &PciIoDevice
->PciExpressCapabilityOffset
,
1961 if (!EFI_ERROR (Status
)) {
1962 PciIoDevice
->IsPciExp
= TRUE
;
1965 if (PcdGetBool (PcdAriSupport
)) {
1967 // Check if the device is an ARI device.
1969 Status
= LocatePciExpressCapabilityRegBlock (
1971 EFI_PCIE_CAPABILITY_ID_ARI
,
1972 &PciIoDevice
->AriCapabilityOffset
,
1975 if (!EFI_ERROR (Status
)) {
1977 // We need to enable ARI feature before calculate BusReservation,
1978 // because FirstVFOffset and VFStride may change after that.
1980 EFI_PCI_IO_PROTOCOL
*ParentPciIo
;
1984 // Check if its parent supports ARI forwarding.
1986 ParentPciIo
= &Bridge
->PciIo
;
1987 ParentPciIo
->Pci
.Read (
1989 EfiPciIoWidthUint32
,
1990 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET
,
1994 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING
) != 0) {
1996 // ARI forward support in bridge, so enable it.
1998 ParentPciIo
->Pci
.Read (
2000 EfiPciIoWidthUint32
,
2001 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2005 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
) == 0) {
2006 Data32
|= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
;
2007 ParentPciIo
->Pci
.Write (
2009 EfiPciIoWidthUint32
,
2010 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2016 "PCI B%x.D%x.F%x - ARI forwarding enabled\n",
2017 (UINTN
)Bridge
->BusNumber
,
2018 (UINTN
)Bridge
->DeviceNumber
,
2019 (UINTN
)Bridge
->FunctionNumber
2026 "PCI ARI B%x.D%x.F%x - ARI Cap offset - 0x%x\n",
2030 (UINTN
)PciIoDevice
->AriCapabilityOffset
2036 // Initialization for SR-IOV
2039 if (PcdGetBool (PcdSrIovSupport
)) {
2040 Status
= LocatePciExpressCapabilityRegBlock (
2042 EFI_PCIE_CAPABILITY_ID_SRIOV
,
2043 &PciIoDevice
->SrIovCapabilityOffset
,
2046 if (!EFI_ERROR (Status
)) {
2048 UINT16 FirstVFOffset
;
2054 // If the SR-IOV device is an ARI device, then Set ARI Capable Hierarchy for the device.
2056 if (PcdGetBool (PcdAriSupport
) && PciIoDevice
->AriCapabilityOffset
!= 0) {
2059 EfiPciIoWidthUint16
,
2060 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2064 Data16
|= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY
;
2067 EfiPciIoWidthUint16
,
2068 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2075 // Calculate SystemPageSize
2080 EfiPciIoWidthUint32
,
2081 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE
,
2083 &PciIoDevice
->SystemPageSize
2087 "PCI SR-IOV B%x.D%x.F%x - SupportedPageSize - 0x%x\n",
2091 PciIoDevice
->SystemPageSize
2094 PciIoDevice
->SystemPageSize
= (PcdGet32 (PcdSrIovSystemPageSize
) & PciIoDevice
->SystemPageSize
);
2095 ASSERT (PciIoDevice
->SystemPageSize
!= 0);
2099 EfiPciIoWidthUint32
,
2100 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE
,
2102 &PciIoDevice
->SystemPageSize
2106 "PCI SR-IOV B%x.D%x.F%x - SystemPageSize - 0x%x\n",
2110 PciIoDevice
->SystemPageSize
2113 // Adjust SystemPageSize for Alignment usage later
2115 PciIoDevice
->SystemPageSize
<<= 12;
2118 // Calculate BusReservation for PCI IOV
2122 // Read First FirstVFOffset, InitialVFs, and VFStride
2126 EfiPciIoWidthUint16
,
2127 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF
,
2133 "PCI SR-IOV B%x.D%x.F%x - FirstVFOffset - 0x%x\n",
2137 (UINTN
)FirstVFOffset
2142 EfiPciIoWidthUint16
,
2143 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS
,
2145 &PciIoDevice
->InitialVFs
2149 "PCI SR-IOV B%x.D%x.F%x - InitialVFs - 0x%x\n",
2153 (UINTN
)PciIoDevice
->InitialVFs
2158 EfiPciIoWidthUint16
,
2159 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE
,
2165 "PCI SR-IOV B%x.D%x.F%x - VFStride - 0x%x\n",
2175 PFRid
= EFI_PCI_RID(Bus
, Device
, Func
);
2176 LastVF
= PFRid
+ FirstVFOffset
+ (PciIoDevice
->InitialVFs
- 1) * VFStride
;
2179 // Calculate ReservedBusNum for this PF
2181 PciIoDevice
->ReservedBusNum
= (UINT16
)(EFI_PCI_BUS_OF_RID (LastVF
) - Bus
+ 1);
2184 "PCI SR-IOV B%x.D%x.F%x - reserved bus number - 0x%x\n",
2188 (UINTN
)PciIoDevice
->ReservedBusNum
2193 "PCI SR-IOV B%x.D%x.F%x - SRIOV Cap offset - 0x%x\n",
2197 (UINTN
)PciIoDevice
->SrIovCapabilityOffset
2202 if (PcdGetBool (PcdMrIovSupport
)) {
2203 Status
= LocatePciExpressCapabilityRegBlock (
2205 EFI_PCIE_CAPABILITY_ID_MRIOV
,
2206 &PciIoDevice
->MrIovCapabilityOffset
,
2209 if (!EFI_ERROR (Status
)) {
2212 "PCI MR-IOV B%x.D%x.F%x - MRIOV Cap offset - 0x%x\n",
2216 (UINTN
)PciIoDevice
->MrIovCapabilityOffset
2222 // Initialize the reserved resource list
2224 InitializeListHead (&PciIoDevice
->ReservedResourceList
);
2227 // Initialize the driver list
2229 InitializeListHead (&PciIoDevice
->OptionRomDriverList
);
2232 // Initialize the child list
2234 InitializeListHead (&PciIoDevice
->ChildList
);
2240 This routine is used to enumerate entire pci bus system
2241 in a given platform.
2243 It is only called on the second start on the same Root Bridge.
2245 @param Controller Parent bridge handler.
2247 @retval EFI_SUCCESS PCI enumeration finished successfully.
2248 @retval other Some error occurred when enumerating the pci bus system.
2252 PciEnumeratorLight (
2253 IN EFI_HANDLE Controller
2258 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2259 PCI_IO_DEVICE
*RootBridgeDev
;
2262 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2265 MaxBus
= PCI_MAX_BUS
;
2269 // If this root bridge has been already enumerated, then return successfully
2271 if (GetRootBridgeByHandle (Controller
) != NULL
) {
2276 // Open pci root bridge io protocol
2278 Status
= gBS
->OpenProtocol (
2280 &gEfiPciRootBridgeIoProtocolGuid
,
2281 (VOID
**) &PciRootBridgeIo
,
2282 gPciBusDriverBinding
.DriverBindingHandle
,
2284 EFI_OPEN_PROTOCOL_BY_DRIVER
2286 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
2290 Status
= PciRootBridgeIo
->Configuration (PciRootBridgeIo
, (VOID
**) &Descriptors
);
2292 if (EFI_ERROR (Status
)) {
2296 while (PciGetBusRange (&Descriptors
, &MinBus
, &MaxBus
, NULL
) == EFI_SUCCESS
) {
2299 // Create a device node for root bridge device with a NULL host bridge controller handle
2301 RootBridgeDev
= CreateRootBridge (Controller
);
2303 if (RootBridgeDev
== NULL
) {
2309 // Record the root bridgeio protocol
2311 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2313 Status
= PciPciDeviceInfoCollector (
2318 if (!EFI_ERROR (Status
)) {
2321 // Remove those PCI devices which are rejected when full enumeration
2323 RemoveRejectedPciDevices (RootBridgeDev
->Handle
, RootBridgeDev
);
2326 // Process option rom light
2328 ProcessOptionRomLight (RootBridgeDev
);
2331 // Determine attributes for all devices under this root bridge
2333 DetermineDeviceAttribute (RootBridgeDev
);
2336 // If successfully, insert the node into device pool
2338 InsertRootBridge (RootBridgeDev
);
2342 // If unsuccessly, destroy the entire node
2344 DestroyRootBridge (RootBridgeDev
);
2354 Get bus range from PCI resource descriptor list.
2356 @param Descriptors A pointer to the address space descriptor.
2357 @param MinBus The min bus returned.
2358 @param MaxBus The max bus returned.
2359 @param BusRange The bus range returned.
2361 @retval EFI_SUCCESS Successfully got bus range.
2362 @retval EFI_NOT_FOUND Can not find the specific bus.
2367 IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
2370 OUT UINT16
*BusRange
2373 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
2374 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
2375 if (MinBus
!= NULL
) {
2376 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
2379 if (MaxBus
!= NULL
) {
2380 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
2383 if (BusRange
!= NULL
) {
2384 *BusRange
= (UINT16
) (*Descriptors
)->AddrLen
;
2393 return EFI_NOT_FOUND
;
2397 This routine can be used to start the root bridge.
2399 @param RootBridgeDev Pci device instance.
2401 @retval EFI_SUCCESS This device started.
2402 @retval other Failed to get PCI Root Bridge I/O protocol.
2406 StartManagingRootBridge (
2407 IN PCI_IO_DEVICE
*RootBridgeDev
2410 EFI_HANDLE RootBridgeHandle
;
2412 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2415 // Get the root bridge handle
2417 RootBridgeHandle
= RootBridgeDev
->Handle
;
2418 PciRootBridgeIo
= NULL
;
2421 // Get the pci root bridge io protocol
2423 Status
= gBS
->OpenProtocol (
2425 &gEfiPciRootBridgeIoProtocolGuid
,
2426 (VOID
**) &PciRootBridgeIo
,
2427 gPciBusDriverBinding
.DriverBindingHandle
,
2429 EFI_OPEN_PROTOCOL_BY_DRIVER
2432 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
2437 // Store the PciRootBridgeIo protocol into root bridge private data
2439 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2446 This routine can be used to check whether a PCI device should be rejected when light enumeration.
2448 @param PciIoDevice Pci device instance.
2450 @retval TRUE This device should be rejected.
2451 @retval FALSE This device shouldn't be rejected.
2455 IsPciDeviceRejected (
2456 IN PCI_IO_DEVICE
*PciIoDevice
2466 // PPB should be skip!
2468 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
2472 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
2474 // Only test base registers for P2C
2476 for (BarOffset
= 0x1C; BarOffset
<= 0x38; BarOffset
+= 2 * sizeof (UINT32
)) {
2478 Mask
= (BarOffset
< 0x2C) ? 0xFFFFF000 : 0xFFFFFFFC;
2479 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2480 if (EFI_ERROR (Status
)) {
2484 TestValue
= TestValue
& Mask
;
2485 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2487 // The bar isn't programed, so it should be rejected
2496 for (BarOffset
= 0x14; BarOffset
<= 0x24; BarOffset
+= sizeof (UINT32
)) {
2500 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2501 if (EFI_ERROR (Status
)) {
2505 if ((TestValue
& 0x01) != 0) {
2511 TestValue
= TestValue
& Mask
;
2512 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2522 TestValue
= TestValue
& Mask
;
2524 if ((TestValue
& 0x07) == 0x04) {
2529 BarOffset
+= sizeof (UINT32
);
2530 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2533 // Test its high 32-Bit BAR
2535 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2536 if (TestValue
== OldValue
) {
2546 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2557 Reset all bus number from specific bridge.
2559 @param Bridge Parent specific bridge.
2560 @param StartBusNumber Start bus number.
2564 ResetAllPpbBusNumber (
2565 IN PCI_IO_DEVICE
*Bridge
,
2566 IN UINT8 StartBusNumber
2576 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2578 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
2580 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2581 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2584 // Check to see whether a pci device is present
2586 Status
= PciDevicePresent (
2594 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
))) {
2597 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x18);
2598 Status
= PciRootBridgeIo
->Pci
.Read (
2605 SecondaryBus
= (UINT8
)(Register
>> 8);
2607 if (SecondaryBus
!= 0) {
2608 ResetAllPpbBusNumber (Bridge
, SecondaryBus
);
2612 // Reset register 18h, 19h, 1Ah on PCI Bridge
2614 Register
&= 0xFF000000;
2615 Status
= PciRootBridgeIo
->Pci
.Write (
2624 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
2626 // Skip sub functions, this is not a multi function device
2628 Func
= PCI_MAX_FUNC
;