2 PCI emumeration support functions implementation for PCI Bus module.
4 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 extern CHAR16
*mBarTypeStr
[];
21 This routine is used to check whether the pci device is present.
23 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
24 @param Pci Output buffer for PCI device configuration space.
25 @param Bus PCI bus NO.
26 @param Device PCI device NO.
27 @param Func PCI Func NO.
29 @retval EFI_NOT_FOUND PCI device not present.
30 @retval EFI_SUCCESS PCI device is found.
35 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
,
46 // Create PCI address map in terms of Bus, Device and Func
48 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
51 // Read the Vendor ID register
53 Status
= PciRootBridgeIo
->Pci
.Read (
61 if (!EFI_ERROR (Status
) && (Pci
->Hdr
).VendorId
!= 0xffff) {
63 // Read the entire config header for the device
65 Status
= PciRootBridgeIo
->Pci
.Read (
69 sizeof (PCI_TYPE00
) / sizeof (UINT32
),
80 Collect all the resource information under this root bridge.
82 A database that records all the information about pci device subject to this
83 root bridge will then be created.
85 @param Bridge Parent bridge instance.
86 @param StartBusNumber Bus number of begining.
88 @retval EFI_SUCCESS PCI device is found.
89 @retval other Some error occurred when reading PCI bridge information.
93 PciPciDeviceInfoCollector (
94 IN PCI_IO_DEVICE
*Bridge
,
95 IN UINT8 StartBusNumber
103 PCI_IO_DEVICE
*PciIoDevice
;
104 EFI_PCI_IO_PROTOCOL
*PciIo
;
106 Status
= EFI_SUCCESS
;
109 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
111 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
114 // Check to see whether PCI device is present
116 Status
= PciDevicePresent (
117 Bridge
->PciRootBridgeIo
,
119 (UINT8
) StartBusNumber
,
124 if (EFI_ERROR (Status
) && Func
== 0) {
126 // go to next device if there is no Function 0
131 if (!EFI_ERROR (Status
)) {
134 // Call back to host bridge function
136 PreprocessController (Bridge
, (UINT8
) StartBusNumber
, Device
, Func
, EfiPciBeforeResourceCollection
);
139 // Collect all the information about the PCI device discovered
141 Status
= PciSearchDevice (
144 (UINT8
) StartBusNumber
,
151 // Recursively scan PCI busses on the other side of PCI-PCI bridges
154 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
) || IS_CARDBUS_BRIDGE (&Pci
))) {
157 // If it is PPB, we need to get the secondary bus to continue the enumeration
159 PciIo
= &(PciIoDevice
->PciIo
);
161 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
, 1, &SecBus
);
163 if (EFI_ERROR (Status
)) {
168 // Get resource padding for PPB
170 GetResourcePaddingPpb (PciIoDevice
);
173 // Deep enumerate the next level bus
175 Status
= PciPciDeviceInfoCollector (
182 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
185 // Skip sub functions, this is not a multi function device
198 Seach required device and create PCI device instance.
200 @param Bridge Parent bridge instance.
201 @param Pci Input PCI device information block.
202 @param Bus PCI bus NO.
203 @param Device PCI device NO.
204 @param Func PCI func NO.
205 @param PciDevice Output of searched PCI device instance.
207 @retval EFI_SUCCESS Successfully created PCI device instance.
208 @retval EFI_OUT_OF_RESOURCES Cannot get PCI device information.
213 IN PCI_IO_DEVICE
*Bridge
,
218 OUT PCI_IO_DEVICE
**PciDevice
221 PCI_IO_DEVICE
*PciIoDevice
;
227 "PciBus: Discovered %s @ [%02x|%02x|%02x]\n",
228 IS_PCI_BRIDGE (Pci
) ? L
"PPB" :
229 IS_CARDBUS_BRIDGE (Pci
) ? L
"P2C" :
234 if (!IS_PCI_BRIDGE (Pci
)) {
236 if (IS_CARDBUS_BRIDGE (Pci
)) {
237 PciIoDevice
= GatherP2CInfo (
244 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
245 InitializeP2C (PciIoDevice
);
250 // Create private data for Pci Device
252 PciIoDevice
= GatherDeviceInfo (
265 // Create private data for PPB
267 PciIoDevice
= GatherPpbInfo (
276 // Special initialization for PPB including making the PPB quiet
278 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
279 InitializePpb (PciIoDevice
);
283 if (PciIoDevice
== NULL
) {
284 return EFI_OUT_OF_RESOURCES
;
288 // Update the bar information for this PCI device so as to support some specific device
290 UpdatePciInfo (PciIoDevice
);
292 if (PciIoDevice
->DevicePath
== NULL
) {
293 return EFI_OUT_OF_RESOURCES
;
297 // Detect this function has option rom
299 if (gFullEnumeration
) {
301 if (!IS_CARDBUS_BRIDGE (Pci
)) {
303 GetOpRomInfo (PciIoDevice
);
307 ResetPowerManagementFeature (PciIoDevice
);
312 // Insert it into a global tree for future reference
314 InsertPciDevice (Bridge
, PciIoDevice
);
317 // Determine PCI device attributes
320 if (PciDevice
!= NULL
) {
321 *PciDevice
= PciIoDevice
;
328 Dump the PCI BAR information.
330 @param PciIoDevice PCI IO instance.
334 IN PCI_IO_DEVICE
*PciIoDevice
339 for (Index
= 0; Index
< PCI_MAX_BAR
; Index
++) {
340 if (PciIoDevice
->PciBar
[Index
].BarType
== PciBarTypeUnknown
) {
346 " BAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
347 Index
, mBarTypeStr
[MIN (PciIoDevice
->PciBar
[Index
].BarType
, PciBarTypeMaxType
)],
348 PciIoDevice
->PciBar
[Index
].Alignment
, PciIoDevice
->PciBar
[Index
].Length
, PciIoDevice
->PciBar
[Index
].Offset
352 for (Index
= 0; Index
< PCI_MAX_BAR
; Index
++) {
353 if ((PciIoDevice
->VfPciBar
[Index
].BarType
== PciBarTypeUnknown
) && (PciIoDevice
->VfPciBar
[Index
].Length
== 0)) {
359 " VFBAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
360 Index
, mBarTypeStr
[MIN (PciIoDevice
->VfPciBar
[Index
].BarType
, PciBarTypeMaxType
)],
361 PciIoDevice
->VfPciBar
[Index
].Alignment
, PciIoDevice
->VfPciBar
[Index
].Length
, PciIoDevice
->VfPciBar
[Index
].Offset
364 DEBUG ((EFI_D_INFO
, "\n"));
368 Create PCI device instance for PCI device.
370 @param Bridge Parent bridge instance.
371 @param Pci Input PCI device information block.
372 @param Bus PCI device Bus NO.
373 @param Device PCI device Device NO.
374 @param Func PCI device's func NO.
376 @return Created PCI device instance.
381 IN PCI_IO_DEVICE
*Bridge
,
390 PCI_IO_DEVICE
*PciIoDevice
;
392 PciIoDevice
= CreatePciIoDevice (
400 if (PciIoDevice
== NULL
) {
405 // If it is a full enumeration, disconnect the device in advance
407 if (gFullEnumeration
) {
409 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
414 // Start to parse the bars
416 for (Offset
= 0x10, BarIndex
= 0; Offset
<= 0x24 && BarIndex
< PCI_MAX_BAR
; BarIndex
++) {
417 Offset
= PciParseBar (PciIoDevice
, Offset
, BarIndex
);
421 // Parse the SR-IOV VF bars
423 if (PcdGetBool (PcdSrIovSupport
) && PciIoDevice
->SrIovCapabilityOffset
!= 0) {
424 for (Offset
= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0
, BarIndex
= 0;
425 Offset
<= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5
;
428 ASSERT (BarIndex
< PCI_MAX_BAR
);
429 Offset
= PciIovParseVfBar (PciIoDevice
, Offset
, BarIndex
);
433 DEBUG_CODE (DumpPciBars (PciIoDevice
););
438 Create PCI device instance for PCI-PCI bridge.
440 @param Bridge Parent bridge instance.
441 @param Pci Input PCI device information block.
442 @param Bus PCI device Bus NO.
443 @param Device PCI device Device NO.
444 @param Func PCI device's func NO.
446 @return Created PCI device instance.
451 IN PCI_IO_DEVICE
*Bridge
,
458 PCI_IO_DEVICE
*PciIoDevice
;
461 EFI_PCI_IO_PROTOCOL
*PciIo
;
463 UINT32 PMemBaseLimit
;
464 UINT16 PrefetchableMemoryBase
;
465 UINT16 PrefetchableMemoryLimit
;
467 PciIoDevice
= CreatePciIoDevice (
475 if (PciIoDevice
== NULL
) {
479 if (gFullEnumeration
) {
480 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
483 // Initalize the bridge control register
485 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED
);
490 // PPB can have two BARs
492 if (PciParseBar (PciIoDevice
, 0x10, PPB_BAR_0
) == 0x14) {
496 PciParseBar (PciIoDevice
, 0x14, PPB_BAR_1
);
499 PciIo
= &PciIoDevice
->PciIo
;
502 // Test whether it support 32 decode or not
504 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
505 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
506 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
507 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
510 if ((Value
& 0x01) != 0) {
511 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
513 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO16_DECODE_SUPPORTED
;
518 // if PcdPciBridgeIoAlignmentProbe is TRUE, PCI bus driver probes
519 // PCI bridge supporting non-stardard I/O window alignment less than 4K.
522 PciIoDevice
->BridgeIoAlignment
= 0xFFF;
523 if (FeaturePcdGet (PcdPciBridgeIoAlignmentProbe
)) {
525 // Check any bits of bit 3-1 of I/O Base Register are writable.
526 // if so, it is assumed non-stardard I/O window alignment is supported by this bridge.
527 // Per spec, bit 3-1 of I/O Base Register are reserved bits, so its content can't be assumed.
529 Value
= (UINT8
)(Temp
^ (BIT3
| BIT2
| BIT1
));
530 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
531 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
532 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
533 Value
= (UINT8
)((Value
^ Temp
) & (BIT3
| BIT2
| BIT1
));
536 PciIoDevice
->BridgeIoAlignment
= 0x7FF;
539 PciIoDevice
->BridgeIoAlignment
= 0x3FF;
541 case BIT3
| BIT2
| BIT1
:
542 PciIoDevice
->BridgeIoAlignment
= 0x1FF;
547 Status
= BarExisted (
555 // Test if it supports 64 memory or not
557 // The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory Limit
559 // 0 - the bridge supports only 32 bit addresses.
560 // 1 - the bridge supports 64-bit addresses.
562 PrefetchableMemoryBase
= (UINT16
)(PMemBaseLimit
& 0xffff);
563 PrefetchableMemoryLimit
= (UINT16
)(PMemBaseLimit
>> 16);
564 if (!EFI_ERROR (Status
) &&
565 (PrefetchableMemoryBase
& 0x000f) == 0x0001 &&
566 (PrefetchableMemoryLimit
& 0x000f) == 0x0001) {
567 Status
= BarExisted (
574 if (!EFI_ERROR (Status
)) {
575 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
576 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED
;
578 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
583 // Memory 32 code is required for ppb
585 PciIoDevice
->Decodes
|= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
;
587 GetResourcePaddingPpb (PciIoDevice
);
589 DEBUG_CODE (DumpPciBars (PciIoDevice
););
596 Create PCI device instance for PCI Card bridge device.
598 @param Bridge Parent bridge instance.
599 @param Pci Input PCI device information block.
600 @param Bus PCI device Bus NO.
601 @param Device PCI device Device NO.
602 @param Func PCI device's func NO.
604 @return Created PCI device instance.
609 IN PCI_IO_DEVICE
*Bridge
,
616 PCI_IO_DEVICE
*PciIoDevice
;
618 PciIoDevice
= CreatePciIoDevice (
626 if (PciIoDevice
== NULL
) {
630 if (gFullEnumeration
) {
631 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
634 // Initalize the bridge control register
636 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED
);
640 // P2C only has one bar that is in 0x10
642 PciParseBar (PciIoDevice
, 0x10, P2C_BAR_0
);
645 // Read PciBar information from the bar register
647 GetBackPcCardBar (PciIoDevice
);
648 PciIoDevice
->Decodes
= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
|
649 EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
|
650 EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
652 DEBUG_CODE (DumpPciBars (PciIoDevice
););
658 Create device path for pci deivce.
660 @param ParentDevicePath Parent bridge's path.
661 @param PciIoDevice Pci device instance.
663 @return Device path protocol instance for specific pci device.
666 EFI_DEVICE_PATH_PROTOCOL
*
667 CreatePciDevicePath (
668 IN EFI_DEVICE_PATH_PROTOCOL
*ParentDevicePath
,
669 IN PCI_IO_DEVICE
*PciIoDevice
673 PCI_DEVICE_PATH PciNode
;
676 // Create PCI device path
678 PciNode
.Header
.Type
= HARDWARE_DEVICE_PATH
;
679 PciNode
.Header
.SubType
= HW_PCI_DP
;
680 SetDevicePathNodeLength (&PciNode
.Header
, sizeof (PciNode
));
682 PciNode
.Device
= PciIoDevice
->DeviceNumber
;
683 PciNode
.Function
= PciIoDevice
->FunctionNumber
;
684 PciIoDevice
->DevicePath
= AppendDevicePathNode (ParentDevicePath
, &PciNode
.Header
);
686 return PciIoDevice
->DevicePath
;
690 Check whether the PCI IOV VF bar is existed or not.
692 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
693 @param Offset The offset.
694 @param BarLengthValue The bar length value returned.
695 @param OriginalBarValue The original bar value returned.
697 @retval EFI_NOT_FOUND The bar doesn't exist.
698 @retval EFI_SUCCESS The bar exist.
703 IN PCI_IO_DEVICE
*PciIoDevice
,
705 OUT UINT32
*BarLengthValue
,
706 OUT UINT32
*OriginalBarValue
709 EFI_PCI_IO_PROTOCOL
*PciIo
;
710 UINT32 OriginalValue
;
715 // Ensure it is called properly
717 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
718 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
719 return EFI_NOT_FOUND
;
722 PciIo
= &PciIoDevice
->PciIo
;
725 // Preserve the original value
728 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
731 // Raise TPL to high level to disable timer interrupt while the BAR is probed
733 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
735 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &gAllOne
);
736 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &Value
);
739 // Write back the original value
741 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
744 // Restore TPL to its original level
746 gBS
->RestoreTPL (OldTpl
);
748 if (BarLengthValue
!= NULL
) {
749 *BarLengthValue
= Value
;
752 if (OriginalBarValue
!= NULL
) {
753 *OriginalBarValue
= OriginalValue
;
757 return EFI_NOT_FOUND
;
764 Check whether the bar is existed or not.
766 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
767 @param Offset The offset.
768 @param BarLengthValue The bar length value returned.
769 @param OriginalBarValue The original bar value returned.
771 @retval EFI_NOT_FOUND The bar doesn't exist.
772 @retval EFI_SUCCESS The bar exist.
777 IN PCI_IO_DEVICE
*PciIoDevice
,
779 OUT UINT32
*BarLengthValue
,
780 OUT UINT32
*OriginalBarValue
783 EFI_PCI_IO_PROTOCOL
*PciIo
;
784 UINT32 OriginalValue
;
788 PciIo
= &PciIoDevice
->PciIo
;
791 // Preserve the original value
793 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
796 // Raise TPL to high level to disable timer interrupt while the BAR is probed
798 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
800 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &gAllOne
);
801 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &Value
);
804 // Write back the original value
806 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
809 // Restore TPL to its original level
811 gBS
->RestoreTPL (OldTpl
);
813 if (BarLengthValue
!= NULL
) {
814 *BarLengthValue
= Value
;
817 if (OriginalBarValue
!= NULL
) {
818 *OriginalBarValue
= OriginalValue
;
822 return EFI_NOT_FOUND
;
829 Test whether the device can support given attributes.
831 @param PciIoDevice Pci device instance.
832 @param Command Input command register value, and
833 returned supported register value.
834 @param BridgeControl Inout bridge control value for PPB or P2C, and
835 returned supported bridge control value.
836 @param OldCommand Returned and stored old command register offset.
837 @param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.
841 PciTestSupportedAttribute (
842 IN PCI_IO_DEVICE
*PciIoDevice
,
843 IN OUT UINT16
*Command
,
844 IN OUT UINT16
*BridgeControl
,
845 OUT UINT16
*OldCommand
,
846 OUT UINT16
*OldBridgeControl
852 // Preserve the original value
854 PCI_READ_COMMAND_REGISTER (PciIoDevice
, OldCommand
);
857 // Raise TPL to high level to disable timer interrupt while the BAR is probed
859 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
861 PCI_SET_COMMAND_REGISTER (PciIoDevice
, *Command
);
862 PCI_READ_COMMAND_REGISTER (PciIoDevice
, Command
);
865 // Write back the original value
867 PCI_SET_COMMAND_REGISTER (PciIoDevice
, *OldCommand
);
870 // Restore TPL to its original level
872 gBS
->RestoreTPL (OldTpl
);
874 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
877 // Preserve the original value
879 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, OldBridgeControl
);
882 // Raise TPL to high level to disable timer interrupt while the BAR is probed
884 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
886 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *BridgeControl
);
887 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, BridgeControl
);
890 // Write back the original value
892 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *OldBridgeControl
);
895 // Restore TPL to its original level
897 gBS
->RestoreTPL (OldTpl
);
900 *OldBridgeControl
= 0;
906 Set the supported or current attributes of a PCI device.
908 @param PciIoDevice Structure pointer for PCI device.
909 @param Command Command register value.
910 @param BridgeControl Bridge control value for PPB or P2C.
911 @param Option Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.
915 PciSetDeviceAttribute (
916 IN PCI_IO_DEVICE
*PciIoDevice
,
918 IN UINT16 BridgeControl
,
926 if ((Command
& EFI_PCI_COMMAND_IO_SPACE
) != 0) {
927 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IO
;
930 if ((Command
& EFI_PCI_COMMAND_MEMORY_SPACE
) != 0) {
931 Attributes
|= EFI_PCI_IO_ATTRIBUTE_MEMORY
;
934 if ((Command
& EFI_PCI_COMMAND_BUS_MASTER
) != 0) {
935 Attributes
|= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
;
938 if ((Command
& EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
) != 0) {
939 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
942 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_ISA
) != 0) {
943 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_IO
;
946 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA
) != 0) {
947 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO
;
948 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
949 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
952 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA_16
) != 0) {
953 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
;
954 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
;
957 if (Option
== EFI_SET_SUPPORTS
) {
959 Attributes
|= (UINT64
) (EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE
|
960 EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED
|
961 EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE
|
962 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
963 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
964 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
966 if (IS_PCI_LPC (&PciIoDevice
->Pci
)) {
967 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO
;
968 Attributes
|= (mReserveIsaAliases
? (UINT64
) EFI_PCI_IO_ATTRIBUTE_ISA_IO
: \
969 (UINT64
) EFI_PCI_IO_ATTRIBUTE_ISA_IO_16
);
972 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
974 // For bridge, it should support IDE attributes
976 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
977 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
979 if (mReserveVgaAliases
) {
980 Attributes
&= ~(UINT64
)(EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
| \
981 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
);
983 Attributes
&= ~(UINT64
)(EFI_PCI_IO_ATTRIBUTE_VGA_IO
| \
984 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
);
988 if (IS_PCI_IDE (&PciIoDevice
->Pci
)) {
989 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
990 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
993 if (IS_PCI_VGA (&PciIoDevice
->Pci
)) {
994 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
995 Attributes
|= (mReserveVgaAliases
? (UINT64
) EFI_PCI_IO_ATTRIBUTE_VGA_IO
: \
996 (UINT64
) EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
);
1000 PciIoDevice
->Supports
= Attributes
;
1001 PciIoDevice
->Supports
&= ( (PciIoDevice
->Parent
->Supports
) | \
1002 EFI_PCI_IO_ATTRIBUTE_IO
| EFI_PCI_IO_ATTRIBUTE_MEMORY
| \
1003 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
);
1007 // When this attribute is clear, the RomImage and RomSize fields in the PCI IO were
1008 // initialized based on the PCI option ROM found through the ROM BAR of the PCI controller.
1009 // When this attribute is set, the PCI option ROM described by the RomImage and RomSize
1010 // fields is not from the the ROM BAR of the PCI controller.
1012 if (!PciIoDevice
->EmbeddedRom
) {
1013 Attributes
|= EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
;
1015 PciIoDevice
->Attributes
= Attributes
;
1020 Determine if the device can support Fast Back to Back attribute.
1022 @param PciIoDevice Pci device instance.
1023 @param StatusIndex Status register value.
1025 @retval EFI_SUCCESS This device support Fast Back to Back attribute.
1026 @retval EFI_UNSUPPORTED This device doesn't support Fast Back to Back attribute.
1030 GetFastBackToBackSupport (
1031 IN PCI_IO_DEVICE
*PciIoDevice
,
1032 IN UINT8 StatusIndex
1035 EFI_PCI_IO_PROTOCOL
*PciIo
;
1037 UINT32 StatusRegister
;
1040 // Read the status register
1042 PciIo
= &PciIoDevice
->PciIo
;
1043 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint16
, StatusIndex
, 1, &StatusRegister
);
1044 if (EFI_ERROR (Status
)) {
1045 return EFI_UNSUPPORTED
;
1049 // Check the Fast B2B bit
1051 if ((StatusRegister
& EFI_PCI_FAST_BACK_TO_BACK_CAPABLE
) != 0) {
1054 return EFI_UNSUPPORTED
;
1059 Process the option ROM for all the children of the specified parent PCI device.
1060 It can only be used after the first full Option ROM process.
1062 @param PciIoDevice Pci device instance.
1066 ProcessOptionRomLight (
1067 IN PCI_IO_DEVICE
*PciIoDevice
1070 PCI_IO_DEVICE
*Temp
;
1071 LIST_ENTRY
*CurrentLink
;
1074 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1076 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1077 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1079 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1081 if (!IsListEmpty (&Temp
->ChildList
)) {
1082 ProcessOptionRomLight (Temp
);
1085 PciRomGetImageMapping (Temp
);
1088 // The OpRom has already been processed in the first round
1090 Temp
->AllOpRomProcessed
= TRUE
;
1092 CurrentLink
= CurrentLink
->ForwardLink
;
1097 Determine the related attributes of all devices under a Root Bridge.
1099 @param PciIoDevice PCI device instance.
1103 DetermineDeviceAttribute (
1104 IN PCI_IO_DEVICE
*PciIoDevice
1108 UINT16 BridgeControl
;
1110 UINT16 OldBridgeControl
;
1111 BOOLEAN FastB2BSupport
;
1112 PCI_IO_DEVICE
*Temp
;
1113 LIST_ENTRY
*CurrentLink
;
1117 // For Root Bridge, just copy it by RootBridgeIo proctocol
1118 // so as to keep consistent with the actual attribute
1120 if (PciIoDevice
->Parent
== NULL
) {
1121 Status
= PciIoDevice
->PciRootBridgeIo
->GetAttributes (
1122 PciIoDevice
->PciRootBridgeIo
,
1123 &PciIoDevice
->Supports
,
1124 &PciIoDevice
->Attributes
1126 if (EFI_ERROR (Status
)) {
1130 // Assume the PCI Root Bridge supports DAC
1132 PciIoDevice
->Supports
|= (UINT64
)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
1133 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
1134 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1139 // Set the attributes to be checked for common PCI devices and PPB or P2C
1140 // Since some devices only support part of them, it is better to set the
1141 // attribute according to its command or bridge control register
1143 Command
= EFI_PCI_COMMAND_IO_SPACE
|
1144 EFI_PCI_COMMAND_MEMORY_SPACE
|
1145 EFI_PCI_COMMAND_BUS_MASTER
|
1146 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
;
1148 BridgeControl
= EFI_PCI_BRIDGE_CONTROL_ISA
| EFI_PCI_BRIDGE_CONTROL_VGA
| EFI_PCI_BRIDGE_CONTROL_VGA_16
;
1151 // Test whether the device can support attributes above
1153 PciTestSupportedAttribute (PciIoDevice
, &Command
, &BridgeControl
, &OldCommand
, &OldBridgeControl
);
1156 // Set the supported attributes for specified PCI device
1158 PciSetDeviceAttribute (PciIoDevice
, Command
, BridgeControl
, EFI_SET_SUPPORTS
);
1161 // Set the current attributes for specified PCI device
1163 PciSetDeviceAttribute (PciIoDevice
, OldCommand
, OldBridgeControl
, EFI_SET_ATTRIBUTES
);
1166 // Enable other supported attributes but not defined in PCI_IO_PROTOCOL
1168 PCI_ENABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE
);
1171 FastB2BSupport
= TRUE
;
1174 // P2C can not support FB2B on the secondary side
1176 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
1177 FastB2BSupport
= FALSE
;
1181 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1183 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1184 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1186 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1187 Status
= DetermineDeviceAttribute (Temp
);
1188 if (EFI_ERROR (Status
)) {
1192 // Detect Fast Bact to Bact support for the device under the bridge
1194 Status
= GetFastBackToBackSupport (Temp
, PCI_PRIMARY_STATUS_OFFSET
);
1195 if (FastB2BSupport
&& EFI_ERROR (Status
)) {
1196 FastB2BSupport
= FALSE
;
1199 CurrentLink
= CurrentLink
->ForwardLink
;
1202 // Set or clear Fast Back to Back bit for the whole bridge
1204 if (!IsListEmpty (&PciIoDevice
->ChildList
)) {
1206 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
1208 Status
= GetFastBackToBackSupport (PciIoDevice
, PCI_BRIDGE_STATUS_REGISTER_OFFSET
);
1210 if (EFI_ERROR (Status
) || (!FastB2BSupport
)) {
1211 FastB2BSupport
= FALSE
;
1212 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1214 PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1218 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1219 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1220 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1221 if (FastB2BSupport
) {
1222 PCI_ENABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1224 PCI_DISABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1227 CurrentLink
= CurrentLink
->ForwardLink
;
1231 // End for IsListEmpty
1237 This routine is used to update the bar information for those incompatible PCI device.
1239 @param PciIoDevice Input Pci device instance. Output Pci device instance with updated
1242 @retval EFI_SUCCESS Successfully updated bar information.
1243 @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.
1248 IN OUT PCI_IO_DEVICE
*PciIoDevice
1255 VOID
*Configuration
;
1256 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1258 Configuration
= NULL
;
1259 Status
= EFI_SUCCESS
;
1261 if (gEfiIncompatiblePciDeviceSupport
== NULL
) {
1263 // It can only be supported after the Incompatible PCI Device
1264 // Support Protocol has been installed
1266 Status
= gBS
->LocateProtocol (
1267 &gEfiIncompatiblePciDeviceSupportProtocolGuid
,
1269 (VOID
**) &gEfiIncompatiblePciDeviceSupport
1272 if (Status
== EFI_SUCCESS
) {
1274 // Check whether the device belongs to incompatible devices from protocol or not
1275 // If it is , then get its special requirement in the ACPI table
1277 Status
= gEfiIncompatiblePciDeviceSupport
->CheckDevice (
1278 gEfiIncompatiblePciDeviceSupport
,
1279 PciIoDevice
->Pci
.Hdr
.VendorId
,
1280 PciIoDevice
->Pci
.Hdr
.DeviceId
,
1281 PciIoDevice
->Pci
.Hdr
.RevisionID
,
1282 PciIoDevice
->Pci
.Device
.SubsystemVendorID
,
1283 PciIoDevice
->Pci
.Device
.SubsystemID
,
1289 if (EFI_ERROR (Status
) || Configuration
== NULL
) {
1290 return EFI_UNSUPPORTED
;
1294 // Update PCI device information from the ACPI table
1296 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Configuration
;
1298 while (Ptr
->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
1300 if (Ptr
->Desc
!= ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
1302 // The format is not support
1307 BarIndex
= (UINTN
) Ptr
->AddrTranslationOffset
;
1308 BarEndIndex
= BarIndex
;
1311 // Update all the bars in the device
1313 if (BarIndex
== PCI_BAR_ALL
) {
1315 BarEndIndex
= PCI_MAX_BAR
- 1;
1318 if (BarIndex
> PCI_MAX_BAR
) {
1323 for (; BarIndex
<= BarEndIndex
; BarIndex
++) {
1325 switch (Ptr
->ResType
) {
1326 case ACPI_ADDRESS_SPACE_TYPE_MEM
:
1329 // Make sure the bar is memory type
1331 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeMem
)) {
1336 case ACPI_ADDRESS_SPACE_TYPE_IO
:
1339 // Make sure the bar is IO type
1341 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeIo
)) {
1350 // Update the new alignment for the device
1352 SetNewAlign (&(PciIoDevice
->PciBar
[BarIndex
].Alignment
), Ptr
->AddrRangeMax
);
1355 // Update the new length for the device
1357 if (Ptr
->AddrLen
!= PCI_BAR_NOCHANGE
) {
1358 PciIoDevice
->PciBar
[BarIndex
].Length
= Ptr
->AddrLen
;
1366 FreePool (Configuration
);
1372 This routine will update the alignment with the new alignment.
1374 @param Alignment Input Old alignment. Output updated alignment.
1375 @param NewAlignment New alignment.
1380 IN OUT UINT64
*Alignment
,
1381 IN UINT64 NewAlignment
1384 UINT64 OldAlignment
;
1388 // The new alignment is the same as the original,
1391 if (NewAlignment
== PCI_BAR_OLD_ALIGN
) {
1395 // Check the validity of the parameter
1397 if (NewAlignment
!= PCI_BAR_EVEN_ALIGN
&&
1398 NewAlignment
!= PCI_BAR_SQUAD_ALIGN
&&
1399 NewAlignment
!= PCI_BAR_DQUAD_ALIGN
) {
1400 *Alignment
= NewAlignment
;
1404 OldAlignment
= (*Alignment
) + 1;
1408 // Get the first non-zero hex value of the length
1410 while ((OldAlignment
& 0x0F) == 0x00) {
1411 OldAlignment
= RShiftU64 (OldAlignment
, 4);
1416 // Adjust the alignment to even, quad or double quad boundary
1418 if (NewAlignment
== PCI_BAR_EVEN_ALIGN
) {
1419 if ((OldAlignment
& 0x01) != 0) {
1420 OldAlignment
= OldAlignment
+ 2 - (OldAlignment
& 0x01);
1422 } else if (NewAlignment
== PCI_BAR_SQUAD_ALIGN
) {
1423 if ((OldAlignment
& 0x03) != 0) {
1424 OldAlignment
= OldAlignment
+ 4 - (OldAlignment
& 0x03);
1426 } else if (NewAlignment
== PCI_BAR_DQUAD_ALIGN
) {
1427 if ((OldAlignment
& 0x07) != 0) {
1428 OldAlignment
= OldAlignment
+ 8 - (OldAlignment
& 0x07);
1433 // Update the old value
1435 NewAlignment
= LShiftU64 (OldAlignment
, ShiftBit
) - 1;
1436 *Alignment
= NewAlignment
;
1442 Parse PCI IOV VF bar information and fill them into PCI device instance.
1444 @param PciIoDevice Pci device instance.
1445 @param Offset Bar offset.
1446 @param BarIndex Bar index.
1448 @return Next bar offset.
1453 IN PCI_IO_DEVICE
*PciIoDevice
,
1459 UINT32 OriginalValue
;
1464 // Ensure it is called properly
1466 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
1467 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
1474 Status
= VfBarExisted (
1481 if (EFI_ERROR (Status
)) {
1482 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1483 PciIoDevice
->VfPciBar
[BarIndex
].Length
= 0;
1484 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1487 // Scan all the BARs anyway
1489 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
) Offset
;
1493 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
) Offset
;
1494 if ((Value
& 0x01) != 0) {
1496 // Device I/Os. Impossible
1505 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1507 switch (Value
& 0x07) {
1510 //memory space; anywhere in 32 bit address space
1513 if ((Value
& 0x08) != 0) {
1514 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1516 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1519 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1520 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1525 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1529 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1530 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1536 // memory space; anywhere in 64 bit address space
1539 if ((Value
& 0x08) != 0) {
1540 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1542 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1546 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1547 // is regarded as an extension for the first bar. As a result
1548 // the sizing will be conducted on combined 64 bit value
1549 // Here just store the masked first 32bit value for future size
1552 PciIoDevice
->VfPciBar
[BarIndex
].Length
= Value
& Mask
;
1553 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1555 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1556 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1560 // Increment the offset to point to next DWORD
1564 Status
= VfBarExisted (
1571 if (EFI_ERROR (Status
)) {
1576 // Fix the length to support some spefic 64 bit BAR
1578 Value
|= ((UINT32
) -1 << HighBitSet32 (Value
));
1581 // Calculate the size of 64bit bar
1583 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
) OriginalValue
, 32);
1585 PciIoDevice
->VfPciBar
[BarIndex
].Length
= PciIoDevice
->VfPciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
) Value
, 32);
1586 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(PciIoDevice
->VfPciBar
[BarIndex
].Length
)) + 1;
1587 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1592 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1596 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1597 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1606 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1607 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1608 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1610 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1611 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1619 // Check the length again so as to keep compatible with some special bars
1621 if (PciIoDevice
->VfPciBar
[BarIndex
].Length
== 0) {
1622 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1623 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1624 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1628 // Increment number of bar
1634 Parse PCI bar information and fill them into PCI device instance.
1636 @param PciIoDevice Pci device instance.
1637 @param Offset Bar offset.
1638 @param BarIndex Bar index.
1640 @return Next bar offset.
1645 IN PCI_IO_DEVICE
*PciIoDevice
,
1651 UINT32 OriginalValue
;
1658 Status
= BarExisted (
1665 if (EFI_ERROR (Status
)) {
1666 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1667 PciIoDevice
->PciBar
[BarIndex
].Length
= 0;
1668 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1671 // Some devices don't fully comply to PCI spec 2.2. So be to scan all the BARs anyway
1673 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1677 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1678 if ((Value
& 0x01) != 0) {
1684 if ((Value
& 0xFFFF0000) != 0) {
1688 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo32
;
1689 PciIoDevice
->PciBar
[BarIndex
].Length
= ((~(Value
& Mask
)) + 1);
1690 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1696 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo16
;
1697 PciIoDevice
->PciBar
[BarIndex
].Length
= 0x0000FFFF & ((~(Value
& Mask
)) + 1);
1698 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1702 // Workaround. Some platforms inplement IO bar with 0 length
1703 // Need to treat it as no-bar
1705 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1706 PciIoDevice
->PciBar
[BarIndex
].BarType
= (PCI_BAR_TYPE
) 0;
1709 PciIoDevice
->PciBar
[BarIndex
].Prefetchable
= FALSE
;
1710 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1716 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1718 switch (Value
& 0x07) {
1721 //memory space; anywhere in 32 bit address space
1724 if ((Value
& 0x08) != 0) {
1725 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1727 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1730 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1731 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1733 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1735 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1737 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1742 // memory space; anywhere in 64 bit address space
1745 if ((Value
& 0x08) != 0) {
1746 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1748 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1752 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1753 // is regarded as an extension for the first bar. As a result
1754 // the sizing will be conducted on combined 64 bit value
1755 // Here just store the masked first 32bit value for future size
1758 PciIoDevice
->PciBar
[BarIndex
].Length
= Value
& Mask
;
1759 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1762 // Increment the offset to point to next DWORD
1766 Status
= BarExisted (
1773 if (EFI_ERROR (Status
)) {
1775 // the high 32 bit does not claim any BAR, we need to re-check the low 32 bit BAR again
1777 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1779 // some device implement MMIO bar with 0 length, need to treat it as no-bar
1781 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1787 // Fix the length to support some spefic 64 bit BAR
1790 DEBUG ((EFI_D_INFO
, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
1791 Value
= (UINT32
) -1;
1793 Value
|= ((UINT32
)(-1) << HighBitSet32 (Value
));
1797 // Calculate the size of 64bit bar
1799 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
) OriginalValue
, 32);
1801 PciIoDevice
->PciBar
[BarIndex
].Length
= PciIoDevice
->PciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
) Value
, 32);
1802 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(PciIoDevice
->PciBar
[BarIndex
].Length
)) + 1;
1803 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1805 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1807 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1809 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1818 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1819 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1820 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1822 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1824 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1826 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1833 // Check the length again so as to keep compatible with some special bars
1835 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1836 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1837 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1838 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1842 // Increment number of bar
1848 This routine is used to initialize the bar of a PCI device.
1850 @param PciIoDevice Pci device instance.
1852 @note It can be called typically when a device is going to be rejected.
1856 InitializePciDevice (
1857 IN PCI_IO_DEVICE
*PciIoDevice
1860 EFI_PCI_IO_PROTOCOL
*PciIo
;
1863 PciIo
= &(PciIoDevice
->PciIo
);
1866 // Put all the resource apertures
1867 // Resource base is set to all ones so as to indicate its resource
1868 // has not been alloacted
1870 for (Offset
= 0x10; Offset
<= 0x24; Offset
+= sizeof (UINT32
)) {
1871 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, Offset
, 1, &gAllOne
);
1876 This routine is used to initialize the bar of a PCI-PCI Bridge device.
1878 @param PciIoDevice PCI-PCI bridge device instance.
1883 IN PCI_IO_DEVICE
*PciIoDevice
1886 EFI_PCI_IO_PROTOCOL
*PciIo
;
1888 PciIo
= &(PciIoDevice
->PciIo
);
1891 // Put all the resource apertures including IO16
1892 // Io32, pMem32, pMem64 to quiescent state
1893 // Resource base all ones, Resource limit all zeros
1895 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
1896 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1D, 1, &gAllZero
);
1898 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x20, 1, &gAllOne
);
1899 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x22, 1, &gAllZero
);
1901 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x24, 1, &gAllOne
);
1902 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x26, 1, &gAllZero
);
1904 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllOne
);
1905 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2C, 1, &gAllZero
);
1908 // Don't support use io32 as for now
1910 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x30, 1, &gAllOne
);
1911 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x32, 1, &gAllZero
);
1914 // Force Interrupt line to zero for cards that come up randomly
1916 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
1920 This routine is used to initialize the bar of a PCI Card Bridge device.
1922 @param PciIoDevice PCI Card bridge device.
1927 IN PCI_IO_DEVICE
*PciIoDevice
1930 EFI_PCI_IO_PROTOCOL
*PciIo
;
1932 PciIo
= &(PciIoDevice
->PciIo
);
1935 // Put all the resource apertures including IO16
1936 // Io32, pMem32, pMem64 to quiescent state(
1937 // Resource base all ones, Resource limit all zeros
1939 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x1c, 1, &gAllOne
);
1940 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x20, 1, &gAllZero
);
1942 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x24, 1, &gAllOne
);
1943 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllZero
);
1945 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2c, 1, &gAllOne
);
1946 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x30, 1, &gAllZero
);
1948 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x34, 1, &gAllOne
);
1949 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x38, 1, &gAllZero
);
1952 // Force Interrupt line to zero for cards that come up randomly
1954 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
1958 Create and initiliaze general PCI I/O device instance for
1959 PCI device/bridge device/hotplug bridge device.
1961 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1962 @param Pci Input Pci information block.
1963 @param Bus Device Bus NO.
1964 @param Device Device device NO.
1965 @param Func Device func NO.
1967 @return Instance of PCI device. NULL means no instance created.
1972 IN PCI_IO_DEVICE
*Bridge
,
1979 PCI_IO_DEVICE
*PciIoDevice
;
1980 EFI_PCI_IO_PROTOCOL
*PciIo
;
1983 PciIoDevice
= AllocateZeroPool (sizeof (PCI_IO_DEVICE
));
1984 if (PciIoDevice
== NULL
) {
1988 PciIoDevice
->Signature
= PCI_IO_DEVICE_SIGNATURE
;
1989 PciIoDevice
->Handle
= NULL
;
1990 PciIoDevice
->PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
1991 PciIoDevice
->DevicePath
= NULL
;
1992 PciIoDevice
->BusNumber
= Bus
;
1993 PciIoDevice
->DeviceNumber
= Device
;
1994 PciIoDevice
->FunctionNumber
= Func
;
1995 PciIoDevice
->Decodes
= 0;
1997 if (gFullEnumeration
) {
1998 PciIoDevice
->Allocated
= FALSE
;
2000 PciIoDevice
->Allocated
= TRUE
;
2003 PciIoDevice
->Registered
= FALSE
;
2004 PciIoDevice
->Attributes
= 0;
2005 PciIoDevice
->Supports
= 0;
2006 PciIoDevice
->BusOverride
= FALSE
;
2007 PciIoDevice
->AllOpRomProcessed
= FALSE
;
2009 PciIoDevice
->IsPciExp
= FALSE
;
2011 CopyMem (&(PciIoDevice
->Pci
), Pci
, sizeof (PCI_TYPE01
));
2014 // Initialize the PCI I/O instance structure
2016 InitializePciIoInstance (PciIoDevice
);
2017 InitializePciDriverOverrideInstance (PciIoDevice
);
2018 InitializePciLoadFile2 (PciIoDevice
);
2019 PciIo
= &PciIoDevice
->PciIo
;
2022 // Create a device path for this PCI device and store it into its private data
2024 CreatePciDevicePath (
2030 // Detect if PCI Express Device
2032 PciIoDevice
->PciExpressCapabilityOffset
= 0;
2033 Status
= LocateCapabilityRegBlock (
2035 EFI_PCI_CAPABILITY_ID_PCIEXP
,
2036 &PciIoDevice
->PciExpressCapabilityOffset
,
2039 if (!EFI_ERROR (Status
)) {
2040 PciIoDevice
->IsPciExp
= TRUE
;
2043 if (PcdGetBool (PcdAriSupport
)) {
2045 // Check if the device is an ARI device.
2047 Status
= LocatePciExpressCapabilityRegBlock (
2049 EFI_PCIE_CAPABILITY_ID_ARI
,
2050 &PciIoDevice
->AriCapabilityOffset
,
2053 if (!EFI_ERROR (Status
)) {
2055 // We need to enable ARI feature before calculate BusReservation,
2056 // because FirstVFOffset and VFStride may change after that.
2058 EFI_PCI_IO_PROTOCOL
*ParentPciIo
;
2062 // Check if its parent supports ARI forwarding.
2064 ParentPciIo
= &Bridge
->PciIo
;
2065 ParentPciIo
->Pci
.Read (
2067 EfiPciIoWidthUint32
,
2068 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET
,
2072 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING
) != 0) {
2074 // ARI forward support in bridge, so enable it.
2076 ParentPciIo
->Pci
.Read (
2078 EfiPciIoWidthUint32
,
2079 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2083 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
) == 0) {
2084 Data32
|= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
;
2085 ParentPciIo
->Pci
.Write (
2087 EfiPciIoWidthUint32
,
2088 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2094 " ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",
2096 Bridge
->DeviceNumber
,
2097 Bridge
->FunctionNumber
2102 DEBUG ((EFI_D_INFO
, " ARI: CapOffset = 0x%x\n", PciIoDevice
->AriCapabilityOffset
));
2107 // Initialization for SR-IOV
2110 if (PcdGetBool (PcdSrIovSupport
)) {
2111 Status
= LocatePciExpressCapabilityRegBlock (
2113 EFI_PCIE_CAPABILITY_ID_SRIOV
,
2114 &PciIoDevice
->SrIovCapabilityOffset
,
2117 if (!EFI_ERROR (Status
)) {
2118 UINT32 SupportedPageSize
;
2120 UINT16 FirstVFOffset
;
2126 // If the SR-IOV device is an ARI device, then Set ARI Capable Hierarchy for the device.
2128 if (PcdGetBool (PcdAriSupport
) && PciIoDevice
->AriCapabilityOffset
!= 0) {
2131 EfiPciIoWidthUint16
,
2132 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2136 Data16
|= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY
;
2139 EfiPciIoWidthUint16
,
2140 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2147 // Calculate SystemPageSize
2152 EfiPciIoWidthUint32
,
2153 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE
,
2157 PciIoDevice
->SystemPageSize
= (PcdGet32 (PcdSrIovSystemPageSize
) & SupportedPageSize
);
2158 ASSERT (PciIoDevice
->SystemPageSize
!= 0);
2162 EfiPciIoWidthUint32
,
2163 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE
,
2165 &PciIoDevice
->SystemPageSize
2168 // Adjust SystemPageSize for Alignment usage later
2170 PciIoDevice
->SystemPageSize
<<= 12;
2173 // Calculate BusReservation for PCI IOV
2177 // Read First FirstVFOffset, InitialVFs, and VFStride
2181 EfiPciIoWidthUint16
,
2182 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF
,
2188 EfiPciIoWidthUint16
,
2189 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS
,
2191 &PciIoDevice
->InitialVFs
2195 EfiPciIoWidthUint16
,
2196 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE
,
2203 PFRid
= EFI_PCI_RID(Bus
, Device
, Func
);
2204 LastVF
= PFRid
+ FirstVFOffset
+ (PciIoDevice
->InitialVFs
- 1) * VFStride
;
2207 // Calculate ReservedBusNum for this PF
2209 PciIoDevice
->ReservedBusNum
= (UINT16
)(EFI_PCI_BUS_OF_RID (LastVF
) - Bus
+ 1);
2213 " SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x; FirstVFOffset = 0x%x;\n",
2214 SupportedPageSize
, PciIoDevice
->SystemPageSize
>> 12, FirstVFOffset
2218 " InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",
2219 PciIoDevice
->InitialVFs
, PciIoDevice
->ReservedBusNum
, PciIoDevice
->SrIovCapabilityOffset
2224 if (PcdGetBool (PcdMrIovSupport
)) {
2225 Status
= LocatePciExpressCapabilityRegBlock (
2227 EFI_PCIE_CAPABILITY_ID_MRIOV
,
2228 &PciIoDevice
->MrIovCapabilityOffset
,
2231 if (!EFI_ERROR (Status
)) {
2232 DEBUG ((EFI_D_INFO
, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice
->MrIovCapabilityOffset
));
2237 // Initialize the reserved resource list
2239 InitializeListHead (&PciIoDevice
->ReservedResourceList
);
2242 // Initialize the driver list
2244 InitializeListHead (&PciIoDevice
->OptionRomDriverList
);
2247 // Initialize the child list
2249 InitializeListHead (&PciIoDevice
->ChildList
);
2255 This routine is used to enumerate entire pci bus system
2256 in a given platform.
2258 It is only called on the second start on the same Root Bridge.
2260 @param Controller Parent bridge handler.
2262 @retval EFI_SUCCESS PCI enumeration finished successfully.
2263 @retval other Some error occurred when enumerating the pci bus system.
2267 PciEnumeratorLight (
2268 IN EFI_HANDLE Controller
2273 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2274 PCI_IO_DEVICE
*RootBridgeDev
;
2277 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2280 MaxBus
= PCI_MAX_BUS
;
2284 // If this root bridge has been already enumerated, then return successfully
2286 if (GetRootBridgeByHandle (Controller
) != NULL
) {
2291 // Open pci root bridge io protocol
2293 Status
= gBS
->OpenProtocol (
2295 &gEfiPciRootBridgeIoProtocolGuid
,
2296 (VOID
**) &PciRootBridgeIo
,
2297 gPciBusDriverBinding
.DriverBindingHandle
,
2299 EFI_OPEN_PROTOCOL_BY_DRIVER
2301 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
2305 Status
= PciRootBridgeIo
->Configuration (PciRootBridgeIo
, (VOID
**) &Descriptors
);
2307 if (EFI_ERROR (Status
)) {
2311 while (PciGetBusRange (&Descriptors
, &MinBus
, &MaxBus
, NULL
) == EFI_SUCCESS
) {
2314 // Create a device node for root bridge device with a NULL host bridge controller handle
2316 RootBridgeDev
= CreateRootBridge (Controller
);
2318 if (RootBridgeDev
== NULL
) {
2324 // Record the root bridgeio protocol
2326 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2328 Status
= PciPciDeviceInfoCollector (
2333 if (!EFI_ERROR (Status
)) {
2336 // Remove those PCI devices which are rejected when full enumeration
2338 RemoveRejectedPciDevices (RootBridgeDev
->Handle
, RootBridgeDev
);
2341 // Process option rom light
2343 ProcessOptionRomLight (RootBridgeDev
);
2346 // Determine attributes for all devices under this root bridge
2348 DetermineDeviceAttribute (RootBridgeDev
);
2351 // If successfully, insert the node into device pool
2353 InsertRootBridge (RootBridgeDev
);
2357 // If unsuccessly, destroy the entire node
2359 DestroyRootBridge (RootBridgeDev
);
2369 Get bus range from PCI resource descriptor list.
2371 @param Descriptors A pointer to the address space descriptor.
2372 @param MinBus The min bus returned.
2373 @param MaxBus The max bus returned.
2374 @param BusRange The bus range returned.
2376 @retval EFI_SUCCESS Successfully got bus range.
2377 @retval EFI_NOT_FOUND Can not find the specific bus.
2382 IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
2385 OUT UINT16
*BusRange
2388 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
2389 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
2390 if (MinBus
!= NULL
) {
2391 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
2394 if (MaxBus
!= NULL
) {
2395 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
2398 if (BusRange
!= NULL
) {
2399 *BusRange
= (UINT16
) (*Descriptors
)->AddrLen
;
2408 return EFI_NOT_FOUND
;
2412 This routine can be used to start the root bridge.
2414 @param RootBridgeDev Pci device instance.
2416 @retval EFI_SUCCESS This device started.
2417 @retval other Failed to get PCI Root Bridge I/O protocol.
2421 StartManagingRootBridge (
2422 IN PCI_IO_DEVICE
*RootBridgeDev
2425 EFI_HANDLE RootBridgeHandle
;
2427 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2430 // Get the root bridge handle
2432 RootBridgeHandle
= RootBridgeDev
->Handle
;
2433 PciRootBridgeIo
= NULL
;
2436 // Get the pci root bridge io protocol
2438 Status
= gBS
->OpenProtocol (
2440 &gEfiPciRootBridgeIoProtocolGuid
,
2441 (VOID
**) &PciRootBridgeIo
,
2442 gPciBusDriverBinding
.DriverBindingHandle
,
2444 EFI_OPEN_PROTOCOL_BY_DRIVER
2447 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
2452 // Store the PciRootBridgeIo protocol into root bridge private data
2454 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2461 This routine can be used to check whether a PCI device should be rejected when light enumeration.
2463 @param PciIoDevice Pci device instance.
2465 @retval TRUE This device should be rejected.
2466 @retval FALSE This device shouldn't be rejected.
2470 IsPciDeviceRejected (
2471 IN PCI_IO_DEVICE
*PciIoDevice
2481 // PPB should be skip!
2483 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
2487 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
2489 // Only test base registers for P2C
2491 for (BarOffset
= 0x1C; BarOffset
<= 0x38; BarOffset
+= 2 * sizeof (UINT32
)) {
2493 Mask
= (BarOffset
< 0x2C) ? 0xFFFFF000 : 0xFFFFFFFC;
2494 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2495 if (EFI_ERROR (Status
)) {
2499 TestValue
= TestValue
& Mask
;
2500 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2502 // The bar isn't programed, so it should be rejected
2511 for (BarOffset
= 0x14; BarOffset
<= 0x24; BarOffset
+= sizeof (UINT32
)) {
2515 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2516 if (EFI_ERROR (Status
)) {
2520 if ((TestValue
& 0x01) != 0) {
2526 TestValue
= TestValue
& Mask
;
2527 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2537 TestValue
= TestValue
& Mask
;
2539 if ((TestValue
& 0x07) == 0x04) {
2544 BarOffset
+= sizeof (UINT32
);
2545 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2548 // Test its high 32-Bit BAR
2550 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2551 if (TestValue
== OldValue
) {
2561 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2572 Reset all bus number from specific bridge.
2574 @param Bridge Parent specific bridge.
2575 @param StartBusNumber Start bus number.
2579 ResetAllPpbBusNumber (
2580 IN PCI_IO_DEVICE
*Bridge
,
2581 IN UINT8 StartBusNumber
2591 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2593 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
2595 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2596 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2599 // Check to see whether a pci device is present
2601 Status
= PciDevicePresent (
2609 if (EFI_ERROR (Status
) && Func
== 0) {
2611 // go to next device if there is no Function 0
2616 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
))) {
2619 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x18);
2620 Status
= PciRootBridgeIo
->Pci
.Read (
2627 SecondaryBus
= (UINT8
)(Register
>> 8);
2629 if (SecondaryBus
!= 0) {
2630 ResetAllPpbBusNumber (Bridge
, SecondaryBus
);
2634 // Reset register 18h, 19h, 1Ah on PCI Bridge
2636 Register
&= 0xFF000000;
2637 Status
= PciRootBridgeIo
->Pci
.Write (
2646 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
2648 // Skip sub functions, this is not a multi function device
2650 Func
= PCI_MAX_FUNC
;