2 PCI emumeration support functions implementation for PCI Bus module.
4 Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
12 extern CHAR16
*mBarTypeStr
[];
13 extern EDKII_DEVICE_SECURITY_PROTOCOL
*mDeviceSecurityProtocol
;
15 #define OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
16 #define EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
17 #define SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
18 #define DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
21 This routine is used to check whether the pci device is present.
23 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
24 @param Pci Output buffer for PCI device configuration space.
25 @param Bus PCI bus NO.
26 @param Device PCI device NO.
27 @param Func PCI Func NO.
29 @retval EFI_NOT_FOUND PCI device not present.
30 @retval EFI_SUCCESS PCI device is found.
35 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
,
46 // Create PCI address map in terms of Bus, Device and Func
48 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
51 // Read the Vendor ID register
53 Status
= PciRootBridgeIo
->Pci
.Read (
61 if (!EFI_ERROR (Status
) && (Pci
->Hdr
).VendorId
!= 0xffff) {
63 // Read the entire config header for the device
65 Status
= PciRootBridgeIo
->Pci
.Read (
69 sizeof (PCI_TYPE00
) / sizeof (UINT32
),
80 Collect all the resource information under this root bridge.
82 A database that records all the information about pci device subject to this
83 root bridge will then be created.
85 @param Bridge Parent bridge instance.
86 @param StartBusNumber Bus number of beginning.
88 @retval EFI_SUCCESS PCI device is found.
89 @retval other Some error occurred when reading PCI bridge information.
93 PciPciDeviceInfoCollector (
94 IN PCI_IO_DEVICE
*Bridge
,
95 IN UINT8 StartBusNumber
103 PCI_IO_DEVICE
*PciIoDevice
;
104 EFI_PCI_IO_PROTOCOL
*PciIo
;
106 Status
= EFI_SUCCESS
;
109 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
111 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
114 // Check to see whether PCI device is present
116 Status
= PciDevicePresent (
117 Bridge
->PciRootBridgeIo
,
119 (UINT8
) StartBusNumber
,
124 if (EFI_ERROR (Status
) && Func
== 0) {
126 // go to next device if there is no Function 0
131 if (!EFI_ERROR (Status
)) {
134 // Call back to host bridge function
136 PreprocessController (Bridge
, (UINT8
) StartBusNumber
, Device
, Func
, EfiPciBeforeResourceCollection
);
139 // Collect all the information about the PCI device discovered
141 Status
= PciSearchDevice (
144 (UINT8
) StartBusNumber
,
151 // Recursively scan PCI busses on the other side of PCI-PCI bridges
154 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
) || IS_CARDBUS_BRIDGE (&Pci
))) {
157 // If it is PPB, we need to get the secondary bus to continue the enumeration
159 PciIo
= &(PciIoDevice
->PciIo
);
161 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
, 1, &SecBus
);
163 if (EFI_ERROR (Status
)) {
168 // Ensure secondary bus number is greater than the primary bus number to avoid
169 // any potential dead loop when PcdPciDisableBusEnumeration is set to TRUE
171 if (SecBus
<= StartBusNumber
) {
176 // Get resource padding for PPB
178 GetResourcePaddingPpb (PciIoDevice
);
181 // Deep enumerate the next level bus
183 Status
= PciPciDeviceInfoCollector (
190 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
193 // Skip sub functions, this is not a multi function device
206 Search required device and create PCI device instance.
208 @param Bridge Parent bridge instance.
209 @param Pci Input PCI device information block.
210 @param Bus PCI bus NO.
211 @param Device PCI device NO.
212 @param Func PCI func NO.
213 @param PciDevice Output of searched PCI device instance.
215 @retval EFI_SUCCESS Successfully created PCI device instance.
216 @retval EFI_OUT_OF_RESOURCES Cannot get PCI device information.
221 IN PCI_IO_DEVICE
*Bridge
,
226 OUT PCI_IO_DEVICE
**PciDevice
229 PCI_IO_DEVICE
*PciIoDevice
;
235 "PciBus: Discovered %s @ [%02x|%02x|%02x]\n",
236 IS_PCI_BRIDGE (Pci
) ? L
"PPB" :
237 IS_CARDBUS_BRIDGE (Pci
) ? L
"P2C" :
242 if (!IS_PCI_BRIDGE (Pci
)) {
244 if (IS_CARDBUS_BRIDGE (Pci
)) {
245 PciIoDevice
= GatherP2CInfo (
252 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
253 InitializeP2C (PciIoDevice
);
258 // Create private data for Pci Device
260 PciIoDevice
= GatherDeviceInfo (
273 // Create private data for PPB
275 PciIoDevice
= GatherPpbInfo (
284 // Special initialization for PPB including making the PPB quiet
286 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
287 InitializePpb (PciIoDevice
);
291 if (PciIoDevice
== NULL
) {
292 return EFI_OUT_OF_RESOURCES
;
296 // Update the bar information for this PCI device so as to support some specific device
298 UpdatePciInfo (PciIoDevice
);
300 if (PciIoDevice
->DevicePath
== NULL
) {
301 return EFI_OUT_OF_RESOURCES
;
305 // Detect this function has option rom
307 if (gFullEnumeration
) {
309 if (!IS_CARDBUS_BRIDGE (Pci
)) {
311 GetOpRomInfo (PciIoDevice
);
315 ResetPowerManagementFeature (PciIoDevice
);
320 // Insert it into a global tree for future reference
322 InsertPciDevice (Bridge
, PciIoDevice
);
325 // Determine PCI device attributes
328 if (PciDevice
!= NULL
) {
329 *PciDevice
= PciIoDevice
;
336 Dump the PPB padding resource information.
338 @param PciIoDevice PCI IO instance.
339 @param ResourceType The desired resource type to dump.
340 PciBarTypeUnknown means to dump all types of resources.
343 DumpPpbPaddingResource (
344 IN PCI_IO_DEVICE
*PciIoDevice
,
345 IN PCI_BAR_TYPE ResourceType
348 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptor
;
351 if (PciIoDevice
->ResourcePaddingDescriptors
== NULL
) {
355 if (ResourceType
== PciBarTypeIo16
|| ResourceType
== PciBarTypeIo32
) {
356 ResourceType
= PciBarTypeIo
;
359 for (Descriptor
= PciIoDevice
->ResourcePaddingDescriptors
; Descriptor
->Desc
!= ACPI_END_TAG_DESCRIPTOR
; Descriptor
++) {
361 Type
= PciBarTypeUnknown
;
362 if (Descriptor
->Desc
== ACPI_ADDRESS_SPACE_DESCRIPTOR
&& Descriptor
->ResType
== ACPI_ADDRESS_SPACE_TYPE_IO
) {
364 } else if (Descriptor
->Desc
== ACPI_ADDRESS_SPACE_DESCRIPTOR
&& Descriptor
->ResType
== ACPI_ADDRESS_SPACE_TYPE_MEM
) {
366 if (Descriptor
->AddrSpaceGranularity
== 32) {
370 if (Descriptor
->SpecificFlag
== EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
) {
371 Type
= PciBarTypePMem32
;
377 if (Descriptor
->SpecificFlag
== 0) {
378 Type
= PciBarTypeMem32
;
382 if (Descriptor
->AddrSpaceGranularity
== 64) {
386 if (Descriptor
->SpecificFlag
== EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
) {
387 Type
= PciBarTypePMem64
;
393 if (Descriptor
->SpecificFlag
== 0) {
394 Type
= PciBarTypeMem64
;
399 if ((Type
!= PciBarTypeUnknown
) && ((ResourceType
== PciBarTypeUnknown
) || (ResourceType
== Type
))) {
402 " Padding: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx\n",
403 mBarTypeStr
[Type
], Descriptor
->AddrRangeMax
, Descriptor
->AddrLen
411 Dump the PCI BAR information.
413 @param PciIoDevice PCI IO instance.
417 IN PCI_IO_DEVICE
*PciIoDevice
422 for (Index
= 0; Index
< PCI_MAX_BAR
; Index
++) {
423 if (PciIoDevice
->PciBar
[Index
].BarType
== PciBarTypeUnknown
) {
429 " BAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
430 Index
, mBarTypeStr
[MIN (PciIoDevice
->PciBar
[Index
].BarType
, PciBarTypeMaxType
)],
431 PciIoDevice
->PciBar
[Index
].Alignment
, PciIoDevice
->PciBar
[Index
].Length
, PciIoDevice
->PciBar
[Index
].Offset
435 for (Index
= 0; Index
< PCI_MAX_BAR
; Index
++) {
436 if ((PciIoDevice
->VfPciBar
[Index
].BarType
== PciBarTypeUnknown
) && (PciIoDevice
->VfPciBar
[Index
].Length
== 0)) {
442 " VFBAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
443 Index
, mBarTypeStr
[MIN (PciIoDevice
->VfPciBar
[Index
].BarType
, PciBarTypeMaxType
)],
444 PciIoDevice
->VfPciBar
[Index
].Alignment
, PciIoDevice
->VfPciBar
[Index
].Length
, PciIoDevice
->VfPciBar
[Index
].Offset
447 DEBUG ((EFI_D_INFO
, "\n"));
451 Create PCI device instance for PCI device.
453 @param Bridge Parent bridge instance.
454 @param Pci Input PCI device information block.
455 @param Bus PCI device Bus NO.
456 @param Device PCI device Device NO.
457 @param Func PCI device's func NO.
459 @return Created PCI device instance.
464 IN PCI_IO_DEVICE
*Bridge
,
473 PCI_IO_DEVICE
*PciIoDevice
;
475 PciIoDevice
= CreatePciIoDevice (
483 if (PciIoDevice
== NULL
) {
488 // If it is a full enumeration, disconnect the device in advance
490 if (gFullEnumeration
) {
492 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
497 // Start to parse the bars
499 for (Offset
= 0x10, BarIndex
= 0; Offset
<= 0x24 && BarIndex
< PCI_MAX_BAR
; BarIndex
++) {
500 Offset
= PciParseBar (PciIoDevice
, Offset
, BarIndex
);
504 // Parse the SR-IOV VF bars
506 if (PcdGetBool (PcdSrIovSupport
) && PciIoDevice
->SrIovCapabilityOffset
!= 0) {
507 for (Offset
= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0
, BarIndex
= 0;
508 Offset
<= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5
;
511 ASSERT (BarIndex
< PCI_MAX_BAR
);
512 Offset
= PciIovParseVfBar (PciIoDevice
, Offset
, BarIndex
);
516 DEBUG_CODE (DumpPciBars (PciIoDevice
););
521 Create PCI device instance for PCI-PCI bridge.
523 @param Bridge Parent bridge instance.
524 @param Pci Input PCI device information block.
525 @param Bus PCI device Bus NO.
526 @param Device PCI device Device NO.
527 @param Func PCI device's func NO.
529 @return Created PCI device instance.
534 IN PCI_IO_DEVICE
*Bridge
,
541 PCI_IO_DEVICE
*PciIoDevice
;
544 EFI_PCI_IO_PROTOCOL
*PciIo
;
546 UINT32 PMemBaseLimit
;
547 UINT16 PrefetchableMemoryBase
;
548 UINT16 PrefetchableMemoryLimit
;
550 PciIoDevice
= CreatePciIoDevice (
558 if (PciIoDevice
== NULL
) {
562 if (gFullEnumeration
) {
563 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
566 // Initialize the bridge control register
568 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED
);
573 // PPB can have two BARs
575 if (PciParseBar (PciIoDevice
, 0x10, PPB_BAR_0
) == 0x14) {
579 PciParseBar (PciIoDevice
, 0x14, PPB_BAR_1
);
582 PciIo
= &PciIoDevice
->PciIo
;
585 // Test whether it support 32 decode or not
587 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
588 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
589 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
590 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
593 if ((Value
& 0x01) != 0) {
594 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
596 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO16_DECODE_SUPPORTED
;
601 // if PcdPciBridgeIoAlignmentProbe is TRUE, PCI bus driver probes
602 // PCI bridge supporting non-standard I/O window alignment less than 4K.
605 PciIoDevice
->BridgeIoAlignment
= 0xFFF;
606 if (FeaturePcdGet (PcdPciBridgeIoAlignmentProbe
)) {
608 // Check any bits of bit 3-1 of I/O Base Register are writable.
609 // if so, it is assumed non-standard I/O window alignment is supported by this bridge.
610 // Per spec, bit 3-1 of I/O Base Register are reserved bits, so its content can't be assumed.
612 Value
= (UINT8
)(Temp
^ (BIT3
| BIT2
| BIT1
));
613 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
614 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
615 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
616 Value
= (UINT8
)((Value
^ Temp
) & (BIT3
| BIT2
| BIT1
));
619 PciIoDevice
->BridgeIoAlignment
= 0x7FF;
622 PciIoDevice
->BridgeIoAlignment
= 0x3FF;
624 case BIT3
| BIT2
| BIT1
:
625 PciIoDevice
->BridgeIoAlignment
= 0x1FF;
630 Status
= BarExisted (
638 // Test if it supports 64 memory or not
640 // The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory Limit
642 // 0 - the bridge supports only 32 bit addresses.
643 // 1 - the bridge supports 64-bit addresses.
645 PrefetchableMemoryBase
= (UINT16
)(PMemBaseLimit
& 0xffff);
646 PrefetchableMemoryLimit
= (UINT16
)(PMemBaseLimit
>> 16);
647 if (!EFI_ERROR (Status
) &&
648 (PrefetchableMemoryBase
& 0x000f) == 0x0001 &&
649 (PrefetchableMemoryLimit
& 0x000f) == 0x0001) {
650 Status
= BarExisted (
657 if (!EFI_ERROR (Status
)) {
658 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
659 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED
;
661 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
666 // Memory 32 code is required for ppb
668 PciIoDevice
->Decodes
|= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
;
670 GetResourcePaddingPpb (PciIoDevice
);
673 DumpPpbPaddingResource (PciIoDevice
, PciBarTypeUnknown
);
674 DumpPciBars (PciIoDevice
);
682 Create PCI device instance for PCI Card bridge device.
684 @param Bridge Parent bridge instance.
685 @param Pci Input PCI device information block.
686 @param Bus PCI device Bus NO.
687 @param Device PCI device Device NO.
688 @param Func PCI device's func NO.
690 @return Created PCI device instance.
695 IN PCI_IO_DEVICE
*Bridge
,
702 PCI_IO_DEVICE
*PciIoDevice
;
704 PciIoDevice
= CreatePciIoDevice (
712 if (PciIoDevice
== NULL
) {
716 if (gFullEnumeration
) {
717 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
720 // Initialize the bridge control register
722 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED
);
726 // P2C only has one bar that is in 0x10
728 PciParseBar (PciIoDevice
, 0x10, P2C_BAR_0
);
731 // Read PciBar information from the bar register
733 GetBackPcCardBar (PciIoDevice
);
734 PciIoDevice
->Decodes
= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
|
735 EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
|
736 EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
738 DEBUG_CODE (DumpPciBars (PciIoDevice
););
744 Create device path for pci device.
746 @param ParentDevicePath Parent bridge's path.
747 @param PciIoDevice Pci device instance.
749 @return Device path protocol instance for specific pci device.
752 EFI_DEVICE_PATH_PROTOCOL
*
753 CreatePciDevicePath (
754 IN EFI_DEVICE_PATH_PROTOCOL
*ParentDevicePath
,
755 IN PCI_IO_DEVICE
*PciIoDevice
759 PCI_DEVICE_PATH PciNode
;
762 // Create PCI device path
764 PciNode
.Header
.Type
= HARDWARE_DEVICE_PATH
;
765 PciNode
.Header
.SubType
= HW_PCI_DP
;
766 SetDevicePathNodeLength (&PciNode
.Header
, sizeof (PciNode
));
768 PciNode
.Device
= PciIoDevice
->DeviceNumber
;
769 PciNode
.Function
= PciIoDevice
->FunctionNumber
;
770 PciIoDevice
->DevicePath
= AppendDevicePathNode (ParentDevicePath
, &PciNode
.Header
);
772 return PciIoDevice
->DevicePath
;
776 Check whether the PCI IOV VF bar is existed or not.
778 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
779 @param Offset The offset.
780 @param BarLengthValue The bar length value returned.
781 @param OriginalBarValue The original bar value returned.
783 @retval EFI_NOT_FOUND The bar doesn't exist.
784 @retval EFI_SUCCESS The bar exist.
789 IN PCI_IO_DEVICE
*PciIoDevice
,
791 OUT UINT32
*BarLengthValue
,
792 OUT UINT32
*OriginalBarValue
795 EFI_PCI_IO_PROTOCOL
*PciIo
;
796 UINT32 OriginalValue
;
801 // Ensure it is called properly
803 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
804 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
805 return EFI_NOT_FOUND
;
808 PciIo
= &PciIoDevice
->PciIo
;
811 // Preserve the original value
814 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
817 // Raise TPL to high level to disable timer interrupt while the BAR is probed
819 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
821 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &gAllOne
);
822 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &Value
);
825 // Write back the original value
827 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
830 // Restore TPL to its original level
832 gBS
->RestoreTPL (OldTpl
);
834 if (BarLengthValue
!= NULL
) {
835 *BarLengthValue
= Value
;
838 if (OriginalBarValue
!= NULL
) {
839 *OriginalBarValue
= OriginalValue
;
843 return EFI_NOT_FOUND
;
850 Check whether the bar is existed or not.
852 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
853 @param Offset The offset.
854 @param BarLengthValue The bar length value returned.
855 @param OriginalBarValue The original bar value returned.
857 @retval EFI_NOT_FOUND The bar doesn't exist.
858 @retval EFI_SUCCESS The bar exist.
863 IN PCI_IO_DEVICE
*PciIoDevice
,
865 OUT UINT32
*BarLengthValue
,
866 OUT UINT32
*OriginalBarValue
869 EFI_PCI_IO_PROTOCOL
*PciIo
;
870 UINT32 OriginalValue
;
874 PciIo
= &PciIoDevice
->PciIo
;
877 // Preserve the original value
879 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
882 // Raise TPL to high level to disable timer interrupt while the BAR is probed
884 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
886 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &gAllOne
);
887 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &Value
);
890 // Write back the original value
892 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
895 // Restore TPL to its original level
897 gBS
->RestoreTPL (OldTpl
);
899 if (BarLengthValue
!= NULL
) {
900 *BarLengthValue
= Value
;
903 if (OriginalBarValue
!= NULL
) {
904 *OriginalBarValue
= OriginalValue
;
908 return EFI_NOT_FOUND
;
915 Test whether the device can support given attributes.
917 @param PciIoDevice Pci device instance.
918 @param Command Input command register value, and
919 returned supported register value.
920 @param BridgeControl Input bridge control value for PPB or P2C, and
921 returned supported bridge control value.
922 @param OldCommand Returned and stored old command register offset.
923 @param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.
927 PciTestSupportedAttribute (
928 IN PCI_IO_DEVICE
*PciIoDevice
,
929 IN OUT UINT16
*Command
,
930 IN OUT UINT16
*BridgeControl
,
931 OUT UINT16
*OldCommand
,
932 OUT UINT16
*OldBridgeControl
938 // Preserve the original value
940 PCI_READ_COMMAND_REGISTER (PciIoDevice
, OldCommand
);
943 // Raise TPL to high level to disable timer interrupt while the BAR is probed
945 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
947 PCI_SET_COMMAND_REGISTER (PciIoDevice
, *Command
);
948 PCI_READ_COMMAND_REGISTER (PciIoDevice
, Command
);
951 // Write back the original value
953 PCI_SET_COMMAND_REGISTER (PciIoDevice
, *OldCommand
);
956 // Restore TPL to its original level
958 gBS
->RestoreTPL (OldTpl
);
960 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
963 // Preserve the original value
965 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, OldBridgeControl
);
968 // Raise TPL to high level to disable timer interrupt while the BAR is probed
970 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
972 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *BridgeControl
);
973 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, BridgeControl
);
976 // Write back the original value
978 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *OldBridgeControl
);
981 // Restore TPL to its original level
983 gBS
->RestoreTPL (OldTpl
);
986 *OldBridgeControl
= 0;
992 Set the supported or current attributes of a PCI device.
994 @param PciIoDevice Structure pointer for PCI device.
995 @param Command Command register value.
996 @param BridgeControl Bridge control value for PPB or P2C.
997 @param Option Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.
1001 PciSetDeviceAttribute (
1002 IN PCI_IO_DEVICE
*PciIoDevice
,
1004 IN UINT16 BridgeControl
,
1012 if ((Command
& EFI_PCI_COMMAND_IO_SPACE
) != 0) {
1013 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IO
;
1016 if ((Command
& EFI_PCI_COMMAND_MEMORY_SPACE
) != 0) {
1017 Attributes
|= EFI_PCI_IO_ATTRIBUTE_MEMORY
;
1020 if ((Command
& EFI_PCI_COMMAND_BUS_MASTER
) != 0) {
1021 Attributes
|= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
;
1024 if ((Command
& EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
) != 0) {
1025 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
1028 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_ISA
) != 0) {
1029 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_IO
;
1032 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA
) != 0) {
1033 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO
;
1034 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
1035 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
1038 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA_16
) != 0) {
1039 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
;
1040 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
;
1043 if (Option
== EFI_SET_SUPPORTS
) {
1045 Attributes
|= (UINT64
) (EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE
|
1046 EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED
|
1047 EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE
|
1048 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
1049 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
1050 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1052 if (IS_PCI_LPC (&PciIoDevice
->Pci
)) {
1053 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO
;
1054 Attributes
|= (mReserveIsaAliases
? (UINT64
) EFI_PCI_IO_ATTRIBUTE_ISA_IO
: \
1055 (UINT64
) EFI_PCI_IO_ATTRIBUTE_ISA_IO_16
);
1058 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
1060 // For bridge, it should support IDE attributes
1062 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
1063 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
1065 if (mReserveVgaAliases
) {
1066 Attributes
&= ~(UINT64
)(EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
| \
1067 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
);
1069 Attributes
&= ~(UINT64
)(EFI_PCI_IO_ATTRIBUTE_VGA_IO
| \
1070 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
);
1074 if (IS_PCI_IDE (&PciIoDevice
->Pci
)) {
1075 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
1076 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
1079 if (IS_PCI_VGA (&PciIoDevice
->Pci
)) {
1080 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
1081 Attributes
|= (mReserveVgaAliases
? (UINT64
) EFI_PCI_IO_ATTRIBUTE_VGA_IO
: \
1082 (UINT64
) EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
);
1086 PciIoDevice
->Supports
= Attributes
;
1087 PciIoDevice
->Supports
&= ( (PciIoDevice
->Parent
->Supports
) | \
1088 EFI_PCI_IO_ATTRIBUTE_IO
| EFI_PCI_IO_ATTRIBUTE_MEMORY
| \
1089 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
);
1093 // When this attribute is clear, the RomImage and RomSize fields in the PCI IO were
1094 // initialized based on the PCI option ROM found through the ROM BAR of the PCI controller.
1095 // When this attribute is set, the PCI option ROM described by the RomImage and RomSize
1096 // fields is not from the the ROM BAR of the PCI controller.
1098 if (!PciIoDevice
->EmbeddedRom
) {
1099 Attributes
|= EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
;
1101 PciIoDevice
->Attributes
= Attributes
;
1106 Determine if the device can support Fast Back to Back attribute.
1108 @param PciIoDevice Pci device instance.
1109 @param StatusIndex Status register value.
1111 @retval EFI_SUCCESS This device support Fast Back to Back attribute.
1112 @retval EFI_UNSUPPORTED This device doesn't support Fast Back to Back attribute.
1116 GetFastBackToBackSupport (
1117 IN PCI_IO_DEVICE
*PciIoDevice
,
1118 IN UINT8 StatusIndex
1121 EFI_PCI_IO_PROTOCOL
*PciIo
;
1123 UINT32 StatusRegister
;
1126 // Read the status register
1128 PciIo
= &PciIoDevice
->PciIo
;
1129 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint16
, StatusIndex
, 1, &StatusRegister
);
1130 if (EFI_ERROR (Status
)) {
1131 return EFI_UNSUPPORTED
;
1135 // Check the Fast B2B bit
1137 if ((StatusRegister
& EFI_PCI_FAST_BACK_TO_BACK_CAPABLE
) != 0) {
1140 return EFI_UNSUPPORTED
;
1145 Process the option ROM for all the children of the specified parent PCI device.
1146 It can only be used after the first full Option ROM process.
1148 @param PciIoDevice Pci device instance.
1152 ProcessOptionRomLight (
1153 IN PCI_IO_DEVICE
*PciIoDevice
1156 PCI_IO_DEVICE
*Temp
;
1157 LIST_ENTRY
*CurrentLink
;
1160 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1162 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1163 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1165 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1167 if (!IsListEmpty (&Temp
->ChildList
)) {
1168 ProcessOptionRomLight (Temp
);
1171 Temp
->AllOpRomProcessed
= PciRomGetImageMapping (Temp
);
1173 CurrentLink
= CurrentLink
->ForwardLink
;
1178 Determine the related attributes of all devices under a Root Bridge.
1180 @param PciIoDevice PCI device instance.
1184 DetermineDeviceAttribute (
1185 IN PCI_IO_DEVICE
*PciIoDevice
1189 UINT16 BridgeControl
;
1191 UINT16 OldBridgeControl
;
1192 BOOLEAN FastB2BSupport
;
1193 PCI_IO_DEVICE
*Temp
;
1194 LIST_ENTRY
*CurrentLink
;
1198 // For Root Bridge, just copy it by RootBridgeIo protocol
1199 // so as to keep consistent with the actual attribute
1201 if (PciIoDevice
->Parent
== NULL
) {
1202 Status
= PciIoDevice
->PciRootBridgeIo
->GetAttributes (
1203 PciIoDevice
->PciRootBridgeIo
,
1204 &PciIoDevice
->Supports
,
1205 &PciIoDevice
->Attributes
1207 if (EFI_ERROR (Status
)) {
1211 // Assume the PCI Root Bridge supports DAC
1213 PciIoDevice
->Supports
|= (UINT64
)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
1214 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
1215 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1220 // Set the attributes to be checked for common PCI devices and PPB or P2C
1221 // Since some devices only support part of them, it is better to set the
1222 // attribute according to its command or bridge control register
1224 Command
= EFI_PCI_COMMAND_IO_SPACE
|
1225 EFI_PCI_COMMAND_MEMORY_SPACE
|
1226 EFI_PCI_COMMAND_BUS_MASTER
|
1227 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
;
1229 BridgeControl
= EFI_PCI_BRIDGE_CONTROL_ISA
| EFI_PCI_BRIDGE_CONTROL_VGA
| EFI_PCI_BRIDGE_CONTROL_VGA_16
;
1232 // Test whether the device can support attributes above
1234 PciTestSupportedAttribute (PciIoDevice
, &Command
, &BridgeControl
, &OldCommand
, &OldBridgeControl
);
1237 // Set the supported attributes for specified PCI device
1239 PciSetDeviceAttribute (PciIoDevice
, Command
, BridgeControl
, EFI_SET_SUPPORTS
);
1242 // Set the current attributes for specified PCI device
1244 PciSetDeviceAttribute (PciIoDevice
, OldCommand
, OldBridgeControl
, EFI_SET_ATTRIBUTES
);
1247 // Enable other PCI supported attributes but not defined in PCI_IO_PROTOCOL
1248 // For PCI Express devices, Memory Write and Invalidate is hardwired to 0b so only enable it for PCI devices.
1249 if (!PciIoDevice
->IsPciExp
) {
1250 PCI_ENABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE
);
1254 FastB2BSupport
= TRUE
;
1257 // P2C can not support FB2B on the secondary side
1259 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
1260 FastB2BSupport
= FALSE
;
1264 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1266 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1267 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1269 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1270 Status
= DetermineDeviceAttribute (Temp
);
1271 if (EFI_ERROR (Status
)) {
1275 // Detect Fast Back to Back support for the device under the bridge
1277 Status
= GetFastBackToBackSupport (Temp
, PCI_PRIMARY_STATUS_OFFSET
);
1278 if (FastB2BSupport
&& EFI_ERROR (Status
)) {
1279 FastB2BSupport
= FALSE
;
1282 CurrentLink
= CurrentLink
->ForwardLink
;
1285 // Set or clear Fast Back to Back bit for the whole bridge
1287 if (!IsListEmpty (&PciIoDevice
->ChildList
)) {
1289 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
1291 Status
= GetFastBackToBackSupport (PciIoDevice
, PCI_BRIDGE_STATUS_REGISTER_OFFSET
);
1293 if (EFI_ERROR (Status
) || (!FastB2BSupport
)) {
1294 FastB2BSupport
= FALSE
;
1295 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1297 PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1301 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1302 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1303 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1304 if (FastB2BSupport
) {
1305 PCI_ENABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1307 PCI_DISABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1310 CurrentLink
= CurrentLink
->ForwardLink
;
1314 // End for IsListEmpty
1320 This routine is used to update the bar information for those incompatible PCI device.
1322 @param PciIoDevice Input Pci device instance. Output Pci device instance with updated
1325 @retval EFI_SUCCESS Successfully updated bar information.
1326 @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.
1331 IN OUT PCI_IO_DEVICE
*PciIoDevice
1337 VOID
*Configuration
;
1338 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1340 Configuration
= NULL
;
1341 Status
= EFI_SUCCESS
;
1343 if (gIncompatiblePciDeviceSupport
== NULL
) {
1345 // It can only be supported after the Incompatible PCI Device
1346 // Support Protocol has been installed
1348 Status
= gBS
->LocateProtocol (
1349 &gEfiIncompatiblePciDeviceSupportProtocolGuid
,
1351 (VOID
**) &gIncompatiblePciDeviceSupport
1354 if (Status
== EFI_SUCCESS
) {
1356 // Check whether the device belongs to incompatible devices from protocol or not
1357 // If it is , then get its special requirement in the ACPI table
1359 Status
= gIncompatiblePciDeviceSupport
->CheckDevice (
1360 gIncompatiblePciDeviceSupport
,
1361 PciIoDevice
->Pci
.Hdr
.VendorId
,
1362 PciIoDevice
->Pci
.Hdr
.DeviceId
,
1363 PciIoDevice
->Pci
.Hdr
.RevisionID
,
1364 PciIoDevice
->Pci
.Device
.SubsystemVendorID
,
1365 PciIoDevice
->Pci
.Device
.SubsystemID
,
1371 if (EFI_ERROR (Status
) || Configuration
== NULL
) {
1372 return EFI_UNSUPPORTED
;
1376 // Update PCI device information from the ACPI table
1378 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Configuration
;
1380 while (Ptr
->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
1382 if (Ptr
->Desc
!= ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
1384 // The format is not support
1389 for (BarIndex
= 0; BarIndex
< PCI_MAX_BAR
; BarIndex
++) {
1390 if ((Ptr
->AddrTranslationOffset
!= MAX_UINT64
) &&
1391 (Ptr
->AddrTranslationOffset
!= MAX_UINT8
) &&
1392 (Ptr
->AddrTranslationOffset
!= BarIndex
)
1395 // Skip updating when AddrTranslationOffset is not MAX_UINT64 or MAX_UINT8 (wide match).
1396 // Skip updating when current BarIndex doesn't equal to AddrTranslationOffset.
1397 // Comparing against MAX_UINT8 is to keep backward compatibility.
1403 switch (Ptr
->ResType
) {
1404 case ACPI_ADDRESS_SPACE_TYPE_MEM
:
1407 // Make sure the bar is memory type
1409 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeMem
)) {
1413 // Ignored if granularity is 0.
1414 // Ignored if PCI BAR is I/O or 32-bit memory.
1415 // If PCI BAR is 64-bit memory and granularity is 32, then
1416 // the PCI BAR resource is allocated below 4GB.
1417 // If PCI BAR is 64-bit memory and granularity is 64, then
1418 // the PCI BAR resource is allocated above 4GB.
1420 if (PciIoDevice
->PciBar
[BarIndex
].BarType
== PciBarTypeMem64
) {
1421 switch (Ptr
->AddrSpaceGranularity
) {
1423 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1425 PciIoDevice
->PciBar
[BarIndex
].BarTypeFixed
= TRUE
;
1432 if (PciIoDevice
->PciBar
[BarIndex
].BarType
== PciBarTypePMem64
) {
1433 switch (Ptr
->AddrSpaceGranularity
) {
1435 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1437 PciIoDevice
->PciBar
[BarIndex
].BarTypeFixed
= TRUE
;
1446 case ACPI_ADDRESS_SPACE_TYPE_IO
:
1449 // Make sure the bar is IO type
1451 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeIo
)) {
1460 // Update the new alignment for the device
1462 SetNewAlign (&(PciIoDevice
->PciBar
[BarIndex
].Alignment
), Ptr
->AddrRangeMax
);
1465 // Update the new length for the device
1467 if (Ptr
->AddrLen
!= 0) {
1468 PciIoDevice
->PciBar
[BarIndex
].Length
= Ptr
->AddrLen
;
1476 FreePool (Configuration
);
1482 This routine will update the alignment with the new alignment.
1483 Compare with OLD_ALIGN/EVEN_ALIGN/SQUAD_ALIGN/DQUAD_ALIGN is to keep
1484 backward compatibility.
1486 @param Alignment Input Old alignment. Output updated alignment.
1487 @param NewAlignment New alignment.
1492 IN OUT UINT64
*Alignment
,
1493 IN UINT64 NewAlignment
1496 UINT64 OldAlignment
;
1500 // The new alignment is the same as the original,
1503 if ((NewAlignment
== 0) || (NewAlignment
== OLD_ALIGN
)) {
1507 // Check the validity of the parameter
1509 if (NewAlignment
!= EVEN_ALIGN
&&
1510 NewAlignment
!= SQUAD_ALIGN
&&
1511 NewAlignment
!= DQUAD_ALIGN
) {
1512 *Alignment
= NewAlignment
;
1516 OldAlignment
= (*Alignment
) + 1;
1520 // Get the first non-zero hex value of the length
1522 while ((OldAlignment
& 0x0F) == 0x00) {
1523 OldAlignment
= RShiftU64 (OldAlignment
, 4);
1528 // Adjust the alignment to even, quad or double quad boundary
1530 if (NewAlignment
== EVEN_ALIGN
) {
1531 if ((OldAlignment
& 0x01) != 0) {
1532 OldAlignment
= OldAlignment
+ 2 - (OldAlignment
& 0x01);
1534 } else if (NewAlignment
== SQUAD_ALIGN
) {
1535 if ((OldAlignment
& 0x03) != 0) {
1536 OldAlignment
= OldAlignment
+ 4 - (OldAlignment
& 0x03);
1538 } else if (NewAlignment
== DQUAD_ALIGN
) {
1539 if ((OldAlignment
& 0x07) != 0) {
1540 OldAlignment
= OldAlignment
+ 8 - (OldAlignment
& 0x07);
1545 // Update the old value
1547 NewAlignment
= LShiftU64 (OldAlignment
, ShiftBit
) - 1;
1548 *Alignment
= NewAlignment
;
1554 Parse PCI IOV VF bar information and fill them into PCI device instance.
1556 @param PciIoDevice Pci device instance.
1557 @param Offset Bar offset.
1558 @param BarIndex Bar index.
1560 @return Next bar offset.
1565 IN PCI_IO_DEVICE
*PciIoDevice
,
1571 UINT32 OriginalValue
;
1576 // Ensure it is called properly
1578 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
1579 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
1586 Status
= VfBarExisted (
1593 if (EFI_ERROR (Status
)) {
1594 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1595 PciIoDevice
->VfPciBar
[BarIndex
].Length
= 0;
1596 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1599 // Scan all the BARs anyway
1601 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
) Offset
;
1605 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
) Offset
;
1606 if ((Value
& 0x01) != 0) {
1608 // Device I/Os. Impossible
1617 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1619 switch (Value
& 0x07) {
1622 //memory space; anywhere in 32 bit address space
1625 if ((Value
& 0x08) != 0) {
1626 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1628 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1631 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1632 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1637 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1641 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1642 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1648 // memory space; anywhere in 64 bit address space
1651 if ((Value
& 0x08) != 0) {
1652 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1654 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1658 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1659 // is regarded as an extension for the first bar. As a result
1660 // the sizing will be conducted on combined 64 bit value
1661 // Here just store the masked first 32bit value for future size
1664 PciIoDevice
->VfPciBar
[BarIndex
].Length
= Value
& Mask
;
1665 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1667 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1668 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1672 // Increment the offset to point to next DWORD
1676 Status
= VfBarExisted (
1683 if (EFI_ERROR (Status
)) {
1684 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1689 // Fix the length to support some special 64 bit BAR
1691 Value
|= ((UINT32
) -1 << HighBitSet32 (Value
));
1694 // Calculate the size of 64bit bar
1696 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
) OriginalValue
, 32);
1698 PciIoDevice
->VfPciBar
[BarIndex
].Length
= PciIoDevice
->VfPciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
) Value
, 32);
1699 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(PciIoDevice
->VfPciBar
[BarIndex
].Length
)) + 1;
1700 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1705 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1709 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1710 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1719 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1720 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1721 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1723 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1724 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1732 // Check the length again so as to keep compatible with some special bars
1734 if (PciIoDevice
->VfPciBar
[BarIndex
].Length
== 0) {
1735 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1736 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1737 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1741 // Increment number of bar
1747 Parse PCI bar information and fill them into PCI device instance.
1749 @param PciIoDevice Pci device instance.
1750 @param Offset Bar offset.
1751 @param BarIndex Bar index.
1753 @return Next bar offset.
1758 IN PCI_IO_DEVICE
*PciIoDevice
,
1764 UINT32 OriginalValue
;
1771 Status
= BarExisted (
1778 if (EFI_ERROR (Status
)) {
1779 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1780 PciIoDevice
->PciBar
[BarIndex
].Length
= 0;
1781 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1784 // Some devices don't fully comply to PCI spec 2.2. So be to scan all the BARs anyway
1786 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1790 PciIoDevice
->PciBar
[BarIndex
].BarTypeFixed
= FALSE
;
1791 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1792 if ((Value
& 0x01) != 0) {
1798 if ((Value
& 0xFFFF0000) != 0) {
1802 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo32
;
1803 PciIoDevice
->PciBar
[BarIndex
].Length
= ((~(Value
& Mask
)) + 1);
1804 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1810 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo16
;
1811 PciIoDevice
->PciBar
[BarIndex
].Length
= 0x0000FFFF & ((~(Value
& Mask
)) + 1);
1812 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1816 // Workaround. Some platforms implement IO bar with 0 length
1817 // Need to treat it as no-bar
1819 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1820 PciIoDevice
->PciBar
[BarIndex
].BarType
= (PCI_BAR_TYPE
) 0;
1823 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1829 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1831 switch (Value
& 0x07) {
1834 //memory space; anywhere in 32 bit address space
1837 if ((Value
& 0x08) != 0) {
1838 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1840 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1843 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1844 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1846 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1848 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1850 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1855 // memory space; anywhere in 64 bit address space
1858 if ((Value
& 0x08) != 0) {
1859 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1861 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1865 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1866 // is regarded as an extension for the first bar. As a result
1867 // the sizing will be conducted on combined 64 bit value
1868 // Here just store the masked first 32bit value for future size
1871 PciIoDevice
->PciBar
[BarIndex
].Length
= Value
& Mask
;
1872 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1875 // Increment the offset to point to next DWORD
1879 Status
= BarExisted (
1886 if (EFI_ERROR (Status
)) {
1888 // the high 32 bit does not claim any BAR, we need to re-check the low 32 bit BAR again
1890 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1892 // some device implement MMIO bar with 0 length, need to treat it as no-bar
1894 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1900 // Fix the length to support some special 64 bit BAR
1903 DEBUG ((EFI_D_INFO
, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
1904 Value
= (UINT32
) -1;
1906 Value
|= ((UINT32
)(-1) << HighBitSet32 (Value
));
1910 // Calculate the size of 64bit bar
1912 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
) OriginalValue
, 32);
1914 PciIoDevice
->PciBar
[BarIndex
].Length
= PciIoDevice
->PciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
) Value
, 32);
1915 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(PciIoDevice
->PciBar
[BarIndex
].Length
)) + 1;
1916 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1918 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1920 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1922 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1931 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1932 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1933 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1935 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1937 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1939 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1946 // Check the length again so as to keep compatible with some special bars
1948 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1949 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1950 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1951 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1955 // Increment number of bar
1961 This routine is used to initialize the bar of a PCI device.
1963 @param PciIoDevice Pci device instance.
1965 @note It can be called typically when a device is going to be rejected.
1969 InitializePciDevice (
1970 IN PCI_IO_DEVICE
*PciIoDevice
1973 EFI_PCI_IO_PROTOCOL
*PciIo
;
1976 PciIo
= &(PciIoDevice
->PciIo
);
1979 // Put all the resource apertures
1980 // Resource base is set to all ones so as to indicate its resource
1981 // has not been allocated
1983 for (Offset
= 0x10; Offset
<= 0x24; Offset
+= sizeof (UINT32
)) {
1984 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, Offset
, 1, &gAllOne
);
1989 This routine is used to initialize the bar of a PCI-PCI Bridge device.
1991 @param PciIoDevice PCI-PCI bridge device instance.
1996 IN PCI_IO_DEVICE
*PciIoDevice
1999 EFI_PCI_IO_PROTOCOL
*PciIo
;
2001 PciIo
= &(PciIoDevice
->PciIo
);
2004 // Put all the resource apertures including IO16
2005 // Io32, pMem32, pMem64 to quiescent state
2006 // Resource base all ones, Resource limit all zeros
2008 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
2009 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1D, 1, &gAllZero
);
2011 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x20, 1, &gAllOne
);
2012 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x22, 1, &gAllZero
);
2014 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x24, 1, &gAllOne
);
2015 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x26, 1, &gAllZero
);
2017 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllOne
);
2018 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2C, 1, &gAllZero
);
2021 // Don't support use io32 as for now
2023 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x30, 1, &gAllOne
);
2024 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x32, 1, &gAllZero
);
2027 // Force Interrupt line to zero for cards that come up randomly
2029 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
2033 This routine is used to initialize the bar of a PCI Card Bridge device.
2035 @param PciIoDevice PCI Card bridge device.
2040 IN PCI_IO_DEVICE
*PciIoDevice
2043 EFI_PCI_IO_PROTOCOL
*PciIo
;
2045 PciIo
= &(PciIoDevice
->PciIo
);
2048 // Put all the resource apertures including IO16
2049 // Io32, pMem32, pMem64 to quiescent state(
2050 // Resource base all ones, Resource limit all zeros
2052 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x1c, 1, &gAllOne
);
2053 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x20, 1, &gAllZero
);
2055 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x24, 1, &gAllOne
);
2056 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllZero
);
2058 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2c, 1, &gAllOne
);
2059 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x30, 1, &gAllZero
);
2061 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x34, 1, &gAllOne
);
2062 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x38, 1, &gAllZero
);
2065 // Force Interrupt line to zero for cards that come up randomly
2067 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
2071 Authenticate the PCI device by using DeviceSecurityProtocol.
2073 @param PciIoDevice PCI device.
2075 @retval EFI_SUCCESS The device passes the authentication.
2076 @return not EFI_SUCCESS The device failes the authentication or
2077 unexpected error happen during authentication.
2080 AuthenticatePciDevice (
2081 IN PCI_IO_DEVICE
*PciIoDevice
2084 EDKII_DEVICE_IDENTIFIER DeviceIdentifier
;
2087 if (mDeviceSecurityProtocol
!= NULL
) {
2089 // Prepare the parameter
2091 DeviceIdentifier
.Version
= EDKII_DEVICE_IDENTIFIER_REVISION
;
2092 CopyGuid (&DeviceIdentifier
.DeviceType
, &gEdkiiDeviceIdentifierTypePciGuid
);
2093 DeviceIdentifier
.DeviceHandle
= NULL
;
2094 Status
= gBS
->InstallMultipleProtocolInterfaces (
2095 &DeviceIdentifier
.DeviceHandle
,
2096 &gEfiDevicePathProtocolGuid
,
2097 PciIoDevice
->DevicePath
,
2098 &gEdkiiDeviceIdentifierTypePciGuid
,
2099 &PciIoDevice
->PciIo
,
2102 if (EFI_ERROR(Status
)) {
2107 // Do DeviceAuthentication
2109 Status
= mDeviceSecurityProtocol
->DeviceAuthenticate (mDeviceSecurityProtocol
, &DeviceIdentifier
);
2111 // Always uninstall, because they are only for Authentication.
2112 // No need to check return Status.
2114 gBS
->UninstallMultipleProtocolInterfaces (
2115 DeviceIdentifier
.DeviceHandle
,
2116 &gEfiDevicePathProtocolGuid
,
2117 PciIoDevice
->DevicePath
,
2118 &gEdkiiDeviceIdentifierTypePciGuid
,
2119 &PciIoDevice
->PciIo
,
2126 // Device Security Protocol is not found, just return success
2132 Create and initialize general PCI I/O device instance for
2133 PCI device/bridge device/hotplug bridge device.
2135 @param Bridge Parent bridge instance.
2136 @param Pci Input Pci information block.
2137 @param Bus Device Bus NO.
2138 @param Device Device device NO.
2139 @param Func Device func NO.
2141 @return Instance of PCI device. NULL means no instance created.
2146 IN PCI_IO_DEVICE
*Bridge
,
2153 PCI_IO_DEVICE
*PciIoDevice
;
2154 EFI_PCI_IO_PROTOCOL
*PciIo
;
2157 PciIoDevice
= AllocateZeroPool (sizeof (PCI_IO_DEVICE
));
2158 if (PciIoDevice
== NULL
) {
2162 PciIoDevice
->Signature
= PCI_IO_DEVICE_SIGNATURE
;
2163 PciIoDevice
->Handle
= NULL
;
2164 PciIoDevice
->PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
2165 PciIoDevice
->DevicePath
= NULL
;
2166 PciIoDevice
->BusNumber
= Bus
;
2167 PciIoDevice
->DeviceNumber
= Device
;
2168 PciIoDevice
->FunctionNumber
= Func
;
2169 PciIoDevice
->Decodes
= 0;
2171 if (gFullEnumeration
) {
2172 PciIoDevice
->Allocated
= FALSE
;
2174 PciIoDevice
->Allocated
= TRUE
;
2177 PciIoDevice
->Registered
= FALSE
;
2178 PciIoDevice
->Attributes
= 0;
2179 PciIoDevice
->Supports
= 0;
2180 PciIoDevice
->BusOverride
= FALSE
;
2181 PciIoDevice
->AllOpRomProcessed
= FALSE
;
2183 PciIoDevice
->IsPciExp
= FALSE
;
2185 CopyMem (&(PciIoDevice
->Pci
), Pci
, sizeof (PCI_TYPE01
));
2188 // Initialize the PCI I/O instance structure
2190 InitializePciIoInstance (PciIoDevice
);
2191 InitializePciDriverOverrideInstance (PciIoDevice
);
2192 InitializePciLoadFile2 (PciIoDevice
);
2193 PciIo
= &PciIoDevice
->PciIo
;
2196 // Create a device path for this PCI device and store it into its private data
2198 CreatePciDevicePath (
2204 // Detect if PCI Express Device
2206 PciIoDevice
->PciExpressCapabilityOffset
= 0;
2207 Status
= LocateCapabilityRegBlock (
2209 EFI_PCI_CAPABILITY_ID_PCIEXP
,
2210 &PciIoDevice
->PciExpressCapabilityOffset
,
2213 if (!EFI_ERROR (Status
)) {
2214 PciIoDevice
->IsPciExp
= TRUE
;
2218 // Now we can do the authentication check for the device.
2220 Status
= AuthenticatePciDevice (PciIoDevice
);
2222 // If authentication fails, skip this device.
2224 if (EFI_ERROR(Status
)) {
2225 if (PciIoDevice
->DevicePath
!= NULL
) {
2226 FreePool (PciIoDevice
->DevicePath
);
2228 FreePool (PciIoDevice
);
2232 if (PcdGetBool (PcdAriSupport
)) {
2234 // Check if the device is an ARI device.
2236 Status
= LocatePciExpressCapabilityRegBlock (
2238 EFI_PCIE_CAPABILITY_ID_ARI
,
2239 &PciIoDevice
->AriCapabilityOffset
,
2242 if (!EFI_ERROR (Status
)) {
2244 // We need to enable ARI feature before calculate BusReservation,
2245 // because FirstVFOffset and VFStride may change after that.
2247 EFI_PCI_IO_PROTOCOL
*ParentPciIo
;
2251 // Check if its parent supports ARI forwarding.
2253 ParentPciIo
= &Bridge
->PciIo
;
2254 ParentPciIo
->Pci
.Read (
2256 EfiPciIoWidthUint32
,
2257 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET
,
2261 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING
) != 0) {
2263 // ARI forward support in bridge, so enable it.
2265 ParentPciIo
->Pci
.Read (
2267 EfiPciIoWidthUint32
,
2268 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2272 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
) == 0) {
2273 Data32
|= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
;
2274 ParentPciIo
->Pci
.Write (
2276 EfiPciIoWidthUint32
,
2277 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2283 " ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",
2285 Bridge
->DeviceNumber
,
2286 Bridge
->FunctionNumber
2291 DEBUG ((EFI_D_INFO
, " ARI: CapOffset = 0x%x\n", PciIoDevice
->AriCapabilityOffset
));
2296 // Initialization for SR-IOV
2299 if (PcdGetBool (PcdSrIovSupport
)) {
2300 Status
= LocatePciExpressCapabilityRegBlock (
2302 EFI_PCIE_CAPABILITY_ID_SRIOV
,
2303 &PciIoDevice
->SrIovCapabilityOffset
,
2306 if (!EFI_ERROR (Status
)) {
2307 UINT32 SupportedPageSize
;
2309 UINT16 FirstVFOffset
;
2315 // If the SR-IOV device is an ARI device, then Set ARI Capable Hierarchy for the device.
2317 if (PcdGetBool (PcdAriSupport
) && PciIoDevice
->AriCapabilityOffset
!= 0) {
2320 EfiPciIoWidthUint16
,
2321 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2325 Data16
|= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY
;
2328 EfiPciIoWidthUint16
,
2329 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2336 // Calculate SystemPageSize
2341 EfiPciIoWidthUint32
,
2342 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE
,
2346 PciIoDevice
->SystemPageSize
= (PcdGet32 (PcdSrIovSystemPageSize
) & SupportedPageSize
);
2347 ASSERT (PciIoDevice
->SystemPageSize
!= 0);
2351 EfiPciIoWidthUint32
,
2352 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE
,
2354 &PciIoDevice
->SystemPageSize
2357 // Adjust SystemPageSize for Alignment usage later
2359 PciIoDevice
->SystemPageSize
<<= 12;
2362 // Calculate BusReservation for PCI IOV
2366 // Read First FirstVFOffset, InitialVFs, and VFStride
2370 EfiPciIoWidthUint16
,
2371 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF
,
2377 EfiPciIoWidthUint16
,
2378 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS
,
2380 &PciIoDevice
->InitialVFs
2384 EfiPciIoWidthUint16
,
2385 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE
,
2392 PFRid
= EFI_PCI_RID(Bus
, Device
, Func
);
2393 LastVF
= PFRid
+ FirstVFOffset
+ (PciIoDevice
->InitialVFs
- 1) * VFStride
;
2396 // Calculate ReservedBusNum for this PF
2398 PciIoDevice
->ReservedBusNum
= (UINT16
)(EFI_PCI_BUS_OF_RID (LastVF
) - Bus
+ 1);
2402 " SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x; FirstVFOffset = 0x%x;\n",
2403 SupportedPageSize
, PciIoDevice
->SystemPageSize
>> 12, FirstVFOffset
2407 " InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",
2408 PciIoDevice
->InitialVFs
, PciIoDevice
->ReservedBusNum
, PciIoDevice
->SrIovCapabilityOffset
2413 if (PcdGetBool (PcdMrIovSupport
)) {
2414 Status
= LocatePciExpressCapabilityRegBlock (
2416 EFI_PCIE_CAPABILITY_ID_MRIOV
,
2417 &PciIoDevice
->MrIovCapabilityOffset
,
2420 if (!EFI_ERROR (Status
)) {
2421 DEBUG ((EFI_D_INFO
, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice
->MrIovCapabilityOffset
));
2425 PciIoDevice
->ResizableBarOffset
= 0;
2426 if (PcdGetBool (PcdPcieResizableBarSupport
)) {
2427 Status
= LocatePciExpressCapabilityRegBlock (
2429 PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID
,
2430 &PciIoDevice
->ResizableBarOffset
,
2433 if (!EFI_ERROR (Status
)) {
2434 PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl
;
2436 Offset
= PciIoDevice
->ResizableBarOffset
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
)
2437 + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY
),
2442 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL
),
2443 &ResizableBarControl
2445 PciIoDevice
->ResizableBarNumber
= ResizableBarControl
.Bits
.ResizableBarNumber
;
2446 PciProgramResizableBar (PciIoDevice
, PciResizableBarMax
);
2451 // Initialize the reserved resource list
2453 InitializeListHead (&PciIoDevice
->ReservedResourceList
);
2456 // Initialize the driver list
2458 InitializeListHead (&PciIoDevice
->OptionRomDriverList
);
2461 // Initialize the child list
2463 InitializeListHead (&PciIoDevice
->ChildList
);
2469 This routine is used to enumerate entire pci bus system
2470 in a given platform.
2472 It is only called on the second start on the same Root Bridge.
2474 @param Controller Parent bridge handler.
2476 @retval EFI_SUCCESS PCI enumeration finished successfully.
2477 @retval other Some error occurred when enumerating the pci bus system.
2481 PciEnumeratorLight (
2482 IN EFI_HANDLE Controller
2487 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2488 PCI_IO_DEVICE
*RootBridgeDev
;
2491 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2494 MaxBus
= PCI_MAX_BUS
;
2498 // If this root bridge has been already enumerated, then return successfully
2500 if (GetRootBridgeByHandle (Controller
) != NULL
) {
2505 // Open pci root bridge io protocol
2507 Status
= gBS
->OpenProtocol (
2509 &gEfiPciRootBridgeIoProtocolGuid
,
2510 (VOID
**) &PciRootBridgeIo
,
2511 gPciBusDriverBinding
.DriverBindingHandle
,
2513 EFI_OPEN_PROTOCOL_BY_DRIVER
2515 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
2519 Status
= PciRootBridgeIo
->Configuration (PciRootBridgeIo
, (VOID
**) &Descriptors
);
2521 if (EFI_ERROR (Status
)) {
2525 while (PciGetBusRange (&Descriptors
, &MinBus
, &MaxBus
, NULL
) == EFI_SUCCESS
) {
2528 // Create a device node for root bridge device with a NULL host bridge controller handle
2530 RootBridgeDev
= CreateRootBridge (Controller
);
2532 if (RootBridgeDev
== NULL
) {
2538 // Record the root bridge-io protocol
2540 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2542 Status
= PciPciDeviceInfoCollector (
2547 if (!EFI_ERROR (Status
)) {
2550 // Remove those PCI devices which are rejected when full enumeration
2552 RemoveRejectedPciDevices (RootBridgeDev
->Handle
, RootBridgeDev
);
2555 // Process option rom light
2557 ProcessOptionRomLight (RootBridgeDev
);
2560 // Determine attributes for all devices under this root bridge
2562 DetermineDeviceAttribute (RootBridgeDev
);
2565 // If successfully, insert the node into device pool
2567 InsertRootBridge (RootBridgeDev
);
2571 // If unsuccessfully, destroy the entire node
2573 DestroyRootBridge (RootBridgeDev
);
2583 Get bus range from PCI resource descriptor list.
2585 @param Descriptors A pointer to the address space descriptor.
2586 @param MinBus The min bus returned.
2587 @param MaxBus The max bus returned.
2588 @param BusRange The bus range returned.
2590 @retval EFI_SUCCESS Successfully got bus range.
2591 @retval EFI_NOT_FOUND Can not find the specific bus.
2596 IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
2599 OUT UINT16
*BusRange
2602 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
2603 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
2604 if (MinBus
!= NULL
) {
2605 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
2608 if (MaxBus
!= NULL
) {
2609 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
2612 if (BusRange
!= NULL
) {
2613 *BusRange
= (UINT16
) (*Descriptors
)->AddrLen
;
2622 return EFI_NOT_FOUND
;
2626 This routine can be used to start the root bridge.
2628 @param RootBridgeDev Pci device instance.
2630 @retval EFI_SUCCESS This device started.
2631 @retval other Failed to get PCI Root Bridge I/O protocol.
2635 StartManagingRootBridge (
2636 IN PCI_IO_DEVICE
*RootBridgeDev
2639 EFI_HANDLE RootBridgeHandle
;
2641 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2644 // Get the root bridge handle
2646 RootBridgeHandle
= RootBridgeDev
->Handle
;
2647 PciRootBridgeIo
= NULL
;
2650 // Get the pci root bridge io protocol
2652 Status
= gBS
->OpenProtocol (
2654 &gEfiPciRootBridgeIoProtocolGuid
,
2655 (VOID
**) &PciRootBridgeIo
,
2656 gPciBusDriverBinding
.DriverBindingHandle
,
2658 EFI_OPEN_PROTOCOL_BY_DRIVER
2661 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
2666 // Store the PciRootBridgeIo protocol into root bridge private data
2668 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2675 This routine can be used to check whether a PCI device should be rejected when light enumeration.
2677 @param PciIoDevice Pci device instance.
2679 @retval TRUE This device should be rejected.
2680 @retval FALSE This device shouldn't be rejected.
2684 IsPciDeviceRejected (
2685 IN PCI_IO_DEVICE
*PciIoDevice
2695 // PPB should be skip!
2697 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
2701 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
2703 // Only test base registers for P2C
2705 for (BarOffset
= 0x1C; BarOffset
<= 0x38; BarOffset
+= 2 * sizeof (UINT32
)) {
2707 Mask
= (BarOffset
< 0x2C) ? 0xFFFFF000 : 0xFFFFFFFC;
2708 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2709 if (EFI_ERROR (Status
)) {
2713 TestValue
= TestValue
& Mask
;
2714 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2716 // The bar isn't programed, so it should be rejected
2725 for (BarOffset
= 0x14; BarOffset
<= 0x24; BarOffset
+= sizeof (UINT32
)) {
2729 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2730 if (EFI_ERROR (Status
)) {
2734 if ((TestValue
& 0x01) != 0) {
2740 TestValue
= TestValue
& Mask
;
2741 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2751 TestValue
= TestValue
& Mask
;
2753 if ((TestValue
& 0x07) == 0x04) {
2758 BarOffset
+= sizeof (UINT32
);
2759 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2762 // Test its high 32-Bit BAR
2764 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2765 if (TestValue
== OldValue
) {
2775 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2786 Reset all bus number from specific bridge.
2788 @param Bridge Parent specific bridge.
2789 @param StartBusNumber Start bus number.
2793 ResetAllPpbBusNumber (
2794 IN PCI_IO_DEVICE
*Bridge
,
2795 IN UINT8 StartBusNumber
2805 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2807 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
2809 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2810 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2813 // Check to see whether a pci device is present
2815 Status
= PciDevicePresent (
2823 if (EFI_ERROR (Status
) && Func
== 0) {
2825 // go to next device if there is no Function 0
2830 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
))) {
2833 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x18);
2834 Status
= PciRootBridgeIo
->Pci
.Read (
2841 SecondaryBus
= (UINT8
)(Register
>> 8);
2843 if (SecondaryBus
!= 0) {
2844 ResetAllPpbBusNumber (Bridge
, SecondaryBus
);
2848 // Reset register 18h, 19h, 1Ah on PCI Bridge
2850 Register
&= 0xFF000000;
2851 Status
= PciRootBridgeIo
->Pci
.Write (
2860 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
2862 // Skip sub functions, this is not a multi function device
2864 Func
= PCI_MAX_FUNC
;