2 PCI emumeration support functions implementation for PCI Bus module.
4 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 extern CHAR16
*mBarTypeStr
[];
20 #define OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
21 #define EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
22 #define SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
23 #define DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
26 This routine is used to check whether the pci device is present.
28 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
29 @param Pci Output buffer for PCI device configuration space.
30 @param Bus PCI bus NO.
31 @param Device PCI device NO.
32 @param Func PCI Func NO.
34 @retval EFI_NOT_FOUND PCI device not present.
35 @retval EFI_SUCCESS PCI device is found.
40 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
,
51 // Create PCI address map in terms of Bus, Device and Func
53 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
56 // Read the Vendor ID register
58 Status
= PciRootBridgeIo
->Pci
.Read (
66 if (!EFI_ERROR (Status
) && (Pci
->Hdr
).VendorId
!= 0xffff) {
68 // Read the entire config header for the device
70 Status
= PciRootBridgeIo
->Pci
.Read (
74 sizeof (PCI_TYPE00
) / sizeof (UINT32
),
85 Collect all the resource information under this root bridge.
87 A database that records all the information about pci device subject to this
88 root bridge will then be created.
90 @param Bridge Parent bridge instance.
91 @param StartBusNumber Bus number of begining.
93 @retval EFI_SUCCESS PCI device is found.
94 @retval other Some error occurred when reading PCI bridge information.
98 PciPciDeviceInfoCollector (
99 IN PCI_IO_DEVICE
*Bridge
,
100 IN UINT8 StartBusNumber
108 PCI_IO_DEVICE
*PciIoDevice
;
109 EFI_PCI_IO_PROTOCOL
*PciIo
;
111 Status
= EFI_SUCCESS
;
114 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
116 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
119 // Check to see whether PCI device is present
121 Status
= PciDevicePresent (
122 Bridge
->PciRootBridgeIo
,
124 (UINT8
) StartBusNumber
,
129 if (EFI_ERROR (Status
) && Func
== 0) {
131 // go to next device if there is no Function 0
136 if (!EFI_ERROR (Status
)) {
139 // Call back to host bridge function
141 PreprocessController (Bridge
, (UINT8
) StartBusNumber
, Device
, Func
, EfiPciBeforeResourceCollection
);
144 // Collect all the information about the PCI device discovered
146 Status
= PciSearchDevice (
149 (UINT8
) StartBusNumber
,
156 // Recursively scan PCI busses on the other side of PCI-PCI bridges
159 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
) || IS_CARDBUS_BRIDGE (&Pci
))) {
162 // If it is PPB, we need to get the secondary bus to continue the enumeration
164 PciIo
= &(PciIoDevice
->PciIo
);
166 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
, 1, &SecBus
);
168 if (EFI_ERROR (Status
)) {
173 // Ensure secondary bus number is greater than the primary bus number to avoid
174 // any potential dead loop when PcdPciDisableBusEnumeration is set to TRUE
176 if (SecBus
<= StartBusNumber
) {
181 // Get resource padding for PPB
183 GetResourcePaddingPpb (PciIoDevice
);
186 // Deep enumerate the next level bus
188 Status
= PciPciDeviceInfoCollector (
195 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
198 // Skip sub functions, this is not a multi function device
211 Seach required device and create PCI device instance.
213 @param Bridge Parent bridge instance.
214 @param Pci Input PCI device information block.
215 @param Bus PCI bus NO.
216 @param Device PCI device NO.
217 @param Func PCI func NO.
218 @param PciDevice Output of searched PCI device instance.
220 @retval EFI_SUCCESS Successfully created PCI device instance.
221 @retval EFI_OUT_OF_RESOURCES Cannot get PCI device information.
226 IN PCI_IO_DEVICE
*Bridge
,
231 OUT PCI_IO_DEVICE
**PciDevice
234 PCI_IO_DEVICE
*PciIoDevice
;
240 "PciBus: Discovered %s @ [%02x|%02x|%02x]\n",
241 IS_PCI_BRIDGE (Pci
) ? L
"PPB" :
242 IS_CARDBUS_BRIDGE (Pci
) ? L
"P2C" :
247 if (!IS_PCI_BRIDGE (Pci
)) {
249 if (IS_CARDBUS_BRIDGE (Pci
)) {
250 PciIoDevice
= GatherP2CInfo (
257 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
258 InitializeP2C (PciIoDevice
);
263 // Create private data for Pci Device
265 PciIoDevice
= GatherDeviceInfo (
278 // Create private data for PPB
280 PciIoDevice
= GatherPpbInfo (
289 // Special initialization for PPB including making the PPB quiet
291 if ((PciIoDevice
!= NULL
) && gFullEnumeration
) {
292 InitializePpb (PciIoDevice
);
296 if (PciIoDevice
== NULL
) {
297 return EFI_OUT_OF_RESOURCES
;
301 // Update the bar information for this PCI device so as to support some specific device
303 UpdatePciInfo (PciIoDevice
);
305 if (PciIoDevice
->DevicePath
== NULL
) {
306 return EFI_OUT_OF_RESOURCES
;
310 // Detect this function has option rom
312 if (gFullEnumeration
) {
314 if (!IS_CARDBUS_BRIDGE (Pci
)) {
316 GetOpRomInfo (PciIoDevice
);
320 ResetPowerManagementFeature (PciIoDevice
);
325 // Insert it into a global tree for future reference
327 InsertPciDevice (Bridge
, PciIoDevice
);
330 // Determine PCI device attributes
333 if (PciDevice
!= NULL
) {
334 *PciDevice
= PciIoDevice
;
341 Dump the PPB padding resource information.
343 @param PciIoDevice PCI IO instance.
344 @param ResourceType The desired resource type to dump.
345 PciBarTypeUnknown means to dump all types of resources.
348 DumpPpbPaddingResource (
349 IN PCI_IO_DEVICE
*PciIoDevice
,
350 IN PCI_BAR_TYPE ResourceType
353 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptor
;
356 if (PciIoDevice
->ResourcePaddingDescriptors
== NULL
) {
360 if (ResourceType
== PciBarTypeIo16
|| ResourceType
== PciBarTypeIo32
) {
361 ResourceType
= PciBarTypeIo
;
364 for (Descriptor
= PciIoDevice
->ResourcePaddingDescriptors
; Descriptor
->Desc
!= ACPI_END_TAG_DESCRIPTOR
; Descriptor
++) {
366 Type
= PciBarTypeUnknown
;
367 if (Descriptor
->Desc
== ACPI_ADDRESS_SPACE_DESCRIPTOR
&& Descriptor
->ResType
== ACPI_ADDRESS_SPACE_TYPE_IO
) {
369 } else if (Descriptor
->Desc
== ACPI_ADDRESS_SPACE_DESCRIPTOR
&& Descriptor
->ResType
== ACPI_ADDRESS_SPACE_TYPE_MEM
) {
371 if (Descriptor
->AddrSpaceGranularity
== 32) {
375 if (Descriptor
->SpecificFlag
== EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
) {
376 Type
= PciBarTypePMem32
;
382 if (Descriptor
->SpecificFlag
== 0) {
383 Type
= PciBarTypeMem32
;
387 if (Descriptor
->AddrSpaceGranularity
== 64) {
391 if (Descriptor
->SpecificFlag
== EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
) {
392 Type
= PciBarTypePMem64
;
398 if (Descriptor
->SpecificFlag
== 0) {
399 Type
= PciBarTypeMem64
;
404 if ((Type
!= PciBarTypeUnknown
) && ((ResourceType
== PciBarTypeUnknown
) || (ResourceType
== Type
))) {
407 " Padding: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx\n",
408 mBarTypeStr
[Type
], Descriptor
->AddrRangeMax
, Descriptor
->AddrLen
416 Dump the PCI BAR information.
418 @param PciIoDevice PCI IO instance.
422 IN PCI_IO_DEVICE
*PciIoDevice
427 for (Index
= 0; Index
< PCI_MAX_BAR
; Index
++) {
428 if (PciIoDevice
->PciBar
[Index
].BarType
== PciBarTypeUnknown
) {
434 " BAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
435 Index
, mBarTypeStr
[MIN (PciIoDevice
->PciBar
[Index
].BarType
, PciBarTypeMaxType
)],
436 PciIoDevice
->PciBar
[Index
].Alignment
, PciIoDevice
->PciBar
[Index
].Length
, PciIoDevice
->PciBar
[Index
].Offset
440 for (Index
= 0; Index
< PCI_MAX_BAR
; Index
++) {
441 if ((PciIoDevice
->VfPciBar
[Index
].BarType
== PciBarTypeUnknown
) && (PciIoDevice
->VfPciBar
[Index
].Length
== 0)) {
447 " VFBAR[%d]: Type = %s; Alignment = 0x%lx;\tLength = 0x%lx;\tOffset = 0x%02x\n",
448 Index
, mBarTypeStr
[MIN (PciIoDevice
->VfPciBar
[Index
].BarType
, PciBarTypeMaxType
)],
449 PciIoDevice
->VfPciBar
[Index
].Alignment
, PciIoDevice
->VfPciBar
[Index
].Length
, PciIoDevice
->VfPciBar
[Index
].Offset
452 DEBUG ((EFI_D_INFO
, "\n"));
456 Create PCI device instance for PCI device.
458 @param Bridge Parent bridge instance.
459 @param Pci Input PCI device information block.
460 @param Bus PCI device Bus NO.
461 @param Device PCI device Device NO.
462 @param Func PCI device's func NO.
464 @return Created PCI device instance.
469 IN PCI_IO_DEVICE
*Bridge
,
478 PCI_IO_DEVICE
*PciIoDevice
;
480 PciIoDevice
= CreatePciIoDevice (
488 if (PciIoDevice
== NULL
) {
493 // If it is a full enumeration, disconnect the device in advance
495 if (gFullEnumeration
) {
497 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
502 // Start to parse the bars
504 for (Offset
= 0x10, BarIndex
= 0; Offset
<= 0x24 && BarIndex
< PCI_MAX_BAR
; BarIndex
++) {
505 Offset
= PciParseBar (PciIoDevice
, Offset
, BarIndex
);
509 // Parse the SR-IOV VF bars
511 if (PcdGetBool (PcdSrIovSupport
) && PciIoDevice
->SrIovCapabilityOffset
!= 0) {
512 for (Offset
= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0
, BarIndex
= 0;
513 Offset
<= PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5
;
516 ASSERT (BarIndex
< PCI_MAX_BAR
);
517 Offset
= PciIovParseVfBar (PciIoDevice
, Offset
, BarIndex
);
521 DEBUG_CODE (DumpPciBars (PciIoDevice
););
526 Create PCI device instance for PCI-PCI bridge.
528 @param Bridge Parent bridge instance.
529 @param Pci Input PCI device information block.
530 @param Bus PCI device Bus NO.
531 @param Device PCI device Device NO.
532 @param Func PCI device's func NO.
534 @return Created PCI device instance.
539 IN PCI_IO_DEVICE
*Bridge
,
546 PCI_IO_DEVICE
*PciIoDevice
;
549 EFI_PCI_IO_PROTOCOL
*PciIo
;
551 UINT32 PMemBaseLimit
;
552 UINT16 PrefetchableMemoryBase
;
553 UINT16 PrefetchableMemoryLimit
;
555 PciIoDevice
= CreatePciIoDevice (
563 if (PciIoDevice
== NULL
) {
567 if (gFullEnumeration
) {
568 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
571 // Initalize the bridge control register
573 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED
);
578 // PPB can have two BARs
580 if (PciParseBar (PciIoDevice
, 0x10, PPB_BAR_0
) == 0x14) {
584 PciParseBar (PciIoDevice
, 0x14, PPB_BAR_1
);
587 PciIo
= &PciIoDevice
->PciIo
;
590 // Test whether it support 32 decode or not
592 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
593 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
594 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
595 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
598 if ((Value
& 0x01) != 0) {
599 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
601 PciIoDevice
->Decodes
|= EFI_BRIDGE_IO16_DECODE_SUPPORTED
;
606 // if PcdPciBridgeIoAlignmentProbe is TRUE, PCI bus driver probes
607 // PCI bridge supporting non-standard I/O window alignment less than 4K.
610 PciIoDevice
->BridgeIoAlignment
= 0xFFF;
611 if (FeaturePcdGet (PcdPciBridgeIoAlignmentProbe
)) {
613 // Check any bits of bit 3-1 of I/O Base Register are writable.
614 // if so, it is assumed non-standard I/O window alignment is supported by this bridge.
615 // Per spec, bit 3-1 of I/O Base Register are reserved bits, so its content can't be assumed.
617 Value
= (UINT8
)(Temp
^ (BIT3
| BIT2
| BIT1
));
618 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
619 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Value
);
620 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &Temp
);
621 Value
= (UINT8
)((Value
^ Temp
) & (BIT3
| BIT2
| BIT1
));
624 PciIoDevice
->BridgeIoAlignment
= 0x7FF;
627 PciIoDevice
->BridgeIoAlignment
= 0x3FF;
629 case BIT3
| BIT2
| BIT1
:
630 PciIoDevice
->BridgeIoAlignment
= 0x1FF;
635 Status
= BarExisted (
643 // Test if it supports 64 memory or not
645 // The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory Limit
647 // 0 - the bridge supports only 32 bit addresses.
648 // 1 - the bridge supports 64-bit addresses.
650 PrefetchableMemoryBase
= (UINT16
)(PMemBaseLimit
& 0xffff);
651 PrefetchableMemoryLimit
= (UINT16
)(PMemBaseLimit
>> 16);
652 if (!EFI_ERROR (Status
) &&
653 (PrefetchableMemoryBase
& 0x000f) == 0x0001 &&
654 (PrefetchableMemoryLimit
& 0x000f) == 0x0001) {
655 Status
= BarExisted (
662 if (!EFI_ERROR (Status
)) {
663 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
664 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM64_DECODE_SUPPORTED
;
666 PciIoDevice
->Decodes
|= EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
;
671 // Memory 32 code is required for ppb
673 PciIoDevice
->Decodes
|= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
;
675 GetResourcePaddingPpb (PciIoDevice
);
678 DumpPpbPaddingResource (PciIoDevice
, PciBarTypeUnknown
);
679 DumpPciBars (PciIoDevice
);
687 Create PCI device instance for PCI Card bridge device.
689 @param Bridge Parent bridge instance.
690 @param Pci Input PCI device information block.
691 @param Bus PCI device Bus NO.
692 @param Device PCI device Device NO.
693 @param Func PCI device's func NO.
695 @return Created PCI device instance.
700 IN PCI_IO_DEVICE
*Bridge
,
707 PCI_IO_DEVICE
*PciIoDevice
;
709 PciIoDevice
= CreatePciIoDevice (
717 if (PciIoDevice
== NULL
) {
721 if (gFullEnumeration
) {
722 PCI_DISABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_BITS_OWNED
);
725 // Initalize the bridge control register
727 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED
);
731 // P2C only has one bar that is in 0x10
733 PciParseBar (PciIoDevice
, 0x10, P2C_BAR_0
);
736 // Read PciBar information from the bar register
738 GetBackPcCardBar (PciIoDevice
);
739 PciIoDevice
->Decodes
= EFI_BRIDGE_MEM32_DECODE_SUPPORTED
|
740 EFI_BRIDGE_PMEM32_DECODE_SUPPORTED
|
741 EFI_BRIDGE_IO32_DECODE_SUPPORTED
;
743 DEBUG_CODE (DumpPciBars (PciIoDevice
););
749 Create device path for pci deivce.
751 @param ParentDevicePath Parent bridge's path.
752 @param PciIoDevice Pci device instance.
754 @return Device path protocol instance for specific pci device.
757 EFI_DEVICE_PATH_PROTOCOL
*
758 CreatePciDevicePath (
759 IN EFI_DEVICE_PATH_PROTOCOL
*ParentDevicePath
,
760 IN PCI_IO_DEVICE
*PciIoDevice
764 PCI_DEVICE_PATH PciNode
;
767 // Create PCI device path
769 PciNode
.Header
.Type
= HARDWARE_DEVICE_PATH
;
770 PciNode
.Header
.SubType
= HW_PCI_DP
;
771 SetDevicePathNodeLength (&PciNode
.Header
, sizeof (PciNode
));
773 PciNode
.Device
= PciIoDevice
->DeviceNumber
;
774 PciNode
.Function
= PciIoDevice
->FunctionNumber
;
775 PciIoDevice
->DevicePath
= AppendDevicePathNode (ParentDevicePath
, &PciNode
.Header
);
777 return PciIoDevice
->DevicePath
;
781 Check whether the PCI IOV VF bar is existed or not.
783 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
784 @param Offset The offset.
785 @param BarLengthValue The bar length value returned.
786 @param OriginalBarValue The original bar value returned.
788 @retval EFI_NOT_FOUND The bar doesn't exist.
789 @retval EFI_SUCCESS The bar exist.
794 IN PCI_IO_DEVICE
*PciIoDevice
,
796 OUT UINT32
*BarLengthValue
,
797 OUT UINT32
*OriginalBarValue
800 EFI_PCI_IO_PROTOCOL
*PciIo
;
801 UINT32 OriginalValue
;
806 // Ensure it is called properly
808 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
809 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
810 return EFI_NOT_FOUND
;
813 PciIo
= &PciIoDevice
->PciIo
;
816 // Preserve the original value
819 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
822 // Raise TPL to high level to disable timer interrupt while the BAR is probed
824 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
826 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &gAllOne
);
827 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &Value
);
830 // Write back the original value
832 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT32
)Offset
, 1, &OriginalValue
);
835 // Restore TPL to its original level
837 gBS
->RestoreTPL (OldTpl
);
839 if (BarLengthValue
!= NULL
) {
840 *BarLengthValue
= Value
;
843 if (OriginalBarValue
!= NULL
) {
844 *OriginalBarValue
= OriginalValue
;
848 return EFI_NOT_FOUND
;
855 Check whether the bar is existed or not.
857 @param PciIoDevice A pointer to the PCI_IO_DEVICE.
858 @param Offset The offset.
859 @param BarLengthValue The bar length value returned.
860 @param OriginalBarValue The original bar value returned.
862 @retval EFI_NOT_FOUND The bar doesn't exist.
863 @retval EFI_SUCCESS The bar exist.
868 IN PCI_IO_DEVICE
*PciIoDevice
,
870 OUT UINT32
*BarLengthValue
,
871 OUT UINT32
*OriginalBarValue
874 EFI_PCI_IO_PROTOCOL
*PciIo
;
875 UINT32 OriginalValue
;
879 PciIo
= &PciIoDevice
->PciIo
;
882 // Preserve the original value
884 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
887 // Raise TPL to high level to disable timer interrupt while the BAR is probed
889 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
891 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &gAllOne
);
892 PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &Value
);
895 // Write back the original value
897 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, (UINT8
) Offset
, 1, &OriginalValue
);
900 // Restore TPL to its original level
902 gBS
->RestoreTPL (OldTpl
);
904 if (BarLengthValue
!= NULL
) {
905 *BarLengthValue
= Value
;
908 if (OriginalBarValue
!= NULL
) {
909 *OriginalBarValue
= OriginalValue
;
913 return EFI_NOT_FOUND
;
920 Test whether the device can support given attributes.
922 @param PciIoDevice Pci device instance.
923 @param Command Input command register value, and
924 returned supported register value.
925 @param BridgeControl Inout bridge control value for PPB or P2C, and
926 returned supported bridge control value.
927 @param OldCommand Returned and stored old command register offset.
928 @param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.
932 PciTestSupportedAttribute (
933 IN PCI_IO_DEVICE
*PciIoDevice
,
934 IN OUT UINT16
*Command
,
935 IN OUT UINT16
*BridgeControl
,
936 OUT UINT16
*OldCommand
,
937 OUT UINT16
*OldBridgeControl
943 // Preserve the original value
945 PCI_READ_COMMAND_REGISTER (PciIoDevice
, OldCommand
);
948 // Raise TPL to high level to disable timer interrupt while the BAR is probed
950 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
952 PCI_SET_COMMAND_REGISTER (PciIoDevice
, *Command
);
953 PCI_READ_COMMAND_REGISTER (PciIoDevice
, Command
);
956 // Write back the original value
958 PCI_SET_COMMAND_REGISTER (PciIoDevice
, *OldCommand
);
961 // Restore TPL to its original level
963 gBS
->RestoreTPL (OldTpl
);
965 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
968 // Preserve the original value
970 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, OldBridgeControl
);
973 // Raise TPL to high level to disable timer interrupt while the BAR is probed
975 OldTpl
= gBS
->RaiseTPL (TPL_HIGH_LEVEL
);
977 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *BridgeControl
);
978 PCI_READ_BRIDGE_CONTROL_REGISTER (PciIoDevice
, BridgeControl
);
981 // Write back the original value
983 PCI_SET_BRIDGE_CONTROL_REGISTER (PciIoDevice
, *OldBridgeControl
);
986 // Restore TPL to its original level
988 gBS
->RestoreTPL (OldTpl
);
991 *OldBridgeControl
= 0;
997 Set the supported or current attributes of a PCI device.
999 @param PciIoDevice Structure pointer for PCI device.
1000 @param Command Command register value.
1001 @param BridgeControl Bridge control value for PPB or P2C.
1002 @param Option Make a choice of EFI_SET_SUPPORTS or EFI_SET_ATTRIBUTES.
1006 PciSetDeviceAttribute (
1007 IN PCI_IO_DEVICE
*PciIoDevice
,
1009 IN UINT16 BridgeControl
,
1017 if ((Command
& EFI_PCI_COMMAND_IO_SPACE
) != 0) {
1018 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IO
;
1021 if ((Command
& EFI_PCI_COMMAND_MEMORY_SPACE
) != 0) {
1022 Attributes
|= EFI_PCI_IO_ATTRIBUTE_MEMORY
;
1025 if ((Command
& EFI_PCI_COMMAND_BUS_MASTER
) != 0) {
1026 Attributes
|= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
;
1029 if ((Command
& EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
) != 0) {
1030 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
1033 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_ISA
) != 0) {
1034 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_IO
;
1037 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA
) != 0) {
1038 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO
;
1039 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
1040 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
;
1043 if ((BridgeControl
& EFI_PCI_BRIDGE_CONTROL_VGA_16
) != 0) {
1044 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
;
1045 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
;
1048 if (Option
== EFI_SET_SUPPORTS
) {
1050 Attributes
|= (UINT64
) (EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE
|
1051 EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED
|
1052 EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE
|
1053 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
1054 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
1055 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1057 if (IS_PCI_LPC (&PciIoDevice
->Pci
)) {
1058 Attributes
|= EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO
;
1059 Attributes
|= (mReserveIsaAliases
? (UINT64
) EFI_PCI_IO_ATTRIBUTE_ISA_IO
: \
1060 (UINT64
) EFI_PCI_IO_ATTRIBUTE_ISA_IO_16
);
1063 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
) || IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
1065 // For bridge, it should support IDE attributes
1067 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
1068 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
1070 if (mReserveVgaAliases
) {
1071 Attributes
&= ~(UINT64
)(EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
| \
1072 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16
);
1074 Attributes
&= ~(UINT64
)(EFI_PCI_IO_ATTRIBUTE_VGA_IO
| \
1075 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO
);
1079 if (IS_PCI_IDE (&PciIoDevice
->Pci
)) {
1080 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO
;
1081 Attributes
|= EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO
;
1084 if (IS_PCI_VGA (&PciIoDevice
->Pci
)) {
1085 Attributes
|= EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
;
1086 Attributes
|= (mReserveVgaAliases
? (UINT64
) EFI_PCI_IO_ATTRIBUTE_VGA_IO
: \
1087 (UINT64
) EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
);
1091 PciIoDevice
->Supports
= Attributes
;
1092 PciIoDevice
->Supports
&= ( (PciIoDevice
->Parent
->Supports
) | \
1093 EFI_PCI_IO_ATTRIBUTE_IO
| EFI_PCI_IO_ATTRIBUTE_MEMORY
| \
1094 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
);
1098 // When this attribute is clear, the RomImage and RomSize fields in the PCI IO were
1099 // initialized based on the PCI option ROM found through the ROM BAR of the PCI controller.
1100 // When this attribute is set, the PCI option ROM described by the RomImage and RomSize
1101 // fields is not from the the ROM BAR of the PCI controller.
1103 if (!PciIoDevice
->EmbeddedRom
) {
1104 Attributes
|= EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
;
1106 PciIoDevice
->Attributes
= Attributes
;
1111 Determine if the device can support Fast Back to Back attribute.
1113 @param PciIoDevice Pci device instance.
1114 @param StatusIndex Status register value.
1116 @retval EFI_SUCCESS This device support Fast Back to Back attribute.
1117 @retval EFI_UNSUPPORTED This device doesn't support Fast Back to Back attribute.
1121 GetFastBackToBackSupport (
1122 IN PCI_IO_DEVICE
*PciIoDevice
,
1123 IN UINT8 StatusIndex
1126 EFI_PCI_IO_PROTOCOL
*PciIo
;
1128 UINT32 StatusRegister
;
1131 // Read the status register
1133 PciIo
= &PciIoDevice
->PciIo
;
1134 Status
= PciIo
->Pci
.Read (PciIo
, EfiPciIoWidthUint16
, StatusIndex
, 1, &StatusRegister
);
1135 if (EFI_ERROR (Status
)) {
1136 return EFI_UNSUPPORTED
;
1140 // Check the Fast B2B bit
1142 if ((StatusRegister
& EFI_PCI_FAST_BACK_TO_BACK_CAPABLE
) != 0) {
1145 return EFI_UNSUPPORTED
;
1150 Process the option ROM for all the children of the specified parent PCI device.
1151 It can only be used after the first full Option ROM process.
1153 @param PciIoDevice Pci device instance.
1157 ProcessOptionRomLight (
1158 IN PCI_IO_DEVICE
*PciIoDevice
1161 PCI_IO_DEVICE
*Temp
;
1162 LIST_ENTRY
*CurrentLink
;
1165 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1167 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1168 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1170 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1172 if (!IsListEmpty (&Temp
->ChildList
)) {
1173 ProcessOptionRomLight (Temp
);
1176 PciRomGetImageMapping (Temp
);
1179 // The OpRom has already been processed in the first round
1181 Temp
->AllOpRomProcessed
= TRUE
;
1183 CurrentLink
= CurrentLink
->ForwardLink
;
1188 Determine the related attributes of all devices under a Root Bridge.
1190 @param PciIoDevice PCI device instance.
1194 DetermineDeviceAttribute (
1195 IN PCI_IO_DEVICE
*PciIoDevice
1199 UINT16 BridgeControl
;
1201 UINT16 OldBridgeControl
;
1202 BOOLEAN FastB2BSupport
;
1203 PCI_IO_DEVICE
*Temp
;
1204 LIST_ENTRY
*CurrentLink
;
1208 // For Root Bridge, just copy it by RootBridgeIo proctocol
1209 // so as to keep consistent with the actual attribute
1211 if (PciIoDevice
->Parent
== NULL
) {
1212 Status
= PciIoDevice
->PciRootBridgeIo
->GetAttributes (
1213 PciIoDevice
->PciRootBridgeIo
,
1214 &PciIoDevice
->Supports
,
1215 &PciIoDevice
->Attributes
1217 if (EFI_ERROR (Status
)) {
1221 // Assume the PCI Root Bridge supports DAC
1223 PciIoDevice
->Supports
|= (UINT64
)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE
|
1224 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM
|
1225 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1230 // Set the attributes to be checked for common PCI devices and PPB or P2C
1231 // Since some devices only support part of them, it is better to set the
1232 // attribute according to its command or bridge control register
1234 Command
= EFI_PCI_COMMAND_IO_SPACE
|
1235 EFI_PCI_COMMAND_MEMORY_SPACE
|
1236 EFI_PCI_COMMAND_BUS_MASTER
|
1237 EFI_PCI_COMMAND_VGA_PALETTE_SNOOP
;
1239 BridgeControl
= EFI_PCI_BRIDGE_CONTROL_ISA
| EFI_PCI_BRIDGE_CONTROL_VGA
| EFI_PCI_BRIDGE_CONTROL_VGA_16
;
1242 // Test whether the device can support attributes above
1244 PciTestSupportedAttribute (PciIoDevice
, &Command
, &BridgeControl
, &OldCommand
, &OldBridgeControl
);
1247 // Set the supported attributes for specified PCI device
1249 PciSetDeviceAttribute (PciIoDevice
, Command
, BridgeControl
, EFI_SET_SUPPORTS
);
1252 // Set the current attributes for specified PCI device
1254 PciSetDeviceAttribute (PciIoDevice
, OldCommand
, OldBridgeControl
, EFI_SET_ATTRIBUTES
);
1257 // Enable other supported attributes but not defined in PCI_IO_PROTOCOL
1259 PCI_ENABLE_COMMAND_REGISTER (PciIoDevice
, EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE
);
1262 FastB2BSupport
= TRUE
;
1265 // P2C can not support FB2B on the secondary side
1267 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
1268 FastB2BSupport
= FALSE
;
1272 // For RootBridge, PPB , P2C, go recursively to traverse all its children
1274 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1275 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1277 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1278 Status
= DetermineDeviceAttribute (Temp
);
1279 if (EFI_ERROR (Status
)) {
1283 // Detect Fast Bact to Bact support for the device under the bridge
1285 Status
= GetFastBackToBackSupport (Temp
, PCI_PRIMARY_STATUS_OFFSET
);
1286 if (FastB2BSupport
&& EFI_ERROR (Status
)) {
1287 FastB2BSupport
= FALSE
;
1290 CurrentLink
= CurrentLink
->ForwardLink
;
1293 // Set or clear Fast Back to Back bit for the whole bridge
1295 if (!IsListEmpty (&PciIoDevice
->ChildList
)) {
1297 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
1299 Status
= GetFastBackToBackSupport (PciIoDevice
, PCI_BRIDGE_STATUS_REGISTER_OFFSET
);
1301 if (EFI_ERROR (Status
) || (!FastB2BSupport
)) {
1302 FastB2BSupport
= FALSE
;
1303 PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1305 PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice
, EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK
);
1309 CurrentLink
= PciIoDevice
->ChildList
.ForwardLink
;
1310 while (CurrentLink
!= NULL
&& CurrentLink
!= &PciIoDevice
->ChildList
) {
1311 Temp
= PCI_IO_DEVICE_FROM_LINK (CurrentLink
);
1312 if (FastB2BSupport
) {
1313 PCI_ENABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1315 PCI_DISABLE_COMMAND_REGISTER (Temp
, EFI_PCI_COMMAND_FAST_BACK_TO_BACK
);
1318 CurrentLink
= CurrentLink
->ForwardLink
;
1322 // End for IsListEmpty
1328 This routine is used to update the bar information for those incompatible PCI device.
1330 @param PciIoDevice Input Pci device instance. Output Pci device instance with updated
1333 @retval EFI_SUCCESS Successfully updated bar information.
1334 @retval EFI_UNSUPPORTED Given PCI device doesn't belong to incompatible PCI device list.
1339 IN OUT PCI_IO_DEVICE
*PciIoDevice
1346 VOID
*Configuration
;
1347 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Ptr
;
1349 Configuration
= NULL
;
1350 Status
= EFI_SUCCESS
;
1352 if (gIncompatiblePciDeviceSupport
== NULL
) {
1354 // It can only be supported after the Incompatible PCI Device
1355 // Support Protocol has been installed
1357 Status
= gBS
->LocateProtocol (
1358 &gEfiIncompatiblePciDeviceSupportProtocolGuid
,
1360 (VOID
**) &gIncompatiblePciDeviceSupport
1363 if (Status
== EFI_SUCCESS
) {
1365 // Check whether the device belongs to incompatible devices from protocol or not
1366 // If it is , then get its special requirement in the ACPI table
1368 Status
= gIncompatiblePciDeviceSupport
->CheckDevice (
1369 gIncompatiblePciDeviceSupport
,
1370 PciIoDevice
->Pci
.Hdr
.VendorId
,
1371 PciIoDevice
->Pci
.Hdr
.DeviceId
,
1372 PciIoDevice
->Pci
.Hdr
.RevisionID
,
1373 PciIoDevice
->Pci
.Device
.SubsystemVendorID
,
1374 PciIoDevice
->Pci
.Device
.SubsystemID
,
1380 if (EFI_ERROR (Status
) || Configuration
== NULL
) {
1381 return EFI_UNSUPPORTED
;
1385 // Update PCI device information from the ACPI table
1387 Ptr
= (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*) Configuration
;
1389 while (Ptr
->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
1391 if (Ptr
->Desc
!= ACPI_ADDRESS_SPACE_DESCRIPTOR
) {
1393 // The format is not support
1398 BarIndex
= Ptr
->AddrTranslationOffset
;
1399 BarEndIndex
= BarIndex
;
1402 // Update all the bars in the device
1403 // Compare against 0xFF is to keep backward compatibility.
1405 if ((BarIndex
== MAX_UINT64
) || (BarIndex
== 0xFF)) {
1407 BarEndIndex
= PCI_MAX_BAR
- 1;
1410 if (BarIndex
>= PCI_MAX_BAR
) {
1415 for (; BarIndex
<= BarEndIndex
; BarIndex
++) {
1417 switch (Ptr
->ResType
) {
1418 case ACPI_ADDRESS_SPACE_TYPE_MEM
:
1421 // Make sure the bar is memory type
1423 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeMem
)) {
1427 // Ignored if granularity is 0.
1428 // Ignored if PCI BAR is I/O or 32-bit memory.
1429 // If PCI BAR is 64-bit memory and granularity is 32, then
1430 // the PCI BAR resource is allocated below 4GB.
1431 // If PCI BAR is 64-bit memory and granularity is 64, then
1432 // the PCI BAR resource is allocated above 4GB.
1434 if (PciIoDevice
->PciBar
[BarIndex
].BarType
== PciBarTypeMem64
) {
1435 switch (Ptr
->AddrSpaceGranularity
) {
1437 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1439 PciIoDevice
->PciBar
[BarIndex
].BarTypeFixed
= TRUE
;
1446 if (PciIoDevice
->PciBar
[BarIndex
].BarType
== PciBarTypePMem64
) {
1447 switch (Ptr
->AddrSpaceGranularity
) {
1449 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1451 PciIoDevice
->PciBar
[BarIndex
].BarTypeFixed
= TRUE
;
1460 case ACPI_ADDRESS_SPACE_TYPE_IO
:
1463 // Make sure the bar is IO type
1465 if (CheckBarType (PciIoDevice
, (UINT8
) BarIndex
, PciBarTypeIo
)) {
1474 // Update the new alignment for the device
1476 SetNewAlign (&(PciIoDevice
->PciBar
[BarIndex
].Alignment
), Ptr
->AddrRangeMax
);
1479 // Update the new length for the device
1481 if (Ptr
->AddrLen
!= 0) {
1482 PciIoDevice
->PciBar
[BarIndex
].Length
= Ptr
->AddrLen
;
1490 FreePool (Configuration
);
1496 This routine will update the alignment with the new alignment.
1497 Compare with OLD_ALIGN/EVEN_ALIGN/SQUAD_ALIGN/DQUAD_ALIGN is to keep
1498 backward compatibility.
1500 @param Alignment Input Old alignment. Output updated alignment.
1501 @param NewAlignment New alignment.
1506 IN OUT UINT64
*Alignment
,
1507 IN UINT64 NewAlignment
1510 UINT64 OldAlignment
;
1514 // The new alignment is the same as the original,
1517 if ((NewAlignment
== 0) || (NewAlignment
== OLD_ALIGN
)) {
1521 // Check the validity of the parameter
1523 if (NewAlignment
!= EVEN_ALIGN
&&
1524 NewAlignment
!= SQUAD_ALIGN
&&
1525 NewAlignment
!= DQUAD_ALIGN
) {
1526 *Alignment
= NewAlignment
;
1530 OldAlignment
= (*Alignment
) + 1;
1534 // Get the first non-zero hex value of the length
1536 while ((OldAlignment
& 0x0F) == 0x00) {
1537 OldAlignment
= RShiftU64 (OldAlignment
, 4);
1542 // Adjust the alignment to even, quad or double quad boundary
1544 if (NewAlignment
== EVEN_ALIGN
) {
1545 if ((OldAlignment
& 0x01) != 0) {
1546 OldAlignment
= OldAlignment
+ 2 - (OldAlignment
& 0x01);
1548 } else if (NewAlignment
== SQUAD_ALIGN
) {
1549 if ((OldAlignment
& 0x03) != 0) {
1550 OldAlignment
= OldAlignment
+ 4 - (OldAlignment
& 0x03);
1552 } else if (NewAlignment
== DQUAD_ALIGN
) {
1553 if ((OldAlignment
& 0x07) != 0) {
1554 OldAlignment
= OldAlignment
+ 8 - (OldAlignment
& 0x07);
1559 // Update the old value
1561 NewAlignment
= LShiftU64 (OldAlignment
, ShiftBit
) - 1;
1562 *Alignment
= NewAlignment
;
1568 Parse PCI IOV VF bar information and fill them into PCI device instance.
1570 @param PciIoDevice Pci device instance.
1571 @param Offset Bar offset.
1572 @param BarIndex Bar index.
1574 @return Next bar offset.
1579 IN PCI_IO_DEVICE
*PciIoDevice
,
1585 UINT32 OriginalValue
;
1590 // Ensure it is called properly
1592 ASSERT (PciIoDevice
->SrIovCapabilityOffset
!= 0);
1593 if (PciIoDevice
->SrIovCapabilityOffset
== 0) {
1600 Status
= VfBarExisted (
1607 if (EFI_ERROR (Status
)) {
1608 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1609 PciIoDevice
->VfPciBar
[BarIndex
].Length
= 0;
1610 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1613 // Scan all the BARs anyway
1615 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
) Offset
;
1619 PciIoDevice
->VfPciBar
[BarIndex
].Offset
= (UINT16
) Offset
;
1620 if ((Value
& 0x01) != 0) {
1622 // Device I/Os. Impossible
1631 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1633 switch (Value
& 0x07) {
1636 //memory space; anywhere in 32 bit address space
1639 if ((Value
& 0x08) != 0) {
1640 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1642 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1645 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1646 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1651 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1655 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1656 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1662 // memory space; anywhere in 64 bit address space
1665 if ((Value
& 0x08) != 0) {
1666 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1668 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1672 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1673 // is regarded as an extension for the first bar. As a result
1674 // the sizing will be conducted on combined 64 bit value
1675 // Here just store the masked first 32bit value for future size
1678 PciIoDevice
->VfPciBar
[BarIndex
].Length
= Value
& Mask
;
1679 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1681 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1682 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1686 // Increment the offset to point to next DWORD
1690 Status
= VfBarExisted (
1697 if (EFI_ERROR (Status
)) {
1702 // Fix the length to support some spefic 64 bit BAR
1704 Value
|= ((UINT32
) -1 << HighBitSet32 (Value
));
1707 // Calculate the size of 64bit bar
1709 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
) OriginalValue
, 32);
1711 PciIoDevice
->VfPciBar
[BarIndex
].Length
= PciIoDevice
->VfPciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
) Value
, 32);
1712 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(PciIoDevice
->VfPciBar
[BarIndex
].Length
)) + 1;
1713 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1718 PciIoDevice
->VfPciBar
[BarIndex
].Length
= MultU64x32 (PciIoDevice
->VfPciBar
[BarIndex
].Length
, PciIoDevice
->InitialVFs
);
1722 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1723 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1732 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1733 PciIoDevice
->VfPciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1734 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->VfPciBar
[BarIndex
].Length
- 1;
1736 if (PciIoDevice
->VfPciBar
[BarIndex
].Alignment
< PciIoDevice
->SystemPageSize
- 1) {
1737 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= PciIoDevice
->SystemPageSize
- 1;
1745 // Check the length again so as to keep compatible with some special bars
1747 if (PciIoDevice
->VfPciBar
[BarIndex
].Length
== 0) {
1748 PciIoDevice
->VfPciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1749 PciIoDevice
->VfPciBar
[BarIndex
].BaseAddress
= 0;
1750 PciIoDevice
->VfPciBar
[BarIndex
].Alignment
= 0;
1754 // Increment number of bar
1760 Parse PCI bar information and fill them into PCI device instance.
1762 @param PciIoDevice Pci device instance.
1763 @param Offset Bar offset.
1764 @param BarIndex Bar index.
1766 @return Next bar offset.
1771 IN PCI_IO_DEVICE
*PciIoDevice
,
1777 UINT32 OriginalValue
;
1784 Status
= BarExisted (
1791 if (EFI_ERROR (Status
)) {
1792 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1793 PciIoDevice
->PciBar
[BarIndex
].Length
= 0;
1794 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1797 // Some devices don't fully comply to PCI spec 2.2. So be to scan all the BARs anyway
1799 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1803 PciIoDevice
->PciBar
[BarIndex
].BarTypeFixed
= FALSE
;
1804 PciIoDevice
->PciBar
[BarIndex
].Offset
= (UINT8
) Offset
;
1805 if ((Value
& 0x01) != 0) {
1811 if ((Value
& 0xFFFF0000) != 0) {
1815 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo32
;
1816 PciIoDevice
->PciBar
[BarIndex
].Length
= ((~(Value
& Mask
)) + 1);
1817 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1823 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeIo16
;
1824 PciIoDevice
->PciBar
[BarIndex
].Length
= 0x0000FFFF & ((~(Value
& Mask
)) + 1);
1825 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1829 // Workaround. Some platforms inplement IO bar with 0 length
1830 // Need to treat it as no-bar
1832 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1833 PciIoDevice
->PciBar
[BarIndex
].BarType
= (PCI_BAR_TYPE
) 0;
1836 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1842 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= OriginalValue
& Mask
;
1844 switch (Value
& 0x07) {
1847 //memory space; anywhere in 32 bit address space
1850 if ((Value
& 0x08) != 0) {
1851 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem32
;
1853 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem32
;
1856 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1857 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1859 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1861 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1863 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1868 // memory space; anywhere in 64 bit address space
1871 if ((Value
& 0x08) != 0) {
1872 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypePMem64
;
1874 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeMem64
;
1878 // According to PCI 2.2,if the bar indicates a memory 64 decoding, next bar
1879 // is regarded as an extension for the first bar. As a result
1880 // the sizing will be conducted on combined 64 bit value
1881 // Here just store the masked first 32bit value for future size
1884 PciIoDevice
->PciBar
[BarIndex
].Length
= Value
& Mask
;
1885 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1888 // Increment the offset to point to next DWORD
1892 Status
= BarExisted (
1899 if (EFI_ERROR (Status
)) {
1901 // the high 32 bit does not claim any BAR, we need to re-check the low 32 bit BAR again
1903 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1905 // some device implement MMIO bar with 0 length, need to treat it as no-bar
1907 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1913 // Fix the length to support some spefic 64 bit BAR
1916 DEBUG ((EFI_D_INFO
, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
1917 Value
= (UINT32
) -1;
1919 Value
|= ((UINT32
)(-1) << HighBitSet32 (Value
));
1923 // Calculate the size of 64bit bar
1925 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
|= LShiftU64 ((UINT64
) OriginalValue
, 32);
1927 PciIoDevice
->PciBar
[BarIndex
].Length
= PciIoDevice
->PciBar
[BarIndex
].Length
| LShiftU64 ((UINT64
) Value
, 32);
1928 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(PciIoDevice
->PciBar
[BarIndex
].Length
)) + 1;
1929 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1931 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1933 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1935 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1944 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1945 PciIoDevice
->PciBar
[BarIndex
].Length
= (~(Value
& Mask
)) + 1;
1946 if (PciIoDevice
->PciBar
[BarIndex
].Length
< (SIZE_4KB
)) {
1948 // Force minimum 4KByte alignment for Virtualization technology for Directed I/O
1950 PciIoDevice
->PciBar
[BarIndex
].Alignment
= (SIZE_4KB
- 1);
1952 PciIoDevice
->PciBar
[BarIndex
].Alignment
= PciIoDevice
->PciBar
[BarIndex
].Length
- 1;
1959 // Check the length again so as to keep compatible with some special bars
1961 if (PciIoDevice
->PciBar
[BarIndex
].Length
== 0) {
1962 PciIoDevice
->PciBar
[BarIndex
].BarType
= PciBarTypeUnknown
;
1963 PciIoDevice
->PciBar
[BarIndex
].BaseAddress
= 0;
1964 PciIoDevice
->PciBar
[BarIndex
].Alignment
= 0;
1968 // Increment number of bar
1974 This routine is used to initialize the bar of a PCI device.
1976 @param PciIoDevice Pci device instance.
1978 @note It can be called typically when a device is going to be rejected.
1982 InitializePciDevice (
1983 IN PCI_IO_DEVICE
*PciIoDevice
1986 EFI_PCI_IO_PROTOCOL
*PciIo
;
1989 PciIo
= &(PciIoDevice
->PciIo
);
1992 // Put all the resource apertures
1993 // Resource base is set to all ones so as to indicate its resource
1994 // has not been alloacted
1996 for (Offset
= 0x10; Offset
<= 0x24; Offset
+= sizeof (UINT32
)) {
1997 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, Offset
, 1, &gAllOne
);
2002 This routine is used to initialize the bar of a PCI-PCI Bridge device.
2004 @param PciIoDevice PCI-PCI bridge device instance.
2009 IN PCI_IO_DEVICE
*PciIoDevice
2012 EFI_PCI_IO_PROTOCOL
*PciIo
;
2014 PciIo
= &(PciIoDevice
->PciIo
);
2017 // Put all the resource apertures including IO16
2018 // Io32, pMem32, pMem64 to quiescent state
2019 // Resource base all ones, Resource limit all zeros
2021 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1C, 1, &gAllOne
);
2022 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x1D, 1, &gAllZero
);
2024 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x20, 1, &gAllOne
);
2025 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x22, 1, &gAllZero
);
2027 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x24, 1, &gAllOne
);
2028 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x26, 1, &gAllZero
);
2030 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllOne
);
2031 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2C, 1, &gAllZero
);
2034 // Don't support use io32 as for now
2036 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x30, 1, &gAllOne
);
2037 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x32, 1, &gAllZero
);
2040 // Force Interrupt line to zero for cards that come up randomly
2042 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
2046 This routine is used to initialize the bar of a PCI Card Bridge device.
2048 @param PciIoDevice PCI Card bridge device.
2053 IN PCI_IO_DEVICE
*PciIoDevice
2056 EFI_PCI_IO_PROTOCOL
*PciIo
;
2058 PciIo
= &(PciIoDevice
->PciIo
);
2061 // Put all the resource apertures including IO16
2062 // Io32, pMem32, pMem64 to quiescent state(
2063 // Resource base all ones, Resource limit all zeros
2065 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x1c, 1, &gAllOne
);
2066 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x20, 1, &gAllZero
);
2068 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x24, 1, &gAllOne
);
2069 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x28, 1, &gAllZero
);
2071 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x2c, 1, &gAllOne
);
2072 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x30, 1, &gAllZero
);
2074 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x34, 1, &gAllOne
);
2075 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint32
, 0x38, 1, &gAllZero
);
2078 // Force Interrupt line to zero for cards that come up randomly
2080 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint8
, 0x3C, 1, &gAllZero
);
2084 Create and initiliaze general PCI I/O device instance for
2085 PCI device/bridge device/hotplug bridge device.
2087 @param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
2088 @param Pci Input Pci information block.
2089 @param Bus Device Bus NO.
2090 @param Device Device device NO.
2091 @param Func Device func NO.
2093 @return Instance of PCI device. NULL means no instance created.
2098 IN PCI_IO_DEVICE
*Bridge
,
2105 PCI_IO_DEVICE
*PciIoDevice
;
2106 EFI_PCI_IO_PROTOCOL
*PciIo
;
2109 PciIoDevice
= AllocateZeroPool (sizeof (PCI_IO_DEVICE
));
2110 if (PciIoDevice
== NULL
) {
2114 PciIoDevice
->Signature
= PCI_IO_DEVICE_SIGNATURE
;
2115 PciIoDevice
->Handle
= NULL
;
2116 PciIoDevice
->PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
2117 PciIoDevice
->DevicePath
= NULL
;
2118 PciIoDevice
->BusNumber
= Bus
;
2119 PciIoDevice
->DeviceNumber
= Device
;
2120 PciIoDevice
->FunctionNumber
= Func
;
2121 PciIoDevice
->Decodes
= 0;
2123 if (gFullEnumeration
) {
2124 PciIoDevice
->Allocated
= FALSE
;
2126 PciIoDevice
->Allocated
= TRUE
;
2129 PciIoDevice
->Registered
= FALSE
;
2130 PciIoDevice
->Attributes
= 0;
2131 PciIoDevice
->Supports
= 0;
2132 PciIoDevice
->BusOverride
= FALSE
;
2133 PciIoDevice
->AllOpRomProcessed
= FALSE
;
2135 PciIoDevice
->IsPciExp
= FALSE
;
2137 CopyMem (&(PciIoDevice
->Pci
), Pci
, sizeof (PCI_TYPE01
));
2140 // Initialize the PCI I/O instance structure
2142 InitializePciIoInstance (PciIoDevice
);
2143 InitializePciDriverOverrideInstance (PciIoDevice
);
2144 InitializePciLoadFile2 (PciIoDevice
);
2145 PciIo
= &PciIoDevice
->PciIo
;
2148 // Create a device path for this PCI device and store it into its private data
2150 CreatePciDevicePath (
2156 // Detect if PCI Express Device
2158 PciIoDevice
->PciExpressCapabilityOffset
= 0;
2159 Status
= LocateCapabilityRegBlock (
2161 EFI_PCI_CAPABILITY_ID_PCIEXP
,
2162 &PciIoDevice
->PciExpressCapabilityOffset
,
2165 if (!EFI_ERROR (Status
)) {
2166 PciIoDevice
->IsPciExp
= TRUE
;
2169 if (PcdGetBool (PcdAriSupport
)) {
2171 // Check if the device is an ARI device.
2173 Status
= LocatePciExpressCapabilityRegBlock (
2175 EFI_PCIE_CAPABILITY_ID_ARI
,
2176 &PciIoDevice
->AriCapabilityOffset
,
2179 if (!EFI_ERROR (Status
)) {
2181 // We need to enable ARI feature before calculate BusReservation,
2182 // because FirstVFOffset and VFStride may change after that.
2184 EFI_PCI_IO_PROTOCOL
*ParentPciIo
;
2188 // Check if its parent supports ARI forwarding.
2190 ParentPciIo
= &Bridge
->PciIo
;
2191 ParentPciIo
->Pci
.Read (
2193 EfiPciIoWidthUint32
,
2194 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET
,
2198 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING
) != 0) {
2200 // ARI forward support in bridge, so enable it.
2202 ParentPciIo
->Pci
.Read (
2204 EfiPciIoWidthUint32
,
2205 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2209 if ((Data32
& EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
) == 0) {
2210 Data32
|= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING
;
2211 ParentPciIo
->Pci
.Write (
2213 EfiPciIoWidthUint32
,
2214 Bridge
->PciExpressCapabilityOffset
+ EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET
,
2220 " ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n",
2222 Bridge
->DeviceNumber
,
2223 Bridge
->FunctionNumber
2228 DEBUG ((EFI_D_INFO
, " ARI: CapOffset = 0x%x\n", PciIoDevice
->AriCapabilityOffset
));
2233 // Initialization for SR-IOV
2236 if (PcdGetBool (PcdSrIovSupport
)) {
2237 Status
= LocatePciExpressCapabilityRegBlock (
2239 EFI_PCIE_CAPABILITY_ID_SRIOV
,
2240 &PciIoDevice
->SrIovCapabilityOffset
,
2243 if (!EFI_ERROR (Status
)) {
2244 UINT32 SupportedPageSize
;
2246 UINT16 FirstVFOffset
;
2252 // If the SR-IOV device is an ARI device, then Set ARI Capable Hierarchy for the device.
2254 if (PcdGetBool (PcdAriSupport
) && PciIoDevice
->AriCapabilityOffset
!= 0) {
2257 EfiPciIoWidthUint16
,
2258 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2262 Data16
|= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY
;
2265 EfiPciIoWidthUint16
,
2266 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL
,
2273 // Calculate SystemPageSize
2278 EfiPciIoWidthUint32
,
2279 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE
,
2283 PciIoDevice
->SystemPageSize
= (PcdGet32 (PcdSrIovSystemPageSize
) & SupportedPageSize
);
2284 ASSERT (PciIoDevice
->SystemPageSize
!= 0);
2288 EfiPciIoWidthUint32
,
2289 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE
,
2291 &PciIoDevice
->SystemPageSize
2294 // Adjust SystemPageSize for Alignment usage later
2296 PciIoDevice
->SystemPageSize
<<= 12;
2299 // Calculate BusReservation for PCI IOV
2303 // Read First FirstVFOffset, InitialVFs, and VFStride
2307 EfiPciIoWidthUint16
,
2308 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF
,
2314 EfiPciIoWidthUint16
,
2315 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS
,
2317 &PciIoDevice
->InitialVFs
2321 EfiPciIoWidthUint16
,
2322 PciIoDevice
->SrIovCapabilityOffset
+ EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE
,
2329 PFRid
= EFI_PCI_RID(Bus
, Device
, Func
);
2330 LastVF
= PFRid
+ FirstVFOffset
+ (PciIoDevice
->InitialVFs
- 1) * VFStride
;
2333 // Calculate ReservedBusNum for this PF
2335 PciIoDevice
->ReservedBusNum
= (UINT16
)(EFI_PCI_BUS_OF_RID (LastVF
) - Bus
+ 1);
2339 " SR-IOV: SupportedPageSize = 0x%x; SystemPageSize = 0x%x; FirstVFOffset = 0x%x;\n",
2340 SupportedPageSize
, PciIoDevice
->SystemPageSize
>> 12, FirstVFOffset
2344 " InitialVFs = 0x%x; ReservedBusNum = 0x%x; CapOffset = 0x%x\n",
2345 PciIoDevice
->InitialVFs
, PciIoDevice
->ReservedBusNum
, PciIoDevice
->SrIovCapabilityOffset
2350 if (PcdGetBool (PcdMrIovSupport
)) {
2351 Status
= LocatePciExpressCapabilityRegBlock (
2353 EFI_PCIE_CAPABILITY_ID_MRIOV
,
2354 &PciIoDevice
->MrIovCapabilityOffset
,
2357 if (!EFI_ERROR (Status
)) {
2358 DEBUG ((EFI_D_INFO
, " MR-IOV: CapOffset = 0x%x\n", PciIoDevice
->MrIovCapabilityOffset
));
2363 // Initialize the reserved resource list
2365 InitializeListHead (&PciIoDevice
->ReservedResourceList
);
2368 // Initialize the driver list
2370 InitializeListHead (&PciIoDevice
->OptionRomDriverList
);
2373 // Initialize the child list
2375 InitializeListHead (&PciIoDevice
->ChildList
);
2381 This routine is used to enumerate entire pci bus system
2382 in a given platform.
2384 It is only called on the second start on the same Root Bridge.
2386 @param Controller Parent bridge handler.
2388 @retval EFI_SUCCESS PCI enumeration finished successfully.
2389 @retval other Some error occurred when enumerating the pci bus system.
2393 PciEnumeratorLight (
2394 IN EFI_HANDLE Controller
2399 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2400 PCI_IO_DEVICE
*RootBridgeDev
;
2403 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2406 MaxBus
= PCI_MAX_BUS
;
2410 // If this root bridge has been already enumerated, then return successfully
2412 if (GetRootBridgeByHandle (Controller
) != NULL
) {
2417 // Open pci root bridge io protocol
2419 Status
= gBS
->OpenProtocol (
2421 &gEfiPciRootBridgeIoProtocolGuid
,
2422 (VOID
**) &PciRootBridgeIo
,
2423 gPciBusDriverBinding
.DriverBindingHandle
,
2425 EFI_OPEN_PROTOCOL_BY_DRIVER
2427 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
2431 Status
= PciRootBridgeIo
->Configuration (PciRootBridgeIo
, (VOID
**) &Descriptors
);
2433 if (EFI_ERROR (Status
)) {
2437 while (PciGetBusRange (&Descriptors
, &MinBus
, &MaxBus
, NULL
) == EFI_SUCCESS
) {
2440 // Create a device node for root bridge device with a NULL host bridge controller handle
2442 RootBridgeDev
= CreateRootBridge (Controller
);
2444 if (RootBridgeDev
== NULL
) {
2450 // Record the root bridgeio protocol
2452 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2454 Status
= PciPciDeviceInfoCollector (
2459 if (!EFI_ERROR (Status
)) {
2462 // Remove those PCI devices which are rejected when full enumeration
2464 RemoveRejectedPciDevices (RootBridgeDev
->Handle
, RootBridgeDev
);
2467 // Process option rom light
2469 ProcessOptionRomLight (RootBridgeDev
);
2472 // Determine attributes for all devices under this root bridge
2474 DetermineDeviceAttribute (RootBridgeDev
);
2477 // If successfully, insert the node into device pool
2479 InsertRootBridge (RootBridgeDev
);
2483 // If unsuccessly, destroy the entire node
2485 DestroyRootBridge (RootBridgeDev
);
2495 Get bus range from PCI resource descriptor list.
2497 @param Descriptors A pointer to the address space descriptor.
2498 @param MinBus The min bus returned.
2499 @param MaxBus The max bus returned.
2500 @param BusRange The bus range returned.
2502 @retval EFI_SUCCESS Successfully got bus range.
2503 @retval EFI_NOT_FOUND Can not find the specific bus.
2508 IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
2511 OUT UINT16
*BusRange
2514 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
2515 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
2516 if (MinBus
!= NULL
) {
2517 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
2520 if (MaxBus
!= NULL
) {
2521 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
2524 if (BusRange
!= NULL
) {
2525 *BusRange
= (UINT16
) (*Descriptors
)->AddrLen
;
2534 return EFI_NOT_FOUND
;
2538 This routine can be used to start the root bridge.
2540 @param RootBridgeDev Pci device instance.
2542 @retval EFI_SUCCESS This device started.
2543 @retval other Failed to get PCI Root Bridge I/O protocol.
2547 StartManagingRootBridge (
2548 IN PCI_IO_DEVICE
*RootBridgeDev
2551 EFI_HANDLE RootBridgeHandle
;
2553 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2556 // Get the root bridge handle
2558 RootBridgeHandle
= RootBridgeDev
->Handle
;
2559 PciRootBridgeIo
= NULL
;
2562 // Get the pci root bridge io protocol
2564 Status
= gBS
->OpenProtocol (
2566 &gEfiPciRootBridgeIoProtocolGuid
,
2567 (VOID
**) &PciRootBridgeIo
,
2568 gPciBusDriverBinding
.DriverBindingHandle
,
2570 EFI_OPEN_PROTOCOL_BY_DRIVER
2573 if (EFI_ERROR (Status
) && Status
!= EFI_ALREADY_STARTED
) {
2578 // Store the PciRootBridgeIo protocol into root bridge private data
2580 RootBridgeDev
->PciRootBridgeIo
= PciRootBridgeIo
;
2587 This routine can be used to check whether a PCI device should be rejected when light enumeration.
2589 @param PciIoDevice Pci device instance.
2591 @retval TRUE This device should be rejected.
2592 @retval FALSE This device shouldn't be rejected.
2596 IsPciDeviceRejected (
2597 IN PCI_IO_DEVICE
*PciIoDevice
2607 // PPB should be skip!
2609 if (IS_PCI_BRIDGE (&PciIoDevice
->Pci
)) {
2613 if (IS_CARDBUS_BRIDGE (&PciIoDevice
->Pci
)) {
2615 // Only test base registers for P2C
2617 for (BarOffset
= 0x1C; BarOffset
<= 0x38; BarOffset
+= 2 * sizeof (UINT32
)) {
2619 Mask
= (BarOffset
< 0x2C) ? 0xFFFFF000 : 0xFFFFFFFC;
2620 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2621 if (EFI_ERROR (Status
)) {
2625 TestValue
= TestValue
& Mask
;
2626 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2628 // The bar isn't programed, so it should be rejected
2637 for (BarOffset
= 0x14; BarOffset
<= 0x24; BarOffset
+= sizeof (UINT32
)) {
2641 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2642 if (EFI_ERROR (Status
)) {
2646 if ((TestValue
& 0x01) != 0) {
2652 TestValue
= TestValue
& Mask
;
2653 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2663 TestValue
= TestValue
& Mask
;
2665 if ((TestValue
& 0x07) == 0x04) {
2670 BarOffset
+= sizeof (UINT32
);
2671 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2674 // Test its high 32-Bit BAR
2676 Status
= BarExisted (PciIoDevice
, BarOffset
, &TestValue
, &OldValue
);
2677 if (TestValue
== OldValue
) {
2687 if ((TestValue
!= 0) && (TestValue
== (OldValue
& Mask
))) {
2698 Reset all bus number from specific bridge.
2700 @param Bridge Parent specific bridge.
2701 @param StartBusNumber Start bus number.
2705 ResetAllPpbBusNumber (
2706 IN PCI_IO_DEVICE
*Bridge
,
2707 IN UINT8 StartBusNumber
2717 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
2719 PciRootBridgeIo
= Bridge
->PciRootBridgeIo
;
2721 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2722 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2725 // Check to see whether a pci device is present
2727 Status
= PciDevicePresent (
2735 if (EFI_ERROR (Status
) && Func
== 0) {
2737 // go to next device if there is no Function 0
2742 if (!EFI_ERROR (Status
) && (IS_PCI_BRIDGE (&Pci
))) {
2745 Address
= EFI_PCI_ADDRESS (StartBusNumber
, Device
, Func
, 0x18);
2746 Status
= PciRootBridgeIo
->Pci
.Read (
2753 SecondaryBus
= (UINT8
)(Register
>> 8);
2755 if (SecondaryBus
!= 0) {
2756 ResetAllPpbBusNumber (Bridge
, SecondaryBus
);
2760 // Reset register 18h, 19h, 1Ah on PCI Bridge
2762 Register
&= 0xFF000000;
2763 Status
= PciRootBridgeIo
->Pci
.Write (
2772 if (Func
== 0 && !IS_PCI_MULTI_FUNC (&Pci
)) {
2774 // Skip sub functions, this is not a multi function device
2776 Func
= PCI_MAX_FUNC
;