MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.h

   1 /** @file
   2   EFI PCI IO protocol functions declaration for PCI Bus module.
   3
   4 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
   5 SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #ifndef _EFI_PCI_IO_PROTOCOL_H_
  10 #define _EFI_PCI_IO_PROTOCOL_H_
  11
  12 /**
  13   Initializes a PCI I/O Instance.
  14
  15   @param PciIoDevice    Pci device instance.
  16
  17 **/
  18 VOID
  19 InitializePciIoInstance (
  20   IN PCI_IO_DEVICE               *PciIoDevice
  21   );
  22
  23 /**
  24   Verifies access to a PCI Base Address Register (BAR).
  25
  26   @param PciIoDevice  Pci device instance.
  27   @param BarIndex     The BAR index of the standard PCI Configuration header to use as the
  28                       base address for the memory or I/O operation to perform.
  29   @param Type         Operation type could be memory or I/O.
  30   @param Width        Signifies the width of the memory or I/O operations.
  31   @param Count        The number of memory or I/O operations to perform.
  32   @param Offset       The offset within the PCI configuration space for the PCI controller.
  33
  34   @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.
  35   @retval EFI_SUCCESS           Successfully verified.
  36
  37 **/
  38 EFI_STATUS
  39 PciIoVerifyBarAccess (
  40   IN PCI_IO_DEVICE                   *PciIoDevice,
  41   IN UINT8                           BarIndex,
  42   IN PCI_BAR_TYPE                    Type,
  43   IN IN EFI_PCI_IO_PROTOCOL_WIDTH    Width,
  44   IN IN UINTN                        Count,
  45   IN UINT64                          *Offset
  46   );
  47
  48 /**
  49   Verifies access to a PCI Configuration Header.
  50
  51   @param PciIoDevice  Pci device instance.
  52   @param Width        Signifies the width of the memory or I/O operations.
  53   @param Count        The number of memory or I/O operations to perform.
  54   @param Offset       The offset within the PCI configuration space for the PCI controller.
  55
  56   @retval EFI_INVALID_PARAMETER  Invalid Width
  57   @retval EFI_UNSUPPORTED        Offset overflowed.
  58   @retval EFI_SUCCESS            Successfully verified.
  59
  60 **/
  61 EFI_STATUS
  62 PciIoVerifyConfigAccess (
  63   IN PCI_IO_DEVICE              *PciIoDevice,
  64   IN EFI_PCI_IO_PROTOCOL_WIDTH  Width,
  65   IN UINTN                      Count,
  66   IN UINT64                     *Offset
  67   );
  68
  69 /**
  70   Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
  71   satisfied or after a defined duration.
  72
  73   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
  74   @param  Width                 Signifies the width of the memory or I/O operations.
  75   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
  76                                 base address for the memory operation to perform.
  77   @param  Offset                The offset within the selected BAR to start the memory operation.
  78   @param  Mask                  Mask used for the polling criteria.
  79   @param  Value                 The comparison value used for the polling exit criteria.
  80   @param  Delay                 The number of 100 ns units to poll.
  81   @param  Result                Pointer to the last value read from the memory location.
  82
  83   @retval EFI_SUCCESS           The last data returned from the access matched the poll exit criteria.
  84   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
  85   @retval EFI_UNSUPPORTED       Offset is not valid for the BarIndex of this PCI controller.
  86   @retval EFI_TIMEOUT           Delay expired before a match occurred.
  87   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
  88   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
  89
  90 **/
  91 EFI_STATUS
  92 EFIAPI
  93 PciIoPollMem (
  94   IN  EFI_PCI_IO_PROTOCOL        *This,
  95   IN  EFI_PCI_IO_PROTOCOL_WIDTH  Width,
  96   IN  UINT8                      BarIndex,
  97   IN  UINT64                     Offset,
  98   IN  UINT64                     Mask,
  99   IN  UINT64                     Value,
 100   IN  UINT64                     Delay,
 101   OUT UINT64                     *Result
 102   );
 103
 104 /**
 105   Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
 106   satisfied or after a defined duration.
 107
 108   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 109   @param  Width                 Signifies the width of the memory or I/O operations.
 110   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 111                                 base address for the memory operation to perform.
 112   @param  Offset                The offset within the selected BAR to start the memory operation.
 113   @param  Mask                  Mask used for the polling criteria.
 114   @param  Value                 The comparison value used for the polling exit criteria.
 115   @param  Delay                 The number of 100 ns units to poll.
 116   @param  Result                Pointer to the last value read from the memory location.
 117
 118   @retval EFI_SUCCESS           The last data returned from the access matched the poll exit criteria.
 119   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 120   @retval EFI_UNSUPPORTED       Offset is not valid for the BarIndex of this PCI controller.
 121   @retval EFI_TIMEOUT           Delay expired before a match occurred.
 122   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 123   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 124
 125 **/
 126 EFI_STATUS
 127 EFIAPI
 128 PciIoPollIo (
 129   IN  EFI_PCI_IO_PROTOCOL        *This,
 130   IN  EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 131   IN  UINT8                      BarIndex,
 132   IN  UINT64                     Offset,
 133   IN  UINT64                     Mask,
 134   IN  UINT64                     Value,
 135   IN  UINT64                     Delay,
 136   OUT UINT64                     *Result
 137   );
 138
 139 /**
 140   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
 141
 142   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 143   @param  Width                 Signifies the width of the memory or I/O operations.
 144   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 145                                 base address for the memory or I/O operation to perform.
 146   @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
 147   @param  Count                 The number of memory or I/O operations to perform.
 148   @param  Buffer                For read operations, the destination buffer to store the results. For write
 149                                 operations, the source buffer to write data from.
 150
 151   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 152   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 153   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 154                                 valid for the PCI BAR specified by BarIndex.
 155   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 156   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 157
 158 **/
 159 EFI_STATUS
 160 EFIAPI
 161 PciIoMemRead (
 162   IN     EFI_PCI_IO_PROTOCOL        *This,
 163   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 164   IN     UINT8                      BarIndex,
 165   IN     UINT64                     Offset,
 166   IN     UINTN                      Count,
 167   IN OUT VOID                       *Buffer
 168   );
 169
 170 /**
 171   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
 172
 173   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 174   @param  Width                 Signifies the width of the memory or I/O operations.
 175   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 176                                 base address for the memory or I/O operation to perform.
 177   @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
 178   @param  Count                 The number of memory or I/O operations to perform.
 179   @param  Buffer                For read operations, the destination buffer to store the results. For write
 180                                 operations, the source buffer to write data from.
 181
 182   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 183   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 184   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 185                                 valid for the PCI BAR specified by BarIndex.
 186   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 187   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 188
 189 **/
 190 EFI_STATUS
 191 EFIAPI
 192 PciIoMemWrite (
 193   IN     EFI_PCI_IO_PROTOCOL        *This,
 194   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 195   IN     UINT8                      BarIndex,
 196   IN     UINT64                     Offset,
 197   IN     UINTN                      Count,
 198   IN OUT VOID                       *Buffer
 199   );
 200
 201 /**
 202   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
 203
 204   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 205   @param  Width                 Signifies the width of the memory or I/O operations.
 206   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 207                                 base address for the memory or I/O operation to perform.
 208   @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
 209   @param  Count                 The number of memory or I/O operations to perform.
 210   @param  Buffer                For read operations, the destination buffer to store the results. For write
 211                                 operations, the source buffer to write data from.
 212
 213   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 214   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 215   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 216                                 valid for the PCI BAR specified by BarIndex.
 217   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 218   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 219
 220 **/
 221 EFI_STATUS
 222 EFIAPI
 223 PciIoIoRead (
 224   IN     EFI_PCI_IO_PROTOCOL        *This,
 225   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 226   IN     UINT8                      BarIndex,
 227   IN     UINT64                     Offset,
 228   IN     UINTN                      Count,
 229   IN OUT VOID                       *Buffer
 230   );
 231
 232 /**
 233   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
 234
 235   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 236   @param  Width                 Signifies the width of the memory or I/O operations.
 237   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 238                                 base address for the memory or I/O operation to perform.
 239   @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
 240   @param  Count                 The number of memory or I/O operations to perform.
 241   @param  Buffer                For read operations, the destination buffer to store the results. For write
 242                                 operations, the source buffer to write data from.
 243
 244   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 245   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 246   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 247                                 valid for the PCI BAR specified by BarIndex.
 248   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 249   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 250
 251 **/
 252 EFI_STATUS
 253 EFIAPI
 254 PciIoIoWrite (
 255   IN     EFI_PCI_IO_PROTOCOL        *This,
 256   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 257   IN     UINT8                      BarIndex,
 258   IN     UINT64                     Offset,
 259   IN     UINTN                      Count,
 260   IN OUT VOID                       *Buffer
 261   );
 262
 263 /**
 264   Enable a PCI driver to access PCI controller registers in PCI configuration space.
 265
 266   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 267   @param  Width                 Signifies the width of the memory operations.
 268   @param  Offset                The offset within the PCI configuration space for the PCI controller.
 269   @param  Count                 The number of PCI configuration operations to perform.
 270   @param  Buffer                For read operations, the destination buffer to store the results. For write
 271                                 operations, the source buffer to write data from.
 272
 273
 274   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 275   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 276                                 valid for the PCI configuration header of the PCI controller.
 277   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 278   @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
 279
 280 **/
 281 EFI_STATUS
 282 EFIAPI
 283 PciIoConfigRead (
 284   IN     EFI_PCI_IO_PROTOCOL        *This,
 285   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 286   IN     UINT32                     Offset,
 287   IN     UINTN                      Count,
 288   IN OUT VOID                       *Buffer
 289   );
 290
 291 /**
 292   Enable a PCI driver to access PCI controller registers in PCI configuration space.
 293
 294   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 295   @param  Width                 Signifies the width of the memory operations.
 296   @param  Offset                The offset within the PCI configuration space for the PCI controller.
 297   @param  Count                 The number of PCI configuration operations to perform.
 298   @param  Buffer                For read operations, the destination buffer to store the results. For write
 299                                 operations, the source buffer to write data from.
 300
 301
 302   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 303   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 304                                 valid for the PCI configuration header of the PCI controller.
 305   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 306   @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
 307
 308 **/
 309 EFI_STATUS
 310 EFIAPI
 311 PciIoConfigWrite (
 312   IN     EFI_PCI_IO_PROTOCOL        *This,
 313   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 314   IN     UINT32                     Offset,
 315   IN     UINTN                      Count,
 316   IN OUT VOID                       *Buffer
 317   );
 318
 319 /**
 320   Enables a PCI driver to copy one region of PCI memory space to another region of PCI
 321   memory space.
 322
 323   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 324   @param  Width                 Signifies the width of the memory operations.
 325   @param  DestBarIndex          The BAR index in the standard PCI Configuration header to use as the
 326                                 base address for the memory operation to perform.
 327   @param  DestOffset            The destination offset within the BAR specified by DestBarIndex to
 328                                 start the memory writes for the copy operation.
 329   @param  SrcBarIndex           The BAR index in the standard PCI Configuration header to use as the
 330                                 base address for the memory operation to perform.
 331   @param  SrcOffset             The source offset within the BAR specified by SrcBarIndex to start
 332                                 the memory reads for the copy operation.
 333   @param  Count                 The number of memory operations to perform. Bytes moved is Width
 334                                 size * Count, starting at DestOffset and SrcOffset.
 335
 336   @retval EFI_SUCCESS           The data was copied from one memory region to another memory region.
 337   @retval EFI_UNSUPPORTED       DestBarIndex not valid for this PCI controller.
 338   @retval EFI_UNSUPPORTED       SrcBarIndex not valid for this PCI controller.
 339   @retval EFI_UNSUPPORTED       The address range specified by DestOffset, Width, and Count
 340                                 is not valid for the PCI BAR specified by DestBarIndex.
 341   @retval EFI_UNSUPPORTED       The address range specified by SrcOffset, Width, and Count is
 342                                 not valid for the PCI BAR specified by SrcBarIndex.
 343   @retval EFI_INVALID_PARAMETER Width is invalid.
 344   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 345
 346 **/
 347 EFI_STATUS
 348 EFIAPI
 349 PciIoCopyMem (
 350   IN EFI_PCI_IO_PROTOCOL              *This,
 351   IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
 352   IN     UINT8                        DestBarIndex,
 353   IN     UINT64                       DestOffset,
 354   IN     UINT8                        SrcBarIndex,
 355   IN     UINT64                       SrcOffset,
 356   IN     UINTN                        Count
 357   );
 358
 359 /**
 360   Provides the PCI controller-specific addresses needed to access system memory.
 361
 362   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 363   @param  Operation             Indicates if the bus master is going to read or write to system memory.
 364   @param  HostAddress           The system memory address to map to the PCI controller.
 365   @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes
 366                                 that were mapped.
 367   @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to
 368                                 access the hosts HostAddress.
 369   @param  Mapping               A resulting value to pass to Unmap().
 370
 371   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
 372   @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
 373   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 374   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 375   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
 376
 377 **/
 378 EFI_STATUS
 379 EFIAPI
 380 PciIoMap (
 381   IN     EFI_PCI_IO_PROTOCOL            *This,
 382   IN     EFI_PCI_IO_PROTOCOL_OPERATION  Operation,
 383   IN     VOID                           *HostAddress,
 384   IN OUT UINTN                          *NumberOfBytes,
 385   OUT    EFI_PHYSICAL_ADDRESS           *DeviceAddress,
 386   OUT    VOID                           **Mapping
 387   );
 388
 389 /**
 390   Completes the Map() operation and releases any corresponding resources.
 391
 392   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 393   @param  Mapping               The mapping value returned from Map().
 394
 395   @retval EFI_SUCCESS           The range was unmapped.
 396   @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.
 397
 398 **/
 399 EFI_STATUS
 400 EFIAPI
 401 PciIoUnmap (
 402   IN  EFI_PCI_IO_PROTOCOL  *This,
 403   IN  VOID                 *Mapping
 404   );
 405
 406 /**
 407   Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer
 408   or EfiPciOperationBusMasterCommonBuffer64 mapping.
 409
 410   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 411   @param  Type                  This parameter is not used and must be ignored.
 412   @param  MemoryType            The type of memory to allocate, EfiBootServicesData or
 413                                 EfiRuntimeServicesData.
 414   @param  Pages                 The number of pages to allocate.
 415   @param  HostAddress           A pointer to store the base system memory address of the
 416                                 allocated range.
 417   @param  Attributes            The requested bit mask of attributes for the allocated range.
 418
 419   @retval EFI_SUCCESS           The requested memory pages were allocated.
 420   @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
 421                                 MEMORY_WRITE_COMBINE, MEMORY_CACHED and DUAL_ADDRESS_CYCLE.
 422   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 423   @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
 424
 425 **/
 426 EFI_STATUS
 427 EFIAPI
 428 PciIoAllocateBuffer (
 429   IN  EFI_PCI_IO_PROTOCOL   *This,
 430   IN  EFI_ALLOCATE_TYPE     Type,
 431   IN  EFI_MEMORY_TYPE       MemoryType,
 432   IN  UINTN                 Pages,
 433   OUT VOID                  **HostAddress,
 434   IN  UINT64                Attributes
 435   );
 436
 437 /**
 438   Frees memory that was allocated with AllocateBuffer().
 439
 440   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 441   @param  Pages                 The number of pages to free.
 442   @param  HostAddress           The base system memory address of the allocated range.
 443
 444   @retval EFI_SUCCESS           The requested memory pages were freed.
 445   @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
 446                                 was not allocated with AllocateBuffer().
 447
 448 **/
 449 EFI_STATUS
 450 EFIAPI
 451 PciIoFreeBuffer (
 452   IN  EFI_PCI_IO_PROTOCOL   *This,
 453   IN  UINTN                 Pages,
 454   IN  VOID                  *HostAddress
 455   );
 456
 457 /**
 458   Flushes all PCI posted write transactions from a PCI host bridge to system memory.
 459
 460   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 461
 462   @retval EFI_SUCCESS           The PCI posted write transactions were flushed from the PCI host
 463                                 bridge to system memory.
 464   @retval EFI_DEVICE_ERROR      The PCI posted write transactions were not flushed from the PCI
 465                                 host bridge due to a hardware error.
 466
 467 **/
 468 EFI_STATUS
 469 EFIAPI
 470 PciIoFlush (
 471   IN  EFI_PCI_IO_PROTOCOL  *This
 472   );
 473
 474 /**
 475   Retrieves this PCI controller's current PCI bus number, device number, and function number.
 476
 477   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 478   @param  SegmentNumber         The PCI controller's current PCI segment number.
 479   @param  BusNumber             The PCI controller's current PCI bus number.
 480   @param  DeviceNumber          The PCI controller's current PCI device number.
 481   @param  FunctionNumber        The PCI controller's current PCI function number.
 482
 483   @retval EFI_SUCCESS           The PCI controller location was returned.
 484   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 485
 486 **/
 487 EFI_STATUS
 488 EFIAPI
 489 PciIoGetLocation (
 490   IN  EFI_PCI_IO_PROTOCOL  *This,
 491   OUT UINTN                *Segment,
 492   OUT UINTN                *Bus,
 493   OUT UINTN                *Device,
 494   OUT UINTN                *Function
 495   );
 496
 497 /**
 498   Check BAR type for PCI resource.
 499
 500   @param PciIoDevice   PCI device instance.
 501   @param BarIndex      The BAR index of the standard PCI Configuration header to use as the
 502                        base address for the memory or I/O operation to perform.
 503   @param BarType       Memory or I/O.
 504
 505   @retval TRUE         Pci device's bar type is same with input BarType.
 506   @retval TRUE         Pci device's bar type is not same with input BarType.
 507
 508 **/
 509 BOOLEAN
 510 CheckBarType (
 511   IN PCI_IO_DEVICE          *PciIoDevice,
 512   IN UINT8                  BarIndex,
 513   IN PCI_BAR_TYPE           BarType
 514   );
 515
 516 /**
 517   Set/Disable new attributes to a Root Bridge.
 518
 519   @param  PciIoDevice  Pci device instance.
 520   @param  Attributes   New attribute want to be set.
 521   @param  Operation    Set or Disable.
 522
 523   @retval  EFI_UNSUPPORTED  If root bridge does not support change attribute.
 524   @retval  EFI_SUCCESS      Successfully set new attributes.
 525
 526 **/
 527 EFI_STATUS
 528 ModifyRootBridgeAttributes (
 529   IN  PCI_IO_DEVICE                            *PciIoDevice,
 530   IN  UINT64                                   Attributes,
 531   IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation
 532   );
 533
 534 /**
 535   Check whether this device can be enable/disable to snoop.
 536
 537   @param PciIoDevice  Pci device instance.
 538   @param Operation    Enable/Disable.
 539
 540   @retval EFI_UNSUPPORTED  Pci device is not GFX device or not support snoop.
 541   @retval EFI_SUCCESS      Snoop can be supported.
 542
 543 **/
 544 EFI_STATUS
 545 SupportPaletteSnoopAttributes (
 546   IN PCI_IO_DEVICE                            *PciIoDevice,
 547   IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation
 548   );
 549
 550 /**
 551   Performs an operation on the attributes that this PCI controller supports. The operations include
 552   getting the set of supported attributes, retrieving the current attributes, setting the current
 553   attributes, enabling attributes, and disabling attributes.
 554
 555   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 556   @param  Operation             The operation to perform on the attributes for this PCI controller.
 557   @param  Attributes            The mask of attributes that are used for Set, Enable, and Disable
 558                                 operations.
 559   @param  Result                A pointer to the result mask of attributes that are returned for the Get
 560                                 and Supported operations.
 561
 562   @retval EFI_SUCCESS           The operation on the PCI controller's attributes was completed.
 563   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 564   @retval EFI_UNSUPPORTED       one or more of the bits set in
 565                                 Attributes are not supported by this PCI controller or one of
 566                                 its parent bridges when Operation is Set, Enable or Disable.
 567
 568 **/
 569 EFI_STATUS
 570 EFIAPI
 571 PciIoAttributes (
 572   IN EFI_PCI_IO_PROTOCOL                       * This,
 573   IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation,
 574   IN  UINT64                                   Attributes,
 575   OUT UINT64                                   *Result OPTIONAL
 576   );
 577
 578 /**
 579   Gets the attributes that this PCI controller supports setting on a BAR using
 580   SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.
 581
 582   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 583   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 584                                 base address for resource range. The legal range for this field is 0..5.
 585   @param  Supports              A pointer to the mask of attributes that this PCI controller supports
 586                                 setting for this BAR with SetBarAttributes().
 587   @param  Resources             A pointer to the resource descriptors that describe the current
 588                                 configuration of this BAR of the PCI controller.
 589
 590   @retval EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI
 591                                 controller supports are returned in Supports. If Resources
 592                                 is not NULL, then the resource descriptors that the PCI
 593                                 controller is currently using are returned in Resources.
 594   @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
 595   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 596   @retval EFI_OUT_OF_RESOURCES  There are not enough resources available to allocate
 597                                 Resources.
 598
 599 **/
 600 EFI_STATUS
 601 EFIAPI
 602 PciIoGetBarAttributes (
 603   IN EFI_PCI_IO_PROTOCOL             * This,
 604   IN  UINT8                          BarIndex,
 605   OUT UINT64                         *Supports  OPTIONAL,
 606   OUT VOID                           **Resources OPTIONAL
 607   );
 608
 609 /**
 610   Sets the attributes for a range of a BAR on a PCI controller.
 611
 612   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 613   @param  Attributes            The mask of attributes to set for the resource range specified by
 614                                 BarIndex, Offset, and Length.
 615   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 616                                 base address for resource range. The legal range for this field is 0..5.
 617   @param  Offset                A pointer to the BAR relative base address of the resource range to be
 618                                 modified by the attributes specified by Attributes.
 619   @param  Length                A pointer to the length of the resource range to be modified by the
 620                                 attributes specified by Attributes.
 621
 622   @retval EFI_SUCCESS           The set of attributes specified by Attributes for the resource
 623                                 range specified by BarIndex, Offset, and Length were
 624                                 set on the PCI controller, and the actual resource range is returned
 625                                 in Offset and Length.
 626   @retval EFI_INVALID_PARAMETER Offset or Length is NULL.
 627   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 628   @retval EFI_OUT_OF_RESOURCES  There are not enough resources to set the attributes on the
 629                                 resource range specified by BarIndex, Offset, and
 630                                 Length.
 631
 632 **/
 633 EFI_STATUS
 634 EFIAPI
 635 PciIoSetBarAttributes (
 636   IN EFI_PCI_IO_PROTOCOL              *This,
 637   IN     UINT64                       Attributes,
 638   IN     UINT8                        BarIndex,
 639   IN OUT UINT64                       *Offset,
 640   IN OUT UINT64                       *Length
 641   );
 642
 643
 644 /**
 645   Test whether two Pci devices has same parent bridge.
 646
 647   @param PciDevice1  The first pci device for testing.
 648   @param PciDevice2  The second pci device for testing.
 649
 650   @retval TRUE       Two Pci device has the same parent bridge.
 651   @retval FALSE      Two Pci device has not the same parent bridge.
 652
 653 **/
 654 BOOLEAN
 655 PciDevicesOnTheSamePath (
 656   IN PCI_IO_DEVICE        *PciDevice1,
 657   IN PCI_IO_DEVICE        *PciDevice2
 658   );
 659
 660 #endif