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MdeModulePkg/PciBus: Shadow option ROM after BARs are programmed
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / PciBusDxe / PciLib.c
1 /** @file
2 Internal library implementation for PCI Bus module.
3
4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include "PciBus.h"
17
18 GLOBAL_REMOVE_IF_UNREFERENCED
19 CHAR16 *mBarTypeStr[] = {
20 L"Unknow",
21 L" Io16",
22 L" Io32",
23 L" Mem32",
24 L"PMem32",
25 L" Mem64",
26 L"PMem64",
27 L" OpRom",
28 L" Io",
29 L" Mem",
30 L"Unknow"
31 };
32
33 /**
34 Retrieve the max bus number that is assigned to the Root Bridge hierarchy.
35 It can support the case that there are multiple bus ranges.
36
37 @param Bridge Bridge device instance.
38
39 @retval The max bus number that is assigned to this Root Bridge hierarchy.
40
41 **/
42 UINT16
43 PciGetMaxBusNumber (
44 IN PCI_IO_DEVICE *Bridge
45 )
46 {
47 PCI_IO_DEVICE *RootBridge;
48 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;
49 UINT64 MaxNumberInRange;
50
51 //
52 // Get PCI Root Bridge device
53 //
54 RootBridge = Bridge;
55 while (RootBridge->Parent != NULL) {
56 RootBridge = RootBridge->Parent;
57 }
58 MaxNumberInRange = 0;
59 //
60 // Iterate the bus number ranges to get max PCI bus number
61 //
62 BusNumberRanges = RootBridge->BusNumberRanges;
63 while (BusNumberRanges->Desc != ACPI_END_TAG_DESCRIPTOR) {
64 MaxNumberInRange = BusNumberRanges->AddrRangeMin + BusNumberRanges->AddrLen - 1;
65 BusNumberRanges++;
66 }
67 return (UINT16) MaxNumberInRange;
68 }
69
70 /**
71 Retrieve the PCI Card device BAR information via PciIo interface.
72
73 @param PciIoDevice PCI Card device instance.
74
75 **/
76 VOID
77 GetBackPcCardBar (
78 IN PCI_IO_DEVICE *PciIoDevice
79 )
80 {
81 UINT32 Address;
82
83 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
84 return;
85 }
86
87 //
88 // Read PciBar information from the bar register
89 //
90 if (!gFullEnumeration) {
91 Address = 0;
92 PciIoDevice->PciIo.Pci.Read (
93 &(PciIoDevice->PciIo),
94 EfiPciIoWidthUint32,
95 PCI_CARD_MEMORY_BASE_0,
96 1,
97 &Address
98 );
99
100 (PciIoDevice->PciBar)[P2C_MEM_1].BaseAddress = (UINT64) (Address);
101 (PciIoDevice->PciBar)[P2C_MEM_1].Length = 0x2000000;
102 (PciIoDevice->PciBar)[P2C_MEM_1].BarType = PciBarTypeMem32;
103
104 Address = 0;
105 PciIoDevice->PciIo.Pci.Read (
106 &(PciIoDevice->PciIo),
107 EfiPciIoWidthUint32,
108 PCI_CARD_MEMORY_BASE_1,
109 1,
110 &Address
111 );
112 (PciIoDevice->PciBar)[P2C_MEM_2].BaseAddress = (UINT64) (Address);
113 (PciIoDevice->PciBar)[P2C_MEM_2].Length = 0x2000000;
114 (PciIoDevice->PciBar)[P2C_MEM_2].BarType = PciBarTypePMem32;
115
116 Address = 0;
117 PciIoDevice->PciIo.Pci.Read (
118 &(PciIoDevice->PciIo),
119 EfiPciIoWidthUint32,
120 PCI_CARD_IO_BASE_0_LOWER,
121 1,
122 &Address
123 );
124 (PciIoDevice->PciBar)[P2C_IO_1].BaseAddress = (UINT64) (Address);
125 (PciIoDevice->PciBar)[P2C_IO_1].Length = 0x100;
126 (PciIoDevice->PciBar)[P2C_IO_1].BarType = PciBarTypeIo16;
127
128 Address = 0;
129 PciIoDevice->PciIo.Pci.Read (
130 &(PciIoDevice->PciIo),
131 EfiPciIoWidthUint32,
132 PCI_CARD_IO_BASE_1_LOWER,
133 1,
134 &Address
135 );
136 (PciIoDevice->PciBar)[P2C_IO_2].BaseAddress = (UINT64) (Address);
137 (PciIoDevice->PciBar)[P2C_IO_2].Length = 0x100;
138 (PciIoDevice->PciBar)[P2C_IO_2].BarType = PciBarTypeIo16;
139
140 }
141
142 if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
143 GetResourcePaddingForHpb (PciIoDevice);
144 }
145 }
146
147 /**
148 Remove rejected pci device from specific root bridge
149 handle.
150
151 @param RootBridgeHandle Specific parent root bridge handle.
152 @param Bridge Bridge device instance.
153
154 **/
155 VOID
156 RemoveRejectedPciDevices (
157 IN EFI_HANDLE RootBridgeHandle,
158 IN PCI_IO_DEVICE *Bridge
159 )
160 {
161 PCI_IO_DEVICE *Temp;
162 LIST_ENTRY *CurrentLink;
163 LIST_ENTRY *LastLink;
164
165 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
166 return;
167 }
168
169 CurrentLink = Bridge->ChildList.ForwardLink;
170
171 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
172
173 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
174
175 if (IS_PCI_BRIDGE (&Temp->Pci)) {
176 //
177 // Remove rejected devices recusively
178 //
179 RemoveRejectedPciDevices (RootBridgeHandle, Temp);
180 } else {
181 //
182 // Skip rejection for all PPBs, while detect rejection for others
183 //
184 if (IsPciDeviceRejected (Temp)) {
185
186 //
187 // For P2C, remove all devices on it
188 //
189 if (!IsListEmpty (&Temp->ChildList)) {
190 RemoveAllPciDeviceOnBridge (RootBridgeHandle, Temp);
191 }
192
193 //
194 // Finally remove itself
195 //
196 LastLink = CurrentLink->BackLink;
197 RemoveEntryList (CurrentLink);
198 FreePciDevice (Temp);
199
200 CurrentLink = LastLink;
201 }
202 }
203
204 CurrentLink = CurrentLink->ForwardLink;
205 }
206 }
207
208 /**
209 Dump the resourc map of the bridge device.
210
211 @param[in] BridgeResource Resource descriptor of the bridge device.
212 **/
213 VOID
214 DumpBridgeResource (
215 IN PCI_RESOURCE_NODE *BridgeResource
216 )
217 {
218 LIST_ENTRY *Link;
219 PCI_RESOURCE_NODE *Resource;
220 PCI_BAR *Bar;
221
222 if ((BridgeResource != NULL) && (BridgeResource->Length != 0)) {
223 DEBUG ((
224 EFI_D_INFO, "Type = %s; Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx\n",
225 mBarTypeStr[MIN (BridgeResource->ResType, PciBarTypeMaxType)],
226 BridgeResource->PciDev->PciBar[BridgeResource->Bar].BaseAddress,
227 BridgeResource->Length, BridgeResource->Alignment
228 ));
229 for ( Link = GetFirstNode (&BridgeResource->ChildList)
230 ; !IsNull (&BridgeResource->ChildList, Link)
231 ; Link = GetNextNode (&BridgeResource->ChildList, Link)
232 ) {
233 Resource = RESOURCE_NODE_FROM_LINK (Link);
234 if (Resource->ResourceUsage == PciResUsageTypical) {
235 Bar = Resource->Virtual ? Resource->PciDev->VfPciBar : Resource->PciDev->PciBar;
236 DEBUG ((
237 EFI_D_INFO, " Base = 0x%lx;\tLength = 0x%lx;\tAlignment = 0x%lx;\tOwner = %s [%02x|%02x|%02x:",
238 Bar[Resource->Bar].BaseAddress, Resource->Length, Resource->Alignment,
239 IS_PCI_BRIDGE (&Resource->PciDev->Pci) ? L"PPB" :
240 IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) ? L"P2C" :
241 L"PCI",
242 Resource->PciDev->BusNumber, Resource->PciDev->DeviceNumber,
243 Resource->PciDev->FunctionNumber
244 ));
245
246 if ((!IS_PCI_BRIDGE (&Resource->PciDev->Pci) && !IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci)) ||
247 (IS_PCI_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < PPB_IO_RANGE)) ||
248 (IS_CARDBUS_BRIDGE (&Resource->PciDev->Pci) && (Resource->Bar < P2C_MEM_1))
249 ) {
250 //
251 // The resource requirement comes from the device itself.
252 //
253 DEBUG ((EFI_D_INFO, "%02x]", Bar[Resource->Bar].Offset));
254 } else {
255 //
256 // The resource requirement comes from the subordinate devices.
257 //
258 DEBUG ((EFI_D_INFO, "**]"));
259 }
260 } else {
261 DEBUG ((EFI_D_INFO, " Base = Padding;\tLength = 0x%lx;\tAlignment = 0x%lx", Resource->Length, Resource->Alignment));
262 }
263 if (BridgeResource->ResType != Resource->ResType) {
264 DEBUG ((EFI_D_INFO, "; Type = %s", mBarTypeStr[MIN (Resource->ResType, PciBarTypeMaxType)]));
265 }
266 DEBUG ((EFI_D_INFO, "\n"));
267 }
268 }
269 }
270
271 /**
272 Find the corresponding resource node for the Device in child list of BridgeResource.
273
274 @param[in] Device Pointer to PCI_IO_DEVICE.
275 @param[in] BridgeResource Pointer to PCI_RESOURCE_NODE.
276 @param[out] DeviceResources Pointer to a buffer to receive resources for the Device.
277
278 @return Count of the resource descriptors returned.
279 **/
280 UINTN
281 FindResourceNode (
282 IN PCI_IO_DEVICE *Device,
283 IN PCI_RESOURCE_NODE *BridgeResource,
284 OUT PCI_RESOURCE_NODE **DeviceResources OPTIONAL
285 )
286 {
287 LIST_ENTRY *Link;
288 PCI_RESOURCE_NODE *Resource;
289 UINTN Count;
290
291 Count = 0;
292 for ( Link = BridgeResource->ChildList.ForwardLink
293 ; Link != &BridgeResource->ChildList
294 ; Link = Link->ForwardLink
295 ) {
296 Resource = RESOURCE_NODE_FROM_LINK (Link);
297 if (Resource->PciDev == Device) {
298 if (DeviceResources != NULL) {
299 DeviceResources[Count] = Resource;
300 }
301 Count++;
302 }
303 }
304
305 return Count;
306 }
307
308 /**
309 Dump the resource map of all the devices under Bridge.
310
311 @param[in] Bridge Bridge device instance.
312 @param[in] Resources Resource descriptors for the bridge device.
313 @param[in] ResourceCount Count of resource descriptors.
314 **/
315 VOID
316 DumpResourceMap (
317 IN PCI_IO_DEVICE *Bridge,
318 IN PCI_RESOURCE_NODE **Resources,
319 IN UINTN ResourceCount
320 )
321 {
322 EFI_STATUS Status;
323 LIST_ENTRY *Link;
324 PCI_IO_DEVICE *Device;
325 UINTN Index;
326 CHAR16 *Str;
327 PCI_RESOURCE_NODE **ChildResources;
328 UINTN ChildResourceCount;
329
330 DEBUG ((EFI_D_INFO, "PciBus: Resource Map for "));
331
332 Status = gBS->OpenProtocol (
333 Bridge->Handle,
334 &gEfiPciRootBridgeIoProtocolGuid,
335 NULL,
336 NULL,
337 NULL,
338 EFI_OPEN_PROTOCOL_TEST_PROTOCOL
339 );
340 if (EFI_ERROR (Status)) {
341 DEBUG ((
342 EFI_D_INFO, "Bridge [%02x|%02x|%02x]\n",
343 Bridge->BusNumber, Bridge->DeviceNumber, Bridge->FunctionNumber
344 ));
345 } else {
346 Str = ConvertDevicePathToText (
347 DevicePathFromHandle (Bridge->Handle),
348 FALSE,
349 FALSE
350 );
351 DEBUG ((EFI_D_INFO, "Root Bridge %s\n", Str != NULL ? Str : L""));
352 if (Str != NULL) {
353 FreePool (Str);
354 }
355 }
356
357 for (Index = 0; Index < ResourceCount; Index++) {
358 DumpBridgeResource (Resources[Index]);
359 }
360 DEBUG ((EFI_D_INFO, "\n"));
361
362 for ( Link = Bridge->ChildList.ForwardLink
363 ; Link != &Bridge->ChildList
364 ; Link = Link->ForwardLink
365 ) {
366 Device = PCI_IO_DEVICE_FROM_LINK (Link);
367 if (IS_PCI_BRIDGE (&Device->Pci)) {
368
369 ChildResourceCount = 0;
370 for (Index = 0; Index < ResourceCount; Index++) {
371 ChildResourceCount += FindResourceNode (Device, Resources[Index], NULL);
372 }
373 ChildResources = AllocatePool (sizeof (PCI_RESOURCE_NODE *) * ChildResourceCount);
374 ASSERT (ChildResources != NULL);
375 ChildResourceCount = 0;
376 for (Index = 0; Index < ResourceCount; Index++) {
377 ChildResourceCount += FindResourceNode (Device, Resources[Index], &ChildResources[ChildResourceCount]);
378 }
379
380 DumpResourceMap (Device, ChildResources, ChildResourceCount);
381 FreePool (ChildResources);
382 }
383 }
384 }
385
386 /**
387 Submits the I/O and memory resource requirements for the specified PCI Host Bridge.
388
389 @param PciResAlloc Point to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
390
391 @retval EFI_SUCCESS Successfully finished resource allocation.
392 @retval EFI_NOT_FOUND Cannot get root bridge instance.
393 @retval EFI_OUT_OF_RESOURCES Platform failed to program the resources if no hot plug supported.
394 @retval other Some error occurred when allocating resources for the PCI Host Bridge.
395
396 @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.
397
398 **/
399 EFI_STATUS
400 PciHostBridgeResourceAllocator (
401 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
402 )
403 {
404 PCI_IO_DEVICE *RootBridgeDev;
405 EFI_HANDLE RootBridgeHandle;
406 VOID *AcpiConfig;
407 EFI_STATUS Status;
408 UINT64 IoBase;
409 UINT64 Mem32Base;
410 UINT64 PMem32Base;
411 UINT64 Mem64Base;
412 UINT64 PMem64Base;
413 UINT64 IoResStatus;
414 UINT64 Mem32ResStatus;
415 UINT64 PMem32ResStatus;
416 UINT64 Mem64ResStatus;
417 UINT64 PMem64ResStatus;
418 UINT64 MaxOptionRomSize;
419 PCI_RESOURCE_NODE *IoBridge;
420 PCI_RESOURCE_NODE *Mem32Bridge;
421 PCI_RESOURCE_NODE *PMem32Bridge;
422 PCI_RESOURCE_NODE *Mem64Bridge;
423 PCI_RESOURCE_NODE *PMem64Bridge;
424 PCI_RESOURCE_NODE IoPool;
425 PCI_RESOURCE_NODE Mem32Pool;
426 PCI_RESOURCE_NODE PMem32Pool;
427 PCI_RESOURCE_NODE Mem64Pool;
428 PCI_RESOURCE_NODE PMem64Pool;
429 EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD HandleExtendedData;
430 EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;
431
432 //
433 // It may try several times if the resource allocation fails
434 //
435 while (TRUE) {
436 //
437 // Initialize resource pool
438 //
439 InitializeResourcePool (&IoPool, PciBarTypeIo16);
440 InitializeResourcePool (&Mem32Pool, PciBarTypeMem32);
441 InitializeResourcePool (&PMem32Pool, PciBarTypePMem32);
442 InitializeResourcePool (&Mem64Pool, PciBarTypeMem64);
443 InitializeResourcePool (&PMem64Pool, PciBarTypePMem64);
444
445 RootBridgeDev = NULL;
446 RootBridgeHandle = 0;
447
448 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
449 //
450 // Get Root Bridge Device by handle
451 //
452 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
453
454 if (RootBridgeDev == NULL) {
455 return EFI_NOT_FOUND;
456 }
457
458 //
459 // Create the entire system resource map from the information collected by
460 // enumerator. Several resource tree was created
461 //
462
463 //
464 // If non-standard PCI Bridge I/O window alignment is supported,
465 // set I/O aligment to minimum possible alignment for root bridge.
466 //
467 IoBridge = CreateResourceNode (
468 RootBridgeDev,
469 0,
470 FeaturePcdGet (PcdPciBridgeIoAlignmentProbe) ? 0x1FF: 0xFFF,
471 RB_IO_RANGE,
472 PciBarTypeIo16,
473 PciResUsageTypical
474 );
475
476 Mem32Bridge = CreateResourceNode (
477 RootBridgeDev,
478 0,
479 0xFFFFF,
480 RB_MEM32_RANGE,
481 PciBarTypeMem32,
482 PciResUsageTypical
483 );
484
485 PMem32Bridge = CreateResourceNode (
486 RootBridgeDev,
487 0,
488 0xFFFFF,
489 RB_PMEM32_RANGE,
490 PciBarTypePMem32,
491 PciResUsageTypical
492 );
493
494 Mem64Bridge = CreateResourceNode (
495 RootBridgeDev,
496 0,
497 0xFFFFF,
498 RB_MEM64_RANGE,
499 PciBarTypeMem64,
500 PciResUsageTypical
501 );
502
503 PMem64Bridge = CreateResourceNode (
504 RootBridgeDev,
505 0,
506 0xFFFFF,
507 RB_PMEM64_RANGE,
508 PciBarTypePMem64,
509 PciResUsageTypical
510 );
511
512 //
513 // Get the max ROM size that the root bridge can process
514 // Insert to resource map so that there will be dedicate MEM32 resource range for Option ROM.
515 // All devices' Option ROM share the same MEM32 resource.
516 //
517 MaxOptionRomSize = GetMaxOptionRomSize (RootBridgeDev);
518 RootBridgeDev->PciBar[0].BarType = PciBarTypeOpRom;
519 RootBridgeDev->PciBar[0].Length = MaxOptionRomSize;
520 RootBridgeDev->PciBar[0].Alignment = MaxOptionRomSize - 1;
521 GetResourceFromDevice (RootBridgeDev, IoBridge, Mem32Bridge, PMem32Bridge, Mem64Bridge, PMem64Bridge);
522
523 //
524 // Create resourcemap by going through all the devices subject to this root bridge
525 //
526 CreateResourceMap (
527 RootBridgeDev,
528 IoBridge,
529 Mem32Bridge,
530 PMem32Bridge,
531 Mem64Bridge,
532 PMem64Bridge
533 );
534
535 //
536 // Based on the all the resource tree, construct ACPI resource node to
537 // submit the resource aperture to pci host bridge protocol
538 //
539 Status = ConstructAcpiResourceRequestor (
540 RootBridgeDev,
541 IoBridge,
542 Mem32Bridge,
543 PMem32Bridge,
544 Mem64Bridge,
545 PMem64Bridge,
546 &AcpiConfig
547 );
548
549 //
550 // Insert these resource nodes into the database
551 //
552 InsertResourceNode (&IoPool, IoBridge);
553 InsertResourceNode (&Mem32Pool, Mem32Bridge);
554 InsertResourceNode (&PMem32Pool, PMem32Bridge);
555 InsertResourceNode (&Mem64Pool, Mem64Bridge);
556 InsertResourceNode (&PMem64Pool, PMem64Bridge);
557
558 if (Status == EFI_SUCCESS) {
559 //
560 // Submit the resource requirement
561 //
562 Status = PciResAlloc->SubmitResources (
563 PciResAlloc,
564 RootBridgeDev->Handle,
565 AcpiConfig
566 );
567 //
568 // If SubmitResources returns error, PciBus isn't able to start.
569 // It's a fatal error so assertion is added.
570 //
571 DEBUG ((EFI_D_INFO, "PciBus: HostBridge->SubmitResources() - %r\n", Status));
572 ASSERT_EFI_ERROR (Status);
573 }
574
575 //
576 // Free acpi resource node
577 //
578 if (AcpiConfig != NULL) {
579 FreePool (AcpiConfig);
580 }
581
582 if (EFI_ERROR (Status)) {
583 //
584 // Destroy all the resource tree
585 //
586 DestroyResourceTree (&IoPool);
587 DestroyResourceTree (&Mem32Pool);
588 DestroyResourceTree (&PMem32Pool);
589 DestroyResourceTree (&Mem64Pool);
590 DestroyResourceTree (&PMem64Pool);
591 return Status;
592 }
593 }
594 //
595 // End while, at least one Root Bridge should be found.
596 //
597 ASSERT (RootBridgeDev != NULL);
598
599 //
600 // Notify platform to start to program the resource
601 //
602 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeAllocateResources);
603 DEBUG ((EFI_D_INFO, "PciBus: HostBridge->NotifyPhase(AllocateResources) - %r\n", Status));
604 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
605 //
606 // If Hot Plug is not supported
607 //
608 if (EFI_ERROR (Status)) {
609 //
610 // Allocation failed, then return
611 //
612 return EFI_OUT_OF_RESOURCES;
613 }
614 //
615 // Allocation succeed.
616 // Get host bridge handle for status report, and then skip the main while
617 //
618 HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;
619
620 break;
621
622 } else {
623 //
624 // If Hot Plug is supported
625 //
626 if (!EFI_ERROR (Status)) {
627 //
628 // Allocation succeed, then continue the following
629 //
630 break;
631 }
632
633 //
634 // If the resource allocation is unsuccessful, free resources on bridge
635 //
636
637 RootBridgeDev = NULL;
638 RootBridgeHandle = 0;
639
640 IoResStatus = EFI_RESOURCE_SATISFIED;
641 Mem32ResStatus = EFI_RESOURCE_SATISFIED;
642 PMem32ResStatus = EFI_RESOURCE_SATISFIED;
643 Mem64ResStatus = EFI_RESOURCE_SATISFIED;
644 PMem64ResStatus = EFI_RESOURCE_SATISFIED;
645
646 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
647 //
648 // Get RootBridg Device by handle
649 //
650 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
651 if (RootBridgeDev == NULL) {
652 return EFI_NOT_FOUND;
653 }
654
655 //
656 // Get host bridge handle for status report
657 //
658 HandleExtendedData.Handle = RootBridgeDev->PciRootBridgeIo->ParentHandle;
659
660 //
661 // Get acpi resource node for all the resource types
662 //
663 AcpiConfig = NULL;
664
665 Status = PciResAlloc->GetProposedResources (
666 PciResAlloc,
667 RootBridgeDev->Handle,
668 &AcpiConfig
669 );
670
671 if (EFI_ERROR (Status)) {
672 return Status;
673 }
674
675 if (AcpiConfig != NULL) {
676 //
677 // Adjust resource allocation policy for each RB
678 //
679 GetResourceAllocationStatus (
680 AcpiConfig,
681 &IoResStatus,
682 &Mem32ResStatus,
683 &PMem32ResStatus,
684 &Mem64ResStatus,
685 &PMem64ResStatus
686 );
687 FreePool (AcpiConfig);
688 }
689 }
690 //
691 // End while
692 //
693
694 //
695 // Raise the EFI_IOB_EC_RESOURCE_CONFLICT status code
696 //
697 //
698 // It is very difficult to follow the spec here
699 // Device path , Bar index can not be get here
700 //
701 ZeroMem (&AllocFailExtendedData, sizeof (AllocFailExtendedData));
702
703 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
704 EFI_PROGRESS_CODE,
705 EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT,
706 (VOID *) &AllocFailExtendedData,
707 sizeof (AllocFailExtendedData)
708 );
709
710 Status = PciHostBridgeAdjustAllocation (
711 &IoPool,
712 &Mem32Pool,
713 &PMem32Pool,
714 &Mem64Pool,
715 &PMem64Pool,
716 IoResStatus,
717 Mem32ResStatus,
718 PMem32ResStatus,
719 Mem64ResStatus,
720 PMem64ResStatus
721 );
722
723 //
724 // Destroy all the resource tree
725 //
726 DestroyResourceTree (&IoPool);
727 DestroyResourceTree (&Mem32Pool);
728 DestroyResourceTree (&PMem32Pool);
729 DestroyResourceTree (&Mem64Pool);
730 DestroyResourceTree (&PMem64Pool);
731
732 NotifyPhase (PciResAlloc, EfiPciHostBridgeFreeResources);
733
734 if (EFI_ERROR (Status)) {
735 return Status;
736 }
737 }
738 }
739 //
740 // End main while
741 //
742
743 //
744 // Raise the EFI_IOB_PCI_RES_ALLOC status code
745 //
746 REPORT_STATUS_CODE_WITH_EXTENDED_DATA (
747 EFI_PROGRESS_CODE,
748 EFI_IO_BUS_PCI | EFI_IOB_PCI_RES_ALLOC,
749 (VOID *) &HandleExtendedData,
750 sizeof (HandleExtendedData)
751 );
752
753 //
754 // Notify pci bus driver starts to program the resource
755 //
756 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeSetResources);
757
758 if (EFI_ERROR (Status)) {
759 return Status;
760 }
761
762 RootBridgeDev = NULL;
763
764 RootBridgeHandle = 0;
765
766 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
767 //
768 // Get RootBridg Device by handle
769 //
770 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
771
772 if (RootBridgeDev == NULL) {
773 return EFI_NOT_FOUND;
774 }
775
776 //
777 // Get acpi resource node for all the resource types
778 //
779 AcpiConfig = NULL;
780 Status = PciResAlloc->GetProposedResources (
781 PciResAlloc,
782 RootBridgeDev->Handle,
783 &AcpiConfig
784 );
785
786 if (EFI_ERROR (Status)) {
787 return Status;
788 }
789
790 //
791 // Get the resource base by interpreting acpi resource node
792 //
793 //
794 GetResourceBase (
795 AcpiConfig,
796 &IoBase,
797 &Mem32Base,
798 &PMem32Base,
799 &Mem64Base,
800 &PMem64Base
801 );
802
803 //
804 // Create the entire system resource map from the information collected by
805 // enumerator. Several resource tree was created
806 //
807 FindResourceNode (RootBridgeDev, &IoPool, &IoBridge);
808 FindResourceNode (RootBridgeDev, &Mem32Pool, &Mem32Bridge);
809 FindResourceNode (RootBridgeDev, &PMem32Pool, &PMem32Bridge);
810 FindResourceNode (RootBridgeDev, &Mem64Pool, &Mem64Bridge);
811 FindResourceNode (RootBridgeDev, &PMem64Pool, &PMem64Bridge);
812
813 ASSERT (IoBridge != NULL);
814 ASSERT (Mem32Bridge != NULL);
815 ASSERT (PMem32Bridge != NULL);
816 ASSERT (Mem64Bridge != NULL);
817 ASSERT (PMem64Bridge != NULL);
818
819 //
820 // Program IO resources
821 //
822 ProgramResource (
823 IoBase,
824 IoBridge
825 );
826
827 //
828 // Program Mem32 resources
829 //
830 ProgramResource (
831 Mem32Base,
832 Mem32Bridge
833 );
834
835 //
836 // Program PMem32 resources
837 //
838 ProgramResource (
839 PMem32Base,
840 PMem32Bridge
841 );
842
843 //
844 // Program Mem64 resources
845 //
846 ProgramResource (
847 Mem64Base,
848 Mem64Bridge
849 );
850
851 //
852 // Program PMem64 resources
853 //
854 ProgramResource (
855 PMem64Base,
856 PMem64Bridge
857 );
858
859 //
860 // Process Option ROM for this root bridge after all BARs are programmed.
861 // The PPB's MEM32 RANGE BAR is re-programmed to the Option ROM BAR Base in order to
862 // shadow the Option ROM of the devices under the PPB.
863 // After the shadow, Option ROM BAR decoding is turned off and the PPB's MEM32 RANGE
864 // BAR is restored back to the original value.
865 // The original value is programmed by ProgramResource() above.
866 //
867 DEBUG ((
868 DEBUG_INFO, "Process Option ROM: BAR Base/Length = %lx/%lx\n",
869 RootBridgeDev->PciBar[0].BaseAddress, RootBridgeDev->PciBar[0].Length
870 ));
871 ProcessOptionRom (RootBridgeDev, RootBridgeDev->PciBar[0].BaseAddress, RootBridgeDev->PciBar[0].Length);
872
873 IoBridge ->PciDev->PciBar[IoBridge ->Bar].BaseAddress = IoBase;
874 Mem32Bridge ->PciDev->PciBar[Mem32Bridge ->Bar].BaseAddress = Mem32Base;
875 PMem32Bridge->PciDev->PciBar[PMem32Bridge->Bar].BaseAddress = PMem32Base;
876 Mem64Bridge ->PciDev->PciBar[Mem64Bridge ->Bar].BaseAddress = Mem64Base;
877 PMem64Bridge->PciDev->PciBar[PMem64Bridge->Bar].BaseAddress = PMem64Base;
878
879 //
880 // Dump the resource map for current root bridge
881 //
882 DEBUG_CODE (
883 PCI_RESOURCE_NODE *Resources[5];
884 Resources[0] = IoBridge;
885 Resources[1] = Mem32Bridge;
886 Resources[2] = PMem32Bridge;
887 Resources[3] = Mem64Bridge;
888 Resources[4] = PMem64Bridge;
889 DumpResourceMap (RootBridgeDev, Resources, ARRAY_SIZE (Resources));
890 );
891
892 FreePool (AcpiConfig);
893 }
894
895 //
896 // Destroy all the resource tree
897 //
898 DestroyResourceTree (&IoPool);
899 DestroyResourceTree (&Mem32Pool);
900 DestroyResourceTree (&PMem32Pool);
901 DestroyResourceTree (&Mem64Pool);
902 DestroyResourceTree (&PMem64Pool);
903
904 //
905 // Notify the resource allocation phase is to end
906 //
907 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeEndResourceAllocation);
908
909 return Status;
910 }
911
912 /**
913 Allocate NumberOfBuses buses and return the next available PCI bus number.
914
915 @param Bridge Bridge device instance.
916 @param StartBusNumber Current available PCI bus number.
917 @param NumberOfBuses Number of buses enumerated below the StartBusNumber.
918 @param NextBusNumber Next available PCI bus number.
919
920 @retval EFI_SUCCESS Available bus number resource is enough. Next available PCI bus number
921 is returned in NextBusNumber.
922 @retval EFI_OUT_OF_RESOURCES Available bus number resource is not enough for allocation.
923
924 **/
925 EFI_STATUS
926 PciAllocateBusNumber (
927 IN PCI_IO_DEVICE *Bridge,
928 IN UINT8 StartBusNumber,
929 IN UINT8 NumberOfBuses,
930 OUT UINT8 *NextBusNumber
931 )
932 {
933 PCI_IO_DEVICE *RootBridge;
934 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges;
935 UINT8 NextNumber;
936 UINT64 MaxNumberInRange;
937
938 //
939 // Get PCI Root Bridge device
940 //
941 RootBridge = Bridge;
942 while (RootBridge->Parent != NULL) {
943 RootBridge = RootBridge->Parent;
944 }
945
946 //
947 // Get next available PCI bus number
948 //
949 BusNumberRanges = RootBridge->BusNumberRanges;
950 while (BusNumberRanges->Desc != ACPI_END_TAG_DESCRIPTOR) {
951 MaxNumberInRange = BusNumberRanges->AddrRangeMin + BusNumberRanges->AddrLen - 1;
952 if (StartBusNumber >= BusNumberRanges->AddrRangeMin && StartBusNumber <= MaxNumberInRange) {
953 NextNumber = (UINT8)(StartBusNumber + NumberOfBuses);
954 while (NextNumber > MaxNumberInRange) {
955 ++BusNumberRanges;
956 if (BusNumberRanges->Desc == ACPI_END_TAG_DESCRIPTOR) {
957 return EFI_OUT_OF_RESOURCES;
958 }
959 NextNumber = (UINT8)(NextNumber + (BusNumberRanges->AddrRangeMin - (MaxNumberInRange + 1)));
960 MaxNumberInRange = BusNumberRanges->AddrRangeMin + BusNumberRanges->AddrLen - 1;
961 }
962 *NextBusNumber = NextNumber;
963 return EFI_SUCCESS;
964 }
965 BusNumberRanges++;
966 }
967 return EFI_OUT_OF_RESOURCES;
968 }
969
970 /**
971 Scan pci bus and assign bus number to the given PCI bus system.
972
973 @param Bridge Bridge device instance.
974 @param StartBusNumber start point.
975 @param SubBusNumber Point to sub bus number.
976 @param PaddedBusRange Customized bus number.
977
978 @retval EFI_SUCCESS Successfully scanned and assigned bus number.
979 @retval other Some error occurred when scanning pci bus.
980
981 @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.
982
983 **/
984 EFI_STATUS
985 PciScanBus (
986 IN PCI_IO_DEVICE *Bridge,
987 IN UINT8 StartBusNumber,
988 OUT UINT8 *SubBusNumber,
989 OUT UINT8 *PaddedBusRange
990 )
991 {
992 EFI_STATUS Status;
993 PCI_TYPE00 Pci;
994 UINT8 Device;
995 UINT8 Func;
996 UINT64 Address;
997 UINT8 SecondBus;
998 UINT8 PaddedSubBus;
999 UINT16 Register;
1000 UINTN HpIndex;
1001 PCI_IO_DEVICE *PciDevice;
1002 EFI_EVENT Event;
1003 EFI_HPC_STATE State;
1004 UINT64 PciAddress;
1005 EFI_HPC_PADDING_ATTRIBUTES Attributes;
1006 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
1007 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *NextDescriptors;
1008 UINT16 BusRange;
1009 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
1010 BOOLEAN BusPadding;
1011 UINT32 TempReservedBusNum;
1012
1013 PciRootBridgeIo = Bridge->PciRootBridgeIo;
1014 SecondBus = 0;
1015 Register = 0;
1016 State = 0;
1017 Attributes = (EFI_HPC_PADDING_ATTRIBUTES) 0;
1018 BusRange = 0;
1019 BusPadding = FALSE;
1020 PciDevice = NULL;
1021 PciAddress = 0;
1022
1023 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
1024 TempReservedBusNum = 0;
1025 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
1026
1027 //
1028 // Check to see whether a pci device is present
1029 //
1030 Status = PciDevicePresent (
1031 PciRootBridgeIo,
1032 &Pci,
1033 StartBusNumber,
1034 Device,
1035 Func
1036 );
1037
1038 if (EFI_ERROR (Status) && Func == 0) {
1039 //
1040 // go to next device if there is no Function 0
1041 //
1042 break;
1043 }
1044
1045 if (EFI_ERROR (Status)) {
1046 continue;
1047 }
1048
1049 //
1050 // Get the PCI device information
1051 //
1052 Status = PciSearchDevice (
1053 Bridge,
1054 &Pci,
1055 StartBusNumber,
1056 Device,
1057 Func,
1058 &PciDevice
1059 );
1060
1061 ASSERT (!EFI_ERROR (Status));
1062
1063 PciAddress = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, 0);
1064
1065 if (!IS_PCI_BRIDGE (&Pci)) {
1066 //
1067 // PCI bridges will be called later
1068 // Here just need for PCI device or PCI to cardbus controller
1069 // EfiPciBeforeChildBusEnumeration for PCI Device Node
1070 //
1071 PreprocessController (
1072 PciDevice,
1073 PciDevice->BusNumber,
1074 PciDevice->DeviceNumber,
1075 PciDevice->FunctionNumber,
1076 EfiPciBeforeChildBusEnumeration
1077 );
1078 }
1079
1080 if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1081 //
1082 // For Pci Hotplug controller devcie only
1083 //
1084 if (gPciHotPlugInit != NULL) {
1085 //
1086 // Check if it is a Hotplug PCI controller
1087 //
1088 if (IsRootPciHotPlugController (PciDevice->DevicePath, &HpIndex)) {
1089 gPciRootHpcData[HpIndex].Found = TRUE;
1090
1091 if (!gPciRootHpcData[HpIndex].Initialized) {
1092
1093 Status = CreateEventForHpc (HpIndex, &Event);
1094
1095 ASSERT (!EFI_ERROR (Status));
1096
1097 Status = gPciHotPlugInit->InitializeRootHpc (
1098 gPciHotPlugInit,
1099 gPciRootHpcPool[HpIndex].HpcDevicePath,
1100 PciAddress,
1101 Event,
1102 &State
1103 );
1104
1105 PreprocessController (
1106 PciDevice,
1107 PciDevice->BusNumber,
1108 PciDevice->DeviceNumber,
1109 PciDevice->FunctionNumber,
1110 EfiPciBeforeChildBusEnumeration
1111 );
1112 }
1113 }
1114 }
1115 }
1116
1117 if (IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci)) {
1118 //
1119 // For PPB
1120 //
1121 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1122 //
1123 // If Hot Plug is not supported,
1124 // get the bridge information
1125 //
1126 Status = PciSearchDevice (
1127 Bridge,
1128 &Pci,
1129 StartBusNumber,
1130 Device,
1131 Func,
1132 &PciDevice
1133 );
1134
1135 if (EFI_ERROR (Status)) {
1136 return Status;
1137 }
1138 } else {
1139 //
1140 // If Hot Plug is supported,
1141 // Get the bridge information
1142 //
1143 BusPadding = FALSE;
1144 if (gPciHotPlugInit != NULL) {
1145
1146 if (IsPciHotPlugBus (PciDevice)) {
1147
1148 //
1149 // If it is initialized, get the padded bus range
1150 //
1151 Status = gPciHotPlugInit->GetResourcePadding (
1152 gPciHotPlugInit,
1153 PciDevice->DevicePath,
1154 PciAddress,
1155 &State,
1156 (VOID **) &Descriptors,
1157 &Attributes
1158 );
1159
1160 if (EFI_ERROR (Status)) {
1161 return Status;
1162 }
1163
1164 BusRange = 0;
1165 NextDescriptors = Descriptors;
1166 Status = PciGetBusRange (
1167 &NextDescriptors,
1168 NULL,
1169 NULL,
1170 &BusRange
1171 );
1172
1173 FreePool (Descriptors);
1174
1175 if (!EFI_ERROR (Status)) {
1176 BusPadding = TRUE;
1177 } else if (Status != EFI_NOT_FOUND) {
1178 //
1179 // EFI_NOT_FOUND is not a real error. It indicates no bus number padding requested.
1180 //
1181 return Status;
1182 }
1183 }
1184 }
1185 }
1186
1187 Status = PciAllocateBusNumber (Bridge, *SubBusNumber, 1, SubBusNumber);
1188 if (EFI_ERROR (Status)) {
1189 return Status;
1190 }
1191 SecondBus = *SubBusNumber;
1192
1193 Register = (UINT16) ((SecondBus << 8) | (UINT16) StartBusNumber);
1194 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET);
1195
1196 Status = PciRootBridgeIo->Pci.Write (
1197 PciRootBridgeIo,
1198 EfiPciWidthUint16,
1199 Address,
1200 1,
1201 &Register
1202 );
1203
1204
1205 //
1206 // If it is PPB, resursively search down this bridge
1207 //
1208 if (IS_PCI_BRIDGE (&Pci)) {
1209
1210 //
1211 // Temporarily initialize SubBusNumber to maximum bus number to ensure the
1212 // PCI configuration transaction to go through any PPB
1213 //
1214 Register = PciGetMaxBusNumber (Bridge);
1215 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
1216 Status = PciRootBridgeIo->Pci.Write (
1217 PciRootBridgeIo,
1218 EfiPciWidthUint8,
1219 Address,
1220 1,
1221 &Register
1222 );
1223
1224 //
1225 // Nofify EfiPciBeforeChildBusEnumeration for PCI Brige
1226 //
1227 PreprocessController (
1228 PciDevice,
1229 PciDevice->BusNumber,
1230 PciDevice->DeviceNumber,
1231 PciDevice->FunctionNumber,
1232 EfiPciBeforeChildBusEnumeration
1233 );
1234
1235 Status = PciScanBus (
1236 PciDevice,
1237 SecondBus,
1238 SubBusNumber,
1239 PaddedBusRange
1240 );
1241 if (EFI_ERROR (Status)) {
1242 return Status;
1243 }
1244 }
1245
1246 if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport) && BusPadding) {
1247 //
1248 // Ensure the device is enabled and initialized
1249 //
1250 if ((Attributes == EfiPaddingPciRootBridge) &&
1251 (State & EFI_HPC_STATE_ENABLED) != 0 &&
1252 (State & EFI_HPC_STATE_INITIALIZED) != 0) {
1253 *PaddedBusRange = (UINT8) ((UINT8) (BusRange) + *PaddedBusRange);
1254 } else {
1255 //
1256 // Reserve the larger one between the actual occupied bus number and padded bus number
1257 //
1258 Status = PciAllocateBusNumber (PciDevice, SecondBus, (UINT8) (BusRange), &PaddedSubBus);
1259 if (EFI_ERROR (Status)) {
1260 return Status;
1261 }
1262 *SubBusNumber = MAX (PaddedSubBus, *SubBusNumber);
1263 }
1264 }
1265
1266 //
1267 // Set the current maximum bus number under the PPB
1268 //
1269 Address = EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
1270
1271 Status = PciRootBridgeIo->Pci.Write (
1272 PciRootBridgeIo,
1273 EfiPciWidthUint8,
1274 Address,
1275 1,
1276 SubBusNumber
1277 );
1278 } else {
1279 //
1280 // It is device. Check PCI IOV for Bus reservation
1281 // Go through each function, just reserve the MAX ReservedBusNum for one device
1282 //
1283 if (PcdGetBool (PcdSrIovSupport) && PciDevice->SrIovCapabilityOffset != 0) {
1284 if (TempReservedBusNum < PciDevice->ReservedBusNum) {
1285
1286 Status = PciAllocateBusNumber (PciDevice, *SubBusNumber, (UINT8) (PciDevice->ReservedBusNum - TempReservedBusNum), SubBusNumber);
1287 if (EFI_ERROR (Status)) {
1288 return Status;
1289 }
1290 TempReservedBusNum = PciDevice->ReservedBusNum;
1291
1292 if (Func == 0) {
1293 DEBUG ((EFI_D_INFO, "PCI-IOV ScanBus - SubBusNumber - 0x%x\n", *SubBusNumber));
1294 } else {
1295 DEBUG ((EFI_D_INFO, "PCI-IOV ScanBus - SubBusNumber - 0x%x (Update)\n", *SubBusNumber));
1296 }
1297 }
1298 }
1299 }
1300
1301 if (Func == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
1302
1303 //
1304 // Skip sub functions, this is not a multi function device
1305 //
1306
1307 Func = PCI_MAX_FUNC;
1308 }
1309 }
1310 }
1311
1312 return EFI_SUCCESS;
1313 }
1314
1315 /**
1316 Process Option Rom on the specified root bridge.
1317
1318 @param Bridge Pci root bridge device instance.
1319
1320 @retval EFI_SUCCESS Success process.
1321 @retval other Some error occurred when processing Option Rom on the root bridge.
1322
1323 **/
1324 EFI_STATUS
1325 PciRootBridgeP2CProcess (
1326 IN PCI_IO_DEVICE *Bridge
1327 )
1328 {
1329 LIST_ENTRY *CurrentLink;
1330 PCI_IO_DEVICE *Temp;
1331 EFI_HPC_STATE State;
1332 UINT64 PciAddress;
1333 EFI_STATUS Status;
1334
1335 CurrentLink = Bridge->ChildList.ForwardLink;
1336
1337 while (CurrentLink != NULL && CurrentLink != &Bridge->ChildList) {
1338
1339 Temp = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
1340
1341 if (IS_CARDBUS_BRIDGE (&Temp->Pci)) {
1342
1343 if (gPciHotPlugInit != NULL && Temp->Allocated && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1344
1345 //
1346 // Raise the EFI_IOB_PCI_HPC_INIT status code
1347 //
1348 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1349 EFI_PROGRESS_CODE,
1350 EFI_IO_BUS_PCI | EFI_IOB_PCI_HPC_INIT,
1351 Temp->DevicePath
1352 );
1353
1354 PciAddress = EFI_PCI_ADDRESS (Temp->BusNumber, Temp->DeviceNumber, Temp->FunctionNumber, 0);
1355 Status = gPciHotPlugInit->InitializeRootHpc (
1356 gPciHotPlugInit,
1357 Temp->DevicePath,
1358 PciAddress,
1359 NULL,
1360 &State
1361 );
1362
1363 if (!EFI_ERROR (Status)) {
1364 Status = PciBridgeEnumerator (Temp);
1365
1366 if (EFI_ERROR (Status)) {
1367 return Status;
1368 }
1369 }
1370
1371 CurrentLink = CurrentLink->ForwardLink;
1372 continue;
1373
1374 }
1375 }
1376
1377 if (!IsListEmpty (&Temp->ChildList)) {
1378 Status = PciRootBridgeP2CProcess (Temp);
1379 }
1380
1381 CurrentLink = CurrentLink->ForwardLink;
1382 }
1383
1384 return EFI_SUCCESS;
1385 }
1386
1387 /**
1388 Process Option Rom on the specified host bridge.
1389
1390 @param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
1391
1392 @retval EFI_SUCCESS Success process.
1393 @retval EFI_NOT_FOUND Can not find the root bridge instance.
1394 @retval other Some error occurred when processing Option Rom on the host bridge.
1395
1396 **/
1397 EFI_STATUS
1398 PciHostBridgeP2CProcess (
1399 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
1400 )
1401 {
1402 EFI_HANDLE RootBridgeHandle;
1403 PCI_IO_DEVICE *RootBridgeDev;
1404 EFI_STATUS Status;
1405
1406 if (!FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1407 return EFI_SUCCESS;
1408 }
1409
1410 RootBridgeHandle = NULL;
1411
1412 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
1413
1414 //
1415 // Get RootBridg Device by handle
1416 //
1417 RootBridgeDev = GetRootBridgeByHandle (RootBridgeHandle);
1418
1419 if (RootBridgeDev == NULL) {
1420 return EFI_NOT_FOUND;
1421 }
1422
1423 Status = PciRootBridgeP2CProcess (RootBridgeDev);
1424 if (EFI_ERROR (Status)) {
1425 return Status;
1426 }
1427
1428 }
1429
1430 return EFI_SUCCESS;
1431 }
1432
1433 /**
1434 This function is used to enumerate the entire host bridge
1435 in a given platform.
1436
1437 @param PciResAlloc A pointer to the PCI Host Resource Allocation protocol.
1438
1439 @retval EFI_SUCCESS Successfully enumerated the host bridge.
1440 @retval EFI_OUT_OF_RESOURCES No enough memory available.
1441 @retval other Some error occurred when enumerating the host bridge.
1442
1443 **/
1444 EFI_STATUS
1445 PciHostBridgeEnumerator (
1446 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
1447 )
1448 {
1449 EFI_HANDLE RootBridgeHandle;
1450 PCI_IO_DEVICE *RootBridgeDev;
1451 EFI_STATUS Status;
1452 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
1453 UINT16 MinBus;
1454 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
1455 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;
1456 UINT8 StartBusNumber;
1457 LIST_ENTRY RootBridgeList;
1458 LIST_ENTRY *Link;
1459
1460 if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1461 InitializeHotPlugSupport ();
1462 }
1463
1464 InitializeListHead (&RootBridgeList);
1465
1466 //
1467 // Notify the bus allocation phase is about to start
1468 //
1469 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);
1470
1471 if (EFI_ERROR (Status)) {
1472 return Status;
1473 }
1474
1475 DEBUG((EFI_D_INFO, "PCI Bus First Scanning\n"));
1476 RootBridgeHandle = NULL;
1477 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
1478
1479 //
1480 // if a root bridge instance is found, create root bridge device for it
1481 //
1482
1483 RootBridgeDev = CreateRootBridge (RootBridgeHandle);
1484
1485 if (RootBridgeDev == NULL) {
1486 return EFI_OUT_OF_RESOURCES;
1487 }
1488
1489 //
1490 // Enumerate all the buses under this root bridge
1491 //
1492 Status = PciRootBridgeEnumerator (
1493 PciResAlloc,
1494 RootBridgeDev
1495 );
1496
1497 if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1498 InsertTailList (&RootBridgeList, &(RootBridgeDev->Link));
1499 } else {
1500 DestroyRootBridge (RootBridgeDev);
1501 }
1502 if (EFI_ERROR (Status)) {
1503 return Status;
1504 }
1505 }
1506
1507 //
1508 // Notify the bus allocation phase is finished for the first time
1509 //
1510 NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);
1511
1512 if (gPciHotPlugInit != NULL && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {
1513 //
1514 // Reset all assigned PCI bus number in all PPB
1515 //
1516 RootBridgeHandle = NULL;
1517 Link = GetFirstNode (&RootBridgeList);
1518 while ((PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) &&
1519 (!IsNull (&RootBridgeList, Link))) {
1520 RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (Link);
1521 //
1522 // Get the Bus information
1523 //
1524 Status = PciResAlloc->StartBusEnumeration (
1525 PciResAlloc,
1526 RootBridgeHandle,
1527 (VOID **) &Configuration
1528 );
1529 if (EFI_ERROR (Status)) {
1530 return Status;
1531 }
1532
1533 //
1534 // Get the bus number to start with
1535 //
1536 StartBusNumber = (UINT8) (Configuration->AddrRangeMin);
1537
1538 ResetAllPpbBusNumber (
1539 RootBridgeDev,
1540 StartBusNumber
1541 );
1542
1543 FreePool (Configuration);
1544 Link = RemoveEntryList (Link);
1545 DestroyRootBridge (RootBridgeDev);
1546 }
1547
1548 //
1549 // Wait for all HPC initialized
1550 //
1551 Status = AllRootHPCInitialized (STALL_1_SECOND * 15);
1552
1553 if (EFI_ERROR (Status)) {
1554 DEBUG ((EFI_D_ERROR, "Some root HPC failed to initialize\n"));
1555 return Status;
1556 }
1557
1558 //
1559 // Notify the bus allocation phase is about to start for the 2nd time
1560 //
1561 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);
1562
1563 if (EFI_ERROR (Status)) {
1564 return Status;
1565 }
1566
1567 DEBUG((EFI_D_INFO, "PCI Bus Second Scanning\n"));
1568 RootBridgeHandle = NULL;
1569 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
1570
1571 //
1572 // if a root bridge instance is found, create root bridge device for it
1573 //
1574 RootBridgeDev = CreateRootBridge (RootBridgeHandle);
1575
1576 if (RootBridgeDev == NULL) {
1577 return EFI_OUT_OF_RESOURCES;
1578 }
1579
1580 //
1581 // Enumerate all the buses under this root bridge
1582 //
1583 Status = PciRootBridgeEnumerator (
1584 PciResAlloc,
1585 RootBridgeDev
1586 );
1587
1588 DestroyRootBridge (RootBridgeDev);
1589 if (EFI_ERROR (Status)) {
1590 return Status;
1591 }
1592 }
1593
1594 //
1595 // Notify the bus allocation phase is to end for the 2nd time
1596 //
1597 NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);
1598 }
1599
1600 //
1601 // Notify the resource allocation phase is to start
1602 //
1603 Status = NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginResourceAllocation);
1604
1605 if (EFI_ERROR (Status)) {
1606 return Status;
1607 }
1608
1609 RootBridgeHandle = NULL;
1610 while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {
1611
1612 //
1613 // if a root bridge instance is found, create root bridge device for it
1614 //
1615 RootBridgeDev = CreateRootBridge (RootBridgeHandle);
1616
1617 if (RootBridgeDev == NULL) {
1618 return EFI_OUT_OF_RESOURCES;
1619 }
1620
1621 Status = StartManagingRootBridge (RootBridgeDev);
1622
1623 if (EFI_ERROR (Status)) {
1624 return Status;
1625 }
1626
1627 PciRootBridgeIo = RootBridgeDev->PciRootBridgeIo;
1628 Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);
1629
1630 if (EFI_ERROR (Status)) {
1631 return Status;
1632 }
1633
1634 Status = PciGetBusRange (&Descriptors, &MinBus, NULL, NULL);
1635
1636 if (EFI_ERROR (Status)) {
1637 return Status;
1638 }
1639
1640 //
1641 // Determine root bridge attribute by calling interface of Pcihostbridge
1642 // protocol
1643 //
1644 DetermineRootBridgeAttributes (
1645 PciResAlloc,
1646 RootBridgeDev
1647 );
1648
1649 //
1650 // Collect all the resource information under this root bridge
1651 // A database that records all the information about pci device subject to this
1652 // root bridge will then be created
1653 //
1654 Status = PciPciDeviceInfoCollector (
1655 RootBridgeDev,
1656 (UINT8) MinBus
1657 );
1658
1659 if (EFI_ERROR (Status)) {
1660 return Status;
1661 }
1662
1663 InsertRootBridge (RootBridgeDev);
1664
1665 //
1666 // Record the hostbridge handle
1667 //
1668 AddHostBridgeEnumerator (RootBridgeDev->PciRootBridgeIo->ParentHandle);
1669 }
1670
1671 return EFI_SUCCESS;
1672 }
EFI Development Kit II mirror for PVE