3 PCI Root Bridge Io Protocol code.
5 Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "PciHostBridge.h"
17 #include "PciRootBridge.h"
18 #include "PciHostResource.h"
20 extern EDKII_IOMMU_PROTOCOL
*mIoMmuProtocol
;
22 #define NO_MAPPING (VOID *) (UINTN) -1
24 #define RESOURCE_VALID(Resource) ((Resource)->Base <= (Resource)->Limit)
27 // Lookup table for increment values based on transfer widths
30 1, // EfiPciWidthUint8
31 2, // EfiPciWidthUint16
32 4, // EfiPciWidthUint32
33 8, // EfiPciWidthUint64
34 0, // EfiPciWidthFifoUint8
35 0, // EfiPciWidthFifoUint16
36 0, // EfiPciWidthFifoUint32
37 0, // EfiPciWidthFifoUint64
38 1, // EfiPciWidthFillUint8
39 2, // EfiPciWidthFillUint16
40 4, // EfiPciWidthFillUint32
41 8 // EfiPciWidthFillUint64
45 // Lookup table for increment values based on transfer widths
47 UINT8 mOutStride
[] = {
48 1, // EfiPciWidthUint8
49 2, // EfiPciWidthUint16
50 4, // EfiPciWidthUint32
51 8, // EfiPciWidthUint64
52 1, // EfiPciWidthFifoUint8
53 2, // EfiPciWidthFifoUint16
54 4, // EfiPciWidthFifoUint32
55 8, // EfiPciWidthFifoUint64
56 0, // EfiPciWidthFillUint8
57 0, // EfiPciWidthFillUint16
58 0, // EfiPciWidthFillUint32
59 0 // EfiPciWidthFillUint64
63 Construct the Pci Root Bridge instance.
65 @param Bridge The root bridge instance.
67 @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created
68 or NULL if creation fails.
70 PCI_ROOT_BRIDGE_INSTANCE
*
72 IN PCI_ROOT_BRIDGE
*Bridge
75 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
76 PCI_RESOURCE_TYPE Index
;
77 CHAR16
*DevicePathStr
;
78 PCI_ROOT_BRIDGE_APERTURE
*Aperture
;
82 DEBUG ((EFI_D_INFO
, "RootBridge: "));
83 DEBUG ((EFI_D_INFO
, "%s\n", DevicePathStr
= ConvertDevicePathToText (Bridge
->DevicePath
, FALSE
, FALSE
)));
84 DEBUG ((EFI_D_INFO
, " Support/Attr: %lx / %lx\n", Bridge
->Supports
, Bridge
->Attributes
));
85 DEBUG ((EFI_D_INFO
, " DmaAbove4G: %s\n", Bridge
->DmaAbove4G
? L
"Yes" : L
"No"));
86 DEBUG ((EFI_D_INFO
, "NoExtConfSpace: %s\n", Bridge
->NoExtendedConfigSpace
? L
"Yes" : L
"No"));
87 DEBUG ((EFI_D_INFO
, " AllocAttr: %lx (%s%s)\n", Bridge
->AllocationAttributes
,
88 (Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
) != 0 ? L
"CombineMemPMem " : L
"",
89 (Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_MEM64_DECODE
) != 0 ? L
"Mem64Decode" : L
""
92 EFI_D_INFO
, " Bus: %lx - %lx Translation=%lx\n",
93 Bridge
->Bus
.Base
, Bridge
->Bus
.Limit
, Bridge
->Bus
.Translation
96 // Translation for bus is not supported.
98 ASSERT (Bridge
->Bus
.Translation
== 0);
99 if (Bridge
->Bus
.Translation
!= 0) {
104 DEBUG_INFO
, " Io: %lx - %lx Translation=%lx\n",
105 Bridge
->Io
.Base
, Bridge
->Io
.Limit
, Bridge
->Io
.Translation
108 DEBUG_INFO
, " Mem: %lx - %lx Translation=%lx\n",
109 Bridge
->Mem
.Base
, Bridge
->Mem
.Limit
, Bridge
->Mem
.Translation
112 DEBUG_INFO
, " MemAbove4G: %lx - %lx Translation=%lx\n",
113 Bridge
->MemAbove4G
.Base
, Bridge
->MemAbove4G
.Limit
, Bridge
->MemAbove4G
.Translation
116 DEBUG_INFO
, " PMem: %lx - %lx Translation=%lx\n",
117 Bridge
->PMem
.Base
, Bridge
->PMem
.Limit
, Bridge
->PMem
.Translation
120 DEBUG_INFO
, " PMemAbove4G: %lx - %lx Translation=%lx\n",
121 Bridge
->PMemAbove4G
.Base
, Bridge
->PMemAbove4G
.Limit
, Bridge
->PMemAbove4G
.Translation
125 // Make sure Mem and MemAbove4G apertures are valid
127 if (RESOURCE_VALID (&Bridge
->Mem
)) {
128 ASSERT (Bridge
->Mem
.Limit
< SIZE_4GB
);
129 if (Bridge
->Mem
.Limit
>= SIZE_4GB
) {
133 if (RESOURCE_VALID (&Bridge
->MemAbove4G
)) {
134 ASSERT (Bridge
->MemAbove4G
.Base
>= SIZE_4GB
);
135 if (Bridge
->MemAbove4G
.Base
< SIZE_4GB
) {
139 if (RESOURCE_VALID (&Bridge
->PMem
)) {
140 ASSERT (Bridge
->PMem
.Limit
< SIZE_4GB
);
141 if (Bridge
->PMem
.Limit
>= SIZE_4GB
) {
145 if (RESOURCE_VALID (&Bridge
->PMemAbove4G
)) {
146 ASSERT (Bridge
->PMemAbove4G
.Base
>= SIZE_4GB
);
147 if (Bridge
->PMemAbove4G
.Base
< SIZE_4GB
) {
153 // Ignore AllocationAttributes when resources were already assigned.
155 if (!Bridge
->ResourceAssigned
) {
156 if ((Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
) != 0) {
158 // If this bit is set, then the PCI Root Bridge does not
159 // support separate windows for Non-prefetchable and Prefetchable
162 ASSERT (!RESOURCE_VALID (&Bridge
->PMem
));
163 ASSERT (!RESOURCE_VALID (&Bridge
->PMemAbove4G
));
164 if (RESOURCE_VALID (&Bridge
->PMem
) || RESOURCE_VALID (&Bridge
->PMemAbove4G
)) {
169 if ((Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_MEM64_DECODE
) == 0) {
171 // If this bit is not set, then the PCI Root Bridge does not support
172 // 64 bit memory windows.
174 ASSERT (!RESOURCE_VALID (&Bridge
->MemAbove4G
));
175 ASSERT (!RESOURCE_VALID (&Bridge
->PMemAbove4G
));
176 if (RESOURCE_VALID (&Bridge
->MemAbove4G
) || RESOURCE_VALID (&Bridge
->PMemAbove4G
)) {
182 RootBridge
= AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE
));
183 ASSERT (RootBridge
!= NULL
);
185 RootBridge
->Signature
= PCI_ROOT_BRIDGE_SIGNATURE
;
186 RootBridge
->Supports
= Bridge
->Supports
;
187 RootBridge
->Attributes
= Bridge
->Attributes
;
188 RootBridge
->DmaAbove4G
= Bridge
->DmaAbove4G
;
189 RootBridge
->NoExtendedConfigSpace
= Bridge
->NoExtendedConfigSpace
;
190 RootBridge
->AllocationAttributes
= Bridge
->AllocationAttributes
;
191 RootBridge
->DevicePath
= DuplicateDevicePath (Bridge
->DevicePath
);
192 RootBridge
->DevicePathStr
= DevicePathStr
;
193 RootBridge
->ConfigBuffer
= AllocatePool (
194 TypeMax
* sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
)
196 ASSERT (RootBridge
->ConfigBuffer
!= NULL
);
197 InitializeListHead (&RootBridge
->Maps
);
199 CopyMem (&RootBridge
->Bus
, &Bridge
->Bus
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
200 CopyMem (&RootBridge
->Io
, &Bridge
->Io
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
201 CopyMem (&RootBridge
->Mem
, &Bridge
->Mem
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
202 CopyMem (&RootBridge
->MemAbove4G
, &Bridge
->MemAbove4G
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
203 CopyMem (&RootBridge
->PMem
, &Bridge
->PMem
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
204 CopyMem (&RootBridge
->PMemAbove4G
, &Bridge
->PMemAbove4G
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
206 for (Index
= TypeIo
; Index
< TypeMax
; Index
++) {
209 Aperture
= &RootBridge
->Bus
;
212 Aperture
= &RootBridge
->Io
;
215 Aperture
= &RootBridge
->Mem
;
218 Aperture
= &RootBridge
->MemAbove4G
;
221 Aperture
= &RootBridge
->PMem
;
224 Aperture
= &RootBridge
->PMemAbove4G
;
231 RootBridge
->ResAllocNode
[Index
].Type
= Index
;
232 if (Bridge
->ResourceAssigned
&& (Aperture
->Limit
>= Aperture
->Base
)) {
234 // Base in ResAllocNode is a host address, while Base in Aperture is a
237 RootBridge
->ResAllocNode
[Index
].Base
= TO_HOST_ADDRESS (Aperture
->Base
,
238 Aperture
->Translation
);
239 RootBridge
->ResAllocNode
[Index
].Length
= Aperture
->Limit
- Aperture
->Base
+ 1;
240 RootBridge
->ResAllocNode
[Index
].Status
= ResAllocated
;
242 RootBridge
->ResAllocNode
[Index
].Base
= 0;
243 RootBridge
->ResAllocNode
[Index
].Length
= 0;
244 RootBridge
->ResAllocNode
[Index
].Status
= ResNone
;
248 RootBridge
->RootBridgeIo
.SegmentNumber
= Bridge
->Segment
;
249 RootBridge
->RootBridgeIo
.PollMem
= RootBridgeIoPollMem
;
250 RootBridge
->RootBridgeIo
.PollIo
= RootBridgeIoPollIo
;
251 RootBridge
->RootBridgeIo
.Mem
.Read
= RootBridgeIoMemRead
;
252 RootBridge
->RootBridgeIo
.Mem
.Write
= RootBridgeIoMemWrite
;
253 RootBridge
->RootBridgeIo
.Io
.Read
= RootBridgeIoIoRead
;
254 RootBridge
->RootBridgeIo
.Io
.Write
= RootBridgeIoIoWrite
;
255 RootBridge
->RootBridgeIo
.CopyMem
= RootBridgeIoCopyMem
;
256 RootBridge
->RootBridgeIo
.Pci
.Read
= RootBridgeIoPciRead
;
257 RootBridge
->RootBridgeIo
.Pci
.Write
= RootBridgeIoPciWrite
;
258 RootBridge
->RootBridgeIo
.Map
= RootBridgeIoMap
;
259 RootBridge
->RootBridgeIo
.Unmap
= RootBridgeIoUnmap
;
260 RootBridge
->RootBridgeIo
.AllocateBuffer
= RootBridgeIoAllocateBuffer
;
261 RootBridge
->RootBridgeIo
.FreeBuffer
= RootBridgeIoFreeBuffer
;
262 RootBridge
->RootBridgeIo
.Flush
= RootBridgeIoFlush
;
263 RootBridge
->RootBridgeIo
.GetAttributes
= RootBridgeIoGetAttributes
;
264 RootBridge
->RootBridgeIo
.SetAttributes
= RootBridgeIoSetAttributes
;
265 RootBridge
->RootBridgeIo
.Configuration
= RootBridgeIoConfiguration
;
271 Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
273 The I/O operations are carried out exactly as requested. The caller is
274 responsible for satisfying any alignment and I/O width restrictions that a PI
275 System on a platform might require. For example on some platforms, width
276 requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other
277 hand, will be handled by the driver.
279 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
281 @param[in] OperationType I/O operation type: IO/MMIO/PCI.
283 @param[in] Width Signifies the width of the I/O or Memory operation.
285 @param[in] Address The base address of the I/O operation.
287 @param[in] Count The number of I/O operations to perform. The number
288 of bytes moved is Width size * Count, starting at
291 @param[in] Buffer For read operations, the destination buffer to
292 store the results. For write operations, the source
293 buffer from which to write data.
295 @retval EFI_SUCCESS The parameters for this request pass the
298 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
300 @retval EFI_INVALID_PARAMETER Buffer is NULL.
302 @retval EFI_INVALID_PARAMETER Address or Count is invalid.
304 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
306 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
307 and Count is not valid for this PI system.
310 RootBridgeIoCheckParameter (
311 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
312 IN OPERATION_TYPE OperationType
,
313 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
319 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
320 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*PciRbAddr
;
327 // Check to see if Buffer is NULL
329 if (Buffer
== NULL
) {
330 return EFI_INVALID_PARAMETER
;
334 // Check to see if Width is in the valid range
336 if ((UINT32
) Width
>= EfiPciWidthMaximum
) {
337 return EFI_INVALID_PARAMETER
;
341 // For FIFO type, the device address won't increase during the access,
342 // so treat Count as 1
344 if (Width
>= EfiPciWidthFifoUint8
&& Width
<= EfiPciWidthFifoUint64
) {
348 Width
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
352 // Make sure (Count * Size) doesn't exceed MAX_UINT64
354 if (Count
> DivU64x32 (MAX_UINT64
, Size
)) {
355 return EFI_INVALID_PARAMETER
;
359 // Check to see if Address is aligned
361 if ((Address
& (Size
- 1)) != 0) {
362 return EFI_UNSUPPORTED
;
366 // Make sure (Address + Count * Size) doesn't exceed MAX_UINT64
368 Length
= MultU64x32 (Count
, Size
);
369 if (Address
> MAX_UINT64
- Length
) {
370 return EFI_INVALID_PARAMETER
;
373 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
376 // Check to see if any address associated with this transfer exceeds the
377 // maximum allowed address. The maximum address implied by the parameters
378 // passed in is Address + Size * Count. If the following condition is met,
379 // then the transfer is not supported.
381 // Address + Size * Count > Limit + 1
383 // Since Limit can be the maximum integer value supported by the CPU and
384 // Count can also be the maximum integer value supported by the CPU, this
385 // range check must be adjusted to avoid all oveflow conditions.
387 if (OperationType
== IoOperation
) {
389 // Allow Legacy IO access
391 if (Address
+ Length
<= 0x1000) {
392 if ((RootBridge
->Attributes
& (
393 EFI_PCI_ATTRIBUTE_ISA_IO
| EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO
| EFI_PCI_ATTRIBUTE_VGA_IO
|
394 EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO
| EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO
|
395 EFI_PCI_ATTRIBUTE_ISA_IO_16
| EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
| EFI_PCI_ATTRIBUTE_VGA_IO_16
)) != 0) {
399 Base
= RootBridge
->Io
.Base
;
400 Limit
= RootBridge
->Io
.Limit
;
401 } else if (OperationType
== MemOperation
) {
403 // Allow Legacy MMIO access
405 if ((Address
>= 0xA0000) && (Address
+ Length
) <= 0xC0000) {
406 if ((RootBridge
->Attributes
& EFI_PCI_ATTRIBUTE_VGA_MEMORY
) != 0) {
411 // By comparing the Address against Limit we know which range to be used
414 if ((Address
>= RootBridge
->Mem
.Base
) && (Address
+ Length
<= RootBridge
->Mem
.Limit
+ 1)) {
415 Base
= RootBridge
->Mem
.Base
;
416 Limit
= RootBridge
->Mem
.Limit
;
417 } else if ((Address
>= RootBridge
->PMem
.Base
) && (Address
+ Length
<= RootBridge
->PMem
.Limit
+ 1)) {
418 Base
= RootBridge
->PMem
.Base
;
419 Limit
= RootBridge
->PMem
.Limit
;
420 } else if ((Address
>= RootBridge
->MemAbove4G
.Base
) && (Address
+ Length
<= RootBridge
->MemAbove4G
.Limit
+ 1)) {
421 Base
= RootBridge
->MemAbove4G
.Base
;
422 Limit
= RootBridge
->MemAbove4G
.Limit
;
424 Base
= RootBridge
->PMemAbove4G
.Base
;
425 Limit
= RootBridge
->PMemAbove4G
.Limit
;
428 PciRbAddr
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*) &Address
;
429 if (PciRbAddr
->Bus
< RootBridge
->Bus
.Base
||
430 PciRbAddr
->Bus
> RootBridge
->Bus
.Limit
) {
431 return EFI_INVALID_PARAMETER
;
434 if (PciRbAddr
->Device
> PCI_MAX_DEVICE
||
435 PciRbAddr
->Function
> PCI_MAX_FUNC
) {
436 return EFI_INVALID_PARAMETER
;
439 if (PciRbAddr
->ExtendedRegister
!= 0) {
440 Address
= PciRbAddr
->ExtendedRegister
;
442 Address
= PciRbAddr
->Register
;
445 Limit
= RootBridge
->NoExtendedConfigSpace
? 0xFF : 0xFFF;
448 if (Address
< Base
) {
449 return EFI_INVALID_PARAMETER
;
452 if (Address
+ Length
> Limit
+ 1) {
453 return EFI_INVALID_PARAMETER
;
460 Use address to match apertures of memory type and then get the corresponding
463 @param RootBridge The root bridge instance.
464 @param Address The address used to match aperture.
465 @param Translation Pointer containing the output translation.
467 @return EFI_SUCCESS Get translation successfully.
468 @return EFI_INVALID_PARAMETER No matched memory aperture; the input Address
472 RootBridgeIoGetMemTranslationByAddress (
473 IN PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
,
475 IN OUT UINT64
*Translation
478 if (Address
>= RootBridge
->Mem
.Base
&& Address
<= RootBridge
->Mem
.Limit
) {
479 *Translation
= RootBridge
->Mem
.Translation
;
480 } else if (Address
>= RootBridge
->PMem
.Base
&& Address
<= RootBridge
->PMem
.Limit
) {
481 *Translation
= RootBridge
->PMem
.Translation
;
482 } else if (Address
>= RootBridge
->MemAbove4G
.Base
&& Address
<= RootBridge
->MemAbove4G
.Limit
) {
483 *Translation
= RootBridge
->MemAbove4G
.Translation
;
484 } else if (Address
>= RootBridge
->PMemAbove4G
.Base
&& Address
<= RootBridge
->PMemAbove4G
.Limit
) {
485 *Translation
= RootBridge
->PMemAbove4G
.Translation
;
487 return EFI_INVALID_PARAMETER
;
494 Return the result of (Multiplicand * Multiplier / Divisor).
496 @param Multiplicand A 64-bit unsigned value.
497 @param Multiplier A 64-bit unsigned value.
498 @param Divisor A 32-bit unsigned value.
499 @param Remainder A pointer to a 32-bit unsigned value. This parameter is
500 optional and may be NULL.
502 @return Multiplicand * Multiplier / Divisor.
505 MultThenDivU64x64x32 (
506 IN UINT64 Multiplicand
,
507 IN UINT64 Multiplier
,
509 OUT UINT32
*Remainder OPTIONAL
513 UINT32 LocalRemainder
;
515 if (Multiplicand
> DivU64x64Remainder (MAX_UINT64
, Multiplier
, NULL
)) {
517 // Make sure Multiplicand is the bigger one.
519 if (Multiplicand
< Multiplier
) {
520 Uint64
= Multiplicand
;
521 Multiplicand
= Multiplier
;
525 // Because Multiplicand * Multiplier overflows,
526 // Multiplicand * Multiplier / Divisor
527 // = (2 * Multiplicand' + 1) * Multiplier / Divisor
528 // = 2 * (Multiplicand' * Multiplier / Divisor) + Multiplier / Divisor
530 Uint64
= MultThenDivU64x64x32 (RShiftU64 (Multiplicand
, 1), Multiplier
, Divisor
, &LocalRemainder
);
531 Uint64
= LShiftU64 (Uint64
, 1);
533 if ((Multiplicand
& 0x1) == 1) {
534 Uint64
+= DivU64x32Remainder (Multiplier
, Divisor
, &Uint32
);
536 return Uint64
+ DivU64x32Remainder (Uint32
+ LShiftU64 (LocalRemainder
, 1), Divisor
, Remainder
);
538 return DivU64x32Remainder (MultU64x64 (Multiplicand
, Multiplier
), Divisor
, Remainder
);
543 Return the elapsed tick count from CurrentTick.
545 @param CurrentTick On input, the previous tick count.
546 On output, the current tick count.
547 @param StartTick The value the performance counter starts with when it
549 @param EndTick The value that the performance counter ends with before
552 @return The elapsed tick count from CurrentTick.
563 PreviousTick
= *CurrentTick
;
564 *CurrentTick
= GetPerformanceCounter();
565 if (StartTick
< EndTick
) {
566 return *CurrentTick
- PreviousTick
;
568 return PreviousTick
- *CurrentTick
;
573 Polls an address in memory mapped I/O space until an exit condition is met,
576 This function provides a standard way to poll a PCI memory location. A PCI
577 memory read operation is performed at the PCI memory address specified by
578 Address for the width specified by Width. The result of this PCI memory read
579 operation is stored in Result. This PCI memory read operation is repeated
580 until either a timeout of Delay 100 ns units has expired, or (Result & Mask)
583 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
584 @param[in] Width Signifies the width of the memory operations.
585 @param[in] Address The base address of the memory operations. The caller
586 is responsible for aligning Address if required.
587 @param[in] Mask Mask used for the polling criteria. Bytes above Width
588 in Mask are ignored. The bits in the bytes below Width
589 which are zero in Mask are ignored when polling the
591 @param[in] Value The comparison value used for the polling exit
593 @param[in] Delay The number of 100 ns units to poll. Note that timer
594 available may be of poorer granularity.
595 @param[out] Result Pointer to the last value read from the memory
598 @retval EFI_SUCCESS The last data returned from the access matched
599 the poll exit criteria.
600 @retval EFI_INVALID_PARAMETER Width is invalid.
601 @retval EFI_INVALID_PARAMETER Result is NULL.
602 @retval EFI_TIMEOUT Delay expired before a match occurred.
603 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
608 RootBridgeIoPollMem (
609 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
610 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
619 UINT64 NumberOfTicks
;
627 if (Result
== NULL
) {
628 return EFI_INVALID_PARAMETER
;
631 if ((UINT32
)Width
> EfiPciWidthUint64
) {
632 return EFI_INVALID_PARAMETER
;
636 // No matter what, always do a single poll.
638 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
639 if (EFI_ERROR (Status
)) {
643 if ((*Result
& Mask
) == Value
) {
652 // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
654 Frequency
= GetPerformanceCounterProperties (&StartTick
, &EndTick
);
655 NumberOfTicks
= MultThenDivU64x64x32 (Frequency
, Delay
, (UINT32
)EFI_TIMER_PERIOD_SECONDS(1), &Remainder
);
656 if (Remainder
>= (UINTN
)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
659 for ( ElapsedTick
= 0, CurrentTick
= GetPerformanceCounter()
660 ; ElapsedTick
<= NumberOfTicks
661 ; ElapsedTick
+= GetElapsedTick (&CurrentTick
, StartTick
, EndTick
)
663 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
664 if (EFI_ERROR (Status
)) {
668 if ((*Result
& Mask
) == Value
) {
677 Reads from the I/O space of a PCI Root Bridge. Returns when either the
678 polling exit criteria is satisfied or after a defined duration.
680 This function provides a standard way to poll a PCI I/O location. A PCI I/O
681 read operation is performed at the PCI I/O address specified by Address for
682 the width specified by Width.
683 The result of this PCI I/O read operation is stored in Result. This PCI I/O
684 read operation is repeated until either a timeout of Delay 100 ns units has
685 expired, or (Result & Mask) is equal to Value.
687 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
688 @param[in] Width Signifies the width of the I/O operations.
689 @param[in] Address The base address of the I/O operations. The caller is
690 responsible for aligning Address if required.
691 @param[in] Mask Mask used for the polling criteria. Bytes above Width in
692 Mask are ignored. The bits in the bytes below Width
693 which are zero in Mask are ignored when polling the I/O
695 @param[in] Value The comparison value used for the polling exit criteria.
696 @param[in] Delay The number of 100 ns units to poll. Note that timer
697 available may be of poorer granularity.
698 @param[out] Result Pointer to the last value read from the memory location.
700 @retval EFI_SUCCESS The last data returned from the access matched
701 the poll exit criteria.
702 @retval EFI_INVALID_PARAMETER Width is invalid.
703 @retval EFI_INVALID_PARAMETER Result is NULL.
704 @retval EFI_TIMEOUT Delay expired before a match occurred.
705 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
711 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
712 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
721 UINT64 NumberOfTicks
;
730 // No matter what, always do a single poll.
733 if (Result
== NULL
) {
734 return EFI_INVALID_PARAMETER
;
737 if ((UINT32
)Width
> EfiPciWidthUint64
) {
738 return EFI_INVALID_PARAMETER
;
741 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
742 if (EFI_ERROR (Status
)) {
745 if ((*Result
& Mask
) == Value
) {
754 // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
756 Frequency
= GetPerformanceCounterProperties (&StartTick
, &EndTick
);
757 NumberOfTicks
= MultThenDivU64x64x32 (Frequency
, Delay
, (UINT32
)EFI_TIMER_PERIOD_SECONDS(1), &Remainder
);
758 if (Remainder
>= (UINTN
)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
761 for ( ElapsedTick
= 0, CurrentTick
= GetPerformanceCounter()
762 ; ElapsedTick
<= NumberOfTicks
763 ; ElapsedTick
+= GetElapsedTick (&CurrentTick
, StartTick
, EndTick
)
765 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
766 if (EFI_ERROR (Status
)) {
770 if ((*Result
& Mask
) == Value
) {
779 Enables a PCI driver to access PCI controller registers in the PCI root
782 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
783 controller registers in the PCI root bridge memory space.
784 The memory operations are carried out exactly as requested. The caller is
785 responsible for satisfying any alignment and memory width restrictions that a
786 PCI Root Bridge on a platform might require.
788 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
789 @param[in] Width Signifies the width of the memory operation.
790 @param[in] Address The base address of the memory operation. The caller
791 is responsible for aligning the Address if required.
792 @param[in] Count The number of memory operations to perform. Bytes
793 moved is Width size * Count, starting at Address.
794 @param[out] Buffer For read operations, the destination buffer to store
795 the results. For write operations, the source buffer
798 @retval EFI_SUCCESS The data was read from or written to the PCI
800 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
801 @retval EFI_INVALID_PARAMETER Buffer is NULL.
802 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
807 RootBridgeIoMemRead (
808 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
809 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
816 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
819 Status
= RootBridgeIoCheckParameter (This
, MemOperation
, Width
, Address
,
821 if (EFI_ERROR (Status
)) {
825 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
826 Status
= RootBridgeIoGetMemTranslationByAddress (RootBridge
, Address
, &Translation
);
827 if (EFI_ERROR (Status
)) {
831 // Address passed to CpuIo->Mem.Read needs to be a host address instead of
833 return mCpuIo
->Mem
.Read (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
834 TO_HOST_ADDRESS (Address
, Translation
), Count
, Buffer
);
838 Enables a PCI driver to access PCI controller registers in the PCI root
841 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
842 controller registers in the PCI root bridge memory space.
843 The memory operations are carried out exactly as requested. The caller is
844 responsible for satisfying any alignment and memory width restrictions that a
845 PCI Root Bridge on a platform might require.
847 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
848 @param[in] Width Signifies the width of the memory operation.
849 @param[in] Address The base address of the memory operation. The caller
850 is responsible for aligning the Address if required.
851 @param[in] Count The number of memory operations to perform. Bytes
852 moved is Width size * Count, starting at Address.
853 @param[in] Buffer For read operations, the destination buffer to store
854 the results. For write operations, the source buffer
857 @retval EFI_SUCCESS The data was read from or written to the PCI
859 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
860 @retval EFI_INVALID_PARAMETER Buffer is NULL.
861 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
866 RootBridgeIoMemWrite (
867 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
868 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
875 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
878 Status
= RootBridgeIoCheckParameter (This
, MemOperation
, Width
, Address
,
880 if (EFI_ERROR (Status
)) {
884 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
885 Status
= RootBridgeIoGetMemTranslationByAddress (RootBridge
, Address
, &Translation
);
886 if (EFI_ERROR (Status
)) {
890 // Address passed to CpuIo->Mem.Write needs to be a host address instead of
892 return mCpuIo
->Mem
.Write (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
893 TO_HOST_ADDRESS (Address
, Translation
), Count
, Buffer
);
897 Enables a PCI driver to access PCI controller registers in the PCI root
900 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
901 @param[in] Width Signifies the width of the memory operations.
902 @param[in] Address The base address of the I/O operation. The caller is
903 responsible for aligning the Address if required.
904 @param[in] Count The number of I/O operations to perform. Bytes moved
905 is Width size * Count, starting at Address.
906 @param[out] Buffer For read operations, the destination buffer to store
907 the results. For write operations, the source buffer
910 @retval EFI_SUCCESS The data was read from or written to the PCI
912 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
913 @retval EFI_INVALID_PARAMETER Buffer is NULL.
914 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
920 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
921 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
928 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
930 Status
= RootBridgeIoCheckParameter (
931 This
, IoOperation
, Width
,
932 Address
, Count
, Buffer
934 if (EFI_ERROR (Status
)) {
938 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
940 // Address passed to CpuIo->Io.Read needs to be a host address instead of
942 return mCpuIo
->Io
.Read (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
943 TO_HOST_ADDRESS (Address
, RootBridge
->Io
.Translation
), Count
, Buffer
);
947 Enables a PCI driver to access PCI controller registers in the PCI root
950 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
951 @param[in] Width Signifies the width of the memory operations.
952 @param[in] Address The base address of the I/O operation. The caller is
953 responsible for aligning the Address if required.
954 @param[in] Count The number of I/O operations to perform. Bytes moved
955 is Width size * Count, starting at Address.
956 @param[in] Buffer For read operations, the destination buffer to store
957 the results. For write operations, the source buffer
960 @retval EFI_SUCCESS The data was read from or written to the PCI
962 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
963 @retval EFI_INVALID_PARAMETER Buffer is NULL.
964 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
969 RootBridgeIoIoWrite (
970 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
971 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
978 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
980 Status
= RootBridgeIoCheckParameter (
981 This
, IoOperation
, Width
,
982 Address
, Count
, Buffer
984 if (EFI_ERROR (Status
)) {
988 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
990 // Address passed to CpuIo->Io.Write needs to be a host address instead of
992 return mCpuIo
->Io
.Write (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
993 TO_HOST_ADDRESS (Address
, RootBridge
->Io
.Translation
), Count
, Buffer
);
997 Enables a PCI driver to copy one region of PCI root bridge memory space to
998 another region of PCI root bridge memory space.
1000 The CopyMem() function enables a PCI driver to copy one region of PCI root
1001 bridge memory space to another region of PCI root bridge memory space. This
1002 is especially useful for video scroll operation on a memory mapped video
1004 The memory operations are carried out exactly as requested. The caller is
1005 responsible for satisfying any alignment and memory width restrictions that a
1006 PCI root bridge on a platform might require.
1008 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1010 @param[in] Width Signifies the width of the memory operations.
1011 @param[in] DestAddress The destination address of the memory operation. The
1012 caller is responsible for aligning the DestAddress if
1014 @param[in] SrcAddress The source address of the memory operation. The caller
1015 is responsible for aligning the SrcAddress if
1017 @param[in] Count The number of memory operations to perform. Bytes
1018 moved is Width size * Count, starting at DestAddress
1021 @retval EFI_SUCCESS The data was copied from one memory region
1022 to another memory region.
1023 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1024 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
1029 RootBridgeIoCopyMem (
1030 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1031 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1032 IN UINT64 DestAddress
,
1033 IN UINT64 SrcAddress
,
1043 if ((UINT32
) Width
> EfiPciWidthUint64
) {
1044 return EFI_INVALID_PARAMETER
;
1047 if (DestAddress
== SrcAddress
) {
1051 Stride
= (UINTN
) (1 << Width
);
1054 if ((DestAddress
> SrcAddress
) &&
1055 (DestAddress
< (SrcAddress
+ Count
* Stride
))) {
1057 SrcAddress
= SrcAddress
+ (Count
- 1) * Stride
;
1058 DestAddress
= DestAddress
+ (Count
- 1) * Stride
;
1061 for (Index
= 0; Index
< Count
; Index
++) {
1062 Status
= RootBridgeIoMemRead (
1069 if (EFI_ERROR (Status
)) {
1072 Status
= RootBridgeIoMemWrite (
1079 if (EFI_ERROR (Status
)) {
1083 SrcAddress
+= Stride
;
1084 DestAddress
+= Stride
;
1086 SrcAddress
-= Stride
;
1087 DestAddress
-= Stride
;
1095 PCI configuration space access.
1097 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1098 @param Read TRUE indicating it's a read operation.
1099 @param Width Signifies the width of the memory operation.
1100 @param Address The address within the PCI configuration space
1101 for the PCI controller.
1102 @param Count The number of PCI configuration operations
1104 @param Buffer The destination buffer to store the results.
1106 @retval EFI_SUCCESS The data was read/written from/to the PCI root bridge.
1107 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1111 RootBridgeIoPciAccess (
1112 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1114 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1121 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1122 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress
;
1128 Status
= RootBridgeIoCheckParameter (This
, PciOperation
, Width
, Address
, Count
, Buffer
);
1129 if (EFI_ERROR (Status
)) {
1134 // Read Pci configuration space
1136 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1137 CopyMem (&PciAddress
, &Address
, sizeof (PciAddress
));
1139 if (PciAddress
.ExtendedRegister
== 0) {
1140 PciAddress
.ExtendedRegister
= PciAddress
.Register
;
1143 Address
= PCI_SEGMENT_LIB_ADDRESS (
1144 RootBridge
->RootBridgeIo
.SegmentNumber
,
1147 PciAddress
.Function
,
1148 PciAddress
.ExtendedRegister
1152 // Select loop based on the width of the transfer
1154 InStride
= mInStride
[Width
];
1155 OutStride
= mOutStride
[Width
];
1156 Size
= (UINTN
) (1 << (Width
& 0x03));
1157 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
1159 PciSegmentReadBuffer (Address
, Size
, Uint8Buffer
);
1161 PciSegmentWriteBuffer (Address
, Size
, Uint8Buffer
);
1168 Allows read from PCI configuration space.
1170 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1171 @param Width Signifies the width of the memory operation.
1172 @param Address The address within the PCI configuration space
1173 for the PCI controller.
1174 @param Count The number of PCI configuration operations
1176 @param Buffer The destination buffer to store the results.
1178 @retval EFI_SUCCESS The data was read from the PCI root bridge.
1179 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1183 RootBridgeIoPciRead (
1184 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1185 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1191 return RootBridgeIoPciAccess (This
, TRUE
, Width
, Address
, Count
, Buffer
);
1195 Allows write to PCI configuration space.
1197 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1198 @param Width Signifies the width of the memory operation.
1199 @param Address The address within the PCI configuration space
1200 for the PCI controller.
1201 @param Count The number of PCI configuration operations
1203 @param Buffer The source buffer to get the results.
1205 @retval EFI_SUCCESS The data was written to the PCI root bridge.
1206 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1210 RootBridgeIoPciWrite (
1211 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1212 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1218 return RootBridgeIoPciAccess (This
, FALSE
, Width
, Address
, Count
, Buffer
);
1222 Provides the PCI controller-specific address needed to access
1223 system memory for DMA.
1225 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1226 @param Operation Indicate if the bus master is going to read or write
1228 @param HostAddress The system memory address to map on the PCI controller.
1229 @param NumberOfBytes On input the number of bytes to map.
1230 On output the number of bytes that were mapped.
1231 @param DeviceAddress The resulting map address for the bus master PCI
1232 controller to use to access the system memory's HostAddress.
1233 @param Mapping The value to pass to Unmap() when the bus master DMA
1234 operation is complete.
1236 @retval EFI_SUCCESS Success.
1237 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1238 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
1239 @retval EFI_DEVICE_ERROR The System hardware could not map the requested address.
1240 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to lack of resources.
1245 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1246 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation
,
1247 IN VOID
*HostAddress
,
1248 IN OUT UINTN
*NumberOfBytes
,
1249 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
1254 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1255 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1258 if (HostAddress
== NULL
|| NumberOfBytes
== NULL
|| DeviceAddress
== NULL
||
1260 return EFI_INVALID_PARAMETER
;
1264 // Make sure that Operation is valid
1266 if ((UINT32
) Operation
>= EfiPciOperationMaximum
) {
1267 return EFI_INVALID_PARAMETER
;
1270 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1272 if (mIoMmuProtocol
!= NULL
) {
1273 if (!RootBridge
->DmaAbove4G
) {
1275 // Clear 64bit support
1277 if (Operation
> EfiPciOperationBusMasterCommonBuffer
) {
1278 Operation
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION
) (Operation
- EfiPciOperationBusMasterRead64
);
1281 Status
= mIoMmuProtocol
->Map (
1283 (EDKII_IOMMU_OPERATION
) Operation
,
1292 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
;
1293 if ((!RootBridge
->DmaAbove4G
||
1294 (Operation
!= EfiPciOperationBusMasterRead64
&&
1295 Operation
!= EfiPciOperationBusMasterWrite64
&&
1296 Operation
!= EfiPciOperationBusMasterCommonBuffer64
)) &&
1297 ((PhysicalAddress
+ *NumberOfBytes
) > SIZE_4GB
)) {
1300 // If the root bridge or the device cannot handle performing DMA above
1301 // 4GB but any part of the DMA transfer being mapped is above 4GB, then
1302 // map the DMA transfer to a buffer below 4GB.
1305 if (Operation
== EfiPciOperationBusMasterCommonBuffer
||
1306 Operation
== EfiPciOperationBusMasterCommonBuffer64
) {
1308 // Common Buffer operations can not be remapped. If the common buffer
1309 // if above 4GB, then it is not possible to generate a mapping, so return
1312 return EFI_UNSUPPORTED
;
1316 // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
1319 MapInfo
= AllocatePool (sizeof (MAP_INFO
));
1320 if (MapInfo
== NULL
) {
1322 return EFI_OUT_OF_RESOURCES
;
1326 // Initialize the MAP_INFO structure
1328 MapInfo
->Signature
= MAP_INFO_SIGNATURE
;
1329 MapInfo
->Operation
= Operation
;
1330 MapInfo
->NumberOfBytes
= *NumberOfBytes
;
1331 MapInfo
->NumberOfPages
= EFI_SIZE_TO_PAGES (MapInfo
->NumberOfBytes
);
1332 MapInfo
->HostAddress
= PhysicalAddress
;
1333 MapInfo
->MappedHostAddress
= SIZE_4GB
- 1;
1336 // Allocate a buffer below 4GB to map the transfer to.
1338 Status
= gBS
->AllocatePages (
1340 EfiBootServicesData
,
1341 MapInfo
->NumberOfPages
,
1342 &MapInfo
->MappedHostAddress
1344 if (EFI_ERROR (Status
)) {
1351 // If this is a read operation from the Bus Master's point of view,
1352 // then copy the contents of the real buffer into the mapped buffer
1353 // so the Bus Master can read the contents of the real buffer.
1355 if (Operation
== EfiPciOperationBusMasterRead
||
1356 Operation
== EfiPciOperationBusMasterRead64
) {
1358 (VOID
*) (UINTN
) MapInfo
->MappedHostAddress
,
1359 (VOID
*) (UINTN
) MapInfo
->HostAddress
,
1360 MapInfo
->NumberOfBytes
1364 InsertTailList (&RootBridge
->Maps
, &MapInfo
->Link
);
1367 // The DeviceAddress is the address of the maped buffer below 4GB
1369 *DeviceAddress
= MapInfo
->MappedHostAddress
;
1371 // Return a pointer to the MAP_INFO structure in Mapping
1376 // If the root bridge CAN handle performing DMA above 4GB or
1377 // the transfer is below 4GB, so the DeviceAddress is simply the
1380 *DeviceAddress
= PhysicalAddress
;
1381 *Mapping
= NO_MAPPING
;
1388 Completes the Map() operation and releases any corresponding resources.
1390 The Unmap() function completes the Map() operation and releases any
1391 corresponding resources.
1392 If the operation was an EfiPciOperationBusMasterWrite or
1393 EfiPciOperationBusMasterWrite64, the data is committed to the target system
1395 Any resources used for the mapping are freed.
1397 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1398 @param[in] Mapping The mapping value returned from Map().
1400 @retval EFI_SUCCESS The range was unmapped.
1401 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
1402 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
1407 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1413 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1416 if (mIoMmuProtocol
!= NULL
) {
1417 Status
= mIoMmuProtocol
->Unmap (
1424 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1427 // See if the Map() operation associated with this Unmap() required a mapping
1428 // buffer. If a mapping buffer was not required, then this function simply
1429 // returns EFI_SUCCESS.
1431 if (Mapping
== NO_MAPPING
) {
1435 MapInfo
= NO_MAPPING
;
1436 for (Link
= GetFirstNode (&RootBridge
->Maps
)
1437 ; !IsNull (&RootBridge
->Maps
, Link
)
1438 ; Link
= GetNextNode (&RootBridge
->Maps
, Link
)
1440 MapInfo
= MAP_INFO_FROM_LINK (Link
);
1441 if (MapInfo
== Mapping
) {
1446 // Mapping is not a valid value returned by Map()
1448 if (MapInfo
!= Mapping
) {
1449 return EFI_INVALID_PARAMETER
;
1451 RemoveEntryList (&MapInfo
->Link
);
1454 // If this is a write operation from the Bus Master's point of view,
1455 // then copy the contents of the mapped buffer into the real buffer
1456 // so the processor can read the contents of the real buffer.
1458 if (MapInfo
->Operation
== EfiPciOperationBusMasterWrite
||
1459 MapInfo
->Operation
== EfiPciOperationBusMasterWrite64
) {
1461 (VOID
*) (UINTN
) MapInfo
->HostAddress
,
1462 (VOID
*) (UINTN
) MapInfo
->MappedHostAddress
,
1463 MapInfo
->NumberOfBytes
1468 // Free the mapped buffer and the MAP_INFO structure.
1470 gBS
->FreePages (MapInfo
->MappedHostAddress
, MapInfo
->NumberOfPages
);
1476 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer
1477 or EfiPciOperationBusMasterCommonBuffer64 mapping.
1479 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1480 @param Type This parameter is not used and must be ignored.
1481 @param MemoryType The type of memory to allocate, EfiBootServicesData or
1482 EfiRuntimeServicesData.
1483 @param Pages The number of pages to allocate.
1484 @param HostAddress A pointer to store the base system memory address of the
1486 @param Attributes The requested bit mask of attributes for the allocated
1487 range. Only the attributes
1488 EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,
1489 EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and
1490 EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this
1493 @retval EFI_SUCCESS The requested memory pages were allocated.
1494 @retval EFI_INVALID_PARAMETER MemoryType is invalid.
1495 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
1496 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal
1497 attribute bits are MEMORY_WRITE_COMBINE,
1498 MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
1499 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1503 RootBridgeIoAllocateBuffer (
1504 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1505 IN EFI_ALLOCATE_TYPE Type
,
1506 IN EFI_MEMORY_TYPE MemoryType
,
1508 OUT VOID
**HostAddress
,
1509 IN UINT64 Attributes
1513 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1514 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1515 EFI_ALLOCATE_TYPE AllocateType
;
1518 // Validate Attributes
1520 if ((Attributes
& EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER
) != 0) {
1521 return EFI_UNSUPPORTED
;
1525 // Check for invalid inputs
1527 if (HostAddress
== NULL
) {
1528 return EFI_INVALID_PARAMETER
;
1532 // The only valid memory types are EfiBootServicesData and
1533 // EfiRuntimeServicesData
1535 if (MemoryType
!= EfiBootServicesData
&&
1536 MemoryType
!= EfiRuntimeServicesData
) {
1537 return EFI_INVALID_PARAMETER
;
1540 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1542 if (mIoMmuProtocol
!= NULL
) {
1543 if (!RootBridge
->DmaAbove4G
) {
1545 // Clear DUAL_ADDRESS_CYCLE
1547 Attributes
&= ~((UINT64
) EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1549 Status
= mIoMmuProtocol
->AllocateBuffer (
1560 AllocateType
= AllocateAnyPages
;
1561 if (!RootBridge
->DmaAbove4G
||
1562 (Attributes
& EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE
) == 0) {
1564 // Limit allocations to memory below 4GB
1566 AllocateType
= AllocateMaxAddress
;
1567 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
) (SIZE_4GB
- 1);
1569 Status
= gBS
->AllocatePages (
1575 if (!EFI_ERROR (Status
)) {
1576 *HostAddress
= (VOID
*) (UINTN
) PhysicalAddress
;
1583 Frees memory that was allocated with AllocateBuffer().
1585 The FreeBuffer() function frees memory that was allocated with
1588 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1589 @param Pages The number of pages to free.
1590 @param HostAddress The base system memory address of the allocated range.
1592 @retval EFI_SUCCESS The requested memory pages were freed.
1593 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and
1594 Pages was not allocated with AllocateBuffer().
1598 RootBridgeIoFreeBuffer (
1599 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1601 OUT VOID
*HostAddress
1606 if (mIoMmuProtocol
!= NULL
) {
1607 Status
= mIoMmuProtocol
->FreeBuffer (
1615 return gBS
->FreePages ((EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
, Pages
);
1619 Flushes all PCI posted write transactions from a PCI host bridge to system
1622 The Flush() function flushes any PCI posted write transactions from a PCI
1623 host bridge to system memory. Posted write transactions are generated by PCI
1624 bus masters when they perform write transactions to target addresses in
1626 This function does not flush posted write transactions from any PCI bridges.
1627 A PCI controller specific action must be taken to guarantee that the posted
1628 write transactions have been flushed from the PCI controller and from all the
1629 PCI bridges into the PCI host bridge. This is typically done with a PCI read
1630 transaction from the PCI controller prior to calling Flush().
1632 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1634 @retval EFI_SUCCESS The PCI posted write transactions were flushed
1635 from the PCI host bridge to system memory.
1636 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed
1637 from the PCI host bridge due to a hardware error.
1642 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
1649 Gets the attributes that a PCI root bridge supports setting with
1650 SetAttributes(), and the attributes that a PCI root bridge is currently
1653 The GetAttributes() function returns the mask of attributes that this PCI
1654 root bridge supports and the mask of attributes that the PCI root bridge is
1657 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1658 @param Supported A pointer to the mask of attributes that this PCI root
1659 bridge supports setting with SetAttributes().
1660 @param Attributes A pointer to the mask of attributes that this PCI root
1661 bridge is currently using.
1663 @retval EFI_SUCCESS If Supports is not NULL, then the attributes
1664 that the PCI root bridge supports is returned
1665 in Supports. If Attributes is not NULL, then
1666 the attributes that the PCI root bridge is
1667 currently using is returned in Attributes.
1668 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1672 RootBridgeIoGetAttributes (
1673 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1674 OUT UINT64
*Supported
,
1675 OUT UINT64
*Attributes
1678 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1680 if (Attributes
== NULL
&& Supported
== NULL
) {
1681 return EFI_INVALID_PARAMETER
;
1684 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1686 // Set the return value for Supported and Attributes
1688 if (Supported
!= NULL
) {
1689 *Supported
= RootBridge
->Supports
;
1692 if (Attributes
!= NULL
) {
1693 *Attributes
= RootBridge
->Attributes
;
1700 Sets attributes for a resource range on a PCI root bridge.
1702 The SetAttributes() function sets the attributes specified in Attributes for
1703 the PCI root bridge on the resource range specified by ResourceBase and
1704 ResourceLength. Since the granularity of setting these attributes may vary
1705 from resource type to resource type, and from platform to platform, the
1706 actual resource range and the one passed in by the caller may differ. As a
1707 result, this function may set the attributes specified by Attributes on a
1708 larger resource range than the caller requested. The actual range is returned
1709 in ResourceBase and ResourceLength. The caller is responsible for verifying
1710 that the actual range for which the attributes were set is acceptable.
1712 @param This A pointer to the
1713 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1714 @param Attributes The mask of attributes to set. If the
1715 attribute bit MEMORY_WRITE_COMBINE,
1716 MEMORY_CACHED, or MEMORY_DISABLE is set,
1717 then the resource range is specified by
1718 ResourceBase and ResourceLength. If
1719 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
1720 MEMORY_DISABLE are not set, then
1721 ResourceBase and ResourceLength are ignored,
1723 @param ResourceBase A pointer to the base address of the
1724 resource range to be modified by the
1725 attributes specified by Attributes.
1726 @param ResourceLength A pointer to the length of the resource
1727 range to be modified by the attributes
1728 specified by Attributes.
1730 @retval EFI_SUCCESS The current configuration of this PCI root bridge
1731 was returned in Resources.
1732 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
1733 could not be retrieved.
1737 RootBridgeIoSetAttributes (
1738 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1739 IN UINT64 Attributes
,
1740 IN OUT UINT64
*ResourceBase
,
1741 IN OUT UINT64
*ResourceLength
1744 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1746 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1748 if ((Attributes
& (~RootBridge
->Supports
)) != 0) {
1749 return EFI_UNSUPPORTED
;
1752 RootBridge
->Attributes
= Attributes
;
1757 Retrieves the current resource settings of this PCI root bridge in the form
1758 of a set of ACPI resource descriptors.
1760 There are only two resource descriptor types from the ACPI Specification that
1761 may be used to describe the current resources allocated to a PCI root bridge.
1762 These are the QWORD Address Space Descriptor, and the End Tag. The QWORD
1763 Address Space Descriptor can describe memory, I/O, and bus number ranges for
1764 dynamic or fixed resources. The configuration of a PCI root bridge is described
1765 with one or more QWORD Address Space Descriptors followed by an End Tag.
1767 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1768 @param[out] Resources A pointer to the resource descriptors that
1769 describe the current configuration of this PCI root
1770 bridge. The storage for the resource
1771 descriptors is allocated by this function. The
1772 caller must treat the return buffer as read-only
1773 data, and the buffer must not be freed by the
1776 @retval EFI_SUCCESS The current configuration of this PCI root bridge
1777 was returned in Resources.
1778 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
1779 could not be retrieved.
1783 RootBridgeIoConfiguration (
1784 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1785 OUT VOID
**Resources
1788 PCI_RESOURCE_TYPE Index
;
1789 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1790 PCI_RES_NODE
*ResAllocNode
;
1791 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptor
;
1792 EFI_ACPI_END_TAG_DESCRIPTOR
*End
;
1795 // Get this instance of the Root Bridge.
1797 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1799 RootBridge
->ConfigBuffer
,
1800 TypeMax
* sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
)
1802 Descriptor
= RootBridge
->ConfigBuffer
;
1803 for (Index
= TypeIo
; Index
< TypeMax
; Index
++) {
1805 ResAllocNode
= &RootBridge
->ResAllocNode
[Index
];
1807 if (ResAllocNode
->Status
!= ResAllocated
) {
1811 Descriptor
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1812 Descriptor
->Len
= sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3;
1813 // According to UEFI 2.7, RootBridgeIo->Configuration should return address
1814 // range in CPU view (host address), and ResAllocNode->Base is already a CPU
1815 // view address (host address).
1816 Descriptor
->AddrRangeMin
= ResAllocNode
->Base
;
1817 Descriptor
->AddrRangeMax
= ResAllocNode
->Base
+ ResAllocNode
->Length
- 1;
1818 Descriptor
->AddrLen
= ResAllocNode
->Length
;
1819 Descriptor
->AddrTranslationOffset
= GetTranslationByResourceType (
1824 switch (ResAllocNode
->Type
) {
1827 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_IO
;
1831 Descriptor
->SpecificFlag
= EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
;
1833 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1834 Descriptor
->AddrSpaceGranularity
= 32;
1838 Descriptor
->SpecificFlag
= EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
;
1840 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1841 Descriptor
->AddrSpaceGranularity
= 64;
1845 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_BUS
;
1855 // Terminate the entries.
1857 End
= (EFI_ACPI_END_TAG_DESCRIPTOR
*) Descriptor
;
1858 End
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
1859 End
->Checksum
= 0x0;
1861 *Resources
= RootBridge
->ConfigBuffer
;