3 PCI Root Bridge Io Protocol code.
5 Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "PciHostBridge.h"
17 #include "PciRootBridge.h"
18 #include "PciHostResource.h"
20 extern EDKII_IOMMU_PROTOCOL
*mIoMmuProtocol
;
22 #define NO_MAPPING (VOID *) (UINTN) -1
25 // Lookup table for increment values based on transfer widths
28 1, // EfiPciWidthUint8
29 2, // EfiPciWidthUint16
30 4, // EfiPciWidthUint32
31 8, // EfiPciWidthUint64
32 0, // EfiPciWidthFifoUint8
33 0, // EfiPciWidthFifoUint16
34 0, // EfiPciWidthFifoUint32
35 0, // EfiPciWidthFifoUint64
36 1, // EfiPciWidthFillUint8
37 2, // EfiPciWidthFillUint16
38 4, // EfiPciWidthFillUint32
39 8 // EfiPciWidthFillUint64
43 // Lookup table for increment values based on transfer widths
45 UINT8 mOutStride
[] = {
46 1, // EfiPciWidthUint8
47 2, // EfiPciWidthUint16
48 4, // EfiPciWidthUint32
49 8, // EfiPciWidthUint64
50 1, // EfiPciWidthFifoUint8
51 2, // EfiPciWidthFifoUint16
52 4, // EfiPciWidthFifoUint32
53 8, // EfiPciWidthFifoUint64
54 0, // EfiPciWidthFillUint8
55 0, // EfiPciWidthFillUint16
56 0, // EfiPciWidthFillUint32
57 0 // EfiPciWidthFillUint64
61 Construct the Pci Root Bridge instance.
63 @param Bridge The root bridge instance.
65 @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created
66 or NULL if creation fails.
68 PCI_ROOT_BRIDGE_INSTANCE
*
70 IN PCI_ROOT_BRIDGE
*Bridge
73 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
74 PCI_RESOURCE_TYPE Index
;
75 CHAR16
*DevicePathStr
;
76 PCI_ROOT_BRIDGE_APERTURE
*Aperture
;
80 DEBUG ((EFI_D_INFO
, "RootBridge: "));
81 DEBUG ((EFI_D_INFO
, "%s\n", DevicePathStr
= ConvertDevicePathToText (Bridge
->DevicePath
, FALSE
, FALSE
)));
82 DEBUG ((EFI_D_INFO
, " Support/Attr: %lx / %lx\n", Bridge
->Supports
, Bridge
->Attributes
));
83 DEBUG ((EFI_D_INFO
, " DmaAbove4G: %s\n", Bridge
->DmaAbove4G
? L
"Yes" : L
"No"));
84 DEBUG ((EFI_D_INFO
, "NoExtConfSpace: %s\n", Bridge
->NoExtendedConfigSpace
? L
"Yes" : L
"No"));
85 DEBUG ((EFI_D_INFO
, " AllocAttr: %lx (%s%s)\n", Bridge
->AllocationAttributes
,
86 (Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
) != 0 ? L
"CombineMemPMem " : L
"",
87 (Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_MEM64_DECODE
) != 0 ? L
"Mem64Decode" : L
""
90 EFI_D_INFO
, " Bus: %lx - %lx Translation=%lx\n",
91 Bridge
->Bus
.Base
, Bridge
->Bus
.Limit
, Bridge
->Bus
.Translation
94 // Translation for bus is not supported.
96 ASSERT (Bridge
->Bus
.Translation
== 0);
97 if (Bridge
->Bus
.Translation
!= 0) {
102 DEBUG_INFO
, " Io: %lx - %lx Translation=%lx\n",
103 Bridge
->Io
.Base
, Bridge
->Io
.Limit
, Bridge
->Io
.Translation
106 DEBUG_INFO
, " Mem: %lx - %lx Translation=%lx\n",
107 Bridge
->Mem
.Base
, Bridge
->Mem
.Limit
, Bridge
->Mem
.Translation
110 DEBUG_INFO
, " MemAbove4G: %lx - %lx Translation=%lx\n",
111 Bridge
->MemAbove4G
.Base
, Bridge
->MemAbove4G
.Limit
, Bridge
->MemAbove4G
.Translation
114 DEBUG_INFO
, " PMem: %lx - %lx Translation=%lx\n",
115 Bridge
->PMem
.Base
, Bridge
->PMem
.Limit
, Bridge
->PMem
.Translation
118 DEBUG_INFO
, " PMemAbove4G: %lx - %lx Translation=%lx\n",
119 Bridge
->PMemAbove4G
.Base
, Bridge
->PMemAbove4G
.Limit
, Bridge
->PMemAbove4G
.Translation
123 // Make sure Mem and MemAbove4G apertures are valid
125 if (Bridge
->Mem
.Base
<= Bridge
->Mem
.Limit
) {
126 ASSERT (Bridge
->Mem
.Limit
< SIZE_4GB
);
127 if (Bridge
->Mem
.Limit
>= SIZE_4GB
) {
131 if (Bridge
->MemAbove4G
.Base
<= Bridge
->MemAbove4G
.Limit
) {
132 ASSERT (Bridge
->MemAbove4G
.Base
>= SIZE_4GB
);
133 if (Bridge
->MemAbove4G
.Base
< SIZE_4GB
) {
137 if (Bridge
->PMem
.Base
<= Bridge
->PMem
.Limit
) {
138 ASSERT (Bridge
->PMem
.Limit
< SIZE_4GB
);
139 if (Bridge
->PMem
.Limit
>= SIZE_4GB
) {
143 if (Bridge
->PMemAbove4G
.Base
<= Bridge
->PMemAbove4G
.Limit
) {
144 ASSERT (Bridge
->PMemAbove4G
.Base
>= SIZE_4GB
);
145 if (Bridge
->PMemAbove4G
.Base
< SIZE_4GB
) {
151 // Ignore AllocationAttributes when resources were already assigned.
153 if (!Bridge
->ResourceAssigned
) {
154 if ((Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
) != 0) {
156 // If this bit is set, then the PCI Root Bridge does not
157 // support separate windows for Non-prefetchable and Prefetchable
160 ASSERT (Bridge
->PMem
.Base
> Bridge
->PMem
.Limit
);
161 ASSERT (Bridge
->PMemAbove4G
.Base
> Bridge
->PMemAbove4G
.Limit
);
162 if ((Bridge
->PMem
.Base
<= Bridge
->PMem
.Limit
) ||
163 (Bridge
->PMemAbove4G
.Base
<= Bridge
->PMemAbove4G
.Limit
)
169 if ((Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_MEM64_DECODE
) == 0) {
171 // If this bit is not set, then the PCI Root Bridge does not support
172 // 64 bit memory windows.
174 ASSERT (Bridge
->MemAbove4G
.Base
> Bridge
->MemAbove4G
.Limit
);
175 ASSERT (Bridge
->PMemAbove4G
.Base
> Bridge
->PMemAbove4G
.Limit
);
176 if ((Bridge
->MemAbove4G
.Base
<= Bridge
->MemAbove4G
.Limit
) ||
177 (Bridge
->PMemAbove4G
.Base
<= Bridge
->PMemAbove4G
.Limit
)
184 RootBridge
= AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE
));
185 ASSERT (RootBridge
!= NULL
);
187 RootBridge
->Signature
= PCI_ROOT_BRIDGE_SIGNATURE
;
188 RootBridge
->Supports
= Bridge
->Supports
;
189 RootBridge
->Attributes
= Bridge
->Attributes
;
190 RootBridge
->DmaAbove4G
= Bridge
->DmaAbove4G
;
191 RootBridge
->NoExtendedConfigSpace
= Bridge
->NoExtendedConfigSpace
;
192 RootBridge
->AllocationAttributes
= Bridge
->AllocationAttributes
;
193 RootBridge
->DevicePath
= DuplicateDevicePath (Bridge
->DevicePath
);
194 RootBridge
->DevicePathStr
= DevicePathStr
;
195 RootBridge
->ConfigBuffer
= AllocatePool (
196 TypeMax
* sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
)
198 ASSERT (RootBridge
->ConfigBuffer
!= NULL
);
199 InitializeListHead (&RootBridge
->Maps
);
201 CopyMem (&RootBridge
->Bus
, &Bridge
->Bus
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
202 CopyMem (&RootBridge
->Io
, &Bridge
->Io
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
203 CopyMem (&RootBridge
->Mem
, &Bridge
->Mem
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
204 CopyMem (&RootBridge
->MemAbove4G
, &Bridge
->MemAbove4G
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
205 CopyMem (&RootBridge
->PMem
, &Bridge
->PMem
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
206 CopyMem (&RootBridge
->PMemAbove4G
, &Bridge
->PMemAbove4G
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
208 for (Index
= TypeIo
; Index
< TypeMax
; Index
++) {
211 Aperture
= &RootBridge
->Bus
;
214 Aperture
= &RootBridge
->Io
;
217 Aperture
= &RootBridge
->Mem
;
220 Aperture
= &RootBridge
->MemAbove4G
;
223 Aperture
= &RootBridge
->PMem
;
226 Aperture
= &RootBridge
->PMemAbove4G
;
233 RootBridge
->ResAllocNode
[Index
].Type
= Index
;
234 if (Bridge
->ResourceAssigned
&& (Aperture
->Limit
>= Aperture
->Base
)) {
236 // Base in ResAllocNode is a host address, while Base in Aperture is a
239 RootBridge
->ResAllocNode
[Index
].Base
= TO_HOST_ADDRESS (Aperture
->Base
,
240 Aperture
->Translation
);
241 RootBridge
->ResAllocNode
[Index
].Length
= Aperture
->Limit
- Aperture
->Base
+ 1;
242 RootBridge
->ResAllocNode
[Index
].Status
= ResAllocated
;
244 RootBridge
->ResAllocNode
[Index
].Base
= 0;
245 RootBridge
->ResAllocNode
[Index
].Length
= 0;
246 RootBridge
->ResAllocNode
[Index
].Status
= ResNone
;
250 RootBridge
->RootBridgeIo
.SegmentNumber
= Bridge
->Segment
;
251 RootBridge
->RootBridgeIo
.PollMem
= RootBridgeIoPollMem
;
252 RootBridge
->RootBridgeIo
.PollIo
= RootBridgeIoPollIo
;
253 RootBridge
->RootBridgeIo
.Mem
.Read
= RootBridgeIoMemRead
;
254 RootBridge
->RootBridgeIo
.Mem
.Write
= RootBridgeIoMemWrite
;
255 RootBridge
->RootBridgeIo
.Io
.Read
= RootBridgeIoIoRead
;
256 RootBridge
->RootBridgeIo
.Io
.Write
= RootBridgeIoIoWrite
;
257 RootBridge
->RootBridgeIo
.CopyMem
= RootBridgeIoCopyMem
;
258 RootBridge
->RootBridgeIo
.Pci
.Read
= RootBridgeIoPciRead
;
259 RootBridge
->RootBridgeIo
.Pci
.Write
= RootBridgeIoPciWrite
;
260 RootBridge
->RootBridgeIo
.Map
= RootBridgeIoMap
;
261 RootBridge
->RootBridgeIo
.Unmap
= RootBridgeIoUnmap
;
262 RootBridge
->RootBridgeIo
.AllocateBuffer
= RootBridgeIoAllocateBuffer
;
263 RootBridge
->RootBridgeIo
.FreeBuffer
= RootBridgeIoFreeBuffer
;
264 RootBridge
->RootBridgeIo
.Flush
= RootBridgeIoFlush
;
265 RootBridge
->RootBridgeIo
.GetAttributes
= RootBridgeIoGetAttributes
;
266 RootBridge
->RootBridgeIo
.SetAttributes
= RootBridgeIoSetAttributes
;
267 RootBridge
->RootBridgeIo
.Configuration
= RootBridgeIoConfiguration
;
273 Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
275 The I/O operations are carried out exactly as requested. The caller is
276 responsible for satisfying any alignment and I/O width restrictions that a PI
277 System on a platform might require. For example on some platforms, width
278 requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other
279 hand, will be handled by the driver.
281 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
283 @param[in] OperationType I/O operation type: IO/MMIO/PCI.
285 @param[in] Width Signifies the width of the I/O or Memory operation.
287 @param[in] Address The base address of the I/O operation.
289 @param[in] Count The number of I/O operations to perform. The number
290 of bytes moved is Width size * Count, starting at
293 @param[in] Buffer For read operations, the destination buffer to
294 store the results. For write operations, the source
295 buffer from which to write data.
297 @retval EFI_SUCCESS The parameters for this request pass the
300 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
302 @retval EFI_INVALID_PARAMETER Buffer is NULL.
304 @retval EFI_INVALID_PARAMETER Address or Count is invalid.
306 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
308 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
309 and Count is not valid for this PI system.
312 RootBridgeIoCheckParameter (
313 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
314 IN OPERATION_TYPE OperationType
,
315 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
321 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
322 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*PciRbAddr
;
329 // Check to see if Buffer is NULL
331 if (Buffer
== NULL
) {
332 return EFI_INVALID_PARAMETER
;
336 // Check to see if Width is in the valid range
338 if ((UINT32
) Width
>= EfiPciWidthMaximum
) {
339 return EFI_INVALID_PARAMETER
;
343 // For FIFO type, the device address won't increase during the access,
344 // so treat Count as 1
346 if (Width
>= EfiPciWidthFifoUint8
&& Width
<= EfiPciWidthFifoUint64
) {
350 Width
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
354 // Make sure (Count * Size) doesn't exceed MAX_UINT64
356 if (Count
> DivU64x32 (MAX_UINT64
, Size
)) {
357 return EFI_INVALID_PARAMETER
;
361 // Check to see if Address is aligned
363 if ((Address
& (Size
- 1)) != 0) {
364 return EFI_UNSUPPORTED
;
368 // Make sure (Address + Count * Size) doesn't exceed MAX_UINT64
370 Length
= MultU64x32 (Count
, Size
);
371 if (Address
> MAX_UINT64
- Length
) {
372 return EFI_INVALID_PARAMETER
;
375 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
378 // Check to see if any address associated with this transfer exceeds the
379 // maximum allowed address. The maximum address implied by the parameters
380 // passed in is Address + Size * Count. If the following condition is met,
381 // then the transfer is not supported.
383 // Address + Size * Count > Limit + 1
385 // Since Limit can be the maximum integer value supported by the CPU and
386 // Count can also be the maximum integer value supported by the CPU, this
387 // range check must be adjusted to avoid all oveflow conditions.
389 if (OperationType
== IoOperation
) {
391 // Allow Legacy IO access
393 if (Address
+ Length
<= 0x1000) {
394 if ((RootBridge
->Attributes
& (
395 EFI_PCI_ATTRIBUTE_ISA_IO
| EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO
| EFI_PCI_ATTRIBUTE_VGA_IO
|
396 EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO
| EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO
|
397 EFI_PCI_ATTRIBUTE_ISA_IO_16
| EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
| EFI_PCI_ATTRIBUTE_VGA_IO_16
)) != 0) {
401 Base
= RootBridge
->Io
.Base
;
402 Limit
= RootBridge
->Io
.Limit
;
403 } else if (OperationType
== MemOperation
) {
405 // Allow Legacy MMIO access
407 if ((Address
>= 0xA0000) && (Address
+ Length
) <= 0xC0000) {
408 if ((RootBridge
->Attributes
& EFI_PCI_ATTRIBUTE_VGA_MEMORY
) != 0) {
413 // By comparing the Address against Limit we know which range to be used
416 if (Address
+ Length
<= RootBridge
->Mem
.Limit
+ 1) {
417 Base
= RootBridge
->Mem
.Base
;
418 Limit
= RootBridge
->Mem
.Limit
;
420 Base
= RootBridge
->MemAbove4G
.Base
;
421 Limit
= RootBridge
->MemAbove4G
.Limit
;
424 PciRbAddr
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*) &Address
;
425 if (PciRbAddr
->Bus
< RootBridge
->Bus
.Base
||
426 PciRbAddr
->Bus
> RootBridge
->Bus
.Limit
) {
427 return EFI_INVALID_PARAMETER
;
430 if (PciRbAddr
->Device
> PCI_MAX_DEVICE
||
431 PciRbAddr
->Function
> PCI_MAX_FUNC
) {
432 return EFI_INVALID_PARAMETER
;
435 if (PciRbAddr
->ExtendedRegister
!= 0) {
436 Address
= PciRbAddr
->ExtendedRegister
;
438 Address
= PciRbAddr
->Register
;
441 Limit
= RootBridge
->NoExtendedConfigSpace
? 0xFF : 0xFFF;
444 if (Address
< Base
) {
445 return EFI_INVALID_PARAMETER
;
448 if (Address
+ Length
> Limit
+ 1) {
449 return EFI_INVALID_PARAMETER
;
456 Use address to match apertures of memory type and then get the corresponding
459 @param RootBridge The root bridge instance.
460 @param Address The address used to match aperture.
461 @param Translation Pointer containing the output translation.
463 @return EFI_SUCCESS Get translation successfully.
464 @return EFI_INVALID_PARAMETER No matched memory aperture; the input Address
468 RootBridgeIoGetMemTranslationByAddress (
469 IN PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
,
471 IN OUT UINT64
*Translation
474 if (Address
>= RootBridge
->Mem
.Base
&& Address
<= RootBridge
->Mem
.Limit
) {
475 *Translation
= RootBridge
->Mem
.Translation
;
476 } else if (Address
>= RootBridge
->PMem
.Base
&& Address
<= RootBridge
->PMem
.Limit
) {
477 *Translation
= RootBridge
->PMem
.Translation
;
478 } else if (Address
>= RootBridge
->MemAbove4G
.Base
&& Address
<= RootBridge
->MemAbove4G
.Limit
) {
479 *Translation
= RootBridge
->MemAbove4G
.Translation
;
480 } else if (Address
>= RootBridge
->PMemAbove4G
.Base
&& Address
<= RootBridge
->PMemAbove4G
.Limit
) {
481 *Translation
= RootBridge
->PMemAbove4G
.Translation
;
483 return EFI_INVALID_PARAMETER
;
490 Return the result of (Multiplicand * Multiplier / Divisor).
492 @param Multiplicand A 64-bit unsigned value.
493 @param Multiplier A 64-bit unsigned value.
494 @param Divisor A 32-bit unsigned value.
495 @param Remainder A pointer to a 32-bit unsigned value. This parameter is
496 optional and may be NULL.
498 @return Multiplicand * Multiplier / Divisor.
501 MultThenDivU64x64x32 (
502 IN UINT64 Multiplicand
,
503 IN UINT64 Multiplier
,
505 OUT UINT32
*Remainder OPTIONAL
509 UINT32 LocalRemainder
;
511 if (Multiplicand
> DivU64x64Remainder (MAX_UINT64
, Multiplier
, NULL
)) {
513 // Make sure Multiplicand is the bigger one.
515 if (Multiplicand
< Multiplier
) {
516 Uint64
= Multiplicand
;
517 Multiplicand
= Multiplier
;
521 // Because Multiplicand * Multiplier overflows,
522 // Multiplicand * Multiplier / Divisor
523 // = (2 * Multiplicand' + 1) * Multiplier / Divisor
524 // = 2 * (Multiplicand' * Multiplier / Divisor) + Multiplier / Divisor
526 Uint64
= MultThenDivU64x64x32 (RShiftU64 (Multiplicand
, 1), Multiplier
, Divisor
, &LocalRemainder
);
527 Uint64
= LShiftU64 (Uint64
, 1);
529 if ((Multiplicand
& 0x1) == 1) {
530 Uint64
+= DivU64x32Remainder (Multiplier
, Divisor
, &Uint32
);
532 return Uint64
+ DivU64x32Remainder (Uint32
+ LShiftU64 (LocalRemainder
, 1), Divisor
, Remainder
);
534 return DivU64x32Remainder (MultU64x64 (Multiplicand
, Multiplier
), Divisor
, Remainder
);
539 Return the elapsed tick count from CurrentTick.
541 @param CurrentTick On input, the previous tick count.
542 On output, the current tick count.
543 @param StartTick The value the performance counter starts with when it
545 @param EndTick The value that the performance counter ends with before
548 @return The elapsed tick count from CurrentTick.
559 PreviousTick
= *CurrentTick
;
560 *CurrentTick
= GetPerformanceCounter();
561 if (StartTick
< EndTick
) {
562 return *CurrentTick
- PreviousTick
;
564 return PreviousTick
- *CurrentTick
;
569 Polls an address in memory mapped I/O space until an exit condition is met,
572 This function provides a standard way to poll a PCI memory location. A PCI
573 memory read operation is performed at the PCI memory address specified by
574 Address for the width specified by Width. The result of this PCI memory read
575 operation is stored in Result. This PCI memory read operation is repeated
576 until either a timeout of Delay 100 ns units has expired, or (Result & Mask)
579 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
580 @param[in] Width Signifies the width of the memory operations.
581 @param[in] Address The base address of the memory operations. The caller
582 is responsible for aligning Address if required.
583 @param[in] Mask Mask used for the polling criteria. Bytes above Width
584 in Mask are ignored. The bits in the bytes below Width
585 which are zero in Mask are ignored when polling the
587 @param[in] Value The comparison value used for the polling exit
589 @param[in] Delay The number of 100 ns units to poll. Note that timer
590 available may be of poorer granularity.
591 @param[out] Result Pointer to the last value read from the memory
594 @retval EFI_SUCCESS The last data returned from the access matched
595 the poll exit criteria.
596 @retval EFI_INVALID_PARAMETER Width is invalid.
597 @retval EFI_INVALID_PARAMETER Result is NULL.
598 @retval EFI_TIMEOUT Delay expired before a match occurred.
599 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
604 RootBridgeIoPollMem (
605 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
606 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
615 UINT64 NumberOfTicks
;
623 if (Result
== NULL
) {
624 return EFI_INVALID_PARAMETER
;
627 if ((UINT32
)Width
> EfiPciWidthUint64
) {
628 return EFI_INVALID_PARAMETER
;
632 // No matter what, always do a single poll.
634 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
635 if (EFI_ERROR (Status
)) {
639 if ((*Result
& Mask
) == Value
) {
648 // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
650 Frequency
= GetPerformanceCounterProperties (&StartTick
, &EndTick
);
651 NumberOfTicks
= MultThenDivU64x64x32 (Frequency
, Delay
, (UINT32
)EFI_TIMER_PERIOD_SECONDS(1), &Remainder
);
652 if (Remainder
>= (UINTN
)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
655 for ( ElapsedTick
= 0, CurrentTick
= GetPerformanceCounter()
656 ; ElapsedTick
<= NumberOfTicks
657 ; ElapsedTick
+= GetElapsedTick (&CurrentTick
, StartTick
, EndTick
)
659 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
660 if (EFI_ERROR (Status
)) {
664 if ((*Result
& Mask
) == Value
) {
673 Reads from the I/O space of a PCI Root Bridge. Returns when either the
674 polling exit criteria is satisfied or after a defined duration.
676 This function provides a standard way to poll a PCI I/O location. A PCI I/O
677 read operation is performed at the PCI I/O address specified by Address for
678 the width specified by Width.
679 The result of this PCI I/O read operation is stored in Result. This PCI I/O
680 read operation is repeated until either a timeout of Delay 100 ns units has
681 expired, or (Result & Mask) is equal to Value.
683 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
684 @param[in] Width Signifies the width of the I/O operations.
685 @param[in] Address The base address of the I/O operations. The caller is
686 responsible for aligning Address if required.
687 @param[in] Mask Mask used for the polling criteria. Bytes above Width in
688 Mask are ignored. The bits in the bytes below Width
689 which are zero in Mask are ignored when polling the I/O
691 @param[in] Value The comparison value used for the polling exit criteria.
692 @param[in] Delay The number of 100 ns units to poll. Note that timer
693 available may be of poorer granularity.
694 @param[out] Result Pointer to the last value read from the memory location.
696 @retval EFI_SUCCESS The last data returned from the access matched
697 the poll exit criteria.
698 @retval EFI_INVALID_PARAMETER Width is invalid.
699 @retval EFI_INVALID_PARAMETER Result is NULL.
700 @retval EFI_TIMEOUT Delay expired before a match occurred.
701 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
707 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
708 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
717 UINT64 NumberOfTicks
;
726 // No matter what, always do a single poll.
729 if (Result
== NULL
) {
730 return EFI_INVALID_PARAMETER
;
733 if ((UINT32
)Width
> EfiPciWidthUint64
) {
734 return EFI_INVALID_PARAMETER
;
737 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
738 if (EFI_ERROR (Status
)) {
741 if ((*Result
& Mask
) == Value
) {
750 // NumberOfTicks = Frenquency * Delay / EFI_TIMER_PERIOD_SECONDS(1)
752 Frequency
= GetPerformanceCounterProperties (&StartTick
, &EndTick
);
753 NumberOfTicks
= MultThenDivU64x64x32 (Frequency
, Delay
, (UINT32
)EFI_TIMER_PERIOD_SECONDS(1), &Remainder
);
754 if (Remainder
>= (UINTN
)EFI_TIMER_PERIOD_SECONDS(1) / 2) {
757 for ( ElapsedTick
= 0, CurrentTick
= GetPerformanceCounter()
758 ; ElapsedTick
<= NumberOfTicks
759 ; ElapsedTick
+= GetElapsedTick (&CurrentTick
, StartTick
, EndTick
)
761 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
762 if (EFI_ERROR (Status
)) {
766 if ((*Result
& Mask
) == Value
) {
775 Enables a PCI driver to access PCI controller registers in the PCI root
778 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
779 controller registers in the PCI root bridge memory space.
780 The memory operations are carried out exactly as requested. The caller is
781 responsible for satisfying any alignment and memory width restrictions that a
782 PCI Root Bridge on a platform might require.
784 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
785 @param[in] Width Signifies the width of the memory operation.
786 @param[in] Address The base address of the memory operation. The caller
787 is responsible for aligning the Address if required.
788 @param[in] Count The number of memory operations to perform. Bytes
789 moved is Width size * Count, starting at Address.
790 @param[out] Buffer For read operations, the destination buffer to store
791 the results. For write operations, the source buffer
794 @retval EFI_SUCCESS The data was read from or written to the PCI
796 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
797 @retval EFI_INVALID_PARAMETER Buffer is NULL.
798 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
803 RootBridgeIoMemRead (
804 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
805 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
812 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
815 Status
= RootBridgeIoCheckParameter (This
, MemOperation
, Width
, Address
,
817 if (EFI_ERROR (Status
)) {
821 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
822 Status
= RootBridgeIoGetMemTranslationByAddress (RootBridge
, Address
, &Translation
);
823 if (EFI_ERROR (Status
)) {
827 // Address passed to CpuIo->Mem.Read needs to be a host address instead of
829 return mCpuIo
->Mem
.Read (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
830 TO_HOST_ADDRESS (Address
, Translation
), Count
, Buffer
);
834 Enables a PCI driver to access PCI controller registers in the PCI root
837 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
838 controller registers in the PCI root bridge memory space.
839 The memory operations are carried out exactly as requested. The caller is
840 responsible for satisfying any alignment and memory width restrictions that a
841 PCI Root Bridge on a platform might require.
843 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
844 @param[in] Width Signifies the width of the memory operation.
845 @param[in] Address The base address of the memory operation. The caller
846 is responsible for aligning the Address if required.
847 @param[in] Count The number of memory operations to perform. Bytes
848 moved is Width size * Count, starting at Address.
849 @param[in] Buffer For read operations, the destination buffer to store
850 the results. For write operations, the source buffer
853 @retval EFI_SUCCESS The data was read from or written to the PCI
855 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
856 @retval EFI_INVALID_PARAMETER Buffer is NULL.
857 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
862 RootBridgeIoMemWrite (
863 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
864 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
871 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
874 Status
= RootBridgeIoCheckParameter (This
, MemOperation
, Width
, Address
,
876 if (EFI_ERROR (Status
)) {
880 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
881 Status
= RootBridgeIoGetMemTranslationByAddress (RootBridge
, Address
, &Translation
);
882 if (EFI_ERROR (Status
)) {
886 // Address passed to CpuIo->Mem.Write needs to be a host address instead of
888 return mCpuIo
->Mem
.Write (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
889 TO_HOST_ADDRESS (Address
, Translation
), Count
, Buffer
);
893 Enables a PCI driver to access PCI controller registers in the PCI root
896 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
897 @param[in] Width Signifies the width of the memory operations.
898 @param[in] Address The base address of the I/O operation. The caller is
899 responsible for aligning the Address if required.
900 @param[in] Count The number of I/O operations to perform. Bytes moved
901 is Width size * Count, starting at Address.
902 @param[out] Buffer For read operations, the destination buffer to store
903 the results. For write operations, the source buffer
906 @retval EFI_SUCCESS The data was read from or written to the PCI
908 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
909 @retval EFI_INVALID_PARAMETER Buffer is NULL.
910 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
916 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
917 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
924 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
926 Status
= RootBridgeIoCheckParameter (
927 This
, IoOperation
, Width
,
928 Address
, Count
, Buffer
930 if (EFI_ERROR (Status
)) {
934 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
936 // Address passed to CpuIo->Io.Read needs to be a host address instead of
938 return mCpuIo
->Io
.Read (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
939 TO_HOST_ADDRESS (Address
, RootBridge
->Io
.Translation
), Count
, Buffer
);
943 Enables a PCI driver to access PCI controller registers in the PCI root
946 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
947 @param[in] Width Signifies the width of the memory operations.
948 @param[in] Address The base address of the I/O operation. The caller is
949 responsible for aligning the Address if required.
950 @param[in] Count The number of I/O operations to perform. Bytes moved
951 is Width size * Count, starting at Address.
952 @param[in] Buffer For read operations, the destination buffer to store
953 the results. For write operations, the source buffer
956 @retval EFI_SUCCESS The data was read from or written to the PCI
958 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
959 @retval EFI_INVALID_PARAMETER Buffer is NULL.
960 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
965 RootBridgeIoIoWrite (
966 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
967 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
974 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
976 Status
= RootBridgeIoCheckParameter (
977 This
, IoOperation
, Width
,
978 Address
, Count
, Buffer
980 if (EFI_ERROR (Status
)) {
984 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
986 // Address passed to CpuIo->Io.Write needs to be a host address instead of
988 return mCpuIo
->Io
.Write (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
,
989 TO_HOST_ADDRESS (Address
, RootBridge
->Io
.Translation
), Count
, Buffer
);
993 Enables a PCI driver to copy one region of PCI root bridge memory space to
994 another region of PCI root bridge memory space.
996 The CopyMem() function enables a PCI driver to copy one region of PCI root
997 bridge memory space to another region of PCI root bridge memory space. This
998 is especially useful for video scroll operation on a memory mapped video
1000 The memory operations are carried out exactly as requested. The caller is
1001 responsible for satisfying any alignment and memory width restrictions that a
1002 PCI root bridge on a platform might require.
1004 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1006 @param[in] Width Signifies the width of the memory operations.
1007 @param[in] DestAddress The destination address of the memory operation. The
1008 caller is responsible for aligning the DestAddress if
1010 @param[in] SrcAddress The source address of the memory operation. The caller
1011 is responsible for aligning the SrcAddress if
1013 @param[in] Count The number of memory operations to perform. Bytes
1014 moved is Width size * Count, starting at DestAddress
1017 @retval EFI_SUCCESS The data was copied from one memory region
1018 to another memory region.
1019 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
1020 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
1025 RootBridgeIoCopyMem (
1026 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1027 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1028 IN UINT64 DestAddress
,
1029 IN UINT64 SrcAddress
,
1039 if ((UINT32
) Width
> EfiPciWidthUint64
) {
1040 return EFI_INVALID_PARAMETER
;
1043 if (DestAddress
== SrcAddress
) {
1047 Stride
= (UINTN
) (1 << Width
);
1050 if ((DestAddress
> SrcAddress
) &&
1051 (DestAddress
< (SrcAddress
+ Count
* Stride
))) {
1053 SrcAddress
= SrcAddress
+ (Count
- 1) * Stride
;
1054 DestAddress
= DestAddress
+ (Count
- 1) * Stride
;
1057 for (Index
= 0; Index
< Count
; Index
++) {
1058 Status
= RootBridgeIoMemRead (
1065 if (EFI_ERROR (Status
)) {
1068 Status
= RootBridgeIoMemWrite (
1075 if (EFI_ERROR (Status
)) {
1079 SrcAddress
+= Stride
;
1080 DestAddress
+= Stride
;
1082 SrcAddress
-= Stride
;
1083 DestAddress
-= Stride
;
1091 PCI configuration space access.
1093 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1094 @param Read TRUE indicating it's a read operation.
1095 @param Width Signifies the width of the memory operation.
1096 @param Address The address within the PCI configuration space
1097 for the PCI controller.
1098 @param Count The number of PCI configuration operations
1100 @param Buffer The destination buffer to store the results.
1102 @retval EFI_SUCCESS The data was read/written from/to the PCI root bridge.
1103 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1107 RootBridgeIoPciAccess (
1108 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1110 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1117 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1118 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress
;
1124 Status
= RootBridgeIoCheckParameter (This
, PciOperation
, Width
, Address
, Count
, Buffer
);
1125 if (EFI_ERROR (Status
)) {
1130 // Read Pci configuration space
1132 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1133 CopyMem (&PciAddress
, &Address
, sizeof (PciAddress
));
1135 if (PciAddress
.ExtendedRegister
== 0) {
1136 PciAddress
.ExtendedRegister
= PciAddress
.Register
;
1139 Address
= PCI_SEGMENT_LIB_ADDRESS (
1140 RootBridge
->RootBridgeIo
.SegmentNumber
,
1143 PciAddress
.Function
,
1144 PciAddress
.ExtendedRegister
1148 // Select loop based on the width of the transfer
1150 InStride
= mInStride
[Width
];
1151 OutStride
= mOutStride
[Width
];
1152 Size
= (UINTN
) (1 << (Width
& 0x03));
1153 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
1155 PciSegmentReadBuffer (Address
, Size
, Uint8Buffer
);
1157 PciSegmentWriteBuffer (Address
, Size
, Uint8Buffer
);
1164 Allows read from PCI configuration space.
1166 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1167 @param Width Signifies the width of the memory operation.
1168 @param Address The address within the PCI configuration space
1169 for the PCI controller.
1170 @param Count The number of PCI configuration operations
1172 @param Buffer The destination buffer to store the results.
1174 @retval EFI_SUCCESS The data was read from the PCI root bridge.
1175 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1179 RootBridgeIoPciRead (
1180 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1181 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1187 return RootBridgeIoPciAccess (This
, TRUE
, Width
, Address
, Count
, Buffer
);
1191 Allows write to PCI configuration space.
1193 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1194 @param Width Signifies the width of the memory operation.
1195 @param Address The address within the PCI configuration space
1196 for the PCI controller.
1197 @param Count The number of PCI configuration operations
1199 @param Buffer The source buffer to get the results.
1201 @retval EFI_SUCCESS The data was written to the PCI root bridge.
1202 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1206 RootBridgeIoPciWrite (
1207 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1208 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1214 return RootBridgeIoPciAccess (This
, FALSE
, Width
, Address
, Count
, Buffer
);
1218 Provides the PCI controller-specific address needed to access
1219 system memory for DMA.
1221 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1222 @param Operation Indicate if the bus master is going to read or write
1224 @param HostAddress The system memory address to map on the PCI controller.
1225 @param NumberOfBytes On input the number of bytes to map.
1226 On output the number of bytes that were mapped.
1227 @param DeviceAddress The resulting map address for the bus master PCI
1228 controller to use to access the system memory's HostAddress.
1229 @param Mapping The value to pass to Unmap() when the bus master DMA
1230 operation is complete.
1232 @retval EFI_SUCCESS Success.
1233 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1234 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
1235 @retval EFI_DEVICE_ERROR The System hardware could not map the requested address.
1236 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to lack of resources.
1241 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1242 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation
,
1243 IN VOID
*HostAddress
,
1244 IN OUT UINTN
*NumberOfBytes
,
1245 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
1250 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1251 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1254 if (HostAddress
== NULL
|| NumberOfBytes
== NULL
|| DeviceAddress
== NULL
||
1256 return EFI_INVALID_PARAMETER
;
1260 // Make sure that Operation is valid
1262 if ((UINT32
) Operation
>= EfiPciOperationMaximum
) {
1263 return EFI_INVALID_PARAMETER
;
1266 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1268 if (mIoMmuProtocol
!= NULL
) {
1269 if (!RootBridge
->DmaAbove4G
) {
1271 // Clear 64bit support
1273 if (Operation
> EfiPciOperationBusMasterCommonBuffer
) {
1274 Operation
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION
) (Operation
- EfiPciOperationBusMasterRead64
);
1277 Status
= mIoMmuProtocol
->Map (
1279 (EDKII_IOMMU_OPERATION
) Operation
,
1288 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
;
1289 if ((!RootBridge
->DmaAbove4G
||
1290 (Operation
!= EfiPciOperationBusMasterRead64
&&
1291 Operation
!= EfiPciOperationBusMasterWrite64
&&
1292 Operation
!= EfiPciOperationBusMasterCommonBuffer64
)) &&
1293 ((PhysicalAddress
+ *NumberOfBytes
) > SIZE_4GB
)) {
1296 // If the root bridge or the device cannot handle performing DMA above
1297 // 4GB but any part of the DMA transfer being mapped is above 4GB, then
1298 // map the DMA transfer to a buffer below 4GB.
1301 if (Operation
== EfiPciOperationBusMasterCommonBuffer
||
1302 Operation
== EfiPciOperationBusMasterCommonBuffer64
) {
1304 // Common Buffer operations can not be remapped. If the common buffer
1305 // if above 4GB, then it is not possible to generate a mapping, so return
1308 return EFI_UNSUPPORTED
;
1312 // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
1315 MapInfo
= AllocatePool (sizeof (MAP_INFO
));
1316 if (MapInfo
== NULL
) {
1318 return EFI_OUT_OF_RESOURCES
;
1322 // Initialize the MAP_INFO structure
1324 MapInfo
->Signature
= MAP_INFO_SIGNATURE
;
1325 MapInfo
->Operation
= Operation
;
1326 MapInfo
->NumberOfBytes
= *NumberOfBytes
;
1327 MapInfo
->NumberOfPages
= EFI_SIZE_TO_PAGES (MapInfo
->NumberOfBytes
);
1328 MapInfo
->HostAddress
= PhysicalAddress
;
1329 MapInfo
->MappedHostAddress
= SIZE_4GB
- 1;
1332 // Allocate a buffer below 4GB to map the transfer to.
1334 Status
= gBS
->AllocatePages (
1336 EfiBootServicesData
,
1337 MapInfo
->NumberOfPages
,
1338 &MapInfo
->MappedHostAddress
1340 if (EFI_ERROR (Status
)) {
1347 // If this is a read operation from the Bus Master's point of view,
1348 // then copy the contents of the real buffer into the mapped buffer
1349 // so the Bus Master can read the contents of the real buffer.
1351 if (Operation
== EfiPciOperationBusMasterRead
||
1352 Operation
== EfiPciOperationBusMasterRead64
) {
1354 (VOID
*) (UINTN
) MapInfo
->MappedHostAddress
,
1355 (VOID
*) (UINTN
) MapInfo
->HostAddress
,
1356 MapInfo
->NumberOfBytes
1360 InsertTailList (&RootBridge
->Maps
, &MapInfo
->Link
);
1363 // The DeviceAddress is the address of the maped buffer below 4GB
1365 *DeviceAddress
= MapInfo
->MappedHostAddress
;
1367 // Return a pointer to the MAP_INFO structure in Mapping
1372 // If the root bridge CAN handle performing DMA above 4GB or
1373 // the transfer is below 4GB, so the DeviceAddress is simply the
1376 *DeviceAddress
= PhysicalAddress
;
1377 *Mapping
= NO_MAPPING
;
1384 Completes the Map() operation and releases any corresponding resources.
1386 The Unmap() function completes the Map() operation and releases any
1387 corresponding resources.
1388 If the operation was an EfiPciOperationBusMasterWrite or
1389 EfiPciOperationBusMasterWrite64, the data is committed to the target system
1391 Any resources used for the mapping are freed.
1393 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1394 @param[in] Mapping The mapping value returned from Map().
1396 @retval EFI_SUCCESS The range was unmapped.
1397 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
1398 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
1403 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1409 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1412 if (mIoMmuProtocol
!= NULL
) {
1413 Status
= mIoMmuProtocol
->Unmap (
1420 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1423 // See if the Map() operation associated with this Unmap() required a mapping
1424 // buffer. If a mapping buffer was not required, then this function simply
1425 // returns EFI_SUCCESS.
1427 if (Mapping
== NO_MAPPING
) {
1431 MapInfo
= NO_MAPPING
;
1432 for (Link
= GetFirstNode (&RootBridge
->Maps
)
1433 ; !IsNull (&RootBridge
->Maps
, Link
)
1434 ; Link
= GetNextNode (&RootBridge
->Maps
, Link
)
1436 MapInfo
= MAP_INFO_FROM_LINK (Link
);
1437 if (MapInfo
== Mapping
) {
1442 // Mapping is not a valid value returned by Map()
1444 if (MapInfo
!= Mapping
) {
1445 return EFI_INVALID_PARAMETER
;
1447 RemoveEntryList (&MapInfo
->Link
);
1450 // If this is a write operation from the Bus Master's point of view,
1451 // then copy the contents of the mapped buffer into the real buffer
1452 // so the processor can read the contents of the real buffer.
1454 if (MapInfo
->Operation
== EfiPciOperationBusMasterWrite
||
1455 MapInfo
->Operation
== EfiPciOperationBusMasterWrite64
) {
1457 (VOID
*) (UINTN
) MapInfo
->HostAddress
,
1458 (VOID
*) (UINTN
) MapInfo
->MappedHostAddress
,
1459 MapInfo
->NumberOfBytes
1464 // Free the mapped buffer and the MAP_INFO structure.
1466 gBS
->FreePages (MapInfo
->MappedHostAddress
, MapInfo
->NumberOfPages
);
1472 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer
1473 or EfiPciOperationBusMasterCommonBuffer64 mapping.
1475 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1476 @param Type This parameter is not used and must be ignored.
1477 @param MemoryType The type of memory to allocate, EfiBootServicesData or
1478 EfiRuntimeServicesData.
1479 @param Pages The number of pages to allocate.
1480 @param HostAddress A pointer to store the base system memory address of the
1482 @param Attributes The requested bit mask of attributes for the allocated
1483 range. Only the attributes
1484 EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,
1485 EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and
1486 EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this
1489 @retval EFI_SUCCESS The requested memory pages were allocated.
1490 @retval EFI_INVALID_PARAMETER MemoryType is invalid.
1491 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
1492 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal
1493 attribute bits are MEMORY_WRITE_COMBINE,
1494 MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
1495 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1499 RootBridgeIoAllocateBuffer (
1500 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1501 IN EFI_ALLOCATE_TYPE Type
,
1502 IN EFI_MEMORY_TYPE MemoryType
,
1504 OUT VOID
**HostAddress
,
1505 IN UINT64 Attributes
1509 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1510 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1511 EFI_ALLOCATE_TYPE AllocateType
;
1514 // Validate Attributes
1516 if ((Attributes
& EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER
) != 0) {
1517 return EFI_UNSUPPORTED
;
1521 // Check for invalid inputs
1523 if (HostAddress
== NULL
) {
1524 return EFI_INVALID_PARAMETER
;
1528 // The only valid memory types are EfiBootServicesData and
1529 // EfiRuntimeServicesData
1531 if (MemoryType
!= EfiBootServicesData
&&
1532 MemoryType
!= EfiRuntimeServicesData
) {
1533 return EFI_INVALID_PARAMETER
;
1536 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1538 if (mIoMmuProtocol
!= NULL
) {
1539 if (!RootBridge
->DmaAbove4G
) {
1541 // Clear DUAL_ADDRESS_CYCLE
1543 Attributes
&= ~((UINT64
) EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1545 Status
= mIoMmuProtocol
->AllocateBuffer (
1556 AllocateType
= AllocateAnyPages
;
1557 if (!RootBridge
->DmaAbove4G
||
1558 (Attributes
& EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE
) == 0) {
1560 // Limit allocations to memory below 4GB
1562 AllocateType
= AllocateMaxAddress
;
1563 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
) (SIZE_4GB
- 1);
1565 Status
= gBS
->AllocatePages (
1571 if (!EFI_ERROR (Status
)) {
1572 *HostAddress
= (VOID
*) (UINTN
) PhysicalAddress
;
1579 Frees memory that was allocated with AllocateBuffer().
1581 The FreeBuffer() function frees memory that was allocated with
1584 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1585 @param Pages The number of pages to free.
1586 @param HostAddress The base system memory address of the allocated range.
1588 @retval EFI_SUCCESS The requested memory pages were freed.
1589 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and
1590 Pages was not allocated with AllocateBuffer().
1594 RootBridgeIoFreeBuffer (
1595 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1597 OUT VOID
*HostAddress
1602 if (mIoMmuProtocol
!= NULL
) {
1603 Status
= mIoMmuProtocol
->FreeBuffer (
1611 return gBS
->FreePages ((EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
, Pages
);
1615 Flushes all PCI posted write transactions from a PCI host bridge to system
1618 The Flush() function flushes any PCI posted write transactions from a PCI
1619 host bridge to system memory. Posted write transactions are generated by PCI
1620 bus masters when they perform write transactions to target addresses in
1622 This function does not flush posted write transactions from any PCI bridges.
1623 A PCI controller specific action must be taken to guarantee that the posted
1624 write transactions have been flushed from the PCI controller and from all the
1625 PCI bridges into the PCI host bridge. This is typically done with a PCI read
1626 transaction from the PCI controller prior to calling Flush().
1628 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1630 @retval EFI_SUCCESS The PCI posted write transactions were flushed
1631 from the PCI host bridge to system memory.
1632 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed
1633 from the PCI host bridge due to a hardware error.
1638 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
1645 Gets the attributes that a PCI root bridge supports setting with
1646 SetAttributes(), and the attributes that a PCI root bridge is currently
1649 The GetAttributes() function returns the mask of attributes that this PCI
1650 root bridge supports and the mask of attributes that the PCI root bridge is
1653 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1654 @param Supported A pointer to the mask of attributes that this PCI root
1655 bridge supports setting with SetAttributes().
1656 @param Attributes A pointer to the mask of attributes that this PCI root
1657 bridge is currently using.
1659 @retval EFI_SUCCESS If Supports is not NULL, then the attributes
1660 that the PCI root bridge supports is returned
1661 in Supports. If Attributes is not NULL, then
1662 the attributes that the PCI root bridge is
1663 currently using is returned in Attributes.
1664 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1668 RootBridgeIoGetAttributes (
1669 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1670 OUT UINT64
*Supported
,
1671 OUT UINT64
*Attributes
1674 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1676 if (Attributes
== NULL
&& Supported
== NULL
) {
1677 return EFI_INVALID_PARAMETER
;
1680 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1682 // Set the return value for Supported and Attributes
1684 if (Supported
!= NULL
) {
1685 *Supported
= RootBridge
->Supports
;
1688 if (Attributes
!= NULL
) {
1689 *Attributes
= RootBridge
->Attributes
;
1696 Sets attributes for a resource range on a PCI root bridge.
1698 The SetAttributes() function sets the attributes specified in Attributes for
1699 the PCI root bridge on the resource range specified by ResourceBase and
1700 ResourceLength. Since the granularity of setting these attributes may vary
1701 from resource type to resource type, and from platform to platform, the
1702 actual resource range and the one passed in by the caller may differ. As a
1703 result, this function may set the attributes specified by Attributes on a
1704 larger resource range than the caller requested. The actual range is returned
1705 in ResourceBase and ResourceLength. The caller is responsible for verifying
1706 that the actual range for which the attributes were set is acceptable.
1708 @param This A pointer to the
1709 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1710 @param Attributes The mask of attributes to set. If the
1711 attribute bit MEMORY_WRITE_COMBINE,
1712 MEMORY_CACHED, or MEMORY_DISABLE is set,
1713 then the resource range is specified by
1714 ResourceBase and ResourceLength. If
1715 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
1716 MEMORY_DISABLE are not set, then
1717 ResourceBase and ResourceLength are ignored,
1719 @param ResourceBase A pointer to the base address of the
1720 resource range to be modified by the
1721 attributes specified by Attributes.
1722 @param ResourceLength A pointer to the length of the resource
1723 range to be modified by the attributes
1724 specified by Attributes.
1726 @retval EFI_SUCCESS The current configuration of this PCI root bridge
1727 was returned in Resources.
1728 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
1729 could not be retrieved.
1733 RootBridgeIoSetAttributes (
1734 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1735 IN UINT64 Attributes
,
1736 IN OUT UINT64
*ResourceBase
,
1737 IN OUT UINT64
*ResourceLength
1740 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1742 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1744 if ((Attributes
& (~RootBridge
->Supports
)) != 0) {
1745 return EFI_UNSUPPORTED
;
1748 RootBridge
->Attributes
= Attributes
;
1753 Retrieves the current resource settings of this PCI root bridge in the form
1754 of a set of ACPI resource descriptors.
1756 There are only two resource descriptor types from the ACPI Specification that
1757 may be used to describe the current resources allocated to a PCI root bridge.
1758 These are the QWORD Address Space Descriptor, and the End Tag. The QWORD
1759 Address Space Descriptor can describe memory, I/O, and bus number ranges for
1760 dynamic or fixed resources. The configuration of a PCI root bridge is described
1761 with one or more QWORD Address Space Descriptors followed by an End Tag.
1763 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1764 @param[out] Resources A pointer to the resource descriptors that
1765 describe the current configuration of this PCI root
1766 bridge. The storage for the resource
1767 descriptors is allocated by this function. The
1768 caller must treat the return buffer as read-only
1769 data, and the buffer must not be freed by the
1772 @retval EFI_SUCCESS The current configuration of this PCI root bridge
1773 was returned in Resources.
1774 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
1775 could not be retrieved.
1779 RootBridgeIoConfiguration (
1780 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1781 OUT VOID
**Resources
1784 PCI_RESOURCE_TYPE Index
;
1785 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1786 PCI_RES_NODE
*ResAllocNode
;
1787 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptor
;
1788 EFI_ACPI_END_TAG_DESCRIPTOR
*End
;
1791 // Get this instance of the Root Bridge.
1793 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1795 RootBridge
->ConfigBuffer
,
1796 TypeMax
* sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
)
1798 Descriptor
= RootBridge
->ConfigBuffer
;
1799 for (Index
= TypeIo
; Index
< TypeMax
; Index
++) {
1801 ResAllocNode
= &RootBridge
->ResAllocNode
[Index
];
1803 if (ResAllocNode
->Status
!= ResAllocated
) {
1807 Descriptor
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1808 Descriptor
->Len
= sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3;
1809 // According to UEFI 2.7, RootBridgeIo->Configuration should return address
1810 // range in CPU view (host address), and ResAllocNode->Base is already a CPU
1811 // view address (host address).
1812 Descriptor
->AddrRangeMin
= ResAllocNode
->Base
;
1813 Descriptor
->AddrRangeMax
= ResAllocNode
->Base
+ ResAllocNode
->Length
- 1;
1814 Descriptor
->AddrLen
= ResAllocNode
->Length
;
1815 Descriptor
->AddrTranslationOffset
= GetTranslationByResourceType (
1820 switch (ResAllocNode
->Type
) {
1823 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_IO
;
1827 Descriptor
->SpecificFlag
= EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
;
1829 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1830 Descriptor
->AddrSpaceGranularity
= 32;
1834 Descriptor
->SpecificFlag
= EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
;
1836 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1837 Descriptor
->AddrSpaceGranularity
= 64;
1841 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_BUS
;
1851 // Terminate the entries.
1853 End
= (EFI_ACPI_END_TAG_DESCRIPTOR
*) Descriptor
;
1854 End
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
1855 End
->Checksum
= 0x0;
1857 *Resources
= RootBridge
->ConfigBuffer
;