3 PCI Root Bridge Io Protocol code.
5 Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "PciHostBridge.h"
17 #include "PciRootBridge.h"
18 #include "PciHostResource.h"
20 extern EDKII_IOMMU_PROTOCOL
*mIoMmuProtocol
;
22 #define NO_MAPPING (VOID *) (UINTN) -1
25 // Lookup table for increment values based on transfer widths
28 1, // EfiPciWidthUint8
29 2, // EfiPciWidthUint16
30 4, // EfiPciWidthUint32
31 8, // EfiPciWidthUint64
32 0, // EfiPciWidthFifoUint8
33 0, // EfiPciWidthFifoUint16
34 0, // EfiPciWidthFifoUint32
35 0, // EfiPciWidthFifoUint64
36 1, // EfiPciWidthFillUint8
37 2, // EfiPciWidthFillUint16
38 4, // EfiPciWidthFillUint32
39 8 // EfiPciWidthFillUint64
43 // Lookup table for increment values based on transfer widths
45 UINT8 mOutStride
[] = {
46 1, // EfiPciWidthUint8
47 2, // EfiPciWidthUint16
48 4, // EfiPciWidthUint32
49 8, // EfiPciWidthUint64
50 1, // EfiPciWidthFifoUint8
51 2, // EfiPciWidthFifoUint16
52 4, // EfiPciWidthFifoUint32
53 8, // EfiPciWidthFifoUint64
54 0, // EfiPciWidthFillUint8
55 0, // EfiPciWidthFillUint16
56 0, // EfiPciWidthFillUint32
57 0 // EfiPciWidthFillUint64
61 Construct the Pci Root Bridge instance.
63 @param Bridge The root bridge instance.
65 @return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created
66 or NULL if creation fails.
68 PCI_ROOT_BRIDGE_INSTANCE
*
70 IN PCI_ROOT_BRIDGE
*Bridge
73 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
74 PCI_RESOURCE_TYPE Index
;
75 CHAR16
*DevicePathStr
;
76 PCI_ROOT_BRIDGE_APERTURE
*Aperture
;
80 DEBUG ((EFI_D_INFO
, "RootBridge: "));
81 DEBUG ((EFI_D_INFO
, "%s\n", DevicePathStr
= ConvertDevicePathToText (Bridge
->DevicePath
, FALSE
, FALSE
)));
82 DEBUG ((EFI_D_INFO
, " Support/Attr: %lx / %lx\n", Bridge
->Supports
, Bridge
->Attributes
));
83 DEBUG ((EFI_D_INFO
, " DmaAbove4G: %s\n", Bridge
->DmaAbove4G
? L
"Yes" : L
"No"));
84 DEBUG ((EFI_D_INFO
, "NoExtConfSpace: %s\n", Bridge
->NoExtendedConfigSpace
? L
"Yes" : L
"No"));
85 DEBUG ((EFI_D_INFO
, " AllocAttr: %lx (%s%s)\n", Bridge
->AllocationAttributes
,
86 (Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
) != 0 ? L
"CombineMemPMem " : L
"",
87 (Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_MEM64_DECODE
) != 0 ? L
"Mem64Decode" : L
""
89 DEBUG ((EFI_D_INFO
, " Bus: %lx - %lx\n", Bridge
->Bus
.Base
, Bridge
->Bus
.Limit
));
90 DEBUG ((EFI_D_INFO
, " Io: %lx - %lx\n", Bridge
->Io
.Base
, Bridge
->Io
.Limit
));
91 DEBUG ((EFI_D_INFO
, " Mem: %lx - %lx\n", Bridge
->Mem
.Base
, Bridge
->Mem
.Limit
));
92 DEBUG ((EFI_D_INFO
, " MemAbove4G: %lx - %lx\n", Bridge
->MemAbove4G
.Base
, Bridge
->MemAbove4G
.Limit
));
93 DEBUG ((EFI_D_INFO
, " PMem: %lx - %lx\n", Bridge
->PMem
.Base
, Bridge
->PMem
.Limit
));
94 DEBUG ((EFI_D_INFO
, " PMemAbove4G: %lx - %lx\n", Bridge
->PMemAbove4G
.Base
, Bridge
->PMemAbove4G
.Limit
));
97 // Make sure Mem and MemAbove4G apertures are valid
99 if (Bridge
->Mem
.Base
<= Bridge
->Mem
.Limit
) {
100 ASSERT (Bridge
->Mem
.Limit
< SIZE_4GB
);
101 if (Bridge
->Mem
.Limit
>= SIZE_4GB
) {
105 if (Bridge
->MemAbove4G
.Base
<= Bridge
->MemAbove4G
.Limit
) {
106 ASSERT (Bridge
->MemAbove4G
.Base
>= SIZE_4GB
);
107 if (Bridge
->MemAbove4G
.Base
< SIZE_4GB
) {
111 if (Bridge
->PMem
.Base
<= Bridge
->PMem
.Limit
) {
112 ASSERT (Bridge
->PMem
.Limit
< SIZE_4GB
);
113 if (Bridge
->PMem
.Limit
>= SIZE_4GB
) {
117 if (Bridge
->PMemAbove4G
.Base
<= Bridge
->PMemAbove4G
.Limit
) {
118 ASSERT (Bridge
->PMemAbove4G
.Base
>= SIZE_4GB
);
119 if (Bridge
->PMemAbove4G
.Base
< SIZE_4GB
) {
125 // Ignore AllocationAttributes when resources were already assigned.
127 if (!Bridge
->ResourceAssigned
) {
128 if ((Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
) != 0) {
130 // If this bit is set, then the PCI Root Bridge does not
131 // support separate windows for Non-prefetchable and Prefetchable
134 ASSERT (Bridge
->PMem
.Base
> Bridge
->PMem
.Limit
);
135 ASSERT (Bridge
->PMemAbove4G
.Base
> Bridge
->PMemAbove4G
.Limit
);
136 if ((Bridge
->PMem
.Base
<= Bridge
->PMem
.Limit
) ||
137 (Bridge
->PMemAbove4G
.Base
<= Bridge
->PMemAbove4G
.Limit
)
143 if ((Bridge
->AllocationAttributes
& EFI_PCI_HOST_BRIDGE_MEM64_DECODE
) == 0) {
145 // If this bit is not set, then the PCI Root Bridge does not support
146 // 64 bit memory windows.
148 ASSERT (Bridge
->MemAbove4G
.Base
> Bridge
->MemAbove4G
.Limit
);
149 ASSERT (Bridge
->PMemAbove4G
.Base
> Bridge
->PMemAbove4G
.Limit
);
150 if ((Bridge
->MemAbove4G
.Base
<= Bridge
->MemAbove4G
.Limit
) ||
151 (Bridge
->PMemAbove4G
.Base
<= Bridge
->PMemAbove4G
.Limit
)
158 RootBridge
= AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE
));
159 ASSERT (RootBridge
!= NULL
);
161 RootBridge
->Signature
= PCI_ROOT_BRIDGE_SIGNATURE
;
162 RootBridge
->Supports
= Bridge
->Supports
;
163 RootBridge
->Attributes
= Bridge
->Attributes
;
164 RootBridge
->DmaAbove4G
= Bridge
->DmaAbove4G
;
165 RootBridge
->NoExtendedConfigSpace
= Bridge
->NoExtendedConfigSpace
;
166 RootBridge
->AllocationAttributes
= Bridge
->AllocationAttributes
;
167 RootBridge
->DevicePath
= DuplicateDevicePath (Bridge
->DevicePath
);
168 RootBridge
->DevicePathStr
= DevicePathStr
;
169 RootBridge
->ConfigBuffer
= AllocatePool (
170 TypeMax
* sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
)
172 ASSERT (RootBridge
->ConfigBuffer
!= NULL
);
173 InitializeListHead (&RootBridge
->Maps
);
175 CopyMem (&RootBridge
->Bus
, &Bridge
->Bus
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
176 CopyMem (&RootBridge
->Io
, &Bridge
->Io
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
177 CopyMem (&RootBridge
->Mem
, &Bridge
->Mem
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
178 CopyMem (&RootBridge
->MemAbove4G
, &Bridge
->MemAbove4G
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
179 CopyMem (&RootBridge
->PMem
, &Bridge
->PMem
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
180 CopyMem (&RootBridge
->PMemAbove4G
, &Bridge
->PMemAbove4G
, sizeof (PCI_ROOT_BRIDGE_APERTURE
));
182 for (Index
= TypeIo
; Index
< TypeMax
; Index
++) {
185 Aperture
= &RootBridge
->Bus
;
188 Aperture
= &RootBridge
->Io
;
191 Aperture
= &RootBridge
->Mem
;
194 Aperture
= &RootBridge
->MemAbove4G
;
197 Aperture
= &RootBridge
->PMem
;
200 Aperture
= &RootBridge
->PMemAbove4G
;
207 RootBridge
->ResAllocNode
[Index
].Type
= Index
;
208 if (Bridge
->ResourceAssigned
&& (Aperture
->Limit
>= Aperture
->Base
)) {
209 RootBridge
->ResAllocNode
[Index
].Base
= Aperture
->Base
;
210 RootBridge
->ResAllocNode
[Index
].Length
= Aperture
->Limit
- Aperture
->Base
+ 1;
211 RootBridge
->ResAllocNode
[Index
].Status
= ResAllocated
;
213 RootBridge
->ResAllocNode
[Index
].Base
= 0;
214 RootBridge
->ResAllocNode
[Index
].Length
= 0;
215 RootBridge
->ResAllocNode
[Index
].Status
= ResNone
;
219 RootBridge
->RootBridgeIo
.SegmentNumber
= Bridge
->Segment
;
220 RootBridge
->RootBridgeIo
.PollMem
= RootBridgeIoPollMem
;
221 RootBridge
->RootBridgeIo
.PollIo
= RootBridgeIoPollIo
;
222 RootBridge
->RootBridgeIo
.Mem
.Read
= RootBridgeIoMemRead
;
223 RootBridge
->RootBridgeIo
.Mem
.Write
= RootBridgeIoMemWrite
;
224 RootBridge
->RootBridgeIo
.Io
.Read
= RootBridgeIoIoRead
;
225 RootBridge
->RootBridgeIo
.Io
.Write
= RootBridgeIoIoWrite
;
226 RootBridge
->RootBridgeIo
.CopyMem
= RootBridgeIoCopyMem
;
227 RootBridge
->RootBridgeIo
.Pci
.Read
= RootBridgeIoPciRead
;
228 RootBridge
->RootBridgeIo
.Pci
.Write
= RootBridgeIoPciWrite
;
229 RootBridge
->RootBridgeIo
.Map
= RootBridgeIoMap
;
230 RootBridge
->RootBridgeIo
.Unmap
= RootBridgeIoUnmap
;
231 RootBridge
->RootBridgeIo
.AllocateBuffer
= RootBridgeIoAllocateBuffer
;
232 RootBridge
->RootBridgeIo
.FreeBuffer
= RootBridgeIoFreeBuffer
;
233 RootBridge
->RootBridgeIo
.Flush
= RootBridgeIoFlush
;
234 RootBridge
->RootBridgeIo
.GetAttributes
= RootBridgeIoGetAttributes
;
235 RootBridge
->RootBridgeIo
.SetAttributes
= RootBridgeIoSetAttributes
;
236 RootBridge
->RootBridgeIo
.Configuration
= RootBridgeIoConfiguration
;
242 Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
244 The I/O operations are carried out exactly as requested. The caller is
245 responsible for satisfying any alignment and I/O width restrictions that a PI
246 System on a platform might require. For example on some platforms, width
247 requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other
248 hand, will be handled by the driver.
250 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
252 @param[in] OperationType I/O operation type: IO/MMIO/PCI.
254 @param[in] Width Signifies the width of the I/O or Memory operation.
256 @param[in] Address The base address of the I/O operation.
258 @param[in] Count The number of I/O operations to perform. The number
259 of bytes moved is Width size * Count, starting at
262 @param[in] Buffer For read operations, the destination buffer to
263 store the results. For write operations, the source
264 buffer from which to write data.
266 @retval EFI_SUCCESS The parameters for this request pass the
269 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
271 @retval EFI_INVALID_PARAMETER Buffer is NULL.
273 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
275 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
276 and Count is not valid for this PI system.
279 RootBridgeIoCheckParameter (
280 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
281 IN OPERATION_TYPE OperationType
,
282 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
288 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
289 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*PciRbAddr
;
295 // Check to see if Buffer is NULL
297 if (Buffer
== NULL
) {
298 return EFI_INVALID_PARAMETER
;
302 // Check to see if Width is in the valid range
304 if ((UINT32
) Width
>= EfiPciWidthMaximum
) {
305 return EFI_INVALID_PARAMETER
;
309 // For FIFO type, the target address won't increase during the access,
310 // so treat Count as 1
312 if (Width
>= EfiPciWidthFifoUint8
&& Width
<= EfiPciWidthFifoUint64
) {
316 Width
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
320 // Check to see if Address is aligned
322 if ((Address
& (Size
- 1)) != 0) {
323 return EFI_UNSUPPORTED
;
326 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
329 // Check to see if any address associated with this transfer exceeds the
330 // maximum allowed address. The maximum address implied by the parameters
331 // passed in is Address + Size * Count. If the following condition is met,
332 // then the transfer is not supported.
334 // Address + Size * Count > Limit + 1
336 // Since Limit can be the maximum integer value supported by the CPU and
337 // Count can also be the maximum integer value supported by the CPU, this
338 // range check must be adjusted to avoid all oveflow conditions.
340 if (OperationType
== IoOperation
) {
342 // Allow Legacy IO access
344 if (Address
+ MultU64x32 (Count
, Size
) <= 0x1000) {
345 if ((RootBridge
->Attributes
& (
346 EFI_PCI_ATTRIBUTE_ISA_IO
| EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO
| EFI_PCI_ATTRIBUTE_VGA_IO
|
347 EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO
| EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO
|
348 EFI_PCI_ATTRIBUTE_ISA_IO_16
| EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
| EFI_PCI_ATTRIBUTE_VGA_IO_16
)) != 0) {
352 Base
= RootBridge
->Io
.Base
;
353 Limit
= RootBridge
->Io
.Limit
;
354 } else if (OperationType
== MemOperation
) {
356 // Allow Legacy MMIO access
358 if ((Address
>= 0xA0000) && (Address
+ MultU64x32 (Count
, Size
)) <= 0xC0000) {
359 if ((RootBridge
->Attributes
& EFI_PCI_ATTRIBUTE_VGA_MEMORY
) != 0) {
364 // By comparing the Address against Limit we know which range to be used
367 if (Address
+ MultU64x32 (Count
, Size
) <= RootBridge
->Mem
.Limit
+ 1) {
368 Base
= RootBridge
->Mem
.Base
;
369 Limit
= RootBridge
->Mem
.Limit
;
371 Base
= RootBridge
->MemAbove4G
.Base
;
372 Limit
= RootBridge
->MemAbove4G
.Limit
;
375 PciRbAddr
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS
*) &Address
;
376 if (PciRbAddr
->Bus
< RootBridge
->Bus
.Base
||
377 PciRbAddr
->Bus
> RootBridge
->Bus
.Limit
) {
378 return EFI_INVALID_PARAMETER
;
381 if (PciRbAddr
->Device
> PCI_MAX_DEVICE
||
382 PciRbAddr
->Function
> PCI_MAX_FUNC
) {
383 return EFI_INVALID_PARAMETER
;
386 if (PciRbAddr
->ExtendedRegister
!= 0) {
387 Address
= PciRbAddr
->ExtendedRegister
;
389 Address
= PciRbAddr
->Register
;
392 Limit
= RootBridge
->NoExtendedConfigSpace
? 0xFF : 0xFFF;
395 if (Address
< Base
) {
396 return EFI_INVALID_PARAMETER
;
399 if (Address
+ MultU64x32 (Count
, Size
) > Limit
+ 1) {
400 return EFI_INVALID_PARAMETER
;
407 Polls an address in memory mapped I/O space until an exit condition is met,
410 This function provides a standard way to poll a PCI memory location. A PCI
411 memory read operation is performed at the PCI memory address specified by
412 Address for the width specified by Width. The result of this PCI memory read
413 operation is stored in Result. This PCI memory read operation is repeated
414 until either a timeout of Delay 100 ns units has expired, or (Result & Mask)
417 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
418 @param[in] Width Signifies the width of the memory operations.
419 @param[in] Address The base address of the memory operations. The caller
420 is responsible for aligning Address if required.
421 @param[in] Mask Mask used for the polling criteria. Bytes above Width
422 in Mask are ignored. The bits in the bytes below Width
423 which are zero in Mask are ignored when polling the
425 @param[in] Value The comparison value used for the polling exit
427 @param[in] Delay The number of 100 ns units to poll. Note that timer
428 available may be of poorer granularity.
429 @param[out] Result Pointer to the last value read from the memory
432 @retval EFI_SUCCESS The last data returned from the access matched
433 the poll exit criteria.
434 @retval EFI_INVALID_PARAMETER Width is invalid.
435 @retval EFI_INVALID_PARAMETER Result is NULL.
436 @retval EFI_TIMEOUT Delay expired before a match occurred.
437 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
442 RootBridgeIoPollMem (
443 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
444 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
453 UINT64 NumberOfTicks
;
456 if (Result
== NULL
) {
457 return EFI_INVALID_PARAMETER
;
460 if ((UINT32
)Width
> EfiPciWidthUint64
) {
461 return EFI_INVALID_PARAMETER
;
465 // No matter what, always do a single poll.
467 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
468 if (EFI_ERROR (Status
)) {
472 if ((*Result
& Mask
) == Value
) {
482 // Determine the proper # of metronome ticks to wait for polling the
483 // location. The nuber of ticks is Roundup (Delay /
484 // mMetronome->TickPeriod)+1
485 // The "+1" to account for the possibility of the first tick being short
486 // because we started in the middle of a tick.
488 // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
489 // protocol definition is updated.
491 NumberOfTicks
= DivU64x32Remainder (Delay
, (UINT32
) mMetronome
->TickPeriod
,
493 if (Remainder
!= 0) {
498 while (NumberOfTicks
!= 0) {
500 mMetronome
->WaitForTick (mMetronome
, 1);
502 Status
= This
->Mem
.Read (This
, Width
, Address
, 1, Result
);
503 if (EFI_ERROR (Status
)) {
507 if ((*Result
& Mask
) == Value
) {
518 Reads from the I/O space of a PCI Root Bridge. Returns when either the
519 polling exit criteria is satisfied or after a defined duration.
521 This function provides a standard way to poll a PCI I/O location. A PCI I/O
522 read operation is performed at the PCI I/O address specified by Address for
523 the width specified by Width.
524 The result of this PCI I/O read operation is stored in Result. This PCI I/O
525 read operation is repeated until either a timeout of Delay 100 ns units has
526 expired, or (Result & Mask) is equal to Value.
528 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
529 @param[in] Width Signifies the width of the I/O operations.
530 @param[in] Address The base address of the I/O operations. The caller is
531 responsible for aligning Address if required.
532 @param[in] Mask Mask used for the polling criteria. Bytes above Width in
533 Mask are ignored. The bits in the bytes below Width
534 which are zero in Mask are ignored when polling the I/O
536 @param[in] Value The comparison value used for the polling exit criteria.
537 @param[in] Delay The number of 100 ns units to poll. Note that timer
538 available may be of poorer granularity.
539 @param[out] Result Pointer to the last value read from the memory location.
541 @retval EFI_SUCCESS The last data returned from the access matched
542 the poll exit criteria.
543 @retval EFI_INVALID_PARAMETER Width is invalid.
544 @retval EFI_INVALID_PARAMETER Result is NULL.
545 @retval EFI_TIMEOUT Delay expired before a match occurred.
546 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
552 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
553 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
562 UINT64 NumberOfTicks
;
566 // No matter what, always do a single poll.
569 if (Result
== NULL
) {
570 return EFI_INVALID_PARAMETER
;
573 if ((UINT32
)Width
> EfiPciWidthUint64
) {
574 return EFI_INVALID_PARAMETER
;
577 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
578 if (EFI_ERROR (Status
)) {
581 if ((*Result
& Mask
) == Value
) {
591 // Determine the proper # of metronome ticks to wait for polling the
592 // location. The number of ticks is Roundup (Delay /
593 // mMetronome->TickPeriod)+1
594 // The "+1" to account for the possibility of the first tick being short
595 // because we started in the middle of a tick.
597 NumberOfTicks
= DivU64x32Remainder (Delay
, (UINT32
)mMetronome
->TickPeriod
,
599 if (Remainder
!= 0) {
604 while (NumberOfTicks
!= 0) {
606 mMetronome
->WaitForTick (mMetronome
, 1);
608 Status
= This
->Io
.Read (This
, Width
, Address
, 1, Result
);
609 if (EFI_ERROR (Status
)) {
613 if ((*Result
& Mask
) == Value
) {
624 Enables a PCI driver to access PCI controller registers in the PCI root
627 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
628 controller registers in the PCI root bridge memory space.
629 The memory operations are carried out exactly as requested. The caller is
630 responsible for satisfying any alignment and memory width restrictions that a
631 PCI Root Bridge on a platform might require.
633 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
634 @param[in] Width Signifies the width of the memory operation.
635 @param[in] Address The base address of the memory operation. The caller
636 is responsible for aligning the Address if required.
637 @param[in] Count The number of memory operations to perform. Bytes
638 moved is Width size * Count, starting at Address.
639 @param[out] Buffer For read operations, the destination buffer to store
640 the results. For write operations, the source buffer
643 @retval EFI_SUCCESS The data was read from or written to the PCI
645 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
646 @retval EFI_INVALID_PARAMETER Buffer is NULL.
647 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
652 RootBridgeIoMemRead (
653 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
654 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
662 Status
= RootBridgeIoCheckParameter (This
, MemOperation
, Width
, Address
,
664 if (EFI_ERROR (Status
)) {
667 return mCpuIo
->Mem
.Read (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
, Address
, Count
, Buffer
);
671 Enables a PCI driver to access PCI controller registers in the PCI root
674 The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
675 controller registers in the PCI root bridge memory space.
676 The memory operations are carried out exactly as requested. The caller is
677 responsible for satisfying any alignment and memory width restrictions that a
678 PCI Root Bridge on a platform might require.
680 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
681 @param[in] Width Signifies the width of the memory operation.
682 @param[in] Address The base address of the memory operation. The caller
683 is responsible for aligning the Address if required.
684 @param[in] Count The number of memory operations to perform. Bytes
685 moved is Width size * Count, starting at Address.
686 @param[in] Buffer For read operations, the destination buffer to store
687 the results. For write operations, the source buffer
690 @retval EFI_SUCCESS The data was read from or written to the PCI
692 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
693 @retval EFI_INVALID_PARAMETER Buffer is NULL.
694 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
699 RootBridgeIoMemWrite (
700 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
701 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
709 Status
= RootBridgeIoCheckParameter (This
, MemOperation
, Width
, Address
,
711 if (EFI_ERROR (Status
)) {
714 return mCpuIo
->Mem
.Write (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
, Address
, Count
, Buffer
);
718 Enables a PCI driver to access PCI controller registers in the PCI root
721 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
722 @param[in] Width Signifies the width of the memory operations.
723 @param[in] Address The base address of the I/O operation. The caller is
724 responsible for aligning the Address if required.
725 @param[in] Count The number of I/O operations to perform. Bytes moved
726 is Width size * Count, starting at Address.
727 @param[out] Buffer For read operations, the destination buffer to store
728 the results. For write operations, the source buffer
731 @retval EFI_SUCCESS The data was read from or written to the PCI
733 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
734 @retval EFI_INVALID_PARAMETER Buffer is NULL.
735 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
741 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
742 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
749 Status
= RootBridgeIoCheckParameter (
750 This
, IoOperation
, Width
,
751 Address
, Count
, Buffer
753 if (EFI_ERROR (Status
)) {
756 return mCpuIo
->Io
.Read (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
, Address
, Count
, Buffer
);
760 Enables a PCI driver to access PCI controller registers in the PCI root
763 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
764 @param[in] Width Signifies the width of the memory operations.
765 @param[in] Address The base address of the I/O operation. The caller is
766 responsible for aligning the Address if required.
767 @param[in] Count The number of I/O operations to perform. Bytes moved
768 is Width size * Count, starting at Address.
769 @param[in] Buffer For read operations, the destination buffer to store
770 the results. For write operations, the source buffer
773 @retval EFI_SUCCESS The data was read from or written to the PCI
775 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
776 @retval EFI_INVALID_PARAMETER Buffer is NULL.
777 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
782 RootBridgeIoIoWrite (
783 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
784 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
791 Status
= RootBridgeIoCheckParameter (
792 This
, IoOperation
, Width
,
793 Address
, Count
, Buffer
795 if (EFI_ERROR (Status
)) {
798 return mCpuIo
->Io
.Write (mCpuIo
, (EFI_CPU_IO_PROTOCOL_WIDTH
) Width
, Address
, Count
, Buffer
);
802 Enables a PCI driver to copy one region of PCI root bridge memory space to
803 another region of PCI root bridge memory space.
805 The CopyMem() function enables a PCI driver to copy one region of PCI root
806 bridge memory space to another region of PCI root bridge memory space. This
807 is especially useful for video scroll operation on a memory mapped video
809 The memory operations are carried out exactly as requested. The caller is
810 responsible for satisfying any alignment and memory width restrictions that a
811 PCI root bridge on a platform might require.
813 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
815 @param[in] Width Signifies the width of the memory operations.
816 @param[in] DestAddress The destination address of the memory operation. The
817 caller is responsible for aligning the DestAddress if
819 @param[in] SrcAddress The source address of the memory operation. The caller
820 is responsible for aligning the SrcAddress if
822 @param[in] Count The number of memory operations to perform. Bytes
823 moved is Width size * Count, starting at DestAddress
826 @retval EFI_SUCCESS The data was copied from one memory region
827 to another memory region.
828 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
829 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
834 RootBridgeIoCopyMem (
835 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
836 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
837 IN UINT64 DestAddress
,
838 IN UINT64 SrcAddress
,
848 if ((UINT32
) Width
> EfiPciWidthUint64
) {
849 return EFI_INVALID_PARAMETER
;
852 if (DestAddress
== SrcAddress
) {
856 Stride
= (UINTN
) (1 << Width
);
859 if ((DestAddress
> SrcAddress
) &&
860 (DestAddress
< (SrcAddress
+ Count
* Stride
))) {
862 SrcAddress
= SrcAddress
+ (Count
- 1) * Stride
;
863 DestAddress
= DestAddress
+ (Count
- 1) * Stride
;
866 for (Index
= 0; Index
< Count
; Index
++) {
867 Status
= RootBridgeIoMemRead (
874 if (EFI_ERROR (Status
)) {
877 Status
= RootBridgeIoMemWrite (
884 if (EFI_ERROR (Status
)) {
888 SrcAddress
+= Stride
;
889 DestAddress
+= Stride
;
891 SrcAddress
-= Stride
;
892 DestAddress
-= Stride
;
900 PCI configuration space access.
902 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
903 @param Read TRUE indicating it's a read operation.
904 @param Width Signifies the width of the memory operation.
905 @param Address The address within the PCI configuration space
906 for the PCI controller.
907 @param Count The number of PCI configuration operations
909 @param Buffer The destination buffer to store the results.
911 @retval EFI_SUCCESS The data was read/written from/to the PCI root bridge.
912 @retval EFI_INVALID_PARAMETER Invalid parameters found.
916 RootBridgeIoPciAccess (
917 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
919 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
926 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
927 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress
;
933 Status
= RootBridgeIoCheckParameter (This
, PciOperation
, Width
, Address
, Count
, Buffer
);
934 if (EFI_ERROR (Status
)) {
939 // Read Pci configuration space
941 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
942 CopyMem (&PciAddress
, &Address
, sizeof (PciAddress
));
944 if (PciAddress
.ExtendedRegister
== 0) {
945 PciAddress
.ExtendedRegister
= PciAddress
.Register
;
948 Address
= PCI_SEGMENT_LIB_ADDRESS (
949 RootBridge
->RootBridgeIo
.SegmentNumber
,
953 PciAddress
.ExtendedRegister
957 // Select loop based on the width of the transfer
959 InStride
= mInStride
[Width
];
960 OutStride
= mOutStride
[Width
];
961 Size
= (UINTN
) (1 << (Width
& 0x03));
962 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
964 PciSegmentReadBuffer (Address
, Size
, Uint8Buffer
);
966 PciSegmentWriteBuffer (Address
, Size
, Uint8Buffer
);
973 Allows read from PCI configuration space.
975 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
976 @param Width Signifies the width of the memory operation.
977 @param Address The address within the PCI configuration space
978 for the PCI controller.
979 @param Count The number of PCI configuration operations
981 @param Buffer The destination buffer to store the results.
983 @retval EFI_SUCCESS The data was read from the PCI root bridge.
984 @retval EFI_INVALID_PARAMETER Invalid parameters found.
988 RootBridgeIoPciRead (
989 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
990 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
996 return RootBridgeIoPciAccess (This
, TRUE
, Width
, Address
, Count
, Buffer
);
1000 Allows write to PCI configuration space.
1002 @param This A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
1003 @param Width Signifies the width of the memory operation.
1004 @param Address The address within the PCI configuration space
1005 for the PCI controller.
1006 @param Count The number of PCI configuration operations
1008 @param Buffer The source buffer to get the results.
1010 @retval EFI_SUCCESS The data was written to the PCI root bridge.
1011 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1015 RootBridgeIoPciWrite (
1016 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1017 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
1023 return RootBridgeIoPciAccess (This
, FALSE
, Width
, Address
, Count
, Buffer
);
1027 Provides the PCI controller-specific address needed to access
1028 system memory for DMA.
1030 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1031 @param Operation Indicate if the bus master is going to read or write
1033 @param HostAddress The system memory address to map on the PCI controller.
1034 @param NumberOfBytes On input the number of bytes to map.
1035 On output the number of bytes that were mapped.
1036 @param DeviceAddress The resulting map address for the bus master PCI
1037 controller to use to access the system memory's HostAddress.
1038 @param Mapping The value to pass to Unmap() when the bus master DMA
1039 operation is complete.
1041 @retval EFI_SUCCESS Success.
1042 @retval EFI_INVALID_PARAMETER Invalid parameters found.
1043 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
1044 @retval EFI_DEVICE_ERROR The System hardware could not map the requested address.
1045 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to lack of resources.
1050 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1051 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation
,
1052 IN VOID
*HostAddress
,
1053 IN OUT UINTN
*NumberOfBytes
,
1054 OUT EFI_PHYSICAL_ADDRESS
*DeviceAddress
,
1059 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1060 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1063 if (HostAddress
== NULL
|| NumberOfBytes
== NULL
|| DeviceAddress
== NULL
||
1065 return EFI_INVALID_PARAMETER
;
1069 // Make sure that Operation is valid
1071 if ((UINT32
) Operation
>= EfiPciOperationMaximum
) {
1072 return EFI_INVALID_PARAMETER
;
1075 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1077 if (mIoMmuProtocol
!= NULL
) {
1078 if (!RootBridge
->DmaAbove4G
) {
1080 // Clear 64bit support
1082 if (Operation
> EfiPciOperationBusMasterCommonBuffer
) {
1083 Operation
= (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION
) (Operation
- EfiPciOperationBusMasterRead64
);
1086 Status
= mIoMmuProtocol
->Map (
1088 (EDKII_IOMMU_OPERATION
) Operation
,
1097 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
;
1098 if ((!RootBridge
->DmaAbove4G
||
1099 (Operation
!= EfiPciOperationBusMasterRead64
&&
1100 Operation
!= EfiPciOperationBusMasterWrite64
&&
1101 Operation
!= EfiPciOperationBusMasterCommonBuffer64
)) &&
1102 ((PhysicalAddress
+ *NumberOfBytes
) > SIZE_4GB
)) {
1105 // If the root bridge or the device cannot handle performing DMA above
1106 // 4GB but any part of the DMA transfer being mapped is above 4GB, then
1107 // map the DMA transfer to a buffer below 4GB.
1110 if (Operation
== EfiPciOperationBusMasterCommonBuffer
||
1111 Operation
== EfiPciOperationBusMasterCommonBuffer64
) {
1113 // Common Buffer operations can not be remapped. If the common buffer
1114 // if above 4GB, then it is not possible to generate a mapping, so return
1117 return EFI_UNSUPPORTED
;
1121 // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
1124 MapInfo
= AllocatePool (sizeof (MAP_INFO
));
1125 if (MapInfo
== NULL
) {
1127 return EFI_OUT_OF_RESOURCES
;
1131 // Initialize the MAP_INFO structure
1133 MapInfo
->Signature
= MAP_INFO_SIGNATURE
;
1134 MapInfo
->Operation
= Operation
;
1135 MapInfo
->NumberOfBytes
= *NumberOfBytes
;
1136 MapInfo
->NumberOfPages
= EFI_SIZE_TO_PAGES (MapInfo
->NumberOfBytes
);
1137 MapInfo
->HostAddress
= PhysicalAddress
;
1138 MapInfo
->MappedHostAddress
= SIZE_4GB
- 1;
1141 // Allocate a buffer below 4GB to map the transfer to.
1143 Status
= gBS
->AllocatePages (
1145 EfiBootServicesData
,
1146 MapInfo
->NumberOfPages
,
1147 &MapInfo
->MappedHostAddress
1149 if (EFI_ERROR (Status
)) {
1156 // If this is a read operation from the Bus Master's point of view,
1157 // then copy the contents of the real buffer into the mapped buffer
1158 // so the Bus Master can read the contents of the real buffer.
1160 if (Operation
== EfiPciOperationBusMasterRead
||
1161 Operation
== EfiPciOperationBusMasterRead64
) {
1163 (VOID
*) (UINTN
) MapInfo
->MappedHostAddress
,
1164 (VOID
*) (UINTN
) MapInfo
->HostAddress
,
1165 MapInfo
->NumberOfBytes
1169 InsertTailList (&RootBridge
->Maps
, &MapInfo
->Link
);
1172 // The DeviceAddress is the address of the maped buffer below 4GB
1174 *DeviceAddress
= MapInfo
->MappedHostAddress
;
1176 // Return a pointer to the MAP_INFO structure in Mapping
1181 // If the root bridge CAN handle performing DMA above 4GB or
1182 // the transfer is below 4GB, so the DeviceAddress is simply the
1185 *DeviceAddress
= PhysicalAddress
;
1186 *Mapping
= NO_MAPPING
;
1193 Completes the Map() operation and releases any corresponding resources.
1195 The Unmap() function completes the Map() operation and releases any
1196 corresponding resources.
1197 If the operation was an EfiPciOperationBusMasterWrite or
1198 EfiPciOperationBusMasterWrite64, the data is committed to the target system
1200 Any resources used for the mapping are freed.
1202 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1203 @param[in] Mapping The mapping value returned from Map().
1205 @retval EFI_SUCCESS The range was unmapped.
1206 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
1207 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
1212 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1218 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1221 if (mIoMmuProtocol
!= NULL
) {
1222 Status
= mIoMmuProtocol
->Unmap (
1229 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1232 // See if the Map() operation associated with this Unmap() required a mapping
1233 // buffer. If a mapping buffer was not required, then this function simply
1234 // returns EFI_SUCCESS.
1236 if (Mapping
== NO_MAPPING
) {
1240 MapInfo
= NO_MAPPING
;
1241 for (Link
= GetFirstNode (&RootBridge
->Maps
)
1242 ; !IsNull (&RootBridge
->Maps
, Link
)
1243 ; Link
= GetNextNode (&RootBridge
->Maps
, Link
)
1245 MapInfo
= MAP_INFO_FROM_LINK (Link
);
1246 if (MapInfo
== Mapping
) {
1251 // Mapping is not a valid value returned by Map()
1253 if (MapInfo
!= Mapping
) {
1254 return EFI_INVALID_PARAMETER
;
1256 RemoveEntryList (&MapInfo
->Link
);
1259 // If this is a write operation from the Bus Master's point of view,
1260 // then copy the contents of the mapped buffer into the real buffer
1261 // so the processor can read the contents of the real buffer.
1263 if (MapInfo
->Operation
== EfiPciOperationBusMasterWrite
||
1264 MapInfo
->Operation
== EfiPciOperationBusMasterWrite64
) {
1266 (VOID
*) (UINTN
) MapInfo
->HostAddress
,
1267 (VOID
*) (UINTN
) MapInfo
->MappedHostAddress
,
1268 MapInfo
->NumberOfBytes
1273 // Free the mapped buffer and the MAP_INFO structure.
1275 gBS
->FreePages (MapInfo
->MappedHostAddress
, MapInfo
->NumberOfPages
);
1281 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer
1282 or EfiPciOperationBusMasterCommonBuffer64 mapping.
1284 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1285 @param Type This parameter is not used and must be ignored.
1286 @param MemoryType The type of memory to allocate, EfiBootServicesData or
1287 EfiRuntimeServicesData.
1288 @param Pages The number of pages to allocate.
1289 @param HostAddress A pointer to store the base system memory address of the
1291 @param Attributes The requested bit mask of attributes for the allocated
1292 range. Only the attributes
1293 EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,
1294 EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and
1295 EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this
1298 @retval EFI_SUCCESS The requested memory pages were allocated.
1299 @retval EFI_INVALID_PARAMETER MemoryType is invalid.
1300 @retval EFI_INVALID_PARAMETER HostAddress is NULL.
1301 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal
1302 attribute bits are MEMORY_WRITE_COMBINE,
1303 MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
1304 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1308 RootBridgeIoAllocateBuffer (
1309 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1310 IN EFI_ALLOCATE_TYPE Type
,
1311 IN EFI_MEMORY_TYPE MemoryType
,
1313 OUT VOID
**HostAddress
,
1314 IN UINT64 Attributes
1318 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
1319 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1320 EFI_ALLOCATE_TYPE AllocateType
;
1323 // Validate Attributes
1325 if ((Attributes
& EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER
) != 0) {
1326 return EFI_UNSUPPORTED
;
1330 // Check for invalid inputs
1332 if (HostAddress
== NULL
) {
1333 return EFI_INVALID_PARAMETER
;
1337 // The only valid memory types are EfiBootServicesData and
1338 // EfiRuntimeServicesData
1340 if (MemoryType
!= EfiBootServicesData
&&
1341 MemoryType
!= EfiRuntimeServicesData
) {
1342 return EFI_INVALID_PARAMETER
;
1345 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1347 if (mIoMmuProtocol
!= NULL
) {
1348 if (!RootBridge
->DmaAbove4G
) {
1350 // Clear DUAL_ADDRESS_CYCLE
1352 Attributes
&= ~((UINT64
) EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE
);
1354 Status
= mIoMmuProtocol
->AllocateBuffer (
1365 AllocateType
= AllocateAnyPages
;
1366 if (!RootBridge
->DmaAbove4G
||
1367 (Attributes
& EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE
) == 0) {
1369 // Limit allocations to memory below 4GB
1371 AllocateType
= AllocateMaxAddress
;
1372 PhysicalAddress
= (EFI_PHYSICAL_ADDRESS
) (SIZE_4GB
- 1);
1374 Status
= gBS
->AllocatePages (
1380 if (!EFI_ERROR (Status
)) {
1381 *HostAddress
= (VOID
*) (UINTN
) PhysicalAddress
;
1388 Frees memory that was allocated with AllocateBuffer().
1390 The FreeBuffer() function frees memory that was allocated with
1393 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1394 @param Pages The number of pages to free.
1395 @param HostAddress The base system memory address of the allocated range.
1397 @retval EFI_SUCCESS The requested memory pages were freed.
1398 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and
1399 Pages was not allocated with AllocateBuffer().
1403 RootBridgeIoFreeBuffer (
1404 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1406 OUT VOID
*HostAddress
1411 if (mIoMmuProtocol
!= NULL
) {
1412 Status
= mIoMmuProtocol
->FreeBuffer (
1420 return gBS
->FreePages ((EFI_PHYSICAL_ADDRESS
) (UINTN
) HostAddress
, Pages
);
1424 Flushes all PCI posted write transactions from a PCI host bridge to system
1427 The Flush() function flushes any PCI posted write transactions from a PCI
1428 host bridge to system memory. Posted write transactions are generated by PCI
1429 bus masters when they perform write transactions to target addresses in
1431 This function does not flush posted write transactions from any PCI bridges.
1432 A PCI controller specific action must be taken to guarantee that the posted
1433 write transactions have been flushed from the PCI controller and from all the
1434 PCI bridges into the PCI host bridge. This is typically done with a PCI read
1435 transaction from the PCI controller prior to calling Flush().
1437 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1439 @retval EFI_SUCCESS The PCI posted write transactions were flushed
1440 from the PCI host bridge to system memory.
1441 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed
1442 from the PCI host bridge due to a hardware error.
1447 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
1454 Gets the attributes that a PCI root bridge supports setting with
1455 SetAttributes(), and the attributes that a PCI root bridge is currently
1458 The GetAttributes() function returns the mask of attributes that this PCI
1459 root bridge supports and the mask of attributes that the PCI root bridge is
1462 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1463 @param Supported A pointer to the mask of attributes that this PCI root
1464 bridge supports setting with SetAttributes().
1465 @param Attributes A pointer to the mask of attributes that this PCI root
1466 bridge is currently using.
1468 @retval EFI_SUCCESS If Supports is not NULL, then the attributes
1469 that the PCI root bridge supports is returned
1470 in Supports. If Attributes is not NULL, then
1471 the attributes that the PCI root bridge is
1472 currently using is returned in Attributes.
1473 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1477 RootBridgeIoGetAttributes (
1478 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1479 OUT UINT64
*Supported
,
1480 OUT UINT64
*Attributes
1483 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1485 if (Attributes
== NULL
&& Supported
== NULL
) {
1486 return EFI_INVALID_PARAMETER
;
1489 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1491 // Set the return value for Supported and Attributes
1493 if (Supported
!= NULL
) {
1494 *Supported
= RootBridge
->Supports
;
1497 if (Attributes
!= NULL
) {
1498 *Attributes
= RootBridge
->Attributes
;
1505 Sets attributes for a resource range on a PCI root bridge.
1507 The SetAttributes() function sets the attributes specified in Attributes for
1508 the PCI root bridge on the resource range specified by ResourceBase and
1509 ResourceLength. Since the granularity of setting these attributes may vary
1510 from resource type to resource type, and from platform to platform, the
1511 actual resource range and the one passed in by the caller may differ. As a
1512 result, this function may set the attributes specified by Attributes on a
1513 larger resource range than the caller requested. The actual range is returned
1514 in ResourceBase and ResourceLength. The caller is responsible for verifying
1515 that the actual range for which the attributes were set is acceptable.
1517 @param This A pointer to the
1518 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1519 @param Attributes The mask of attributes to set. If the
1520 attribute bit MEMORY_WRITE_COMBINE,
1521 MEMORY_CACHED, or MEMORY_DISABLE is set,
1522 then the resource range is specified by
1523 ResourceBase and ResourceLength. If
1524 MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
1525 MEMORY_DISABLE are not set, then
1526 ResourceBase and ResourceLength are ignored,
1528 @param ResourceBase A pointer to the base address of the
1529 resource range to be modified by the
1530 attributes specified by Attributes.
1531 @param ResourceLength A pointer to the length of the resource
1532 range to be modified by the attributes
1533 specified by Attributes.
1535 @retval EFI_SUCCESS The current configuration of this PCI root bridge
1536 was returned in Resources.
1537 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
1538 could not be retrieved.
1542 RootBridgeIoSetAttributes (
1543 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1544 IN UINT64 Attributes
,
1545 IN OUT UINT64
*ResourceBase
,
1546 IN OUT UINT64
*ResourceLength
1549 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1551 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1553 if ((Attributes
& (~RootBridge
->Supports
)) != 0) {
1554 return EFI_UNSUPPORTED
;
1557 RootBridge
->Attributes
= Attributes
;
1562 Retrieves the current resource settings of this PCI root bridge in the form
1563 of a set of ACPI 2.0 resource descriptors.
1565 There are only two resource descriptor types from the ACPI Specification that
1566 may be used to describe the current resources allocated to a PCI root bridge.
1567 These are the QWORD Address Space Descriptor (ACPI 2.0 Section 6.4.3.5.1),
1568 and the End Tag (ACPI 2.0 Section 6.4.2.8). The QWORD Address Space
1569 Descriptor can describe memory, I/O, and bus number ranges for dynamic or
1570 fixed resources. The configuration of a PCI root bridge is described with one
1571 or more QWORD Address Space Descriptors followed by an End Tag.
1573 @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
1574 @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that
1575 describe the current configuration of this PCI root
1576 bridge. The storage for the ACPI 2.0 resource
1577 descriptors is allocated by this function. The
1578 caller must treat the return buffer as read-only
1579 data, and the buffer must not be freed by the
1582 @retval EFI_SUCCESS The current configuration of this PCI root bridge
1583 was returned in Resources.
1584 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
1585 could not be retrieved.
1589 RootBridgeIoConfiguration (
1590 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
1591 OUT VOID
**Resources
1594 PCI_RESOURCE_TYPE Index
;
1595 PCI_ROOT_BRIDGE_INSTANCE
*RootBridge
;
1596 PCI_RES_NODE
*ResAllocNode
;
1597 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptor
;
1598 EFI_ACPI_END_TAG_DESCRIPTOR
*End
;
1601 // Get this instance of the Root Bridge.
1603 RootBridge
= ROOT_BRIDGE_FROM_THIS (This
);
1605 RootBridge
->ConfigBuffer
,
1606 TypeMax
* sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR
)
1608 Descriptor
= RootBridge
->ConfigBuffer
;
1609 for (Index
= TypeIo
; Index
< TypeMax
; Index
++) {
1611 ResAllocNode
= &RootBridge
->ResAllocNode
[Index
];
1613 if (ResAllocNode
->Status
!= ResAllocated
) {
1617 Descriptor
->Desc
= ACPI_ADDRESS_SPACE_DESCRIPTOR
;
1618 Descriptor
->Len
= sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
) - 3;
1619 Descriptor
->AddrRangeMin
= ResAllocNode
->Base
;
1620 Descriptor
->AddrRangeMax
= ResAllocNode
->Base
+ ResAllocNode
->Length
- 1;
1621 Descriptor
->AddrLen
= ResAllocNode
->Length
;
1622 switch (ResAllocNode
->Type
) {
1625 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_IO
;
1629 Descriptor
->SpecificFlag
= EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
;
1631 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1632 Descriptor
->AddrSpaceGranularity
= 32;
1636 Descriptor
->SpecificFlag
= EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
;
1638 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_MEM
;
1639 Descriptor
->AddrSpaceGranularity
= 64;
1643 Descriptor
->ResType
= ACPI_ADDRESS_SPACE_TYPE_BUS
;
1653 // Terminate the entries.
1655 End
= (EFI_ACPI_END_TAG_DESCRIPTOR
*) Descriptor
;
1656 End
->Desc
= ACPI_END_TAG_DESCRIPTOR
;
1657 End
->Checksum
= 0x0;
1659 *Resources
= RootBridge
->ConfigBuffer
;