]> git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
projects / mirror_edk2.git / blob
? search:


baa12f44eeacea52453f5c01ea687f665ad72d2d
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00.
4
5 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
6
7 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #include "SdMmcPciHcDxe.h"
19
20 /**
21 Dump the content of SD/MMC host controller's Capability Register.
22
23 @param[in] Slot The slot number of the SD card to send the command to.
24 @param[in] Capability The buffer to store the capability data.
25
26 **/
27 VOID
28 DumpCapabilityReg (
29 IN UINT8 Slot,
30 IN SD_MMC_HC_SLOT_CAP *Capability
31 )
32 {
33 //
34 // Dump Capability Data
35 //
36 DEBUG ((EFI_D_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
37 DEBUG ((EFI_D_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
38 DEBUG ((EFI_D_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
39 DEBUG ((EFI_D_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
40 DEBUG ((EFI_D_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
41 DEBUG ((EFI_D_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
42 DEBUG ((EFI_D_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
43 DEBUG ((EFI_D_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
44 DEBUG ((EFI_D_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
45 DEBUG ((EFI_D_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
46 DEBUG ((EFI_D_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
47 DEBUG ((EFI_D_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
48 DEBUG ((EFI_D_INFO, " 64-bit Sys Bus %a\n", Capability->SysBus64 ? "TRUE" : "FALSE"));
49 DEBUG ((EFI_D_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
50 DEBUG ((EFI_D_INFO, " SlotType "));
51 if (Capability->SlotType == 0x00) {
52 DEBUG ((EFI_D_INFO, "%a\n", "Removable Slot"));
53 } else if (Capability->SlotType == 0x01) {
54 DEBUG ((EFI_D_INFO, "%a\n", "Embedded Slot"));
55 } else if (Capability->SlotType == 0x02) {
56 DEBUG ((EFI_D_INFO, "%a\n", "Shared Bus Slot"));
57 } else {
58 DEBUG ((EFI_D_INFO, "%a\n", "Reserved"));
59 }
60 DEBUG ((EFI_D_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
61 DEBUG ((EFI_D_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
62 DEBUG ((EFI_D_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
63 DEBUG ((EFI_D_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
64 DEBUG ((EFI_D_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
65 DEBUG ((EFI_D_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
66 DEBUG ((EFI_D_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
67 if (Capability->TimerCount == 0) {
68 DEBUG ((EFI_D_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
69 } else {
70 DEBUG ((EFI_D_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
71 }
72 DEBUG ((EFI_D_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
73 DEBUG ((EFI_D_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
74 DEBUG ((EFI_D_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
75 DEBUG ((EFI_D_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
76 return;
77 }
78
79 /**
80 Read SlotInfo register from SD/MMC host controller pci config space.
81
82 @param[in] PciIo The PCI IO protocol instance.
83 @param[out] FirstBar The buffer to store the first BAR value.
84 @param[out] SlotNum The buffer to store the supported slot number.
85
86 @retval EFI_SUCCESS The operation succeeds.
87 @retval Others The operation fails.
88
89 **/
90 EFI_STATUS
91 EFIAPI
92 SdMmcHcGetSlotInfo (
93 IN EFI_PCI_IO_PROTOCOL *PciIo,
94 OUT UINT8 *FirstBar,
95 OUT UINT8 *SlotNum
96 )
97 {
98 EFI_STATUS Status;
99 SD_MMC_HC_SLOT_INFO SlotInfo;
100
101 Status = PciIo->Pci.Read (
102 PciIo,
103 EfiPciIoWidthUint8,
104 SD_MMC_HC_SLOT_OFFSET,
105 sizeof (SlotInfo),
106 &SlotInfo
107 );
108 if (EFI_ERROR (Status)) {
109 return Status;
110 }
111
112 *FirstBar = SlotInfo.FirstBar;
113 *SlotNum = SlotInfo.SlotNum + 1;
114 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
115 return EFI_SUCCESS;
116 }
117
118 /**
119 Read/Write specified SD/MMC host controller mmio register.
120
121 @param[in] PciIo The PCI IO protocol instance.
122 @param[in] BarIndex The BAR index of the standard PCI Configuration
123 header to use as the base address for the memory
124 operation to perform.
125 @param[in] Offset The offset within the selected BAR to start the
126 memory operation.
127 @param[in] Read A boolean to indicate it's read or write operation.
128 @param[in] Count The width of the mmio register in bytes.
129 Must be 1, 2 , 4 or 8 bytes.
130 @param[in, out] Data For read operations, the destination buffer to store
131 the results. For write operations, the source buffer
132 to write data from. The caller is responsible for
133 having ownership of the data buffer and ensuring its
134 size not less than Count bytes.
135
136 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
137 @retval EFI_SUCCESS The read/write operation succeeds.
138 @retval Others The read/write operation fails.
139
140 **/
141 EFI_STATUS
142 EFIAPI
143 SdMmcHcRwMmio (
144 IN EFI_PCI_IO_PROTOCOL *PciIo,
145 IN UINT8 BarIndex,
146 IN UINT32 Offset,
147 IN BOOLEAN Read,
148 IN UINT8 Count,
149 IN OUT VOID *Data
150 )
151 {
152 EFI_STATUS Status;
153
154 if ((PciIo == NULL) || (Data == NULL)) {
155 return EFI_INVALID_PARAMETER;
156 }
157
158 if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
159 return EFI_INVALID_PARAMETER;
160 }
161
162 if (Read) {
163 Status = PciIo->Mem.Read (
164 PciIo,
165 EfiPciIoWidthUint8,
166 BarIndex,
167 (UINT64) Offset,
168 Count,
169 Data
170 );
171 } else {
172 Status = PciIo->Mem.Write (
173 PciIo,
174 EfiPciIoWidthUint8,
175 BarIndex,
176 (UINT64) Offset,
177 Count,
178 Data
179 );
180 }
181
182 return Status;
183 }
184
185 /**
186 Do OR operation with the value of the specified SD/MMC host controller mmio register.
187
188 @param[in] PciIo The PCI IO protocol instance.
189 @param[in] BarIndex The BAR index of the standard PCI Configuration
190 header to use as the base address for the memory
191 operation to perform.
192 @param[in] Offset The offset within the selected BAR to start the
193 memory operation.
194 @param[in] Count The width of the mmio register in bytes.
195 Must be 1, 2 , 4 or 8 bytes.
196 @param[in] OrData The pointer to the data used to do OR operation.
197 The caller is responsible for having ownership of
198 the data buffer and ensuring its size not less than
199 Count bytes.
200
201 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
202 @retval EFI_SUCCESS The OR operation succeeds.
203 @retval Others The OR operation fails.
204
205 **/
206 EFI_STATUS
207 EFIAPI
208 SdMmcHcOrMmio (
209 IN EFI_PCI_IO_PROTOCOL *PciIo,
210 IN UINT8 BarIndex,
211 IN UINT32 Offset,
212 IN UINT8 Count,
213 IN VOID *OrData
214 )
215 {
216 EFI_STATUS Status;
217 UINT64 Data;
218 UINT64 Or;
219
220 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
221 if (EFI_ERROR (Status)) {
222 return Status;
223 }
224
225 if (Count == 1) {
226 Or = *(UINT8*) OrData;
227 } else if (Count == 2) {
228 Or = *(UINT16*) OrData;
229 } else if (Count == 4) {
230 Or = *(UINT32*) OrData;
231 } else if (Count == 8) {
232 Or = *(UINT64*) OrData;
233 } else {
234 return EFI_INVALID_PARAMETER;
235 }
236
237 Data |= Or;
238 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
239
240 return Status;
241 }
242
243 /**
244 Do AND operation with the value of the specified SD/MMC host controller mmio register.
245
246 @param[in] PciIo The PCI IO protocol instance.
247 @param[in] BarIndex The BAR index of the standard PCI Configuration
248 header to use as the base address for the memory
249 operation to perform.
250 @param[in] Offset The offset within the selected BAR to start the
251 memory operation.
252 @param[in] Count The width of the mmio register in bytes.
253 Must be 1, 2 , 4 or 8 bytes.
254 @param[in] AndData The pointer to the data used to do AND operation.
255 The caller is responsible for having ownership of
256 the data buffer and ensuring its size not less than
257 Count bytes.
258
259 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
260 @retval EFI_SUCCESS The AND operation succeeds.
261 @retval Others The AND operation fails.
262
263 **/
264 EFI_STATUS
265 EFIAPI
266 SdMmcHcAndMmio (
267 IN EFI_PCI_IO_PROTOCOL *PciIo,
268 IN UINT8 BarIndex,
269 IN UINT32 Offset,
270 IN UINT8 Count,
271 IN VOID *AndData
272 )
273 {
274 EFI_STATUS Status;
275 UINT64 Data;
276 UINT64 And;
277
278 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
279 if (EFI_ERROR (Status)) {
280 return Status;
281 }
282
283 if (Count == 1) {
284 And = *(UINT8*) AndData;
285 } else if (Count == 2) {
286 And = *(UINT16*) AndData;
287 } else if (Count == 4) {
288 And = *(UINT32*) AndData;
289 } else if (Count == 8) {
290 And = *(UINT64*) AndData;
291 } else {
292 return EFI_INVALID_PARAMETER;
293 }
294
295 Data &= And;
296 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
297
298 return Status;
299 }
300
301 /**
302 Wait for the value of the specified MMIO register set to the test value.
303
304 @param[in] PciIo The PCI IO protocol instance.
305 @param[in] BarIndex The BAR index of the standard PCI Configuration
306 header to use as the base address for the memory
307 operation to perform.
308 @param[in] Offset The offset within the selected BAR to start the
309 memory operation.
310 @param[in] Count The width of the mmio register in bytes.
311 Must be 1, 2, 4 or 8 bytes.
312 @param[in] MaskValue The mask value of memory.
313 @param[in] TestValue The test value of memory.
314
315 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
316 @retval EFI_SUCCESS The MMIO register has expected value.
317 @retval Others The MMIO operation fails.
318
319 **/
320 EFI_STATUS
321 EFIAPI
322 SdMmcHcCheckMmioSet (
323 IN EFI_PCI_IO_PROTOCOL *PciIo,
324 IN UINT8 BarIndex,
325 IN UINT32 Offset,
326 IN UINT8 Count,
327 IN UINT64 MaskValue,
328 IN UINT64 TestValue
329 )
330 {
331 EFI_STATUS Status;
332 UINT64 Value;
333
334 //
335 // Access PCI MMIO space to see if the value is the tested one.
336 //
337 Value = 0;
338 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
339 if (EFI_ERROR (Status)) {
340 return Status;
341 }
342
343 Value &= MaskValue;
344
345 if (Value == TestValue) {
346 return EFI_SUCCESS;
347 }
348
349 return EFI_NOT_READY;
350 }
351
352 /**
353 Wait for the value of the specified MMIO register set to the test value.
354
355 @param[in] PciIo The PCI IO protocol instance.
356 @param[in] BarIndex The BAR index of the standard PCI Configuration
357 header to use as the base address for the memory
358 operation to perform.
359 @param[in] Offset The offset within the selected BAR to start the
360 memory operation.
361 @param[in] Count The width of the mmio register in bytes.
362 Must be 1, 2, 4 or 8 bytes.
363 @param[in] MaskValue The mask value of memory.
364 @param[in] TestValue The test value of memory.
365 @param[in] Timeout The time out value for wait memory set, uses 1
366 microsecond as a unit.
367
368 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
369 range.
370 @retval EFI_SUCCESS The MMIO register has expected value.
371 @retval Others The MMIO operation fails.
372
373 **/
374 EFI_STATUS
375 EFIAPI
376 SdMmcHcWaitMmioSet (
377 IN EFI_PCI_IO_PROTOCOL *PciIo,
378 IN UINT8 BarIndex,
379 IN UINT32 Offset,
380 IN UINT8 Count,
381 IN UINT64 MaskValue,
382 IN UINT64 TestValue,
383 IN UINT64 Timeout
384 )
385 {
386 EFI_STATUS Status;
387 BOOLEAN InfiniteWait;
388
389 if (Timeout == 0) {
390 InfiniteWait = TRUE;
391 } else {
392 InfiniteWait = FALSE;
393 }
394
395 while (InfiniteWait || (Timeout > 0)) {
396 Status = SdMmcHcCheckMmioSet (
397 PciIo,
398 BarIndex,
399 Offset,
400 Count,
401 MaskValue,
402 TestValue
403 );
404 if (Status != EFI_NOT_READY) {
405 return Status;
406 }
407
408 //
409 // Stall for 1 microsecond.
410 //
411 gBS->Stall (1);
412
413 Timeout--;
414 }
415
416 return EFI_TIMEOUT;
417 }
418
419 /**
420 Software reset the specified SD/MMC host controller and enable all interrupts.
421
422 @param[in] PciIo The PCI IO protocol instance.
423 @param[in] Slot The slot number of the SD card to send the command to.
424
425 @retval EFI_SUCCESS The software reset executes successfully.
426 @retval Others The software reset fails.
427
428 **/
429 EFI_STATUS
430 SdMmcHcReset (
431 IN EFI_PCI_IO_PROTOCOL *PciIo,
432 IN UINT8 Slot
433 )
434 {
435 EFI_STATUS Status;
436 UINT8 SwReset;
437
438 SwReset = 0xFF;
439 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);
440
441 if (EFI_ERROR (Status)) {
442 DEBUG ((EFI_D_ERROR, "SdMmcHcReset: write full 1 fails: %r\n", Status));
443 return Status;
444 }
445
446 Status = SdMmcHcWaitMmioSet (
447 PciIo,
448 Slot,
449 SD_MMC_HC_SW_RST,
450 sizeof (SwReset),
451 0xFF,
452 0x00,
453 SD_MMC_HC_GENERIC_TIMEOUT
454 );
455 if (EFI_ERROR (Status)) {
456 DEBUG ((EFI_D_INFO, "SdMmcHcReset: reset done with %r\n", Status));
457 return Status;
458 }
459 //
460 // Enable all interrupt after reset all.
461 //
462 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
463
464 return Status;
465 }
466
467 /**
468 Set all interrupt status bits in Normal and Error Interrupt Status Enable
469 register.
470
471 @param[in] PciIo The PCI IO protocol instance.
472 @param[in] Slot The slot number of the SD card to send the command to.
473
474 @retval EFI_SUCCESS The operation executes successfully.
475 @retval Others The operation fails.
476
477 **/
478 EFI_STATUS
479 SdMmcHcEnableInterrupt (
480 IN EFI_PCI_IO_PROTOCOL *PciIo,
481 IN UINT8 Slot
482 )
483 {
484 EFI_STATUS Status;
485 UINT16 IntStatus;
486
487 //
488 // Enable all bits in Error Interrupt Status Enable Register
489 //
490 IntStatus = 0xFFFF;
491 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
492 if (EFI_ERROR (Status)) {
493 return Status;
494 }
495 //
496 // Enable all bits in Normal Interrupt Status Enable Register
497 //
498 IntStatus = 0xFFFF;
499 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
500
501 return Status;
502 }
503
504 /**
505 Get the capability data from the specified slot.
506
507 @param[in] PciIo The PCI IO protocol instance.
508 @param[in] Slot The slot number of the SD card to send the command to.
509 @param[out] Capability The buffer to store the capability data.
510
511 @retval EFI_SUCCESS The operation executes successfully.
512 @retval Others The operation fails.
513
514 **/
515 EFI_STATUS
516 SdMmcHcGetCapability (
517 IN EFI_PCI_IO_PROTOCOL *PciIo,
518 IN UINT8 Slot,
519 OUT SD_MMC_HC_SLOT_CAP *Capability
520 )
521 {
522 EFI_STATUS Status;
523 UINT64 Cap;
524
525 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
526 if (EFI_ERROR (Status)) {
527 return Status;
528 }
529
530 CopyMem (Capability, &Cap, sizeof (Cap));
531
532 return EFI_SUCCESS;
533 }
534
535 /**
536 Get the maximum current capability data from the specified slot.
537
538 @param[in] PciIo The PCI IO protocol instance.
539 @param[in] Slot The slot number of the SD card to send the command to.
540 @param[out] MaxCurrent The buffer to store the maximum current capability data.
541
542 @retval EFI_SUCCESS The operation executes successfully.
543 @retval Others The operation fails.
544
545 **/
546 EFI_STATUS
547 SdMmcHcGetMaxCurrent (
548 IN EFI_PCI_IO_PROTOCOL *PciIo,
549 IN UINT8 Slot,
550 OUT UINT64 *MaxCurrent
551 )
552 {
553 EFI_STATUS Status;
554
555 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
556
557 return Status;
558 }
559
560 /**
561 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
562 slot.
563
564 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
565
566 @param[in] PciIo The PCI IO protocol instance.
567 @param[in] Slot The slot number of the SD card to send the command to.
568 @param[out] MediaPresent The pointer to the media present boolean value.
569
570 @retval EFI_SUCCESS There is no media change happened.
571 @retval EFI_MEDIA_CHANGED There is media change happened.
572 @retval Others The detection fails.
573
574 **/
575 EFI_STATUS
576 SdMmcHcCardDetect (
577 IN EFI_PCI_IO_PROTOCOL *PciIo,
578 IN UINT8 Slot,
579 OUT BOOLEAN *MediaPresent
580 )
581 {
582 EFI_STATUS Status;
583 UINT16 Data;
584 UINT32 PresentState;
585
586 //
587 // Check Present State Register to see if there is a card presented.
588 //
589 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
590 if (EFI_ERROR (Status)) {
591 return Status;
592 }
593
594 if ((PresentState & BIT16) != 0) {
595 *MediaPresent = TRUE;
596 } else {
597 *MediaPresent = FALSE;
598 }
599
600 //
601 // Check Normal Interrupt Status Register
602 //
603 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
604 if (EFI_ERROR (Status)) {
605 return Status;
606 }
607
608 if ((Data & (BIT6 | BIT7)) != 0) {
609 //
610 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
611 //
612 Data &= BIT6 | BIT7;
613 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
614 if (EFI_ERROR (Status)) {
615 return Status;
616 }
617
618 return EFI_MEDIA_CHANGED;
619 }
620
621 return EFI_SUCCESS;
622 }
623
624 /**
625 Stop SD/MMC card clock.
626
627 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
628
629 @param[in] PciIo The PCI IO protocol instance.
630 @param[in] Slot The slot number of the SD card to send the command to.
631
632 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
633 @retval Others Fail to stop SD/MMC clock.
634
635 **/
636 EFI_STATUS
637 SdMmcHcStopClock (
638 IN EFI_PCI_IO_PROTOCOL *PciIo,
639 IN UINT8 Slot
640 )
641 {
642 EFI_STATUS Status;
643 UINT32 PresentState;
644 UINT16 ClockCtrl;
645
646 //
647 // Ensure no SD transactions are occurring on the SD Bus by
648 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
649 // in the Present State register to be 0.
650 //
651 Status = SdMmcHcWaitMmioSet (
652 PciIo,
653 Slot,
654 SD_MMC_HC_PRESENT_STATE,
655 sizeof (PresentState),
656 BIT0 | BIT1,
657 0,
658 SD_MMC_HC_GENERIC_TIMEOUT
659 );
660 if (EFI_ERROR (Status)) {
661 return Status;
662 }
663
664 //
665 // Set SD Clock Enable in the Clock Control register to 0
666 //
667 ClockCtrl = (UINT16)~BIT2;
668 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
669
670 return Status;
671 }
672
673 /**
674 SD/MMC card clock supply.
675
676 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
677
678 @param[in] PciIo The PCI IO protocol instance.
679 @param[in] Slot The slot number of the SD card to send the command to.
680 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
681 @param[in] Capability The capability of the slot.
682
683 @retval EFI_SUCCESS The clock is supplied successfully.
684 @retval Others The clock isn't supplied successfully.
685
686 **/
687 EFI_STATUS
688 SdMmcHcClockSupply (
689 IN EFI_PCI_IO_PROTOCOL *PciIo,
690 IN UINT8 Slot,
691 IN UINT64 ClockFreq,
692 IN SD_MMC_HC_SLOT_CAP Capability
693 )
694 {
695 EFI_STATUS Status;
696 UINT32 BaseClkFreq;
697 UINT32 SettingFreq;
698 UINT32 Divisor;
699 UINT32 Remainder;
700 UINT16 ControllerVer;
701 UINT16 ClockCtrl;
702
703 //
704 // Calculate a divisor for SD clock frequency
705 //
706 ASSERT (Capability.BaseClkFreq != 0);
707
708 BaseClkFreq = Capability.BaseClkFreq;
709 if ((ClockFreq > (BaseClkFreq * 1000)) || (ClockFreq == 0)) {
710 return EFI_INVALID_PARAMETER;
711 }
712 //
713 // Calculate the divisor of base frequency.
714 //
715 Divisor = 0;
716 SettingFreq = BaseClkFreq * 1000;
717 while (ClockFreq < SettingFreq) {
718 Divisor++;
719
720 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
721 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
722 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
723 break;
724 }
725 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
726 SettingFreq ++;
727 }
728 }
729
730 DEBUG ((EFI_D_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
731
732 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
733 if (EFI_ERROR (Status)) {
734 return Status;
735 }
736 //
737 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
738 //
739 if ((ControllerVer & 0xFF) == 2) {
740 ASSERT (Divisor <= 0x3FF);
741 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
742 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
743 //
744 // Only the most significant bit can be used as divisor.
745 //
746 if (((Divisor - 1) & Divisor) != 0) {
747 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
748 }
749 ASSERT (Divisor <= 0x80);
750 ClockCtrl = (Divisor & 0xFF) << 8;
751 } else {
752 DEBUG ((EFI_D_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
753 return EFI_UNSUPPORTED;
754 }
755
756 //
757 // Stop bus clock at first
758 //
759 Status = SdMmcHcStopClock (PciIo, Slot);
760 if (EFI_ERROR (Status)) {
761 return Status;
762 }
763
764 //
765 // Supply clock frequency with specified divisor
766 //
767 ClockCtrl |= BIT0;
768 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
769 if (EFI_ERROR (Status)) {
770 DEBUG ((EFI_D_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
771 return Status;
772 }
773
774 //
775 // Wait Internal Clock Stable in the Clock Control register to be 1
776 //
777 Status = SdMmcHcWaitMmioSet (
778 PciIo,
779 Slot,
780 SD_MMC_HC_CLOCK_CTRL,
781 sizeof (ClockCtrl),
782 BIT1,
783 BIT1,
784 SD_MMC_HC_GENERIC_TIMEOUT
785 );
786 if (EFI_ERROR (Status)) {
787 return Status;
788 }
789
790 //
791 // Set SD Clock Enable in the Clock Control register to 1
792 //
793 ClockCtrl = BIT2;
794 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
795
796 return Status;
797 }
798
799 /**
800 SD/MMC bus power control.
801
802 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
803
804 @param[in] PciIo The PCI IO protocol instance.
805 @param[in] Slot The slot number of the SD card to send the command to.
806 @param[in] PowerCtrl The value setting to the power control register.
807
808 @retval TRUE There is a SD/MMC card attached.
809 @retval FALSE There is no a SD/MMC card attached.
810
811 **/
812 EFI_STATUS
813 SdMmcHcPowerControl (
814 IN EFI_PCI_IO_PROTOCOL *PciIo,
815 IN UINT8 Slot,
816 IN UINT8 PowerCtrl
817 )
818 {
819 EFI_STATUS Status;
820
821 //
822 // Clr SD Bus Power
823 //
824 PowerCtrl &= (UINT8)~BIT0;
825 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
826 if (EFI_ERROR (Status)) {
827 return Status;
828 }
829
830 //
831 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
832 //
833 PowerCtrl |= BIT0;
834 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
835
836 return Status;
837 }
838
839 /**
840 Set the SD/MMC bus width.
841
842 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
843
844 @param[in] PciIo The PCI IO protocol instance.
845 @param[in] Slot The slot number of the SD card to send the command to.
846 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
847
848 @retval EFI_SUCCESS The bus width is set successfully.
849 @retval Others The bus width isn't set successfully.
850
851 **/
852 EFI_STATUS
853 SdMmcHcSetBusWidth (
854 IN EFI_PCI_IO_PROTOCOL *PciIo,
855 IN UINT8 Slot,
856 IN UINT16 BusWidth
857 )
858 {
859 EFI_STATUS Status;
860 UINT8 HostCtrl1;
861
862 if (BusWidth == 1) {
863 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
864 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
865 } else if (BusWidth == 4) {
866 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
867 if (EFI_ERROR (Status)) {
868 return Status;
869 }
870 HostCtrl1 |= BIT1;
871 HostCtrl1 &= (UINT8)~BIT5;
872 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
873 } else if (BusWidth == 8) {
874 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
875 if (EFI_ERROR (Status)) {
876 return Status;
877 }
878 HostCtrl1 &= (UINT8)~BIT1;
879 HostCtrl1 |= BIT5;
880 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
881 } else {
882 ASSERT (FALSE);
883 return EFI_INVALID_PARAMETER;
884 }
885
886 return Status;
887 }
888
889 /**
890 Supply SD/MMC card with lowest clock frequency at initialization.
891
892 @param[in] PciIo The PCI IO protocol instance.
893 @param[in] Slot The slot number of the SD card to send the command to.
894 @param[in] Capability The capability of the slot.
895
896 @retval EFI_SUCCESS The clock is supplied successfully.
897 @retval Others The clock isn't supplied successfully.
898
899 **/
900 EFI_STATUS
901 SdMmcHcInitClockFreq (
902 IN EFI_PCI_IO_PROTOCOL *PciIo,
903 IN UINT8 Slot,
904 IN SD_MMC_HC_SLOT_CAP Capability
905 )
906 {
907 EFI_STATUS Status;
908 UINT32 InitFreq;
909
910 //
911 // Calculate a divisor for SD clock frequency
912 //
913 if (Capability.BaseClkFreq == 0) {
914 //
915 // Don't support get Base Clock Frequency information via another method
916 //
917 return EFI_UNSUPPORTED;
918 }
919 //
920 // Supply 400KHz clock frequency at initialization phase.
921 //
922 InitFreq = 400;
923 Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability);
924 return Status;
925 }
926
927 /**
928 Supply SD/MMC card with maximum voltage at initialization.
929
930 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
931
932 @param[in] PciIo The PCI IO protocol instance.
933 @param[in] Slot The slot number of the SD card to send the command to.
934 @param[in] Capability The capability of the slot.
935
936 @retval EFI_SUCCESS The voltage is supplied successfully.
937 @retval Others The voltage isn't supplied successfully.
938
939 **/
940 EFI_STATUS
941 SdMmcHcInitPowerVoltage (
942 IN EFI_PCI_IO_PROTOCOL *PciIo,
943 IN UINT8 Slot,
944 IN SD_MMC_HC_SLOT_CAP Capability
945 )
946 {
947 EFI_STATUS Status;
948 UINT8 MaxVoltage;
949 UINT8 HostCtrl2;
950
951 //
952 // Calculate supported maximum voltage according to SD Bus Voltage Select
953 //
954 if (Capability.Voltage33 != 0) {
955 //
956 // Support 3.3V
957 //
958 MaxVoltage = 0x0E;
959 } else if (Capability.Voltage30 != 0) {
960 //
961 // Support 3.0V
962 //
963 MaxVoltage = 0x0C;
964 } else if (Capability.Voltage18 != 0) {
965 //
966 // Support 1.8V
967 //
968 MaxVoltage = 0x0A;
969 HostCtrl2 = BIT3;
970 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
971 gBS->Stall (5000);
972 if (EFI_ERROR (Status)) {
973 return Status;
974 }
975 } else {
976 ASSERT (FALSE);
977 return EFI_DEVICE_ERROR;
978 }
979
980 //
981 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
982 //
983 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
984
985 return Status;
986 }
987
988 /**
989 Initialize the Timeout Control register with most conservative value at initialization.
990
991 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
992
993 @param[in] PciIo The PCI IO protocol instance.
994 @param[in] Slot The slot number of the SD card to send the command to.
995
996 @retval EFI_SUCCESS The timeout control register is configured successfully.
997 @retval Others The timeout control register isn't configured successfully.
998
999 **/
1000 EFI_STATUS
1001 SdMmcHcInitTimeoutCtrl (
1002 IN EFI_PCI_IO_PROTOCOL *PciIo,
1003 IN UINT8 Slot
1004 )
1005 {
1006 EFI_STATUS Status;
1007 UINT8 Timeout;
1008
1009 Timeout = 0x0E;
1010 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1011
1012 return Status;
1013 }
1014
1015 /**
1016 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1017 at initialization.
1018
1019 @param[in] PciIo The PCI IO protocol instance.
1020 @param[in] Slot The slot number of the SD card to send the command to.
1021 @param[in] Capability The capability of the slot.
1022
1023 @retval EFI_SUCCESS The host controller is initialized successfully.
1024 @retval Others The host controller isn't initialized successfully.
1025
1026 **/
1027 EFI_STATUS
1028 SdMmcHcInitHost (
1029 IN EFI_PCI_IO_PROTOCOL *PciIo,
1030 IN UINT8 Slot,
1031 IN SD_MMC_HC_SLOT_CAP Capability
1032 )
1033 {
1034 EFI_STATUS Status;
1035
1036 Status = SdMmcHcInitClockFreq (PciIo, Slot, Capability);
1037 if (EFI_ERROR (Status)) {
1038 return Status;
1039 }
1040
1041 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1042 if (EFI_ERROR (Status)) {
1043 return Status;
1044 }
1045
1046 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1047 return Status;
1048 }
1049
1050 /**
1051 Turn on/off LED.
1052
1053 @param[in] PciIo The PCI IO protocol instance.
1054 @param[in] Slot The slot number of the SD card to send the command to.
1055 @param[in] On The boolean to turn on/off LED.
1056
1057 @retval EFI_SUCCESS The LED is turned on/off successfully.
1058 @retval Others The LED isn't turned on/off successfully.
1059
1060 **/
1061 EFI_STATUS
1062 SdMmcHcLedOnOff (
1063 IN EFI_PCI_IO_PROTOCOL *PciIo,
1064 IN UINT8 Slot,
1065 IN BOOLEAN On
1066 )
1067 {
1068 EFI_STATUS Status;
1069 UINT8 HostCtrl1;
1070
1071 if (On) {
1072 HostCtrl1 = BIT0;
1073 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1074 } else {
1075 HostCtrl1 = (UINT8)~BIT0;
1076 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1077 }
1078
1079 return Status;
1080 }
1081
1082 /**
1083 Build ADMA descriptor table for transfer.
1084
1085 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
1086
1087 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1088
1089 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1090 @retval Others The ADMA descriptor table isn't created successfully.
1091
1092 **/
1093 EFI_STATUS
1094 BuildAdmaDescTable (
1095 IN SD_MMC_HC_TRB *Trb
1096 )
1097 {
1098 EFI_PHYSICAL_ADDRESS Data;
1099 UINT64 DataLen;
1100 UINT64 Entries;
1101 UINT32 Index;
1102 UINT64 Remaining;
1103 UINT32 Address;
1104 UINTN TableSize;
1105 EFI_PCI_IO_PROTOCOL *PciIo;
1106 EFI_STATUS Status;
1107 UINTN Bytes;
1108
1109 Data = Trb->DataPhy;
1110 DataLen = Trb->DataLen;
1111 PciIo = Trb->Private->PciIo;
1112 //
1113 // Only support 32bit ADMA Descriptor Table
1114 //
1115 if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {
1116 return EFI_INVALID_PARAMETER;
1117 }
1118 //
1119 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1120 // for 32-bit address descriptor table.
1121 //
1122 if ((Data & (BIT0 | BIT1)) != 0) {
1123 DEBUG ((EFI_D_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1124 }
1125
1126 Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);
1127 TableSize = (UINTN)MultU64x32 (Entries, sizeof (SD_MMC_HC_ADMA_DESC_LINE));
1128 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1129 Status = PciIo->AllocateBuffer (
1130 PciIo,
1131 AllocateAnyPages,
1132 EfiBootServicesData,
1133 EFI_SIZE_TO_PAGES (TableSize),
1134 (VOID **)&Trb->AdmaDesc,
1135 0
1136 );
1137 if (EFI_ERROR (Status)) {
1138 return EFI_OUT_OF_RESOURCES;
1139 }
1140 ZeroMem (Trb->AdmaDesc, TableSize);
1141 Bytes = TableSize;
1142 Status = PciIo->Map (
1143 PciIo,
1144 EfiPciIoOperationBusMasterCommonBuffer,
1145 Trb->AdmaDesc,
1146 &Bytes,
1147 &Trb->AdmaDescPhy,
1148 &Trb->AdmaMap
1149 );
1150
1151 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1152 //
1153 // Map error or unable to map the whole RFis buffer into a contiguous region.
1154 //
1155 PciIo->FreeBuffer (
1156 PciIo,
1157 EFI_SIZE_TO_PAGES (TableSize),
1158 Trb->AdmaDesc
1159 );
1160 return EFI_OUT_OF_RESOURCES;
1161 }
1162
1163 if ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
1164 //
1165 // The ADMA doesn't support 64bit addressing.
1166 //
1167 PciIo->Unmap (
1168 PciIo,
1169 Trb->AdmaMap
1170 );
1171 PciIo->FreeBuffer (
1172 PciIo,
1173 EFI_SIZE_TO_PAGES (TableSize),
1174 Trb->AdmaDesc
1175 );
1176 return EFI_DEVICE_ERROR;
1177 }
1178
1179 Remaining = DataLen;
1180 Address = (UINT32)Data;
1181 for (Index = 0; Index < Entries; Index++) {
1182 if (Remaining <= ADMA_MAX_DATA_PER_LINE) {
1183 Trb->AdmaDesc[Index].Valid = 1;
1184 Trb->AdmaDesc[Index].Act = 2;
1185 Trb->AdmaDesc[Index].Length = (UINT16)Remaining;
1186 Trb->AdmaDesc[Index].Address = Address;
1187 break;
1188 } else {
1189 Trb->AdmaDesc[Index].Valid = 1;
1190 Trb->AdmaDesc[Index].Act = 2;
1191 Trb->AdmaDesc[Index].Length = 0;
1192 Trb->AdmaDesc[Index].Address = Address;
1193 }
1194
1195 Remaining -= ADMA_MAX_DATA_PER_LINE;
1196 Address += ADMA_MAX_DATA_PER_LINE;
1197 }
1198
1199 //
1200 // Set the last descriptor line as end of descriptor table
1201 //
1202 Trb->AdmaDesc[Index].End = 1;
1203 return EFI_SUCCESS;
1204 }
1205
1206 /**
1207 Create a new TRB for the SD/MMC cmd request.
1208
1209 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1210 @param[in] Slot The slot number of the SD card to send the command to.
1211 @param[in] Packet A pointer to the SD command data structure.
1212 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1213 not NULL, then nonblocking I/O is performed, and Event
1214 will be signaled when the Packet completes.
1215
1216 @return Created Trb or NULL.
1217
1218 **/
1219 SD_MMC_HC_TRB *
1220 SdMmcCreateTrb (
1221 IN SD_MMC_HC_PRIVATE_DATA *Private,
1222 IN UINT8 Slot,
1223 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1224 IN EFI_EVENT Event
1225 )
1226 {
1227 SD_MMC_HC_TRB *Trb;
1228 EFI_STATUS Status;
1229 EFI_TPL OldTpl;
1230 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1231 EFI_PCI_IO_PROTOCOL *PciIo;
1232 UINTN MapLength;
1233
1234 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1235 if (Trb == NULL) {
1236 return NULL;
1237 }
1238
1239 Trb->Signature = SD_MMC_HC_TRB_SIG;
1240 Trb->Slot = Slot;
1241 Trb->BlockSize = 0x200;
1242 Trb->Packet = Packet;
1243 Trb->Event = Event;
1244 Trb->Started = FALSE;
1245 Trb->Timeout = Packet->Timeout;
1246 Trb->Private = Private;
1247
1248 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1249 Trb->Data = Packet->InDataBuffer;
1250 Trb->DataLen = Packet->InTransferLength;
1251 Trb->Read = TRUE;
1252 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1253 Trb->Data = Packet->OutDataBuffer;
1254 Trb->DataLen = Packet->OutTransferLength;
1255 Trb->Read = FALSE;
1256 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1257 Trb->Data = NULL;
1258 Trb->DataLen = 0;
1259 } else {
1260 goto Error;
1261 }
1262
1263 if (Trb->Read) {
1264 Flag = EfiPciIoOperationBusMasterWrite;
1265 } else {
1266 Flag = EfiPciIoOperationBusMasterRead;
1267 }
1268
1269 PciIo = Private->PciIo;
1270 if (Trb->DataLen != 0) {
1271 MapLength = Trb->DataLen;
1272 Status = PciIo->Map (
1273 PciIo,
1274 Flag,
1275 Trb->Data,
1276 &MapLength,
1277 &Trb->DataPhy,
1278 &Trb->DataMap
1279 );
1280 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1281 Status = EFI_BAD_BUFFER_SIZE;
1282 goto Error;
1283 }
1284 }
1285
1286 if ((Trb->DataLen % Trb->BlockSize) != 0) {
1287 if (Trb->DataLen < Trb->BlockSize) {
1288 Trb->BlockSize = (UINT16)Trb->DataLen;
1289 }
1290 }
1291
1292 if (Trb->DataLen == 0) {
1293 Trb->Mode = SdMmcNoData;
1294 } else if (Private->Capability[Slot].Adma2 != 0) {
1295 Trb->Mode = SdMmcAdmaMode;
1296 Status = BuildAdmaDescTable (Trb);
1297 if (EFI_ERROR (Status)) {
1298 PciIo->Unmap (PciIo, Trb->DataMap);
1299 goto Error;
1300 }
1301 } else if (Private->Capability[Slot].Sdma != 0) {
1302 Trb->Mode = SdMmcSdmaMode;
1303 } else {
1304 Trb->Mode = SdMmcPioMode;
1305 }
1306
1307 if (Event != NULL) {
1308 OldTpl = gBS->RaiseTPL (TPL_CALLBACK);
1309 InsertTailList (&Private->Queue, &Trb->TrbList);
1310 gBS->RestoreTPL (OldTpl);
1311 }
1312
1313 return Trb;
1314
1315 Error:
1316 SdMmcFreeTrb (Trb);
1317 return NULL;
1318 }
1319
1320 /**
1321 Free the resource used by the TRB.
1322
1323 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1324
1325 **/
1326 VOID
1327 SdMmcFreeTrb (
1328 IN SD_MMC_HC_TRB *Trb
1329 )
1330 {
1331 EFI_PCI_IO_PROTOCOL *PciIo;
1332
1333 PciIo = Trb->Private->PciIo;
1334
1335 if (Trb->AdmaMap != NULL) {
1336 PciIo->Unmap (
1337 PciIo,
1338 Trb->AdmaMap
1339 );
1340 }
1341 if (Trb->AdmaDesc != NULL) {
1342 PciIo->FreeBuffer (
1343 PciIo,
1344 Trb->AdmaPages,
1345 Trb->AdmaDesc
1346 );
1347 }
1348 if (Trb->DataMap != NULL) {
1349 PciIo->Unmap (
1350 PciIo,
1351 Trb->DataMap
1352 );
1353 }
1354 FreePool (Trb);
1355 return;
1356 }
1357
1358 /**
1359 Check if the env is ready for execute specified TRB.
1360
1361 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1362 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1363
1364 @retval EFI_SUCCESS The env is ready for TRB execution.
1365 @retval EFI_NOT_READY The env is not ready for TRB execution.
1366 @retval Others Some erros happen.
1367
1368 **/
1369 EFI_STATUS
1370 SdMmcCheckTrbEnv (
1371 IN SD_MMC_HC_PRIVATE_DATA *Private,
1372 IN SD_MMC_HC_TRB *Trb
1373 )
1374 {
1375 EFI_STATUS Status;
1376 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1377 EFI_PCI_IO_PROTOCOL *PciIo;
1378 UINT32 PresentState;
1379
1380 Packet = Trb->Packet;
1381
1382 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
1383 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
1384 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
1385 //
1386 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1387 // the Present State register to be 0
1388 //
1389 PresentState = BIT0 | BIT1;
1390 //
1391 // For Send Tuning Block cmd, just wait for Command Inhibit (CMD) to be 0
1392 //
1393 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1394 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1395 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1396 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1397 PresentState = BIT0;
1398 }
1399 } else {
1400 //
1401 // Wait Command Inhibit (CMD) in the Present State register
1402 // to be 0
1403 //
1404 PresentState = BIT0;
1405 }
1406
1407 PciIo = Private->PciIo;
1408 Status = SdMmcHcCheckMmioSet (
1409 PciIo,
1410 Trb->Slot,
1411 SD_MMC_HC_PRESENT_STATE,
1412 sizeof (PresentState),
1413 PresentState,
1414 0
1415 );
1416
1417 return Status;
1418 }
1419
1420 /**
1421 Wait for the env to be ready for execute specified TRB.
1422
1423 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1424 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1425
1426 @retval EFI_SUCCESS The env is ready for TRB execution.
1427 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1428 @retval Others Some erros happen.
1429
1430 **/
1431 EFI_STATUS
1432 SdMmcWaitTrbEnv (
1433 IN SD_MMC_HC_PRIVATE_DATA *Private,
1434 IN SD_MMC_HC_TRB *Trb
1435 )
1436 {
1437 EFI_STATUS Status;
1438 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1439 UINT64 Timeout;
1440 BOOLEAN InfiniteWait;
1441
1442 //
1443 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1444 //
1445 Packet = Trb->Packet;
1446 Timeout = Packet->Timeout;
1447 if (Timeout == 0) {
1448 InfiniteWait = TRUE;
1449 } else {
1450 InfiniteWait = FALSE;
1451 }
1452
1453 while (InfiniteWait || (Timeout > 0)) {
1454 //
1455 // Check Trb execution result by reading Normal Interrupt Status register.
1456 //
1457 Status = SdMmcCheckTrbEnv (Private, Trb);
1458 if (Status != EFI_NOT_READY) {
1459 return Status;
1460 }
1461 //
1462 // Stall for 1 microsecond.
1463 //
1464 gBS->Stall (1);
1465
1466 Timeout--;
1467 }
1468
1469 return EFI_TIMEOUT;
1470 }
1471
1472 /**
1473 Execute the specified TRB.
1474
1475 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1476 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1477
1478 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1479 @retval Others Some erros happen when sending this request to the host controller.
1480
1481 **/
1482 EFI_STATUS
1483 SdMmcExecTrb (
1484 IN SD_MMC_HC_PRIVATE_DATA *Private,
1485 IN SD_MMC_HC_TRB *Trb
1486 )
1487 {
1488 EFI_STATUS Status;
1489 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1490 EFI_PCI_IO_PROTOCOL *PciIo;
1491 UINT16 Cmd;
1492 UINT16 IntStatus;
1493 UINT32 Argument;
1494 UINT16 BlkCount;
1495 UINT16 BlkSize;
1496 UINT16 TransMode;
1497 UINT8 HostCtrl1;
1498 UINT32 SdmaAddr;
1499 UINT64 AdmaAddr;
1500
1501 Packet = Trb->Packet;
1502 PciIo = Trb->Private->PciIo;
1503 //
1504 // Clear all bits in Error Interrupt Status Register
1505 //
1506 IntStatus = 0xFFFF;
1507 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1508 if (EFI_ERROR (Status)) {
1509 return Status;
1510 }
1511 //
1512 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1513 //
1514 IntStatus = 0xFF3F;
1515 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1516 if (EFI_ERROR (Status)) {
1517 return Status;
1518 }
1519 //
1520 // Set Host Control 1 register DMA Select field
1521 //
1522 if (Trb->Mode == SdMmcAdmaMode) {
1523 HostCtrl1 = BIT4;
1524 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1525 if (EFI_ERROR (Status)) {
1526 return Status;
1527 }
1528 }
1529
1530 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
1531
1532 if (Trb->Mode == SdMmcSdmaMode) {
1533 if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {
1534 return EFI_INVALID_PARAMETER;
1535 }
1536
1537 SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;
1538 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);
1539 if (EFI_ERROR (Status)) {
1540 return Status;
1541 }
1542 } else if (Trb->Mode == SdMmcAdmaMode) {
1543 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
1544 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
1545 if (EFI_ERROR (Status)) {
1546 return Status;
1547 }
1548 }
1549
1550 BlkSize = Trb->BlockSize;
1551 if (Trb->Mode == SdMmcSdmaMode) {
1552 //
1553 // Set SDMA boundary to be 512K bytes.
1554 //
1555 BlkSize |= 0x7000;
1556 }
1557
1558 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
1559 if (EFI_ERROR (Status)) {
1560 return Status;
1561 }
1562
1563 BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);
1564 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);
1565 if (EFI_ERROR (Status)) {
1566 return Status;
1567 }
1568
1569 Argument = Packet->SdMmcCmdBlk->CommandArgument;
1570 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
1571 if (EFI_ERROR (Status)) {
1572 return Status;
1573 }
1574
1575 TransMode = 0;
1576 if (Trb->Mode != SdMmcNoData) {
1577 if (Trb->Mode != SdMmcPioMode) {
1578 TransMode |= BIT0;
1579 }
1580 if (Trb->Read) {
1581 TransMode |= BIT4;
1582 }
1583 if (BlkCount != 0) {
1584 TransMode |= BIT5 | BIT1;
1585 }
1586 //
1587 // Only SD memory card needs to use AUTO CMD12 feature.
1588 //
1589 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
1590 if (BlkCount > 1) {
1591 TransMode |= BIT2;
1592 }
1593 }
1594 }
1595
1596 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
1597 if (EFI_ERROR (Status)) {
1598 return Status;
1599 }
1600
1601 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
1602 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
1603 Cmd |= BIT5;
1604 }
1605 //
1606 // Convert ResponseType to value
1607 //
1608 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
1609 switch (Packet->SdMmcCmdBlk->ResponseType) {
1610 case SdMmcResponseTypeR1:
1611 case SdMmcResponseTypeR5:
1612 case SdMmcResponseTypeR6:
1613 case SdMmcResponseTypeR7:
1614 Cmd |= (BIT1 | BIT3 | BIT4);
1615 break;
1616 case SdMmcResponseTypeR2:
1617 Cmd |= (BIT0 | BIT3);
1618 break;
1619 case SdMmcResponseTypeR3:
1620 case SdMmcResponseTypeR4:
1621 Cmd |= BIT1;
1622 break;
1623 case SdMmcResponseTypeR1b:
1624 case SdMmcResponseTypeR5b:
1625 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
1626 break;
1627 default:
1628 ASSERT (FALSE);
1629 break;
1630 }
1631 }
1632 //
1633 // Execute cmd
1634 //
1635 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
1636 return Status;
1637 }
1638
1639 /**
1640 Check the TRB execution result.
1641
1642 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1643 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1644
1645 @retval EFI_SUCCESS The TRB is executed successfully.
1646 @retval EFI_NOT_READY The TRB is not completed for execution.
1647 @retval Others Some erros happen when executing this request.
1648
1649 **/
1650 EFI_STATUS
1651 SdMmcCheckTrbResult (
1652 IN SD_MMC_HC_PRIVATE_DATA *Private,
1653 IN SD_MMC_HC_TRB *Trb
1654 )
1655 {
1656 EFI_STATUS Status;
1657 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1658 UINT16 IntStatus;
1659 UINT32 Response[4];
1660 UINT32 SdmaAddr;
1661 UINT8 Index;
1662 UINT8 SwReset;
1663
1664 SwReset = 0;
1665 Packet = Trb->Packet;
1666 //
1667 // Check Trb execution result by reading Normal Interrupt Status register.
1668 //
1669 Status = SdMmcHcRwMmio (
1670 Private->PciIo,
1671 Trb->Slot,
1672 SD_MMC_HC_NOR_INT_STS,
1673 TRUE,
1674 sizeof (IntStatus),
1675 &IntStatus
1676 );
1677 if (EFI_ERROR (Status)) {
1678 goto Done;
1679 }
1680 //
1681 // Check Transfer Complete bit is set or not.
1682 //
1683 if ((IntStatus & BIT1) == BIT1) {
1684 if ((IntStatus & BIT15) == BIT15) {
1685 //
1686 // Read Error Interrupt Status register to check if the error is
1687 // Data Timeout Error.
1688 // If yes, treat it as success as Transfer Complete has higher
1689 // priority than Data Timeout Error.
1690 //
1691 Status = SdMmcHcRwMmio (
1692 Private->PciIo,
1693 Trb->Slot,
1694 SD_MMC_HC_ERR_INT_STS,
1695 TRUE,
1696 sizeof (IntStatus),
1697 &IntStatus
1698 );
1699 if (!EFI_ERROR (Status)) {
1700 if ((IntStatus & BIT4) == BIT4) {
1701 Status = EFI_SUCCESS;
1702 } else {
1703 Status = EFI_DEVICE_ERROR;
1704 }
1705 }
1706 }
1707
1708 goto Done;
1709 }
1710 //
1711 // Check if there is a error happened during cmd execution.
1712 // If yes, then do error recovery procedure to follow SD Host Controller
1713 // Simplified Spec 3.0 section 3.10.1.
1714 //
1715 if ((IntStatus & BIT15) == BIT15) {
1716 Status = SdMmcHcRwMmio (
1717 Private->PciIo,
1718 Trb->Slot,
1719 SD_MMC_HC_ERR_INT_STS,
1720 TRUE,
1721 sizeof (IntStatus),
1722 &IntStatus
1723 );
1724 if (EFI_ERROR (Status)) {
1725 goto Done;
1726 }
1727 if ((IntStatus & 0x0F) != 0) {
1728 SwReset |= BIT1;
1729 }
1730 if ((IntStatus & 0xF0) != 0) {
1731 SwReset |= BIT2;
1732 }
1733
1734 Status = SdMmcHcRwMmio (
1735 Private->PciIo,
1736 Trb->Slot,
1737 SD_MMC_HC_SW_RST,
1738 FALSE,
1739 sizeof (SwReset),
1740 &SwReset
1741 );
1742 if (EFI_ERROR (Status)) {
1743 goto Done;
1744 }
1745 Status = SdMmcHcWaitMmioSet (
1746 Private->PciIo,
1747 Trb->Slot,
1748 SD_MMC_HC_SW_RST,
1749 sizeof (SwReset),
1750 0xFF,
1751 0,
1752 SD_MMC_HC_GENERIC_TIMEOUT
1753 );
1754 if (EFI_ERROR (Status)) {
1755 goto Done;
1756 }
1757
1758 Status = EFI_DEVICE_ERROR;
1759 goto Done;
1760 }
1761 //
1762 // Check if DMA interrupt is signalled for the SDMA transfer.
1763 //
1764 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
1765 //
1766 // Clear DMA interrupt bit.
1767 //
1768 IntStatus = BIT3;
1769 Status = SdMmcHcRwMmio (
1770 Private->PciIo,
1771 Trb->Slot,
1772 SD_MMC_HC_NOR_INT_STS,
1773 FALSE,
1774 sizeof (IntStatus),
1775 &IntStatus
1776 );
1777 if (EFI_ERROR (Status)) {
1778 goto Done;
1779 }
1780 //
1781 // Update SDMA Address register.
1782 //
1783 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
1784 Status = SdMmcHcRwMmio (
1785 Private->PciIo,
1786 Trb->Slot,
1787 SD_MMC_HC_SDMA_ADDR,
1788 FALSE,
1789 sizeof (UINT32),
1790 &SdmaAddr
1791 );
1792 if (EFI_ERROR (Status)) {
1793 goto Done;
1794 }
1795 Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;
1796 }
1797
1798 if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
1799 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
1800 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
1801 if ((IntStatus & BIT0) == BIT0) {
1802 Status = EFI_SUCCESS;
1803 goto Done;
1804 }
1805 }
1806
1807 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1808 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1809 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1810 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1811 //
1812 // While performing tuning procedure (Execute Tuning is set to 1),
1813 // Transfer Completeis not set to 1
1814 // Refer to SD Host Controller Simplified Specification 3.0 table 2-23 for details.
1815 //
1816 Status = EFI_SUCCESS;
1817 goto Done;
1818 }
1819
1820 Status = EFI_NOT_READY;
1821 Done:
1822 //
1823 // Get response data when the cmd is executed successfully.
1824 //
1825 if (!EFI_ERROR (Status)) {
1826 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
1827 for (Index = 0; Index < 4; Index++) {
1828 Status = SdMmcHcRwMmio (
1829 Private->PciIo,
1830 Trb->Slot,
1831 SD_MMC_HC_RESPONSE + Index * 4,
1832 TRUE,
1833 sizeof (UINT32),
1834 &Response[Index]
1835 );
1836 if (EFI_ERROR (Status)) {
1837 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
1838 return Status;
1839 }
1840 }
1841 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
1842 }
1843 }
1844
1845 if (Status != EFI_NOT_READY) {
1846 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
1847 }
1848
1849 return Status;
1850 }
1851
1852 /**
1853 Wait for the TRB execution result.
1854
1855 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1856 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1857
1858 @retval EFI_SUCCESS The TRB is executed successfully.
1859 @retval Others Some erros happen when executing this request.
1860
1861 **/
1862 EFI_STATUS
1863 SdMmcWaitTrbResult (
1864 IN SD_MMC_HC_PRIVATE_DATA *Private,
1865 IN SD_MMC_HC_TRB *Trb
1866 )
1867 {
1868 EFI_STATUS Status;
1869 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1870 UINT64 Timeout;
1871 BOOLEAN InfiniteWait;
1872
1873 Packet = Trb->Packet;
1874 //
1875 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1876 //
1877 Timeout = Packet->Timeout;
1878 if (Timeout == 0) {
1879 InfiniteWait = TRUE;
1880 } else {
1881 InfiniteWait = FALSE;
1882 }
1883
1884 while (InfiniteWait || (Timeout > 0)) {
1885 //
1886 // Check Trb execution result by reading Normal Interrupt Status register.
1887 //
1888 Status = SdMmcCheckTrbResult (Private, Trb);
1889 if (Status != EFI_NOT_READY) {
1890 return Status;
1891 }
1892 //
1893 // Stall for 1 microsecond.
1894 //
1895 gBS->Stall (1);
1896
1897 Timeout--;
1898 }
1899
1900 return EFI_TIMEOUT;
1901 }
1902
EFI Development Kit II mirror for PVE