]> git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
projects / mirror_edk2.git / blob
? search:


c3eec8bcd4910bab83731a8e029ac9f97807a888
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / SdMmcPciHcDxe / SdMmcPciHci.c
1 /** @file
2 This driver is used to manage SD/MMC PCI host controllers which are compliance
3 with SD Host Controller Simplified Specification version 3.00.
4
5 It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
6
7 Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #include "SdMmcPciHcDxe.h"
19
20 /**
21 Dump the content of SD/MMC host controller's Capability Register.
22
23 @param[in] Slot The slot number of the SD card to send the command to.
24 @param[in] Capability The buffer to store the capability data.
25
26 **/
27 VOID
28 DumpCapabilityReg (
29 IN UINT8 Slot,
30 IN SD_MMC_HC_SLOT_CAP *Capability
31 )
32 {
33 //
34 // Dump Capability Data
35 //
36 DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
37 DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
38 DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
39 DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
40 DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
41 DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
42 DEBUG ((DEBUG_INFO, " HighSpeed Support %a\n", Capability->HighSpeed ? "TRUE" : "FALSE"));
43 DEBUG ((DEBUG_INFO, " SDMA Support %a\n", Capability->Sdma ? "TRUE" : "FALSE"));
44 DEBUG ((DEBUG_INFO, " Suspend/Resume %a\n", Capability->SuspRes ? "TRUE" : "FALSE"));
45 DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE"));
46 DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE"));
47 DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE"));
48 DEBUG ((DEBUG_INFO, " 64-bit Sys Bus %a\n", Capability->SysBus64 ? "TRUE" : "FALSE"));
49 DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE"));
50 DEBUG ((DEBUG_INFO, " SlotType "));
51 if (Capability->SlotType == 0x00) {
52 DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot"));
53 } else if (Capability->SlotType == 0x01) {
54 DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot"));
55 } else if (Capability->SlotType == 0x02) {
56 DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot"));
57 } else {
58 DEBUG ((DEBUG_INFO, "%a\n", "Reserved"));
59 }
60 DEBUG ((DEBUG_INFO, " SDR50 Support %a\n", Capability->Sdr50 ? "TRUE" : "FALSE"));
61 DEBUG ((DEBUG_INFO, " SDR104 Support %a\n", Capability->Sdr104 ? "TRUE" : "FALSE"));
62 DEBUG ((DEBUG_INFO, " DDR50 Support %a\n", Capability->Ddr50 ? "TRUE" : "FALSE"));
63 DEBUG ((DEBUG_INFO, " Driver Type A %a\n", Capability->DriverTypeA ? "TRUE" : "FALSE"));
64 DEBUG ((DEBUG_INFO, " Driver Type C %a\n", Capability->DriverTypeC ? "TRUE" : "FALSE"));
65 DEBUG ((DEBUG_INFO, " Driver Type D %a\n", Capability->DriverTypeD ? "TRUE" : "FALSE"));
66 DEBUG ((DEBUG_INFO, " Driver Type 4 %a\n", Capability->DriverType4 ? "TRUE" : "FALSE"));
67 if (Capability->TimerCount == 0) {
68 DEBUG ((DEBUG_INFO, " Retuning TimerCnt Disabled\n", 2 * (Capability->TimerCount - 1)));
69 } else {
70 DEBUG ((DEBUG_INFO, " Retuning TimerCnt %dseconds\n", 2 * (Capability->TimerCount - 1)));
71 }
72 DEBUG ((DEBUG_INFO, " SDR50 Tuning %a\n", Capability->TuningSDR50 ? "TRUE" : "FALSE"));
73 DEBUG ((DEBUG_INFO, " Retuning Mode Mode %d\n", Capability->RetuningMod + 1));
74 DEBUG ((DEBUG_INFO, " Clock Multiplier M = %d\n", Capability->ClkMultiplier + 1));
75 DEBUG ((DEBUG_INFO, " HS 400 %a\n", Capability->Hs400 ? "TRUE" : "FALSE"));
76 return;
77 }
78
79 /**
80 Read SlotInfo register from SD/MMC host controller pci config space.
81
82 @param[in] PciIo The PCI IO protocol instance.
83 @param[out] FirstBar The buffer to store the first BAR value.
84 @param[out] SlotNum The buffer to store the supported slot number.
85
86 @retval EFI_SUCCESS The operation succeeds.
87 @retval Others The operation fails.
88
89 **/
90 EFI_STATUS
91 EFIAPI
92 SdMmcHcGetSlotInfo (
93 IN EFI_PCI_IO_PROTOCOL *PciIo,
94 OUT UINT8 *FirstBar,
95 OUT UINT8 *SlotNum
96 )
97 {
98 EFI_STATUS Status;
99 SD_MMC_HC_SLOT_INFO SlotInfo;
100
101 Status = PciIo->Pci.Read (
102 PciIo,
103 EfiPciIoWidthUint8,
104 SD_MMC_HC_SLOT_OFFSET,
105 sizeof (SlotInfo),
106 &SlotInfo
107 );
108 if (EFI_ERROR (Status)) {
109 return Status;
110 }
111
112 *FirstBar = SlotInfo.FirstBar;
113 *SlotNum = SlotInfo.SlotNum + 1;
114 ASSERT ((*FirstBar + *SlotNum) < SD_MMC_HC_MAX_SLOT);
115 return EFI_SUCCESS;
116 }
117
118 /**
119 Read/Write specified SD/MMC host controller mmio register.
120
121 @param[in] PciIo The PCI IO protocol instance.
122 @param[in] BarIndex The BAR index of the standard PCI Configuration
123 header to use as the base address for the memory
124 operation to perform.
125 @param[in] Offset The offset within the selected BAR to start the
126 memory operation.
127 @param[in] Read A boolean to indicate it's read or write operation.
128 @param[in] Count The width of the mmio register in bytes.
129 Must be 1, 2 , 4 or 8 bytes.
130 @param[in, out] Data For read operations, the destination buffer to store
131 the results. For write operations, the source buffer
132 to write data from. The caller is responsible for
133 having ownership of the data buffer and ensuring its
134 size not less than Count bytes.
135
136 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
137 @retval EFI_SUCCESS The read/write operation succeeds.
138 @retval Others The read/write operation fails.
139
140 **/
141 EFI_STATUS
142 EFIAPI
143 SdMmcHcRwMmio (
144 IN EFI_PCI_IO_PROTOCOL *PciIo,
145 IN UINT8 BarIndex,
146 IN UINT32 Offset,
147 IN BOOLEAN Read,
148 IN UINT8 Count,
149 IN OUT VOID *Data
150 )
151 {
152 EFI_STATUS Status;
153
154 if ((PciIo == NULL) || (Data == NULL)) {
155 return EFI_INVALID_PARAMETER;
156 }
157
158 if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
159 return EFI_INVALID_PARAMETER;
160 }
161
162 if (Read) {
163 Status = PciIo->Mem.Read (
164 PciIo,
165 EfiPciIoWidthUint8,
166 BarIndex,
167 (UINT64) Offset,
168 Count,
169 Data
170 );
171 } else {
172 Status = PciIo->Mem.Write (
173 PciIo,
174 EfiPciIoWidthUint8,
175 BarIndex,
176 (UINT64) Offset,
177 Count,
178 Data
179 );
180 }
181
182 return Status;
183 }
184
185 /**
186 Do OR operation with the value of the specified SD/MMC host controller mmio register.
187
188 @param[in] PciIo The PCI IO protocol instance.
189 @param[in] BarIndex The BAR index of the standard PCI Configuration
190 header to use as the base address for the memory
191 operation to perform.
192 @param[in] Offset The offset within the selected BAR to start the
193 memory operation.
194 @param[in] Count The width of the mmio register in bytes.
195 Must be 1, 2 , 4 or 8 bytes.
196 @param[in] OrData The pointer to the data used to do OR operation.
197 The caller is responsible for having ownership of
198 the data buffer and ensuring its size not less than
199 Count bytes.
200
201 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
202 @retval EFI_SUCCESS The OR operation succeeds.
203 @retval Others The OR operation fails.
204
205 **/
206 EFI_STATUS
207 EFIAPI
208 SdMmcHcOrMmio (
209 IN EFI_PCI_IO_PROTOCOL *PciIo,
210 IN UINT8 BarIndex,
211 IN UINT32 Offset,
212 IN UINT8 Count,
213 IN VOID *OrData
214 )
215 {
216 EFI_STATUS Status;
217 UINT64 Data;
218 UINT64 Or;
219
220 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
221 if (EFI_ERROR (Status)) {
222 return Status;
223 }
224
225 if (Count == 1) {
226 Or = *(UINT8*) OrData;
227 } else if (Count == 2) {
228 Or = *(UINT16*) OrData;
229 } else if (Count == 4) {
230 Or = *(UINT32*) OrData;
231 } else if (Count == 8) {
232 Or = *(UINT64*) OrData;
233 } else {
234 return EFI_INVALID_PARAMETER;
235 }
236
237 Data |= Or;
238 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
239
240 return Status;
241 }
242
243 /**
244 Do AND operation with the value of the specified SD/MMC host controller mmio register.
245
246 @param[in] PciIo The PCI IO protocol instance.
247 @param[in] BarIndex The BAR index of the standard PCI Configuration
248 header to use as the base address for the memory
249 operation to perform.
250 @param[in] Offset The offset within the selected BAR to start the
251 memory operation.
252 @param[in] Count The width of the mmio register in bytes.
253 Must be 1, 2 , 4 or 8 bytes.
254 @param[in] AndData The pointer to the data used to do AND operation.
255 The caller is responsible for having ownership of
256 the data buffer and ensuring its size not less than
257 Count bytes.
258
259 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
260 @retval EFI_SUCCESS The AND operation succeeds.
261 @retval Others The AND operation fails.
262
263 **/
264 EFI_STATUS
265 EFIAPI
266 SdMmcHcAndMmio (
267 IN EFI_PCI_IO_PROTOCOL *PciIo,
268 IN UINT8 BarIndex,
269 IN UINT32 Offset,
270 IN UINT8 Count,
271 IN VOID *AndData
272 )
273 {
274 EFI_STATUS Status;
275 UINT64 Data;
276 UINT64 And;
277
278 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Data);
279 if (EFI_ERROR (Status)) {
280 return Status;
281 }
282
283 if (Count == 1) {
284 And = *(UINT8*) AndData;
285 } else if (Count == 2) {
286 And = *(UINT16*) AndData;
287 } else if (Count == 4) {
288 And = *(UINT32*) AndData;
289 } else if (Count == 8) {
290 And = *(UINT64*) AndData;
291 } else {
292 return EFI_INVALID_PARAMETER;
293 }
294
295 Data &= And;
296 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, FALSE, Count, &Data);
297
298 return Status;
299 }
300
301 /**
302 Wait for the value of the specified MMIO register set to the test value.
303
304 @param[in] PciIo The PCI IO protocol instance.
305 @param[in] BarIndex The BAR index of the standard PCI Configuration
306 header to use as the base address for the memory
307 operation to perform.
308 @param[in] Offset The offset within the selected BAR to start the
309 memory operation.
310 @param[in] Count The width of the mmio register in bytes.
311 Must be 1, 2, 4 or 8 bytes.
312 @param[in] MaskValue The mask value of memory.
313 @param[in] TestValue The test value of memory.
314
315 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
316 @retval EFI_SUCCESS The MMIO register has expected value.
317 @retval Others The MMIO operation fails.
318
319 **/
320 EFI_STATUS
321 EFIAPI
322 SdMmcHcCheckMmioSet (
323 IN EFI_PCI_IO_PROTOCOL *PciIo,
324 IN UINT8 BarIndex,
325 IN UINT32 Offset,
326 IN UINT8 Count,
327 IN UINT64 MaskValue,
328 IN UINT64 TestValue
329 )
330 {
331 EFI_STATUS Status;
332 UINT64 Value;
333
334 //
335 // Access PCI MMIO space to see if the value is the tested one.
336 //
337 Value = 0;
338 Status = SdMmcHcRwMmio (PciIo, BarIndex, Offset, TRUE, Count, &Value);
339 if (EFI_ERROR (Status)) {
340 return Status;
341 }
342
343 Value &= MaskValue;
344
345 if (Value == TestValue) {
346 return EFI_SUCCESS;
347 }
348
349 return EFI_NOT_READY;
350 }
351
352 /**
353 Wait for the value of the specified MMIO register set to the test value.
354
355 @param[in] PciIo The PCI IO protocol instance.
356 @param[in] BarIndex The BAR index of the standard PCI Configuration
357 header to use as the base address for the memory
358 operation to perform.
359 @param[in] Offset The offset within the selected BAR to start the
360 memory operation.
361 @param[in] Count The width of the mmio register in bytes.
362 Must be 1, 2, 4 or 8 bytes.
363 @param[in] MaskValue The mask value of memory.
364 @param[in] TestValue The test value of memory.
365 @param[in] Timeout The time out value for wait memory set, uses 1
366 microsecond as a unit.
367
368 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
369 range.
370 @retval EFI_SUCCESS The MMIO register has expected value.
371 @retval Others The MMIO operation fails.
372
373 **/
374 EFI_STATUS
375 EFIAPI
376 SdMmcHcWaitMmioSet (
377 IN EFI_PCI_IO_PROTOCOL *PciIo,
378 IN UINT8 BarIndex,
379 IN UINT32 Offset,
380 IN UINT8 Count,
381 IN UINT64 MaskValue,
382 IN UINT64 TestValue,
383 IN UINT64 Timeout
384 )
385 {
386 EFI_STATUS Status;
387 BOOLEAN InfiniteWait;
388
389 if (Timeout == 0) {
390 InfiniteWait = TRUE;
391 } else {
392 InfiniteWait = FALSE;
393 }
394
395 while (InfiniteWait || (Timeout > 0)) {
396 Status = SdMmcHcCheckMmioSet (
397 PciIo,
398 BarIndex,
399 Offset,
400 Count,
401 MaskValue,
402 TestValue
403 );
404 if (Status != EFI_NOT_READY) {
405 return Status;
406 }
407
408 //
409 // Stall for 1 microsecond.
410 //
411 gBS->Stall (1);
412
413 Timeout--;
414 }
415
416 return EFI_TIMEOUT;
417 }
418
419 /**
420 Software reset the specified SD/MMC host controller and enable all interrupts.
421
422 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
423 @param[in] Slot The slot number of the SD card to send the command to.
424
425 @retval EFI_SUCCESS The software reset executes successfully.
426 @retval Others The software reset fails.
427
428 **/
429 EFI_STATUS
430 SdMmcHcReset (
431 IN SD_MMC_HC_PRIVATE_DATA *Private,
432 IN UINT8 Slot
433 )
434 {
435 EFI_STATUS Status;
436 UINT8 SwReset;
437 EFI_PCI_IO_PROTOCOL *PciIo;
438
439 //
440 // Notify the SD/MMC override protocol that we are about to reset
441 // the SD/MMC host controller.
442 //
443 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
444 Status = mOverride->NotifyPhase (
445 Private->ControllerHandle,
446 Slot,
447 EdkiiSdMmcResetPre,
448 NULL);
449 if (EFI_ERROR (Status)) {
450 DEBUG ((DEBUG_WARN,
451 "%a: SD/MMC pre reset notifier callback failed - %r\n",
452 __FUNCTION__, Status));
453 return Status;
454 }
455 }
456
457 PciIo = Private->PciIo;
458 SwReset = BIT0;
459 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_SW_RST, sizeof (SwReset), &SwReset);
460
461 if (EFI_ERROR (Status)) {
462 DEBUG ((DEBUG_ERROR, "SdMmcHcReset: write SW Reset for All fails: %r\n", Status));
463 return Status;
464 }
465
466 Status = SdMmcHcWaitMmioSet (
467 PciIo,
468 Slot,
469 SD_MMC_HC_SW_RST,
470 sizeof (SwReset),
471 BIT0,
472 0x00,
473 SD_MMC_HC_GENERIC_TIMEOUT
474 );
475 if (EFI_ERROR (Status)) {
476 DEBUG ((DEBUG_INFO, "SdMmcHcReset: reset done with %r\n", Status));
477 return Status;
478 }
479
480 //
481 // Enable all interrupt after reset all.
482 //
483 Status = SdMmcHcEnableInterrupt (PciIo, Slot);
484 if (EFI_ERROR (Status)) {
485 DEBUG ((DEBUG_INFO, "SdMmcHcReset: SdMmcHcEnableInterrupt done with %r\n",
486 Status));
487 return Status;
488 }
489
490 //
491 // Notify the SD/MMC override protocol that we have just reset
492 // the SD/MMC host controller.
493 //
494 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
495 Status = mOverride->NotifyPhase (
496 Private->ControllerHandle,
497 Slot,
498 EdkiiSdMmcResetPost,
499 NULL);
500 if (EFI_ERROR (Status)) {
501 DEBUG ((DEBUG_WARN,
502 "%a: SD/MMC post reset notifier callback failed - %r\n",
503 __FUNCTION__, Status));
504 }
505 }
506
507 return Status;
508 }
509
510 /**
511 Set all interrupt status bits in Normal and Error Interrupt Status Enable
512 register.
513
514 @param[in] PciIo The PCI IO protocol instance.
515 @param[in] Slot The slot number of the SD card to send the command to.
516
517 @retval EFI_SUCCESS The operation executes successfully.
518 @retval Others The operation fails.
519
520 **/
521 EFI_STATUS
522 SdMmcHcEnableInterrupt (
523 IN EFI_PCI_IO_PROTOCOL *PciIo,
524 IN UINT8 Slot
525 )
526 {
527 EFI_STATUS Status;
528 UINT16 IntStatus;
529
530 //
531 // Enable all bits in Error Interrupt Status Enable Register
532 //
533 IntStatus = 0xFFFF;
534 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
535 if (EFI_ERROR (Status)) {
536 return Status;
537 }
538 //
539 // Enable all bits in Normal Interrupt Status Enable Register
540 //
541 IntStatus = 0xFFFF;
542 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
543
544 return Status;
545 }
546
547 /**
548 Get the capability data from the specified slot.
549
550 @param[in] PciIo The PCI IO protocol instance.
551 @param[in] Slot The slot number of the SD card to send the command to.
552 @param[out] Capability The buffer to store the capability data.
553
554 @retval EFI_SUCCESS The operation executes successfully.
555 @retval Others The operation fails.
556
557 **/
558 EFI_STATUS
559 SdMmcHcGetCapability (
560 IN EFI_PCI_IO_PROTOCOL *PciIo,
561 IN UINT8 Slot,
562 OUT SD_MMC_HC_SLOT_CAP *Capability
563 )
564 {
565 EFI_STATUS Status;
566 UINT64 Cap;
567
568 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CAP, TRUE, sizeof (Cap), &Cap);
569 if (EFI_ERROR (Status)) {
570 return Status;
571 }
572
573 CopyMem (Capability, &Cap, sizeof (Cap));
574
575 return EFI_SUCCESS;
576 }
577
578 /**
579 Get the maximum current capability data from the specified slot.
580
581 @param[in] PciIo The PCI IO protocol instance.
582 @param[in] Slot The slot number of the SD card to send the command to.
583 @param[out] MaxCurrent The buffer to store the maximum current capability data.
584
585 @retval EFI_SUCCESS The operation executes successfully.
586 @retval Others The operation fails.
587
588 **/
589 EFI_STATUS
590 SdMmcHcGetMaxCurrent (
591 IN EFI_PCI_IO_PROTOCOL *PciIo,
592 IN UINT8 Slot,
593 OUT UINT64 *MaxCurrent
594 )
595 {
596 EFI_STATUS Status;
597
598 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_MAX_CURRENT_CAP, TRUE, sizeof (UINT64), MaxCurrent);
599
600 return Status;
601 }
602
603 /**
604 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
605 slot.
606
607 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
608
609 @param[in] PciIo The PCI IO protocol instance.
610 @param[in] Slot The slot number of the SD card to send the command to.
611 @param[out] MediaPresent The pointer to the media present boolean value.
612
613 @retval EFI_SUCCESS There is no media change happened.
614 @retval EFI_MEDIA_CHANGED There is media change happened.
615 @retval Others The detection fails.
616
617 **/
618 EFI_STATUS
619 SdMmcHcCardDetect (
620 IN EFI_PCI_IO_PROTOCOL *PciIo,
621 IN UINT8 Slot,
622 OUT BOOLEAN *MediaPresent
623 )
624 {
625 EFI_STATUS Status;
626 UINT16 Data;
627 UINT32 PresentState;
628
629 //
630 // Check Present State Register to see if there is a card presented.
631 //
632 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
633 if (EFI_ERROR (Status)) {
634 return Status;
635 }
636
637 if ((PresentState & BIT16) != 0) {
638 *MediaPresent = TRUE;
639 } else {
640 *MediaPresent = FALSE;
641 }
642
643 //
644 // Check Normal Interrupt Status Register
645 //
646 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
647 if (EFI_ERROR (Status)) {
648 return Status;
649 }
650
651 if ((Data & (BIT6 | BIT7)) != 0) {
652 //
653 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
654 //
655 Data &= BIT6 | BIT7;
656 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
657 if (EFI_ERROR (Status)) {
658 return Status;
659 }
660
661 return EFI_MEDIA_CHANGED;
662 }
663
664 return EFI_SUCCESS;
665 }
666
667 /**
668 Stop SD/MMC card clock.
669
670 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
671
672 @param[in] PciIo The PCI IO protocol instance.
673 @param[in] Slot The slot number of the SD card to send the command to.
674
675 @retval EFI_SUCCESS Succeed to stop SD/MMC clock.
676 @retval Others Fail to stop SD/MMC clock.
677
678 **/
679 EFI_STATUS
680 SdMmcHcStopClock (
681 IN EFI_PCI_IO_PROTOCOL *PciIo,
682 IN UINT8 Slot
683 )
684 {
685 EFI_STATUS Status;
686 UINT32 PresentState;
687 UINT16 ClockCtrl;
688
689 //
690 // Ensure no SD transactions are occurring on the SD Bus by
691 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
692 // in the Present State register to be 0.
693 //
694 Status = SdMmcHcWaitMmioSet (
695 PciIo,
696 Slot,
697 SD_MMC_HC_PRESENT_STATE,
698 sizeof (PresentState),
699 BIT0 | BIT1,
700 0,
701 SD_MMC_HC_GENERIC_TIMEOUT
702 );
703 if (EFI_ERROR (Status)) {
704 return Status;
705 }
706
707 //
708 // Set SD Clock Enable in the Clock Control register to 0
709 //
710 ClockCtrl = (UINT16)~BIT2;
711 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
712
713 return Status;
714 }
715
716 /**
717 SD/MMC card clock supply.
718
719 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
720
721 @param[in] PciIo The PCI IO protocol instance.
722 @param[in] Slot The slot number of the SD card to send the command to.
723 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
724 @param[in] Capability The capability of the slot.
725
726 @retval EFI_SUCCESS The clock is supplied successfully.
727 @retval Others The clock isn't supplied successfully.
728
729 **/
730 EFI_STATUS
731 SdMmcHcClockSupply (
732 IN EFI_PCI_IO_PROTOCOL *PciIo,
733 IN UINT8 Slot,
734 IN UINT64 ClockFreq,
735 IN SD_MMC_HC_SLOT_CAP Capability
736 )
737 {
738 EFI_STATUS Status;
739 UINT32 BaseClkFreq;
740 UINT32 SettingFreq;
741 UINT32 Divisor;
742 UINT32 Remainder;
743 UINT16 ControllerVer;
744 UINT16 ClockCtrl;
745
746 //
747 // Calculate a divisor for SD clock frequency
748 //
749 ASSERT (Capability.BaseClkFreq != 0);
750
751 BaseClkFreq = Capability.BaseClkFreq;
752 if (ClockFreq == 0) {
753 return EFI_INVALID_PARAMETER;
754 }
755
756 if (ClockFreq > (BaseClkFreq * 1000)) {
757 ClockFreq = BaseClkFreq * 1000;
758 }
759
760 //
761 // Calculate the divisor of base frequency.
762 //
763 Divisor = 0;
764 SettingFreq = BaseClkFreq * 1000;
765 while (ClockFreq < SettingFreq) {
766 Divisor++;
767
768 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
769 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
770 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
771 break;
772 }
773 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
774 SettingFreq ++;
775 }
776 }
777
778 DEBUG ((DEBUG_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
779
780 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
781 if (EFI_ERROR (Status)) {
782 return Status;
783 }
784 //
785 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
786 //
787 if (((ControllerVer & 0xFF) >= SD_MMC_HC_CTRL_VER_300) &&
788 ((ControllerVer & 0xFF) <= SD_MMC_HC_CTRL_VER_420)) {
789 ASSERT (Divisor <= 0x3FF);
790 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
791 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
792 //
793 // Only the most significant bit can be used as divisor.
794 //
795 if (((Divisor - 1) & Divisor) != 0) {
796 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
797 }
798 ASSERT (Divisor <= 0x80);
799 ClockCtrl = (Divisor & 0xFF) << 8;
800 } else {
801 DEBUG ((DEBUG_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
802 return EFI_UNSUPPORTED;
803 }
804
805 //
806 // Stop bus clock at first
807 //
808 Status = SdMmcHcStopClock (PciIo, Slot);
809 if (EFI_ERROR (Status)) {
810 return Status;
811 }
812
813 //
814 // Supply clock frequency with specified divisor
815 //
816 ClockCtrl |= BIT0;
817 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
818 if (EFI_ERROR (Status)) {
819 DEBUG ((DEBUG_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
820 return Status;
821 }
822
823 //
824 // Wait Internal Clock Stable in the Clock Control register to be 1
825 //
826 Status = SdMmcHcWaitMmioSet (
827 PciIo,
828 Slot,
829 SD_MMC_HC_CLOCK_CTRL,
830 sizeof (ClockCtrl),
831 BIT1,
832 BIT1,
833 SD_MMC_HC_GENERIC_TIMEOUT
834 );
835 if (EFI_ERROR (Status)) {
836 return Status;
837 }
838
839 //
840 // Set SD Clock Enable in the Clock Control register to 1
841 //
842 ClockCtrl = BIT2;
843 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
844
845 return Status;
846 }
847
848 /**
849 SD/MMC bus power control.
850
851 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
852
853 @param[in] PciIo The PCI IO protocol instance.
854 @param[in] Slot The slot number of the SD card to send the command to.
855 @param[in] PowerCtrl The value setting to the power control register.
856
857 @retval TRUE There is a SD/MMC card attached.
858 @retval FALSE There is no a SD/MMC card attached.
859
860 **/
861 EFI_STATUS
862 SdMmcHcPowerControl (
863 IN EFI_PCI_IO_PROTOCOL *PciIo,
864 IN UINT8 Slot,
865 IN UINT8 PowerCtrl
866 )
867 {
868 EFI_STATUS Status;
869
870 //
871 // Clr SD Bus Power
872 //
873 PowerCtrl &= (UINT8)~BIT0;
874 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
875 if (EFI_ERROR (Status)) {
876 return Status;
877 }
878
879 //
880 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
881 //
882 PowerCtrl |= BIT0;
883 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
884
885 return Status;
886 }
887
888 /**
889 Set the SD/MMC bus width.
890
891 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
892
893 @param[in] PciIo The PCI IO protocol instance.
894 @param[in] Slot The slot number of the SD card to send the command to.
895 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8.
896
897 @retval EFI_SUCCESS The bus width is set successfully.
898 @retval Others The bus width isn't set successfully.
899
900 **/
901 EFI_STATUS
902 SdMmcHcSetBusWidth (
903 IN EFI_PCI_IO_PROTOCOL *PciIo,
904 IN UINT8 Slot,
905 IN UINT16 BusWidth
906 )
907 {
908 EFI_STATUS Status;
909 UINT8 HostCtrl1;
910
911 if (BusWidth == 1) {
912 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
913 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
914 } else if (BusWidth == 4) {
915 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
916 if (EFI_ERROR (Status)) {
917 return Status;
918 }
919 HostCtrl1 |= BIT1;
920 HostCtrl1 &= (UINT8)~BIT5;
921 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
922 } else if (BusWidth == 8) {
923 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
924 if (EFI_ERROR (Status)) {
925 return Status;
926 }
927 HostCtrl1 &= (UINT8)~BIT1;
928 HostCtrl1 |= BIT5;
929 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
930 } else {
931 ASSERT (FALSE);
932 return EFI_INVALID_PARAMETER;
933 }
934
935 return Status;
936 }
937
938 /**
939 Supply SD/MMC card with lowest clock frequency at initialization.
940
941 @param[in] PciIo The PCI IO protocol instance.
942 @param[in] Slot The slot number of the SD card to send the command to.
943 @param[in] Capability The capability of the slot.
944
945 @retval EFI_SUCCESS The clock is supplied successfully.
946 @retval Others The clock isn't supplied successfully.
947
948 **/
949 EFI_STATUS
950 SdMmcHcInitClockFreq (
951 IN EFI_PCI_IO_PROTOCOL *PciIo,
952 IN UINT8 Slot,
953 IN SD_MMC_HC_SLOT_CAP Capability
954 )
955 {
956 EFI_STATUS Status;
957 UINT32 InitFreq;
958
959 //
960 // Calculate a divisor for SD clock frequency
961 //
962 if (Capability.BaseClkFreq == 0) {
963 //
964 // Don't support get Base Clock Frequency information via another method
965 //
966 return EFI_UNSUPPORTED;
967 }
968 //
969 // Supply 400KHz clock frequency at initialization phase.
970 //
971 InitFreq = 400;
972 Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability);
973 return Status;
974 }
975
976 /**
977 Supply SD/MMC card with maximum voltage at initialization.
978
979 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
980
981 @param[in] PciIo The PCI IO protocol instance.
982 @param[in] Slot The slot number of the SD card to send the command to.
983 @param[in] Capability The capability of the slot.
984
985 @retval EFI_SUCCESS The voltage is supplied successfully.
986 @retval Others The voltage isn't supplied successfully.
987
988 **/
989 EFI_STATUS
990 SdMmcHcInitPowerVoltage (
991 IN EFI_PCI_IO_PROTOCOL *PciIo,
992 IN UINT8 Slot,
993 IN SD_MMC_HC_SLOT_CAP Capability
994 )
995 {
996 EFI_STATUS Status;
997 UINT8 MaxVoltage;
998 UINT8 HostCtrl2;
999
1000 //
1001 // Calculate supported maximum voltage according to SD Bus Voltage Select
1002 //
1003 if (Capability.Voltage33 != 0) {
1004 //
1005 // Support 3.3V
1006 //
1007 MaxVoltage = 0x0E;
1008 } else if (Capability.Voltage30 != 0) {
1009 //
1010 // Support 3.0V
1011 //
1012 MaxVoltage = 0x0C;
1013 } else if (Capability.Voltage18 != 0) {
1014 //
1015 // Support 1.8V
1016 //
1017 MaxVoltage = 0x0A;
1018 HostCtrl2 = BIT3;
1019 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1020 gBS->Stall (5000);
1021 if (EFI_ERROR (Status)) {
1022 return Status;
1023 }
1024 } else {
1025 ASSERT (FALSE);
1026 return EFI_DEVICE_ERROR;
1027 }
1028
1029 //
1030 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
1031 //
1032 Status = SdMmcHcPowerControl (PciIo, Slot, MaxVoltage);
1033
1034 return Status;
1035 }
1036
1037 /**
1038 Initialize the Timeout Control register with most conservative value at initialization.
1039
1040 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
1041
1042 @param[in] PciIo The PCI IO protocol instance.
1043 @param[in] Slot The slot number of the SD card to send the command to.
1044
1045 @retval EFI_SUCCESS The timeout control register is configured successfully.
1046 @retval Others The timeout control register isn't configured successfully.
1047
1048 **/
1049 EFI_STATUS
1050 SdMmcHcInitTimeoutCtrl (
1051 IN EFI_PCI_IO_PROTOCOL *PciIo,
1052 IN UINT8 Slot
1053 )
1054 {
1055 EFI_STATUS Status;
1056 UINT8 Timeout;
1057
1058 Timeout = 0x0E;
1059 Status = SdMmcHcRwMmio (PciIo, Slot, SD_MMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
1060
1061 return Status;
1062 }
1063
1064 /**
1065 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value
1066 at initialization.
1067
1068 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1069 @param[in] Slot The slot number of the SD card to send the command to.
1070
1071 @retval EFI_SUCCESS The host controller is initialized successfully.
1072 @retval Others The host controller isn't initialized successfully.
1073
1074 **/
1075 EFI_STATUS
1076 SdMmcHcInitHost (
1077 IN SD_MMC_HC_PRIVATE_DATA *Private,
1078 IN UINT8 Slot
1079 )
1080 {
1081 EFI_STATUS Status;
1082 EFI_PCI_IO_PROTOCOL *PciIo;
1083 SD_MMC_HC_SLOT_CAP Capability;
1084
1085 //
1086 // Notify the SD/MMC override protocol that we are about to initialize
1087 // the SD/MMC host controller.
1088 //
1089 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1090 Status = mOverride->NotifyPhase (
1091 Private->ControllerHandle,
1092 Slot,
1093 EdkiiSdMmcInitHostPre,
1094 NULL);
1095 if (EFI_ERROR (Status)) {
1096 DEBUG ((DEBUG_WARN,
1097 "%a: SD/MMC pre init notifier callback failed - %r\n",
1098 __FUNCTION__, Status));
1099 return Status;
1100 }
1101 }
1102
1103 PciIo = Private->PciIo;
1104 Capability = Private->Capability[Slot];
1105
1106 Status = SdMmcHcInitClockFreq (PciIo, Slot, Capability);
1107 if (EFI_ERROR (Status)) {
1108 return Status;
1109 }
1110
1111 Status = SdMmcHcInitPowerVoltage (PciIo, Slot, Capability);
1112 if (EFI_ERROR (Status)) {
1113 return Status;
1114 }
1115
1116 Status = SdMmcHcInitTimeoutCtrl (PciIo, Slot);
1117 if (EFI_ERROR (Status)) {
1118 return Status;
1119 }
1120
1121 //
1122 // Notify the SD/MMC override protocol that we are have just initialized
1123 // the SD/MMC host controller.
1124 //
1125 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1126 Status = mOverride->NotifyPhase (
1127 Private->ControllerHandle,
1128 Slot,
1129 EdkiiSdMmcInitHostPost,
1130 NULL);
1131 if (EFI_ERROR (Status)) {
1132 DEBUG ((DEBUG_WARN,
1133 "%a: SD/MMC post init notifier callback failed - %r\n",
1134 __FUNCTION__, Status));
1135 }
1136 }
1137 return Status;
1138 }
1139
1140 /**
1141 Set SD Host Controler control 2 registry according to selected speed.
1142
1143 @param[in] ControllerHandle The handle of the controller.
1144 @param[in] PciIo The PCI IO protocol instance.
1145 @param[in] Slot The slot number of the SD card to send the command to.
1146 @param[in] Timing The timing to select.
1147
1148 @retval EFI_SUCCESS The timing is set successfully.
1149 @retval Others The timing isn't set successfully.
1150 **/
1151 EFI_STATUS
1152 SdMmcHcUhsSignaling (
1153 IN EFI_HANDLE ControllerHandle,
1154 IN EFI_PCI_IO_PROTOCOL *PciIo,
1155 IN UINT8 Slot,
1156 IN SD_MMC_BUS_MODE Timing
1157 )
1158 {
1159 EFI_STATUS Status;
1160 UINT8 HostCtrl2;
1161
1162 HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
1163 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1164 if (EFI_ERROR (Status)) {
1165 return Status;
1166 }
1167
1168 switch (Timing) {
1169 case SdMmcUhsSdr12:
1170 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
1171 break;
1172 case SdMmcUhsSdr25:
1173 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
1174 break;
1175 case SdMmcUhsSdr50:
1176 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
1177 break;
1178 case SdMmcUhsSdr104:
1179 HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
1180 break;
1181 case SdMmcUhsDdr50:
1182 HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
1183 break;
1184 case SdMmcMmcLegacy:
1185 HostCtrl2 = SD_MMC_HC_CTRL_MMC_LEGACY;
1186 break;
1187 case SdMmcMmcHsSdr:
1188 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_SDR;
1189 break;
1190 case SdMmcMmcHsDdr:
1191 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS_DDR;
1192 break;
1193 case SdMmcMmcHs200:
1194 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS200;
1195 break;
1196 case SdMmcMmcHs400:
1197 HostCtrl2 = SD_MMC_HC_CTRL_MMC_HS400;
1198 break;
1199 default:
1200 HostCtrl2 = 0;
1201 break;
1202 }
1203 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
1204 if (EFI_ERROR (Status)) {
1205 return Status;
1206 }
1207
1208 if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
1209 Status = mOverride->NotifyPhase (
1210 ControllerHandle,
1211 Slot,
1212 EdkiiSdMmcUhsSignaling,
1213 &Timing
1214 );
1215 if (EFI_ERROR (Status)) {
1216 DEBUG ((
1217 DEBUG_ERROR,
1218 "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
1219 __FUNCTION__,
1220 Status
1221 ));
1222 return Status;
1223 }
1224 }
1225
1226 return EFI_SUCCESS;
1227 }
1228
1229 /**
1230 Turn on/off LED.
1231
1232 @param[in] PciIo The PCI IO protocol instance.
1233 @param[in] Slot The slot number of the SD card to send the command to.
1234 @param[in] On The boolean to turn on/off LED.
1235
1236 @retval EFI_SUCCESS The LED is turned on/off successfully.
1237 @retval Others The LED isn't turned on/off successfully.
1238
1239 **/
1240 EFI_STATUS
1241 SdMmcHcLedOnOff (
1242 IN EFI_PCI_IO_PROTOCOL *PciIo,
1243 IN UINT8 Slot,
1244 IN BOOLEAN On
1245 )
1246 {
1247 EFI_STATUS Status;
1248 UINT8 HostCtrl1;
1249
1250 if (On) {
1251 HostCtrl1 = BIT0;
1252 Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1253 } else {
1254 HostCtrl1 = (UINT8)~BIT0;
1255 Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1256 }
1257
1258 return Status;
1259 }
1260
1261 /**
1262 Build ADMA descriptor table for transfer.
1263
1264 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
1265
1266 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1267
1268 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
1269 @retval Others The ADMA descriptor table isn't created successfully.
1270
1271 **/
1272 EFI_STATUS
1273 BuildAdmaDescTable (
1274 IN SD_MMC_HC_TRB *Trb
1275 )
1276 {
1277 EFI_PHYSICAL_ADDRESS Data;
1278 UINT64 DataLen;
1279 UINT64 Entries;
1280 UINT32 Index;
1281 UINT64 Remaining;
1282 UINT32 Address;
1283 UINTN TableSize;
1284 EFI_PCI_IO_PROTOCOL *PciIo;
1285 EFI_STATUS Status;
1286 UINTN Bytes;
1287
1288 Data = Trb->DataPhy;
1289 DataLen = Trb->DataLen;
1290 PciIo = Trb->Private->PciIo;
1291 //
1292 // Only support 32bit ADMA Descriptor Table
1293 //
1294 if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {
1295 return EFI_INVALID_PARAMETER;
1296 }
1297 //
1298 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
1299 // for 32-bit address descriptor table.
1300 //
1301 if ((Data & (BIT0 | BIT1)) != 0) {
1302 DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
1303 }
1304
1305 Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);
1306 TableSize = (UINTN)MultU64x32 (Entries, sizeof (SD_MMC_HC_ADMA_DESC_LINE));
1307 Trb->AdmaPages = (UINT32)EFI_SIZE_TO_PAGES (TableSize);
1308 Status = PciIo->AllocateBuffer (
1309 PciIo,
1310 AllocateAnyPages,
1311 EfiBootServicesData,
1312 EFI_SIZE_TO_PAGES (TableSize),
1313 (VOID **)&Trb->AdmaDesc,
1314 0
1315 );
1316 if (EFI_ERROR (Status)) {
1317 return EFI_OUT_OF_RESOURCES;
1318 }
1319 ZeroMem (Trb->AdmaDesc, TableSize);
1320 Bytes = TableSize;
1321 Status = PciIo->Map (
1322 PciIo,
1323 EfiPciIoOperationBusMasterCommonBuffer,
1324 Trb->AdmaDesc,
1325 &Bytes,
1326 &Trb->AdmaDescPhy,
1327 &Trb->AdmaMap
1328 );
1329
1330 if (EFI_ERROR (Status) || (Bytes != TableSize)) {
1331 //
1332 // Map error or unable to map the whole RFis buffer into a contiguous region.
1333 //
1334 PciIo->FreeBuffer (
1335 PciIo,
1336 EFI_SIZE_TO_PAGES (TableSize),
1337 Trb->AdmaDesc
1338 );
1339 return EFI_OUT_OF_RESOURCES;
1340 }
1341
1342 if ((UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) {
1343 //
1344 // The ADMA doesn't support 64bit addressing.
1345 //
1346 PciIo->Unmap (
1347 PciIo,
1348 Trb->AdmaMap
1349 );
1350 PciIo->FreeBuffer (
1351 PciIo,
1352 EFI_SIZE_TO_PAGES (TableSize),
1353 Trb->AdmaDesc
1354 );
1355 return EFI_DEVICE_ERROR;
1356 }
1357
1358 Remaining = DataLen;
1359 Address = (UINT32)Data;
1360 for (Index = 0; Index < Entries; Index++) {
1361 if (Remaining <= ADMA_MAX_DATA_PER_LINE) {
1362 Trb->AdmaDesc[Index].Valid = 1;
1363 Trb->AdmaDesc[Index].Act = 2;
1364 Trb->AdmaDesc[Index].Length = (UINT16)Remaining;
1365 Trb->AdmaDesc[Index].Address = Address;
1366 break;
1367 } else {
1368 Trb->AdmaDesc[Index].Valid = 1;
1369 Trb->AdmaDesc[Index].Act = 2;
1370 Trb->AdmaDesc[Index].Length = 0;
1371 Trb->AdmaDesc[Index].Address = Address;
1372 }
1373
1374 Remaining -= ADMA_MAX_DATA_PER_LINE;
1375 Address += ADMA_MAX_DATA_PER_LINE;
1376 }
1377
1378 //
1379 // Set the last descriptor line as end of descriptor table
1380 //
1381 Trb->AdmaDesc[Index].End = 1;
1382 return EFI_SUCCESS;
1383 }
1384
1385 /**
1386 Create a new TRB for the SD/MMC cmd request.
1387
1388 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1389 @param[in] Slot The slot number of the SD card to send the command to.
1390 @param[in] Packet A pointer to the SD command data structure.
1391 @param[in] Event If Event is NULL, blocking I/O is performed. If Event is
1392 not NULL, then nonblocking I/O is performed, and Event
1393 will be signaled when the Packet completes.
1394
1395 @return Created Trb or NULL.
1396
1397 **/
1398 SD_MMC_HC_TRB *
1399 SdMmcCreateTrb (
1400 IN SD_MMC_HC_PRIVATE_DATA *Private,
1401 IN UINT8 Slot,
1402 IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,
1403 IN EFI_EVENT Event
1404 )
1405 {
1406 SD_MMC_HC_TRB *Trb;
1407 EFI_STATUS Status;
1408 EFI_TPL OldTpl;
1409 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1410 EFI_PCI_IO_PROTOCOL *PciIo;
1411 UINTN MapLength;
1412
1413 Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
1414 if (Trb == NULL) {
1415 return NULL;
1416 }
1417
1418 Trb->Signature = SD_MMC_HC_TRB_SIG;
1419 Trb->Slot = Slot;
1420 Trb->BlockSize = 0x200;
1421 Trb->Packet = Packet;
1422 Trb->Event = Event;
1423 Trb->Started = FALSE;
1424 Trb->Timeout = Packet->Timeout;
1425 Trb->Private = Private;
1426
1427 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1428 Trb->Data = Packet->InDataBuffer;
1429 Trb->DataLen = Packet->InTransferLength;
1430 Trb->Read = TRUE;
1431 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1432 Trb->Data = Packet->OutDataBuffer;
1433 Trb->DataLen = Packet->OutTransferLength;
1434 Trb->Read = FALSE;
1435 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1436 Trb->Data = NULL;
1437 Trb->DataLen = 0;
1438 } else {
1439 goto Error;
1440 }
1441
1442 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1443 Trb->BlockSize = (UINT16)Trb->DataLen;
1444 }
1445
1446 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1447 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1448 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1449 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1450 Trb->Mode = SdMmcPioMode;
1451 } else {
1452 if (Trb->Read) {
1453 Flag = EfiPciIoOperationBusMasterWrite;
1454 } else {
1455 Flag = EfiPciIoOperationBusMasterRead;
1456 }
1457
1458 PciIo = Private->PciIo;
1459 if (Trb->DataLen != 0) {
1460 MapLength = Trb->DataLen;
1461 Status = PciIo->Map (
1462 PciIo,
1463 Flag,
1464 Trb->Data,
1465 &MapLength,
1466 &Trb->DataPhy,
1467 &Trb->DataMap
1468 );
1469 if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
1470 Status = EFI_BAD_BUFFER_SIZE;
1471 goto Error;
1472 }
1473 }
1474
1475 if (Trb->DataLen == 0) {
1476 Trb->Mode = SdMmcNoData;
1477 } else if (Private->Capability[Slot].Adma2 != 0) {
1478 Trb->Mode = SdMmcAdmaMode;
1479 Status = BuildAdmaDescTable (Trb);
1480 if (EFI_ERROR (Status)) {
1481 PciIo->Unmap (PciIo, Trb->DataMap);
1482 goto Error;
1483 }
1484 } else if (Private->Capability[Slot].Sdma != 0) {
1485 Trb->Mode = SdMmcSdmaMode;
1486 } else {
1487 Trb->Mode = SdMmcPioMode;
1488 }
1489 }
1490
1491 if (Event != NULL) {
1492 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1493 InsertTailList (&Private->Queue, &Trb->TrbList);
1494 gBS->RestoreTPL (OldTpl);
1495 }
1496
1497 return Trb;
1498
1499 Error:
1500 SdMmcFreeTrb (Trb);
1501 return NULL;
1502 }
1503
1504 /**
1505 Free the resource used by the TRB.
1506
1507 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1508
1509 **/
1510 VOID
1511 SdMmcFreeTrb (
1512 IN SD_MMC_HC_TRB *Trb
1513 )
1514 {
1515 EFI_PCI_IO_PROTOCOL *PciIo;
1516
1517 PciIo = Trb->Private->PciIo;
1518
1519 if (Trb->AdmaMap != NULL) {
1520 PciIo->Unmap (
1521 PciIo,
1522 Trb->AdmaMap
1523 );
1524 }
1525 if (Trb->AdmaDesc != NULL) {
1526 PciIo->FreeBuffer (
1527 PciIo,
1528 Trb->AdmaPages,
1529 Trb->AdmaDesc
1530 );
1531 }
1532 if (Trb->DataMap != NULL) {
1533 PciIo->Unmap (
1534 PciIo,
1535 Trb->DataMap
1536 );
1537 }
1538 FreePool (Trb);
1539 return;
1540 }
1541
1542 /**
1543 Check if the env is ready for execute specified TRB.
1544
1545 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1546 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1547
1548 @retval EFI_SUCCESS The env is ready for TRB execution.
1549 @retval EFI_NOT_READY The env is not ready for TRB execution.
1550 @retval Others Some erros happen.
1551
1552 **/
1553 EFI_STATUS
1554 SdMmcCheckTrbEnv (
1555 IN SD_MMC_HC_PRIVATE_DATA *Private,
1556 IN SD_MMC_HC_TRB *Trb
1557 )
1558 {
1559 EFI_STATUS Status;
1560 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1561 EFI_PCI_IO_PROTOCOL *PciIo;
1562 UINT32 PresentState;
1563
1564 Packet = Trb->Packet;
1565
1566 if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) ||
1567 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR1b) ||
1568 (Packet->SdMmcCmdBlk->ResponseType == SdMmcResponseTypeR5b)) {
1569 //
1570 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1571 // the Present State register to be 0
1572 //
1573 PresentState = BIT0 | BIT1;
1574 } else {
1575 //
1576 // Wait Command Inhibit (CMD) in the Present State register
1577 // to be 0
1578 //
1579 PresentState = BIT0;
1580 }
1581
1582 PciIo = Private->PciIo;
1583 Status = SdMmcHcCheckMmioSet (
1584 PciIo,
1585 Trb->Slot,
1586 SD_MMC_HC_PRESENT_STATE,
1587 sizeof (PresentState),
1588 PresentState,
1589 0
1590 );
1591
1592 return Status;
1593 }
1594
1595 /**
1596 Wait for the env to be ready for execute specified TRB.
1597
1598 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1599 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1600
1601 @retval EFI_SUCCESS The env is ready for TRB execution.
1602 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1603 @retval Others Some erros happen.
1604
1605 **/
1606 EFI_STATUS
1607 SdMmcWaitTrbEnv (
1608 IN SD_MMC_HC_PRIVATE_DATA *Private,
1609 IN SD_MMC_HC_TRB *Trb
1610 )
1611 {
1612 EFI_STATUS Status;
1613 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1614 UINT64 Timeout;
1615 BOOLEAN InfiniteWait;
1616
1617 //
1618 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1619 //
1620 Packet = Trb->Packet;
1621 Timeout = Packet->Timeout;
1622 if (Timeout == 0) {
1623 InfiniteWait = TRUE;
1624 } else {
1625 InfiniteWait = FALSE;
1626 }
1627
1628 while (InfiniteWait || (Timeout > 0)) {
1629 //
1630 // Check Trb execution result by reading Normal Interrupt Status register.
1631 //
1632 Status = SdMmcCheckTrbEnv (Private, Trb);
1633 if (Status != EFI_NOT_READY) {
1634 return Status;
1635 }
1636 //
1637 // Stall for 1 microsecond.
1638 //
1639 gBS->Stall (1);
1640
1641 Timeout--;
1642 }
1643
1644 return EFI_TIMEOUT;
1645 }
1646
1647 /**
1648 Execute the specified TRB.
1649
1650 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1651 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1652
1653 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1654 @retval Others Some erros happen when sending this request to the host controller.
1655
1656 **/
1657 EFI_STATUS
1658 SdMmcExecTrb (
1659 IN SD_MMC_HC_PRIVATE_DATA *Private,
1660 IN SD_MMC_HC_TRB *Trb
1661 )
1662 {
1663 EFI_STATUS Status;
1664 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1665 EFI_PCI_IO_PROTOCOL *PciIo;
1666 UINT16 Cmd;
1667 UINT16 IntStatus;
1668 UINT32 Argument;
1669 UINT16 BlkCount;
1670 UINT16 BlkSize;
1671 UINT16 TransMode;
1672 UINT8 HostCtrl1;
1673 UINT32 SdmaAddr;
1674 UINT64 AdmaAddr;
1675
1676 Packet = Trb->Packet;
1677 PciIo = Trb->Private->PciIo;
1678 //
1679 // Clear all bits in Error Interrupt Status Register
1680 //
1681 IntStatus = 0xFFFF;
1682 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1683 if (EFI_ERROR (Status)) {
1684 return Status;
1685 }
1686 //
1687 // Clear all bits in Normal Interrupt Status Register excepts for Card Removal & Card Insertion bits.
1688 //
1689 IntStatus = 0xFF3F;
1690 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1691 if (EFI_ERROR (Status)) {
1692 return Status;
1693 }
1694 //
1695 // Set Host Control 1 register DMA Select field
1696 //
1697 if (Trb->Mode == SdMmcAdmaMode) {
1698 HostCtrl1 = BIT4;
1699 Status = SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1700 if (EFI_ERROR (Status)) {
1701 return Status;
1702 }
1703 }
1704
1705 SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE);
1706
1707 if (Trb->Mode == SdMmcSdmaMode) {
1708 if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {
1709 return EFI_INVALID_PARAMETER;
1710 }
1711
1712 SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;
1713 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);
1714 if (EFI_ERROR (Status)) {
1715 return Status;
1716 }
1717 } else if (Trb->Mode == SdMmcAdmaMode) {
1718 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDescPhy;
1719 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
1720 if (EFI_ERROR (Status)) {
1721 return Status;
1722 }
1723 }
1724
1725 BlkSize = Trb->BlockSize;
1726 if (Trb->Mode == SdMmcSdmaMode) {
1727 //
1728 // Set SDMA boundary to be 512K bytes.
1729 //
1730 BlkSize |= 0x7000;
1731 }
1732
1733 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
1734 if (EFI_ERROR (Status)) {
1735 return Status;
1736 }
1737
1738 BlkCount = 0;
1739 if (Trb->Mode != SdMmcNoData) {
1740 //
1741 // Calcuate Block Count.
1742 //
1743 BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);
1744 }
1745 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);
1746 if (EFI_ERROR (Status)) {
1747 return Status;
1748 }
1749
1750 Argument = Packet->SdMmcCmdBlk->CommandArgument;
1751 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);
1752 if (EFI_ERROR (Status)) {
1753 return Status;
1754 }
1755
1756 TransMode = 0;
1757 if (Trb->Mode != SdMmcNoData) {
1758 if (Trb->Mode != SdMmcPioMode) {
1759 TransMode |= BIT0;
1760 }
1761 if (Trb->Read) {
1762 TransMode |= BIT4;
1763 }
1764 if (BlkCount > 1) {
1765 TransMode |= BIT5 | BIT1;
1766 }
1767 //
1768 // Only SD memory card needs to use AUTO CMD12 feature.
1769 //
1770 if (Private->Slot[Trb->Slot].CardType == SdCardType) {
1771 if (BlkCount > 1) {
1772 TransMode |= BIT2;
1773 }
1774 }
1775 }
1776
1777 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
1778 if (EFI_ERROR (Status)) {
1779 return Status;
1780 }
1781
1782 Cmd = (UINT16)LShiftU64(Packet->SdMmcCmdBlk->CommandIndex, 8);
1783 if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc) {
1784 Cmd |= BIT5;
1785 }
1786 //
1787 // Convert ResponseType to value
1788 //
1789 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
1790 switch (Packet->SdMmcCmdBlk->ResponseType) {
1791 case SdMmcResponseTypeR1:
1792 case SdMmcResponseTypeR5:
1793 case SdMmcResponseTypeR6:
1794 case SdMmcResponseTypeR7:
1795 Cmd |= (BIT1 | BIT3 | BIT4);
1796 break;
1797 case SdMmcResponseTypeR2:
1798 Cmd |= (BIT0 | BIT3);
1799 break;
1800 case SdMmcResponseTypeR3:
1801 case SdMmcResponseTypeR4:
1802 Cmd |= BIT1;
1803 break;
1804 case SdMmcResponseTypeR1b:
1805 case SdMmcResponseTypeR5b:
1806 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
1807 break;
1808 default:
1809 ASSERT (FALSE);
1810 break;
1811 }
1812 }
1813 //
1814 // Execute cmd
1815 //
1816 Status = SdMmcHcRwMmio (PciIo, Trb->Slot, SD_MMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
1817 return Status;
1818 }
1819
1820 /**
1821 Check the TRB execution result.
1822
1823 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
1824 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
1825
1826 @retval EFI_SUCCESS The TRB is executed successfully.
1827 @retval EFI_NOT_READY The TRB is not completed for execution.
1828 @retval Others Some erros happen when executing this request.
1829
1830 **/
1831 EFI_STATUS
1832 SdMmcCheckTrbResult (
1833 IN SD_MMC_HC_PRIVATE_DATA *Private,
1834 IN SD_MMC_HC_TRB *Trb
1835 )
1836 {
1837 EFI_STATUS Status;
1838 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
1839 UINT16 IntStatus;
1840 UINT32 Response[4];
1841 UINT32 SdmaAddr;
1842 UINT8 Index;
1843 UINT8 SwReset;
1844 UINT32 PioLength;
1845
1846 SwReset = 0;
1847 Packet = Trb->Packet;
1848 //
1849 // Check Trb execution result by reading Normal Interrupt Status register.
1850 //
1851 Status = SdMmcHcRwMmio (
1852 Private->PciIo,
1853 Trb->Slot,
1854 SD_MMC_HC_NOR_INT_STS,
1855 TRUE,
1856 sizeof (IntStatus),
1857 &IntStatus
1858 );
1859 if (EFI_ERROR (Status)) {
1860 goto Done;
1861 }
1862 //
1863 // Check Transfer Complete bit is set or not.
1864 //
1865 if ((IntStatus & BIT1) == BIT1) {
1866 if ((IntStatus & BIT15) == BIT15) {
1867 //
1868 // Read Error Interrupt Status register to check if the error is
1869 // Data Timeout Error.
1870 // If yes, treat it as success as Transfer Complete has higher
1871 // priority than Data Timeout Error.
1872 //
1873 Status = SdMmcHcRwMmio (
1874 Private->PciIo,
1875 Trb->Slot,
1876 SD_MMC_HC_ERR_INT_STS,
1877 TRUE,
1878 sizeof (IntStatus),
1879 &IntStatus
1880 );
1881 if (!EFI_ERROR (Status)) {
1882 if ((IntStatus & BIT4) == BIT4) {
1883 Status = EFI_SUCCESS;
1884 } else {
1885 Status = EFI_DEVICE_ERROR;
1886 }
1887 }
1888 }
1889
1890 goto Done;
1891 }
1892 //
1893 // Check if there is a error happened during cmd execution.
1894 // If yes, then do error recovery procedure to follow SD Host Controller
1895 // Simplified Spec 3.0 section 3.10.1.
1896 //
1897 if ((IntStatus & BIT15) == BIT15) {
1898 Status = SdMmcHcRwMmio (
1899 Private->PciIo,
1900 Trb->Slot,
1901 SD_MMC_HC_ERR_INT_STS,
1902 TRUE,
1903 sizeof (IntStatus),
1904 &IntStatus
1905 );
1906 if (EFI_ERROR (Status)) {
1907 goto Done;
1908 }
1909 if ((IntStatus & 0x0F) != 0) {
1910 SwReset |= BIT1;
1911 }
1912 if ((IntStatus & 0xF0) != 0) {
1913 SwReset |= BIT2;
1914 }
1915
1916 Status = SdMmcHcRwMmio (
1917 Private->PciIo,
1918 Trb->Slot,
1919 SD_MMC_HC_SW_RST,
1920 FALSE,
1921 sizeof (SwReset),
1922 &SwReset
1923 );
1924 if (EFI_ERROR (Status)) {
1925 goto Done;
1926 }
1927 Status = SdMmcHcWaitMmioSet (
1928 Private->PciIo,
1929 Trb->Slot,
1930 SD_MMC_HC_SW_RST,
1931 sizeof (SwReset),
1932 0xFF,
1933 0,
1934 SD_MMC_HC_GENERIC_TIMEOUT
1935 );
1936 if (EFI_ERROR (Status)) {
1937 goto Done;
1938 }
1939
1940 Status = EFI_DEVICE_ERROR;
1941 goto Done;
1942 }
1943 //
1944 // Check if DMA interrupt is signalled for the SDMA transfer.
1945 //
1946 if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
1947 //
1948 // Clear DMA interrupt bit.
1949 //
1950 IntStatus = BIT3;
1951 Status = SdMmcHcRwMmio (
1952 Private->PciIo,
1953 Trb->Slot,
1954 SD_MMC_HC_NOR_INT_STS,
1955 FALSE,
1956 sizeof (IntStatus),
1957 &IntStatus
1958 );
1959 if (EFI_ERROR (Status)) {
1960 goto Done;
1961 }
1962 //
1963 // Update SDMA Address register.
1964 //
1965 SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
1966 Status = SdMmcHcRwMmio (
1967 Private->PciIo,
1968 Trb->Slot,
1969 SD_MMC_HC_SDMA_ADDR,
1970 FALSE,
1971 sizeof (UINT32),
1972 &SdmaAddr
1973 );
1974 if (EFI_ERROR (Status)) {
1975 goto Done;
1976 }
1977 Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;
1978 }
1979
1980 if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
1981 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
1982 (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
1983 if ((IntStatus & BIT0) == BIT0) {
1984 Status = EFI_SUCCESS;
1985 goto Done;
1986 }
1987 }
1988
1989 if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) &&
1990 (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) ||
1991 ((Private->Slot[Trb->Slot].CardType == SdCardType) &&
1992 (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
1993 //
1994 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
1995 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
1996 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
1997 //
1998 if ((IntStatus & BIT5) == BIT5) {
1999 //
2000 // Clear Buffer Read Ready interrupt at first.
2001 //
2002 IntStatus = BIT5;
2003 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
2004 //
2005 // Read data out from Buffer Port register
2006 //
2007 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
2008 SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
2009 }
2010 Status = EFI_SUCCESS;
2011 goto Done;
2012 }
2013 }
2014
2015 Status = EFI_NOT_READY;
2016 Done:
2017 //
2018 // Get response data when the cmd is executed successfully.
2019 //
2020 if (!EFI_ERROR (Status)) {
2021 if (Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeBc) {
2022 for (Index = 0; Index < 4; Index++) {
2023 Status = SdMmcHcRwMmio (
2024 Private->PciIo,
2025 Trb->Slot,
2026 SD_MMC_HC_RESPONSE + Index * 4,
2027 TRUE,
2028 sizeof (UINT32),
2029 &Response[Index]
2030 );
2031 if (EFI_ERROR (Status)) {
2032 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2033 return Status;
2034 }
2035 }
2036 CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
2037 }
2038 }
2039
2040 if (Status != EFI_NOT_READY) {
2041 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
2042 }
2043
2044 return Status;
2045 }
2046
2047 /**
2048 Wait for the TRB execution result.
2049
2050 @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
2051 @param[in] Trb The pointer to the SD_MMC_HC_TRB instance.
2052
2053 @retval EFI_SUCCESS The TRB is executed successfully.
2054 @retval Others Some erros happen when executing this request.
2055
2056 **/
2057 EFI_STATUS
2058 SdMmcWaitTrbResult (
2059 IN SD_MMC_HC_PRIVATE_DATA *Private,
2060 IN SD_MMC_HC_TRB *Trb
2061 )
2062 {
2063 EFI_STATUS Status;
2064 EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
2065 UINT64 Timeout;
2066 BOOLEAN InfiniteWait;
2067
2068 Packet = Trb->Packet;
2069 //
2070 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
2071 //
2072 Timeout = Packet->Timeout;
2073 if (Timeout == 0) {
2074 InfiniteWait = TRUE;
2075 } else {
2076 InfiniteWait = FALSE;
2077 }
2078
2079 while (InfiniteWait || (Timeout > 0)) {
2080 //
2081 // Check Trb execution result by reading Normal Interrupt Status register.
2082 //
2083 Status = SdMmcCheckTrbResult (Private, Trb);
2084 if (Status != EFI_NOT_READY) {
2085 return Status;
2086 }
2087 //
2088 // Stall for 1 microsecond.
2089 //
2090 gBS->Stall (1);
2091
2092 Timeout--;
2093 }
2094
2095 return EFI_TIMEOUT;
2096 }
2097
EFI Development Kit II mirror for PVE