MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h

   1 /** @file
   2
   3   Provides some data structure definitions used by the SD/MMC host controller driver.
   4
   5 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
   6 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
   7 This program and the accompanying materials
   8 are licensed and made available under the terms and conditions of the BSD License
   9 which accompanies this distribution.  The full text of the license may be found at
  10 http://opensource.org/licenses/bsd-license.php
  11
  12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #ifndef _SD_MMC_PCI_HCI_H_
  18 #define _SD_MMC_PCI_HCI_H_
  19
  20 //
  21 // SD Host Controller SlotInfo Register Offset
  22 //
  23 #define SD_MMC_HC_SLOT_OFFSET         0x40
  24
  25 #define SD_MMC_HC_MAX_SLOT            6
  26
  27 //
  28 // SD Host Controller MMIO Register Offset
  29 //
  30 #define SD_MMC_HC_SDMA_ADDR           0x00
  31 #define SD_MMC_HC_ARG2                0x00
  32 #define SD_MMC_HC_BLK_SIZE            0x04
  33 #define SD_MMC_HC_BLK_COUNT           0x06
  34 #define SD_MMC_HC_ARG1                0x08
  35 #define SD_MMC_HC_TRANS_MOD           0x0C
  36 #define SD_MMC_HC_COMMAND             0x0E
  37 #define SD_MMC_HC_RESPONSE            0x10
  38 #define SD_MMC_HC_BUF_DAT_PORT        0x20
  39 #define SD_MMC_HC_PRESENT_STATE       0x24
  40 #define SD_MMC_HC_HOST_CTRL1          0x28
  41 #define SD_MMC_HC_POWER_CTRL          0x29
  42 #define SD_MMC_HC_BLK_GAP_CTRL        0x2A
  43 #define SD_MMC_HC_WAKEUP_CTRL         0x2B
  44 #define SD_MMC_HC_CLOCK_CTRL          0x2C
  45 #define SD_MMC_HC_TIMEOUT_CTRL        0x2E
  46 #define SD_MMC_HC_SW_RST              0x2F
  47 #define SD_MMC_HC_NOR_INT_STS         0x30
  48 #define SD_MMC_HC_ERR_INT_STS         0x32
  49 #define SD_MMC_HC_NOR_INT_STS_EN      0x34
  50 #define SD_MMC_HC_ERR_INT_STS_EN      0x36
  51 #define SD_MMC_HC_NOR_INT_SIG_EN      0x38
  52 #define SD_MMC_HC_ERR_INT_SIG_EN      0x3A
  53 #define SD_MMC_HC_AUTO_CMD_ERR_STS    0x3C
  54 #define SD_MMC_HC_HOST_CTRL2          0x3E
  55 #define SD_MMC_HC_CAP                 0x40
  56 #define SD_MMC_HC_MAX_CURRENT_CAP     0x48
  57 #define SD_MMC_HC_FORCE_EVT_AUTO_CMD  0x50
  58 #define SD_MMC_HC_FORCE_EVT_ERR_INT   0x52
  59 #define SD_MMC_HC_ADMA_ERR_STS        0x54
  60 #define SD_MMC_HC_ADMA_SYS_ADDR       0x58
  61 #define SD_MMC_HC_PRESET_VAL          0x60
  62 #define SD_MMC_HC_SHARED_BUS_CTRL     0xE0
  63 #define SD_MMC_HC_SLOT_INT_STS        0xFC
  64 #define SD_MMC_HC_CTRL_VER            0xFE
  65
  66 //
  67 // SD Host Controller bits to HOST_CTRL2 register
  68 //
  69 #define SD_MMC_HC_CTRL_UHS_MASK       0x0007
  70 #define SD_MMC_HC_CTRL_UHS_SDR12      0x0000
  71 #define SD_MMC_HC_CTRL_UHS_SDR25      0x0001
  72 #define SD_MMC_HC_CTRL_UHS_SDR50      0x0002
  73 #define SD_MMC_HC_CTRL_UHS_SDR104     0x0003
  74 #define SD_MMC_HC_CTRL_UHS_DDR50      0x0004
  75 #define SD_MMC_HC_CTRL_MMC_LEGACY     0x0000
  76 #define SD_MMC_HC_CTRL_MMC_HS_SDR     0x0001
  77 #define SD_MMC_HC_CTRL_MMC_HS_DDR     0x0004
  78 #define SD_MMC_HC_CTRL_MMC_HS200      0x0003
  79 #define SD_MMC_HC_CTRL_MMC_HS400      0x0005
  80
  81 //
  82 // The transfer modes supported by SD Host Controller
  83 //
  84 typedef enum {
  85   SdMmcNoData,
  86   SdMmcPioMode,
  87   SdMmcSdmaMode,
  88   SdMmcAdma32bMode,
  89   SdMmcAdma64bV3Mode,
  90   SdMmcAdma64bV4Mode
  91 } SD_MMC_HC_TRANSFER_MODE;
  92
  93 //
  94 // The ADMA transfer lengths supported by SD Host Controller
  95 //
  96 typedef enum {
  97   SdMmcAdmaLen16b,
  98   SdMmcAdmaLen26b
  99 } SD_MMC_HC_ADMA_LENGTH_MODE;
 100
 101 //
 102 // The maximum data length of each descriptor line
 103 //
 104 #define ADMA_MAX_DATA_PER_LINE_16B     SIZE_64KB
 105 #define ADMA_MAX_DATA_PER_LINE_26B     SIZE_64MB
 106
 107 //
 108 // ADMA descriptor for 32b addressing.
 109 //
 110 typedef struct {
 111   UINT32 Valid:1;
 112   UINT32 End:1;
 113   UINT32 Int:1;
 114   UINT32 Reserved:1;
 115   UINT32 Act:2;
 116   UINT32 UpperLength:10;
 117   UINT32 LowerLength:16;
 118   UINT32 Address;
 119 } SD_MMC_HC_ADMA_32_DESC_LINE;
 120
 121 //
 122 // ADMA descriptor for 64b addressing.
 123 //
 124 typedef struct {
 125   UINT32 Valid:1;
 126   UINT32 End:1;
 127   UINT32 Int:1;
 128   UINT32 Reserved:1;
 129   UINT32 Act:2;
 130   UINT32 UpperLength:10;
 131   UINT32 LowerLength:16;
 132   UINT32 LowerAddress;
 133   UINT32 UpperAddress;
 134 } SD_MMC_HC_ADMA_64_V3_DESC_LINE;
 135
 136 typedef struct {
 137   UINT32 Valid:1;
 138   UINT32 End:1;
 139   UINT32 Int:1;
 140   UINT32 Reserved:1;
 141   UINT32 Act:2;
 142   UINT32 UpperLength:10;
 143   UINT32 LowerLength:16;
 144   UINT32 LowerAddress;
 145   UINT32 UpperAddress;
 146   UINT32 Reserved1;
 147 } SD_MMC_HC_ADMA_64_V4_DESC_LINE;
 148
 149 #define SD_MMC_SDMA_BOUNDARY          512 * 1024
 150 #define SD_MMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))
 151
 152 typedef struct {
 153   UINT8    FirstBar:3;        // bit 0:2
 154   UINT8    Reserved:1;        // bit 3
 155   UINT8    SlotNum:3;         // bit 4:6
 156   UINT8    Reserved1:1;       // bit 7
 157 } SD_MMC_HC_SLOT_INFO;
 158
 159 typedef struct {
 160   UINT32   TimeoutFreq:6;     // bit 0:5
 161   UINT32   Reserved:1;        // bit 6
 162   UINT32   TimeoutUnit:1;     // bit 7
 163   UINT32   BaseClkFreq:8;     // bit 8:15
 164   UINT32   MaxBlkLen:2;       // bit 16:17
 165   UINT32   BusWidth8:1;       // bit 18
 166   UINT32   Adma2:1;           // bit 19
 167   UINT32   Reserved2:1;       // bit 20
 168   UINT32   HighSpeed:1;       // bit 21
 169   UINT32   Sdma:1;            // bit 22
 170   UINT32   SuspRes:1;         // bit 23
 171   UINT32   Voltage33:1;       // bit 24
 172   UINT32   Voltage30:1;       // bit 25
 173   UINT32   Voltage18:1;       // bit 26
 174   UINT32   SysBus64V4:1;      // bit 27
 175   UINT32   SysBus64V3:1;      // bit 28
 176   UINT32   AsyncInt:1;        // bit 29
 177   UINT32   SlotType:2;        // bit 30:31
 178   UINT32   Sdr50:1;           // bit 32
 179   UINT32   Sdr104:1;          // bit 33
 180   UINT32   Ddr50:1;           // bit 34
 181   UINT32   Reserved3:1;       // bit 35
 182   UINT32   DriverTypeA:1;     // bit 36
 183   UINT32   DriverTypeC:1;     // bit 37
 184   UINT32   DriverTypeD:1;     // bit 38
 185   UINT32   DriverType4:1;     // bit 39
 186   UINT32   TimerCount:4;      // bit 40:43
 187   UINT32   Reserved4:1;       // bit 44
 188   UINT32   TuningSDR50:1;     // bit 45
 189   UINT32   RetuningMod:2;     // bit 46:47
 190   UINT32   ClkMultiplier:8;   // bit 48:55
 191   UINT32   Reserved5:7;       // bit 56:62
 192   UINT32   Hs400:1;           // bit 63
 193 } SD_MMC_HC_SLOT_CAP;
 194
 195 //
 196 // SD Host controller version
 197 //
 198 #define SD_MMC_HC_CTRL_VER_100        0x00
 199 #define SD_MMC_HC_CTRL_VER_200        0x01
 200 #define SD_MMC_HC_CTRL_VER_300        0x02
 201 #define SD_MMC_HC_CTRL_VER_400        0x03
 202 #define SD_MMC_HC_CTRL_VER_410        0x04
 203 #define SD_MMC_HC_CTRL_VER_420        0x05
 204
 205 //
 206 // SD Host controller V4 enhancements
 207 //
 208 #define SD_MMC_HC_V4_EN               BIT12
 209 #define SD_MMC_HC_64_ADDR_EN          BIT13
 210 #define SD_MMC_HC_26_DATA_LEN_ADMA_EN BIT10
 211
 212 /**
 213   Dump the content of SD/MMC host controller's Capability Register.
 214
 215   @param[in]  Slot            The slot number of the SD card to send the command to.
 216   @param[in]  Capability      The buffer to store the capability data.
 217
 218 **/
 219 VOID
 220 DumpCapabilityReg (
 221   IN UINT8                Slot,
 222   IN SD_MMC_HC_SLOT_CAP   *Capability
 223   );
 224
 225 /**
 226   Read SlotInfo register from SD/MMC host controller pci config space.
 227
 228   @param[in]  PciIo        The PCI IO protocol instance.
 229   @param[out] FirstBar     The buffer to store the first BAR value.
 230   @param[out] SlotNum      The buffer to store the supported slot number.
 231
 232   @retval EFI_SUCCESS      The operation succeeds.
 233   @retval Others           The operation fails.
 234
 235 **/
 236 EFI_STATUS
 237 EFIAPI
 238 SdMmcHcGetSlotInfo (
 239   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 240      OUT UINT8                 *FirstBar,
 241      OUT UINT8                 *SlotNum
 242   );
 243
 244 /**
 245   Read/Write specified SD/MMC host controller mmio register.
 246
 247   @param[in]      PciIo        The PCI IO protocol instance.
 248   @param[in]      BarIndex     The BAR index of the standard PCI Configuration
 249                                header to use as the base address for the memory
 250                                operation to perform.
 251   @param[in]      Offset       The offset within the selected BAR to start the
 252                                memory operation.
 253   @param[in]      Read         A boolean to indicate it's read or write operation.
 254   @param[in]      Count        The width of the mmio register in bytes.
 255                                Must be 1, 2 , 4 or 8 bytes.
 256   @param[in, out] Data         For read operations, the destination buffer to store
 257                                the results. For write operations, the source buffer
 258                                to write data from. The caller is responsible for
 259                                having ownership of the data buffer and ensuring its
 260                                size not less than Count bytes.
 261
 262   @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid.
 263   @retval EFI_SUCCESS           The read/write operation succeeds.
 264   @retval Others                The read/write operation fails.
 265
 266 **/
 267 EFI_STATUS
 268 EFIAPI
 269 SdMmcHcRwMmio (
 270   IN     EFI_PCI_IO_PROTOCOL   *PciIo,
 271   IN     UINT8                 BarIndex,
 272   IN     UINT32                Offset,
 273   IN     BOOLEAN               Read,
 274   IN     UINT8                 Count,
 275   IN OUT VOID                  *Data
 276   );
 277
 278 /**
 279   Do OR operation with the value of the specified SD/MMC host controller mmio register.
 280
 281   @param[in] PciIo             The PCI IO protocol instance.
 282   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 283                                header to use as the base address for the memory
 284                                operation to perform.
 285   @param[in] Offset            The offset within the selected BAR to start the
 286                                memory operation.
 287   @param[in] Count             The width of the mmio register in bytes.
 288                                Must be 1, 2 , 4 or 8 bytes.
 289   @param[in] OrData            The pointer to the data used to do OR operation.
 290                                The caller is responsible for having ownership of
 291                                the data buffer and ensuring its size not less than
 292                                Count bytes.
 293
 294   @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid.
 295   @retval EFI_SUCCESS           The OR operation succeeds.
 296   @retval Others                The OR operation fails.
 297
 298 **/
 299 EFI_STATUS
 300 EFIAPI
 301 SdMmcHcOrMmio (
 302   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 303   IN  UINT8                    BarIndex,
 304   IN  UINT32                   Offset,
 305   IN  UINT8                    Count,
 306   IN  VOID                     *OrData
 307   );
 308
 309 /**
 310   Do AND operation with the value of the specified SD/MMC host controller mmio register.
 311
 312   @param[in] PciIo             The PCI IO protocol instance.
 313   @param[in] BarIndex          The BAR index of the standard PCI Configuration
 314                                header to use as the base address for the memory
 315                                operation to perform.
 316   @param[in] Offset            The offset within the selected BAR to start the
 317                                memory operation.
 318   @param[in] Count             The width of the mmio register in bytes.
 319                                Must be 1, 2 , 4 or 8 bytes.
 320   @param[in] AndData           The pointer to the data used to do AND operation.
 321                                The caller is responsible for having ownership of
 322                                the data buffer and ensuring its size not less than
 323                                Count bytes.
 324
 325   @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid.
 326   @retval EFI_SUCCESS           The AND operation succeeds.
 327   @retval Others                The AND operation fails.
 328
 329 **/
 330 EFI_STATUS
 331 EFIAPI
 332 SdMmcHcAndMmio (
 333   IN  EFI_PCI_IO_PROTOCOL      *PciIo,
 334   IN  UINT8                    BarIndex,
 335   IN  UINT32                   Offset,
 336   IN  UINT8                    Count,
 337   IN  VOID                     *AndData
 338   );
 339
 340 /**
 341   Wait for the value of the specified MMIO register set to the test value.
 342
 343   @param[in]  PciIo         The PCI IO protocol instance.
 344   @param[in]  BarIndex      The BAR index of the standard PCI Configuration
 345                             header to use as the base address for the memory
 346                             operation to perform.
 347   @param[in]  Offset        The offset within the selected BAR to start the
 348                             memory operation.
 349   @param[in]  Count         The width of the mmio register in bytes.
 350                             Must be 1, 2, 4 or 8 bytes.
 351   @param[in]  MaskValue     The mask value of memory.
 352   @param[in]  TestValue     The test value of memory.
 353   @param[in]  Timeout       The time out value for wait memory set, uses 1
 354                             microsecond as a unit.
 355
 356   @retval EFI_TIMEOUT       The MMIO register hasn't expected value in timeout
 357                             range.
 358   @retval EFI_SUCCESS       The MMIO register has expected value.
 359   @retval Others            The MMIO operation fails.
 360
 361 **/
 362 EFI_STATUS
 363 EFIAPI
 364 SdMmcHcWaitMmioSet (
 365   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 366   IN  UINT8                     BarIndex,
 367   IN  UINT32                    Offset,
 368   IN  UINT8                     Count,
 369   IN  UINT64                    MaskValue,
 370   IN  UINT64                    TestValue,
 371   IN  UINT64                    Timeout
 372   );
 373
 374 /**
 375   Get the controller version information from the specified slot.
 376
 377   @param[in]  PciIo           The PCI IO protocol instance.
 378   @param[in]  Slot            The slot number of the SD card to send the command to.
 379   @param[out] Version         The buffer to store the version information.
 380
 381   @retval EFI_SUCCESS         The operation executes successfully.
 382   @retval Others              The operation fails.
 383
 384 **/
 385 EFI_STATUS
 386 SdMmcHcGetControllerVersion (
 387   IN  EFI_PCI_IO_PROTOCOL  *PciIo,
 388   IN  UINT8                Slot,
 389   OUT UINT16               *Version
 390   );
 391
 392 /**
 393   Set all interrupt status bits in Normal and Error Interrupt Status Enable
 394   register.
 395
 396   @param[in] PciIo          The PCI IO protocol instance.
 397   @param[in] Slot           The slot number of the SD card to send the command to.
 398
 399   @retval EFI_SUCCESS       The operation executes successfully.
 400   @retval Others            The operation fails.
 401
 402 **/
 403 EFI_STATUS
 404 SdMmcHcEnableInterrupt (
 405   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 406   IN UINT8                  Slot
 407   );
 408
 409 /**
 410   Get the capability data from the specified slot.
 411
 412   @param[in]  PciIo           The PCI IO protocol instance.
 413   @param[in]  Slot            The slot number of the SD card to send the command to.
 414   @param[out] Capability      The buffer to store the capability data.
 415
 416   @retval EFI_SUCCESS         The operation executes successfully.
 417   @retval Others              The operation fails.
 418
 419 **/
 420 EFI_STATUS
 421 SdMmcHcGetCapability (
 422   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 423   IN     UINT8                Slot,
 424      OUT SD_MMC_HC_SLOT_CAP   *Capability
 425   );
 426
 427 /**
 428   Get the maximum current capability data from the specified slot.
 429
 430   @param[in]  PciIo           The PCI IO protocol instance.
 431   @param[in]  Slot            The slot number of the SD card to send the command to.
 432   @param[out] MaxCurrent      The buffer to store the maximum current capability data.
 433
 434   @retval EFI_SUCCESS         The operation executes successfully.
 435   @retval Others              The operation fails.
 436
 437 **/
 438 EFI_STATUS
 439 SdMmcHcGetMaxCurrent (
 440   IN     EFI_PCI_IO_PROTOCOL  *PciIo,
 441   IN     UINT8                Slot,
 442      OUT UINT64               *MaxCurrent
 443   );
 444
 445 /**
 446   Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller
 447   slot.
 448
 449   Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
 450
 451   @param[in]  PciIo         The PCI IO protocol instance.
 452   @param[in]  Slot          The slot number of the SD card to send the command to.
 453   @param[out] MediaPresent  The pointer to the media present boolean value.
 454
 455   @retval EFI_SUCCESS       There is no media change happened.
 456   @retval EFI_MEDIA_CHANGED There is media change happened.
 457   @retval Others            The detection fails.
 458
 459 **/
 460 EFI_STATUS
 461 SdMmcHcCardDetect (
 462   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 463   IN UINT8                  Slot,
 464      OUT BOOLEAN            *MediaPresent
 465   );
 466
 467 /**
 468   Stop SD/MMC card clock.
 469
 470   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
 471
 472   @param[in] PciIo          The PCI IO protocol instance.
 473   @param[in] Slot           The slot number of the SD card to send the command to.
 474
 475   @retval EFI_SUCCESS       Succeed to stop SD/MMC clock.
 476   @retval Others            Fail to stop SD/MMC clock.
 477
 478 **/
 479 EFI_STATUS
 480 SdMmcHcStopClock (
 481   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 482   IN UINT8                  Slot
 483   );
 484
 485 /**
 486   SD/MMC card clock supply.
 487
 488   Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
 489
 490   @param[in] PciIo          The PCI IO protocol instance.
 491   @param[in] Slot           The slot number of the SD card to send the command to.
 492   @param[in] ClockFreq      The max clock frequency to be set. The unit is KHz.
 493   @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.
 494   @param[in] ControllerVer  The version of host controller.
 495
 496   @retval EFI_SUCCESS       The clock is supplied successfully.
 497   @retval Others            The clock isn't supplied successfully.
 498
 499 **/
 500 EFI_STATUS
 501 SdMmcHcClockSupply (
 502   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 503   IN UINT8                  Slot,
 504   IN UINT64                 ClockFreq,
 505   IN UINT32                 BaseClkFreq,
 506   IN UINT16                 ControllerVer
 507   );
 508
 509 /**
 510   SD/MMC bus power control.
 511
 512   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 513
 514   @param[in] PciIo          The PCI IO protocol instance.
 515   @param[in] Slot           The slot number of the SD card to send the command to.
 516   @param[in] PowerCtrl      The value setting to the power control register.
 517
 518   @retval TRUE              There is a SD/MMC card attached.
 519   @retval FALSE             There is no a SD/MMC card attached.
 520
 521 **/
 522 EFI_STATUS
 523 SdMmcHcPowerControl (
 524   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 525   IN UINT8                  Slot,
 526   IN UINT8                  PowerCtrl
 527   );
 528
 529 /**
 530   Set the SD/MMC bus width.
 531
 532   Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
 533
 534   @param[in] PciIo          The PCI IO protocol instance.
 535   @param[in] Slot           The slot number of the SD card to send the command to.
 536   @param[in] BusWidth       The bus width used by the SD/MMC device, it must be 1, 4 or 8.
 537
 538   @retval EFI_SUCCESS       The bus width is set successfully.
 539   @retval Others            The bus width isn't set successfully.
 540
 541 **/
 542 EFI_STATUS
 543 SdMmcHcSetBusWidth (
 544   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 545   IN UINT8                  Slot,
 546   IN UINT16                 BusWidth
 547   );
 548
 549 /**
 550   Supply SD/MMC card with lowest clock frequency at initialization.
 551
 552   @param[in] PciIo          The PCI IO protocol instance.
 553   @param[in] Slot           The slot number of the SD card to send the command to.
 554   @param[in] BaseClkFreq    The base clock frequency of host controller in MHz.
 555   @param[in] ControllerVer  The version of host controller.
 556
 557   @retval EFI_SUCCESS       The clock is supplied successfully.
 558   @retval Others            The clock isn't supplied successfully.
 559
 560 **/
 561 EFI_STATUS
 562 SdMmcHcInitClockFreq (
 563   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 564   IN UINT8                  Slot,
 565   IN UINT32                 BaseClkFreq,
 566   IN UINT16                 ControllerVer
 567   );
 568
 569 /**
 570   Supply SD/MMC card with maximum voltage at initialization.
 571
 572   Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
 573
 574   @param[in] PciIo          The PCI IO protocol instance.
 575   @param[in] Slot           The slot number of the SD card to send the command to.
 576   @param[in] Capability     The capability of the slot.
 577
 578   @retval EFI_SUCCESS       The voltage is supplied successfully.
 579   @retval Others            The voltage isn't supplied successfully.
 580
 581 **/
 582 EFI_STATUS
 583 SdMmcHcInitPowerVoltage (
 584   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 585   IN UINT8                  Slot,
 586   IN SD_MMC_HC_SLOT_CAP     Capability
 587   );
 588
 589 /**
 590   Initialize the Timeout Control register with most conservative value at initialization.
 591
 592   Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
 593
 594   @param[in] PciIo          The PCI IO protocol instance.
 595   @param[in] Slot           The slot number of the SD card to send the command to.
 596
 597   @retval EFI_SUCCESS       The timeout control register is configured successfully.
 598   @retval Others            The timeout control register isn't configured successfully.
 599
 600 **/
 601 EFI_STATUS
 602 SdMmcHcInitTimeoutCtrl (
 603   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 604   IN UINT8                  Slot
 605   );
 606
 607 /**
 608   Set SD Host Controller control 2 registry according to selected speed.
 609
 610   @param[in] ControllerHandle The handle of the controller.
 611   @param[in] PciIo            The PCI IO protocol instance.
 612   @param[in] Slot             The slot number of the SD card to send the command to.
 613   @param[in] Timing           The timing to select.
 614
 615   @retval EFI_SUCCESS         The timing is set successfully.
 616   @retval Others              The timing isn't set successfully.
 617 **/
 618 EFI_STATUS
 619 SdMmcHcUhsSignaling (
 620   IN EFI_HANDLE             ControllerHandle,
 621   IN EFI_PCI_IO_PROTOCOL    *PciIo,
 622   IN UINT8                  Slot,
 623   IN SD_MMC_BUS_MODE        Timing
 624   );
 625
 626 #endif