27d7497b879288c275a4a30e90bf6eb109c13d74
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciDxe / Uhci.h
1 /** @file
2
3 Copyright (c) 2004 - 2007, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 Module Name:
13
14 Uhci.h
15
16 Abstract:
17
18 The definition for UHCI driver model and HC protocol routines.
19
20 Revision History
21
22
23 **/
24
25 #ifndef _UHCI_H
26 #define _UHCI_H
27
28
29 #include <PiDxe.h>
30
31 #include <Protocol/Usb2HostController.h>
32 #include <Protocol/UsbHostController.h>
33 #include <Protocol/PciIo.h>
34
35 #include <Library/DebugLib.h>
36 #include <Library/BaseMemoryLib.h>
37 #include <Library/UefiDriverEntryPoint.h>
38 #include <Library/UefiBootServicesTableLib.h>
39 #include <Library/UefiLib.h>
40 #include <Library/BaseLib.h>
41 #include <Library/MemoryAllocationLib.h>
42
43 #include <IndustryStandard/Pci22.h>
44
45 typedef struct _USB_HC_DEV USB_HC_DEV;
46
47 #include "UsbHcMem.h"
48 #include "UhciQueue.h"
49 #include "UhciReg.h"
50 #include "UhciSched.h"
51 #include "UhciDebug.h"
52
53 enum {
54 //
55 // Stall times
56 //
57 STALL_1_MS = 1000,
58 STALL_1_SECOND = 1000 *STALL_1_MS,
59
60 UHC_SYN_POLL = 50,
61 FORCE_GLOBAL_RESUME_TIME = 20 *STALL_1_MS,
62 ROOT_PORT_REST_TIME = 50 *STALL_1_MS,
63 PORT_RESET_RECOVERY_TIME = 10 *STALL_1_MS,
64 INTERRUPT_POLLING_TIME = 50 * 10000UL,
65
66 //
67 // UHC raises TPL to TPL_NOTIFY to serialize all its operations
68 // to protect shared data structures.
69 //
70 UHCI_TPL = TPL_NOTIFY,
71
72 USB_HC_DEV_SIGNATURE = EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')
73 };
74
75 #pragma pack(1)
76 typedef struct {
77 UINT8 PI;
78 UINT8 SubClassCode;
79 UINT8 BaseCode;
80 } USB_CLASSC;
81 #pragma pack()
82
83 #define UHC_FROM_USB_HC_PROTO(This) CR(This, USB_HC_DEV, UsbHc, USB_HC_DEV_SIGNATURE)
84 #define UHC_FROM_USB2_HC_PROTO(This) CR(This, USB_HC_DEV, Usb2Hc, USB_HC_DEV_SIGNATURE)
85
86 //
87 // USB_HC_DEV support the UHCI hardware controller. It schedules
88 // the asynchronous interrupt transfer with the same method as
89 // EHCI: a reversed tree structure. For synchronous interrupt,
90 // control and bulk transfer, it uses three static queue head to
91 // schedule them. SyncIntQh is for interrupt transfer. LsCtrlQh is
92 // for LOW speed control transfer, and FsCtrlBulkQh is for FULL
93 // speed control or bulk transfer. This is because FULL speed contrl
94 // or bulk transfer can reclaim the unused bandwidth. Some USB
95 // device requires this bandwidth reclamation capability.
96 //
97 struct _USB_HC_DEV {
98 UINT32 Signature;
99 EFI_USB_HC_PROTOCOL UsbHc;
100 EFI_USB2_HC_PROTOCOL Usb2Hc;
101 EFI_PCI_IO_PROTOCOL *PciIo;
102
103 //
104 // Schedule data structures
105 //
106 UINT32 *FrameBase;
107 UHCI_QH_SW *SyncIntQh;
108 UHCI_QH_SW *CtrlQh;
109 UHCI_QH_SW *BulkQh;
110
111 //
112 // Structures to maintain asynchronus interrupt transfers.
113 // When asynchronous interrutp transfer is unlinked from
114 // the frame list, the hardware may still hold a pointer
115 // to it. To synchronize with hardware, its resoureces are
116 // released in two steps using Recycle and RecycleWait.
117 // Check the asynchronous interrupt management routines.
118 //
119 LIST_ENTRY AsyncIntList;
120 EFI_EVENT AsyncIntMonitor;
121 UHCI_ASYNC_REQUEST *Recycle;
122 UHCI_ASYNC_REQUEST *RecycleWait;
123
124
125 UINTN RootPorts;
126 USBHC_MEM_POOL *MemPool;
127 EFI_UNICODE_STRING_TABLE *CtrlNameTable;
128 VOID *FrameMapping;
129 };
130
131 extern EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding;
132 extern EFI_COMPONENT_NAME_PROTOCOL gUhciComponentName;
133
134 #endif