3 The definition for UHCI driver model and HC protocol routines.
5 Copyright (c) 2004 - 2007, Intel Corporation
6 All rights reserved. This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 #include <Protocol/Usb2HostController.h>
23 #include <Protocol/UsbHostController.h>
24 #include <Protocol/PciIo.h>
26 #include <Library/DebugLib.h>
27 #include <Library/BaseMemoryLib.h>
28 #include <Library/UefiDriverEntryPoint.h>
29 #include <Library/UefiBootServicesTableLib.h>
30 #include <Library/UefiLib.h>
31 #include <Library/BaseLib.h>
32 #include <Library/MemoryAllocationLib.h>
33 #include <Library/PcdLib.h>
35 #include <IndustryStandard/Pci22.h>
37 typedef struct _USB_HC_DEV USB_HC_DEV
;
40 #include "UhciQueue.h"
42 #include "UhciSched.h"
43 #include "UhciDebug.h"
46 UHC_1_MICROSECOND
= 1,
47 UHC_1_MILLISECOND
= 1000 * UHC_1_MICROSECOND
,
48 UHC_1_SECOND
= 1000 * UHC_1_MILLISECOND
,
51 // UHCI register operation timeout, set by experience
53 UHC_GENERIC_TIMEOUT
= UHC_1_SECOND
,
56 // Wait for force global resume(FGR) complete, refers to
57 // specification[UHCI11-2.1.1]
59 UHC_FORCE_GLOBAL_RESUME_STALL
= 20 * UHC_1_MILLISECOND
,
62 // Wait for roothub port reset and recovery, reset stall
63 // is set by experience, and recovery stall refers to
64 // specification[UHCI11-2.1.1]
66 UHC_ROOT_PORT_RESET_STALL
= 50 * UHC_1_MILLISECOND
,
67 UHC_ROOT_PORT_RECOVERY_STALL
= 10 * UHC_1_MILLISECOND
,
70 // Sync and Async transfer polling interval, set by experience,
71 // and the unit of Async is 100us.
73 UHC_SYNC_POLL_INTERVAL
= 50 * UHC_1_MICROSECOND
,
74 UHC_ASYNC_POLL_INTERVAL
= 50 * 10000UL
75 }UHC_TIMEOUT_EXPERIENCE_VALUE
;
79 // UHC raises TPL to TPL_NOTIFY to serialize all its operations
80 // to protect shared data structures.
82 #define UHCI_TPL TPL_NOTIFY
84 #define USB_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')
94 #define UHC_FROM_USB2_HC_PROTO(This) CR(This, USB_HC_DEV, Usb2Hc, USB_HC_DEV_SIGNATURE)
97 // USB_HC_DEV support the UHCI hardware controller. It schedules
98 // the asynchronous interrupt transfer with the same method as
99 // EHCI: a reversed tree structure. For synchronous interrupt,
100 // control and bulk transfer, it uses three static queue head to
101 // schedule them. SyncIntQh is for interrupt transfer. LsCtrlQh is
102 // for LOW speed control transfer, and FsCtrlBulkQh is for FULL
103 // speed control or bulk transfer. This is because FULL speed contrl
104 // or bulk transfer can reclaim the unused bandwidth. Some USB
105 // device requires this bandwidth reclamation capability.
109 EFI_USB2_HC_PROTOCOL Usb2Hc
;
110 EFI_PCI_IO_PROTOCOL
*PciIo
;
111 UINT64 OriginalPciAttributes
;
114 // Schedule data structures
117 UHCI_QH_SW
*SyncIntQh
;
122 // Structures to maintain asynchronus interrupt transfers.
123 // When asynchronous interrutp transfer is unlinked from
124 // the frame list, the hardware may still hold a pointer
125 // to it. To synchronize with hardware, its resoureces are
126 // released in two steps using Recycle and RecycleWait.
127 // Check the asynchronous interrupt management routines.
129 LIST_ENTRY AsyncIntList
;
130 EFI_EVENT AsyncIntMonitor
;
131 UHCI_ASYNC_REQUEST
*Recycle
;
132 UHCI_ASYNC_REQUEST
*RecycleWait
;
136 USBHC_MEM_POOL
*MemPool
;
137 EFI_UNICODE_STRING_TABLE
*CtrlNameTable
;
141 extern EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding
;
142 extern EFI_COMPONENT_NAME_PROTOCOL gUhciComponentName
;
143 extern EFI_COMPONENT_NAME2_PROTOCOL gUhciComponentName2
;