MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h

   1 /** @file
   2
   3   The definition for UHCI register operation routines.
   4
   5 Copyright (c) 2007 - 2008, Intel Corporation
   6 All rights reserved. This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _EFI_UHCI_REG_H_
  17 #define _EFI_UHCI_REG_H_
  18
  19 typedef enum {
  20   UHCI_FRAME_NUM        = 1024,
  21
  22   //
  23   // Register offset and PCI related staff
  24   //
  25   USB_BAR_INDEX         = 4,
  26
  27   USBCMD_OFFSET         = 0,
  28   USBSTS_OFFSET         = 2,
  29   USBINTR_OFFSET        = 4,
  30   USBPORTSC_OFFSET      = 0x10,
  31   USB_FRAME_NO_OFFSET   = 6,
  32   USB_FRAME_BASE_OFFSET = 8,
  33   USB_EMULATION_OFFSET  = 0xC0,
  34
  35   //
  36   // Packet IDs
  37   //
  38   SETUP_PACKET_ID       = 0x2D,
  39   INPUT_PACKET_ID       = 0x69,
  40   OUTPUT_PACKET_ID      = 0xE1,
  41   ERROR_PACKET_ID       = 0x55,
  42
  43   //
  44   // USB port status and control bit definition.
  45   //
  46   USBPORTSC_CCS         = BIT0,  // Current Connect Status
  47   USBPORTSC_CSC         = BIT1,  // Connect Status Change
  48   USBPORTSC_PED         = BIT2,  // Port Enable / Disable
  49   USBPORTSC_PEDC        = BIT3,  // Port Enable / Disable Change
  50   USBPORTSC_LSL         = BIT4,  // Line Status Low BIT
  51   USBPORTSC_LSH         = BIT5,  // Line Status High BIT
  52   USBPORTSC_RD          = BIT6,  // Resume Detect
  53   USBPORTSC_LSDA        = BIT8,  // Low Speed Device Attached
  54   USBPORTSC_PR          = BIT9,  // Port Reset
  55   USBPORTSC_SUSP        = BIT12, // Suspend
  56
  57   //
  58   // UHCI Spec said it must implement 2 ports each host at least,
  59   // and if more, check whether the bit7 of PORTSC is always 1.
  60   // So here assume the max of port number each host is 16.
  61   //
  62   USB_MAX_ROOTHUB_PORT  = 0x0F,
  63
  64   //
  65   // Command register bit definitions
  66   //
  67   USBCMD_RS             = BIT0,  // Run/Stop
  68   USBCMD_HCRESET        = BIT1,  // Host reset
  69   USBCMD_GRESET         = BIT2,  // Global reset
  70   USBCMD_EGSM           = BIT3,  // Global Suspend Mode
  71   USBCMD_FGR            = BIT4,  // Force Global Resume
  72   USBCMD_SWDBG          = BIT5,  // SW Debug mode
  73   USBCMD_CF             = BIT6,  // Config Flag (sw only)
  74   USBCMD_MAXP           = BIT7,  // Max Packet (0 = 32, 1 = 64)
  75
  76   //
  77   // USB Status register bit definitions
  78   //
  79   USBSTS_USBINT         = BIT0,  // Interrupt due to IOC
  80   USBSTS_ERROR          = BIT1,  // Interrupt due to error
  81   USBSTS_RD             = BIT2,  // Resume Detect
  82   USBSTS_HSE            = BIT3,  // Host System Error
  83   USBSTS_HCPE           = BIT4,  // Host Controller Process Error
  84   USBSTS_HCH            = BIT5,  // HC Halted
  85
  86   USBTD_ACTIVE          = BIT7,  // TD is still active
  87   USBTD_STALLED         = BIT6,  // TD is stalled
  88   USBTD_BUFFERR         = BIT5,  // Buffer underflow or overflow
  89   USBTD_BABBLE          = BIT4,  // Babble condition
  90   USBTD_NAK             = BIT3,  // NAK is received
  91   USBTD_CRC             = BIT2,  // CRC/Time out error
  92   USBTD_BITSTUFF        = BIT1  // Bit stuff error
  93 }UHCI_REGISTER_OFFSET;
  94
  95
  96 /**
  97   Read a UHCI register.
  98
  99   @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.
 100   @param  Offset       Register offset to USB_BAR_INDEX.
 101
 102   @return Content of register.
 103
 104 **/
 105 UINT16
 106 UhciReadReg (
 107   IN EFI_PCI_IO_PROTOCOL     *PciIo,
 108   IN UINT32                  Offset
 109   );
 110
 111
 112
 113 /**
 114   Write data to UHCI register.
 115
 116   @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.
 117   @param  Offset       Register offset to USB_BAR_INDEX.
 118   @param  Data         Data to write.
 119
 120   @return None.
 121
 122 **/
 123 VOID
 124 UhciWriteReg (
 125   IN EFI_PCI_IO_PROTOCOL     *PciIo,
 126   IN UINT32                  Offset,
 127   IN UINT16                  Data
 128   );
 129
 130
 131
 132 /**
 133   Set a bit of the UHCI Register.
 134
 135   @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.
 136   @param  Offset       Register offset to USB_BAR_INDEX.
 137   @param  Bit          The bit to set.
 138
 139   @return None.
 140
 141 **/
 142 VOID
 143 UhciSetRegBit (
 144   IN EFI_PCI_IO_PROTOCOL     *PciIo,
 145   IN UINT32                  Offset,
 146   IN UINT16                  Bit
 147   );
 148
 149
 150
 151 /**
 152   Clear a bit of the UHCI Register.
 153
 154   @param  PciIo        The PCI_IO protocol to access the PCI.
 155   @param  Offset       Register offset to USB_BAR_INDEX.
 156   @param  Bit          The bit to clear.
 157
 158   @return None.
 159
 160 **/
 161 VOID
 162 UhciClearRegBit (
 163   IN EFI_PCI_IO_PROTOCOL     *PciIo,
 164   IN UINT32                  Offset,
 165   IN UINT16                  Bit
 166   );
 167
 168
 169 /**
 170   Clear all the interrutp status bits, these bits
 171   are Write-Clean.
 172
 173   @param  Uhc          The UHCI device.
 174
 175   @return None.
 176
 177 **/
 178 VOID
 179 UhciAckAllInterrupt (
 180   IN  USB_HC_DEV          *Uhc
 181   );
 182
 183
 184 /**
 185   Stop the host controller.
 186
 187   @param  Uhc          The UHCI device.
 188   @param  Timeout      Max time allowed.
 189
 190   @retval EFI_SUCCESS  The host controller is stopped.
 191   @retval EFI_TIMEOUT  Failed to stop the host controller.
 192
 193 **/
 194 EFI_STATUS
 195 UhciStopHc (
 196   IN USB_HC_DEV         *Uhc,
 197   IN UINTN              Timeout
 198   );
 199
 200
 201
 202 /**
 203   Check whether the host controller operates well.
 204
 205   @param  PciIo        The PCI_IO protocol to use.
 206
 207   @retval TRUE         Host controller is working.
 208   @retval FALSE        Host controller is halted or system error.
 209
 210 **/
 211 BOOLEAN
 212 UhciIsHcWorking (
 213   IN EFI_PCI_IO_PROTOCOL     *PciIo
 214   );
 215
 216
 217 /**
 218   Set the UHCI frame list base address. It can't use
 219   UhciWriteReg which access memory in UINT16.
 220
 221   @param  PciIo        The EFI_PCI_IO_PROTOCOL to use.
 222   @param  Addr         Address to set.
 223
 224   @return None.
 225
 226 **/
 227 VOID
 228 UhciSetFrameListBaseAddr (
 229   IN EFI_PCI_IO_PROTOCOL     *PciIo,
 230   IN VOID                    *Addr
 231   );
 232
 233
 234 /**
 235   Disable USB Emulation.
 236
 237   @param  PciIo        The EFI_PCI_IO_PROTOCOL protocol to use.
 238
 239   @return None.
 240
 241 **/
 242 VOID
 243 UhciTurnOffUsbEmulation (
 244   IN EFI_PCI_IO_PROTOCOL     *PciIo
 245   );
 246 #endif