Import EhciDxe and UhciDxe into MdeModulePkg.
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / UhciDxe / UhciReg.h
1 /** @file
2
3 Copyright (c) 2007, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 Module Name:
13
14 UhciReg.h
15
16 Abstract:
17
18 The definition for UHCI register operation routines.
19
20 Revision History
21
22
23 **/
24
25 #ifndef _EFI_UHCI_REG_H_
26 #define _EFI_UHCI_REG_H_
27
28 #define BIT(a) (1 << (a))
29
30 enum {
31 UHCI_FRAME_NUM = 1024,
32
33 //
34 // Register offset and PCI related staff
35 //
36 CLASSC_OFFSET = 0x09,
37 USBBASE_OFFSET = 0x20,
38 USB_BAR_INDEX = 4,
39 PCI_CLASSC_PI_UHCI = 0x00,
40
41 USBCMD_OFFSET = 0,
42 USBSTS_OFFSET = 2,
43 USBINTR_OFFSET = 4,
44 USBPORTSC_OFFSET = 0x10,
45 USB_FRAME_NO_OFFSET = 6,
46 USB_FRAME_BASE_OFFSET = 8,
47 USB_EMULATION_OFFSET = 0xC0,
48
49 //
50 // Packet IDs
51 //
52 SETUP_PACKET_ID = 0x2D,
53 INPUT_PACKET_ID = 0x69,
54 OUTPUT_PACKET_ID = 0xE1,
55 ERROR_PACKET_ID = 0x55,
56
57 //
58 // USB port status and control bit definition.
59 //
60 USBPORTSC_CCS = BIT(0), // Current Connect Status
61 USBPORTSC_CSC = BIT(1), // Connect Status Change
62 USBPORTSC_PED = BIT(2), // Port Enable / Disable
63 USBPORTSC_PEDC = BIT(3), // Port Enable / Disable Change
64 USBPORTSC_LSL = BIT(4), // Line Status Low BIT
65 USBPORTSC_LSH = BIT(5), // Line Status High BIT
66 USBPORTSC_RD = BIT(6), // Resume Detect
67 USBPORTSC_LSDA = BIT(8), // Low Speed Device Attached
68 USBPORTSC_PR = BIT(9), // Port Reset
69 USBPORTSC_SUSP = BIT(12), // Suspend
70
71 USB_MAX_ROOTHUB_PORT = 0x0F, // Max number of root hub port
72
73 //
74 // Command register bit definitions
75 //
76 USBCMD_RS = BIT(0), // Run/Stop
77 USBCMD_HCRESET = BIT(1), // Host reset
78 USBCMD_GRESET = BIT(2), // Global reset
79 USBCMD_EGSM = BIT(3), // Global Suspend Mode
80 USBCMD_FGR = BIT(4), // Force Global Resume
81 USBCMD_SWDBG = BIT(5), // SW Debug mode
82 USBCMD_CF = BIT(6), // Config Flag (sw only)
83 USBCMD_MAXP = BIT(7), // Max Packet (0 = 32, 1 = 64)
84
85 //
86 // USB Status register bit definitions
87 //
88 USBSTS_USBINT = BIT(0), // Interrupt due to IOC
89 USBSTS_ERROR = BIT(1), // Interrupt due to error
90 USBSTS_RD = BIT(2), // Resume Detect
91 USBSTS_HSE = BIT(3), // Host System Error
92 USBSTS_HCPE = BIT(4), // Host Controller Process Error
93 USBSTS_HCH = BIT(5), // HC Halted
94
95 USBTD_ACTIVE = BIT(7), // TD is still active
96 USBTD_STALLED = BIT(6), // TD is stalled
97 USBTD_BUFFERR = BIT(5), // Buffer underflow or overflow
98 USBTD_BABBLE = BIT(4), // Babble condition
99 USBTD_NAK = BIT(3), // NAK is received
100 USBTD_CRC = BIT(2), // CRC/Time out error
101 USBTD_BITSTUFF = BIT(1), // Bit stuff error
102 };
103
104
105 /**
106 Read a UHCI register
107
108 @param PciIo The EFI_PCI_IO_PROTOCOL to use
109 @param Offset Register offset to USB_BAR_INDEX
110
111 @return Content of register
112
113 **/
114 UINT16
115 UhciReadReg (
116 IN EFI_PCI_IO_PROTOCOL *PciIo,
117 IN UINT32 Offset
118 )
119 ;
120
121
122
123 /**
124 Write data to UHCI register
125
126 @param PciIo The EFI_PCI_IO_PROTOCOL to use
127 @param Offset Register offset to USB_BAR_INDEX
128 @param Data Data to write
129
130 @return VOID
131
132 **/
133 VOID
134 UhciWriteReg (
135 IN EFI_PCI_IO_PROTOCOL *PciIo,
136 IN UINT32 Offset,
137 IN UINT16 Data
138 )
139 ;
140
141
142
143 /**
144 Set a bit of the UHCI Register
145
146 @param PciIo The EFI_PCI_IO_PROTOCOL to use
147 @param Offset Register offset to USB_BAR_INDEX
148 @param Bit The bit to set
149
150 @return None
151
152 **/
153 VOID
154 UhciSetRegBit (
155 IN EFI_PCI_IO_PROTOCOL *PciIo,
156 IN UINT32 Offset,
157 IN UINT16 Bit
158 )
159 ;
160
161
162
163 /**
164 Clear a bit of the UHCI Register
165
166 @param PciIo The PCI_IO protocol to access the PCI
167 @param Offset Register offset to USB_BAR_INDEX
168 @param Bit The bit to clear
169
170 @return None
171
172 **/
173 VOID
174 UhciClearRegBit (
175 IN EFI_PCI_IO_PROTOCOL *PciIo,
176 IN UINT32 Offset,
177 IN UINT16 Bit
178 )
179 ;
180
181
182 /**
183 Clear all the interrutp status bits, these bits
184 are Write-Clean
185
186 @param Uhc The UHCI device
187
188 @return None
189
190 **/
191 VOID
192 UhciAckAllInterrupt (
193 IN USB_HC_DEV *Uhc
194 )
195 ;
196
197
198 /**
199 Stop the host controller
200
201 @param Uhc The UHCI device
202 @param Timeout Max time allowed
203
204 @retval EFI_SUCCESS The host controller is stopped
205 @retval EFI_TIMEOUT Failed to stop the host controller
206
207 **/
208 EFI_STATUS
209 UhciStopHc (
210 IN USB_HC_DEV *Uhc,
211 IN UINTN Timeout
212 )
213 ;
214
215
216
217 /**
218 Check whether the host controller operates well
219
220 @param PciIo The PCI_IO protocol to use
221
222 @retval TRUE Host controller is working
223 @retval FALSE Host controller is halted or system error
224
225 **/
226 BOOLEAN
227 UhciIsHcWorking (
228 IN EFI_PCI_IO_PROTOCOL *PciIo
229 )
230 ;
231
232
233 /**
234 Set the UHCI frame list base address. It can't use
235 UhciWriteReg which access memory in UINT16.
236
237 @param PciIo The EFI_PCI_IO_PROTOCOL to use
238 @param Addr Address to set
239
240 @return VOID
241
242 **/
243 VOID
244 UhciSetFrameListBaseAddr (
245 IN EFI_PCI_IO_PROTOCOL *PciIo,
246 IN VOID *Addr
247 )
248 ;
249
250
251 /**
252 Disable USB Emulation
253
254 @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use
255
256 @return VOID
257
258 **/
259 VOID
260 UhciTurnOffUsbEmulation (
261 IN EFI_PCI_IO_PROTOCOL *PciIo
262 )
263 ;
264 #endif