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git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Bus/Pci/UhciDxe/UhciReg.h
3 The definition for UHCI register operation routines.
5 Copyright (c) 2007 - 2008, Intel Corporation
6 All rights reserved. This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef _EFI_UHCI_REG_H_
17 #define _EFI_UHCI_REG_H_
19 #define BIT(a) (1 << (a))
22 UHCI_FRAME_NUM
= 1024,
25 // Register offset and PCI related staff
28 USBBASE_OFFSET
= 0x20,
30 PCI_CLASSC_PI_UHCI
= 0x00,
35 USBPORTSC_OFFSET
= 0x10,
36 USB_FRAME_NO_OFFSET
= 6,
37 USB_FRAME_BASE_OFFSET
= 8,
38 USB_EMULATION_OFFSET
= 0xC0,
43 SETUP_PACKET_ID
= 0x2D,
44 INPUT_PACKET_ID
= 0x69,
45 OUTPUT_PACKET_ID
= 0xE1,
46 ERROR_PACKET_ID
= 0x55,
49 // USB port status and control bit definition.
51 USBPORTSC_CCS
= BIT(0), // Current Connect Status
52 USBPORTSC_CSC
= BIT(1), // Connect Status Change
53 USBPORTSC_PED
= BIT(2), // Port Enable / Disable
54 USBPORTSC_PEDC
= BIT(3), // Port Enable / Disable Change
55 USBPORTSC_LSL
= BIT(4), // Line Status Low BIT
56 USBPORTSC_LSH
= BIT(5), // Line Status High BIT
57 USBPORTSC_RD
= BIT(6), // Resume Detect
58 USBPORTSC_LSDA
= BIT(8), // Low Speed Device Attached
59 USBPORTSC_PR
= BIT(9), // Port Reset
60 USBPORTSC_SUSP
= BIT(12), // Suspend
63 // UHCI Spec said it must implement 2 ports each host at least,
64 // and if more, check whether the bit7 of PORTSC is always 1.
65 // So here assume the max of port number each host is 16.
67 USB_MAX_ROOTHUB_PORT
= 0x0F,
70 // Command register bit definitions
72 USBCMD_RS
= BIT(0), // Run/Stop
73 USBCMD_HCRESET
= BIT(1), // Host reset
74 USBCMD_GRESET
= BIT(2), // Global reset
75 USBCMD_EGSM
= BIT(3), // Global Suspend Mode
76 USBCMD_FGR
= BIT(4), // Force Global Resume
77 USBCMD_SWDBG
= BIT(5), // SW Debug mode
78 USBCMD_CF
= BIT(6), // Config Flag (sw only)
79 USBCMD_MAXP
= BIT(7), // Max Packet (0 = 32, 1 = 64)
82 // USB Status register bit definitions
84 USBSTS_USBINT
= BIT(0), // Interrupt due to IOC
85 USBSTS_ERROR
= BIT(1), // Interrupt due to error
86 USBSTS_RD
= BIT(2), // Resume Detect
87 USBSTS_HSE
= BIT(3), // Host System Error
88 USBSTS_HCPE
= BIT(4), // Host Controller Process Error
89 USBSTS_HCH
= BIT(5), // HC Halted
91 USBTD_ACTIVE
= BIT(7), // TD is still active
92 USBTD_STALLED
= BIT(6), // TD is stalled
93 USBTD_BUFFERR
= BIT(5), // Buffer underflow or overflow
94 USBTD_BABBLE
= BIT(4), // Babble condition
95 USBTD_NAK
= BIT(3), // NAK is received
96 USBTD_CRC
= BIT(2), // CRC/Time out error
97 USBTD_BITSTUFF
= BIT(1) // Bit stuff error
98 }UHCI_REGISTER_OFFSET
;
102 Read a UHCI register.
104 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
105 @param Offset Register offset to USB_BAR_INDEX.
107 @return Content of register.
112 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
119 Write data to UHCI register.
121 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
122 @param Offset Register offset to USB_BAR_INDEX.
123 @param Data Data to write.
130 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
138 Set a bit of the UHCI Register.
140 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
141 @param Offset Register offset to USB_BAR_INDEX.
142 @param Bit The bit to set.
149 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
157 Clear a bit of the UHCI Register.
159 @param PciIo The PCI_IO protocol to access the PCI.
160 @param Offset Register offset to USB_BAR_INDEX.
161 @param Bit The bit to clear.
168 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
175 Clear all the interrutp status bits, these bits
178 @param Uhc The UHCI device.
184 UhciAckAllInterrupt (
190 Stop the host controller.
192 @param Uhc The UHCI device.
193 @param Timeout Max time allowed.
195 @retval EFI_SUCCESS The host controller is stopped.
196 @retval EFI_TIMEOUT Failed to stop the host controller.
208 Check whether the host controller operates well.
210 @param PciIo The PCI_IO protocol to use.
212 @retval TRUE Host controller is working.
213 @retval FALSE Host controller is halted or system error.
218 IN EFI_PCI_IO_PROTOCOL
*PciIo
223 Set the UHCI frame list base address. It can't use
224 UhciWriteReg which access memory in UINT16.
226 @param PciIo The EFI_PCI_IO_PROTOCOL to use.
227 @param Addr Address to set.
233 UhciSetFrameListBaseAddr (
234 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
240 Disable USB Emulation.
242 @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.
248 UhciTurnOffUsbEmulation (
249 IN EFI_PCI_IO_PROTOCOL
*PciIo