3 The EHCI register operation routines.
5 Copyright (c) 2007 - 2008, Intel Corporation
6 All rights reserved. This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 Create Frame List Structure.
22 @param Uhc UHCI device.
24 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
25 @retval EFI_UNSUPPORTED Map memory fail.
26 @retval EFI_SUCCESS Success.
34 EFI_PHYSICAL_ADDRESS MappedAddr
;
43 // The Frame List is a common buffer that will be
44 // accessed by both the cpu and the usb bus master
45 // at the same time. The Frame List ocupies 4K bytes,
46 // and must be aligned on 4-Kbyte boundaries.
49 Pages
= EFI_SIZE_TO_PAGES (Bytes
);
51 Status
= Uhc
->PciIo
->AllocateBuffer (
60 if (EFI_ERROR (Status
)) {
61 return EFI_OUT_OF_RESOURCES
;
64 Status
= Uhc
->PciIo
->Map (
66 EfiPciIoOperationBusMasterCommonBuffer
,
73 if (EFI_ERROR (Status
) || (Bytes
!= 4096)) {
74 Status
= EFI_UNSUPPORTED
;
78 Uhc
->FrameBase
= (UINT32
*) (UINTN
) MappedAddr
;
79 Uhc
->FrameMapping
= Mapping
;
82 // Allocate the QH used by sync interrupt/control/bulk transfer.
83 // FS ctrl/bulk queue head is set to loopback so additional BW
84 // can be reclaimed. Notice, LS don't support bulk transfer and
85 // also doesn't support BW reclamation.
87 Uhc
->SyncIntQh
= UhciCreateQh (Uhc
, 1);
88 Uhc
->CtrlQh
= UhciCreateQh (Uhc
, 1);
89 Uhc
->BulkQh
= UhciCreateQh (Uhc
, 1);
91 if ((Uhc
->SyncIntQh
== NULL
) || (Uhc
->CtrlQh
== NULL
) || (Uhc
->BulkQh
== NULL
)) {
92 Uhc
->PciIo
->Unmap (Uhc
->PciIo
, Mapping
);
93 Status
= EFI_OUT_OF_RESOURCES
;
100 // Link the three together: SyncIntQh->CtrlQh->BulkQh <---------+
101 // Each frame entry is linked to this sequence of QH. These QH
102 // will remain on the schedul, never got removed
104 Uhc
->SyncIntQh
->QhHw
.HorizonLink
= QH_HLINK (Uhc
->CtrlQh
, FALSE
);
105 Uhc
->SyncIntQh
->NextQh
= Uhc
->CtrlQh
;
107 Uhc
->CtrlQh
->QhHw
.HorizonLink
= QH_HLINK (Uhc
->BulkQh
, FALSE
);
108 Uhc
->CtrlQh
->NextQh
= Uhc
->BulkQh
;
111 // Some old platform such as Intel's Tiger 4 has a difficult time
112 // in supporting the full speed bandwidth reclamation in the previous
113 // mentioned form. Most new platforms don't suffer it.
115 Uhc
->BulkQh
->QhHw
.HorizonLink
= QH_HLINK (Uhc
->BulkQh
, FALSE
);
117 Uhc
->BulkQh
->NextQh
= NULL
;
119 for (Index
= 0; Index
< UHCI_FRAME_NUM
; Index
++) {
120 Uhc
->FrameBase
[Index
] = QH_HLINK (Uhc
->SyncIntQh
, FALSE
);
124 // Tell the Host Controller where the Frame List lies,
125 // by set the Frame List Base Address Register.
127 UhciSetFrameListBaseAddr (Uhc
->PciIo
, (VOID
*) (Uhc
->FrameBase
));
131 if (Uhc
->SyncIntQh
!= NULL
) {
132 UsbHcFreeMem (Uhc
->MemPool
, Uhc
->SyncIntQh
, sizeof (UHCI_QH_SW
));
135 if (Uhc
->CtrlQh
!= NULL
) {
136 UsbHcFreeMem (Uhc
->MemPool
, Uhc
->CtrlQh
, sizeof (UHCI_QH_SW
));
139 if (Uhc
->BulkQh
!= NULL
) {
140 UsbHcFreeMem (Uhc
->MemPool
, Uhc
->BulkQh
, sizeof (UHCI_QH_SW
));
143 Uhc
->PciIo
->FreeBuffer (Uhc
->PciIo
, Pages
, Buffer
);
149 Destory FrameList buffer.
151 @param Uhc The UHCI device.
157 UhciDestoryFrameList (
162 // Unmap the common buffer for framelist entry,
163 // and free the common buffer.
164 // Uhci's frame list occupy 4k memory.
166 Uhc
->PciIo
->Unmap (Uhc
->PciIo
, Uhc
->FrameMapping
);
168 Uhc
->PciIo
->FreeBuffer (
170 EFI_SIZE_TO_PAGES (4096),
171 (VOID
*) Uhc
->FrameBase
174 if (Uhc
->SyncIntQh
!= NULL
) {
175 UsbHcFreeMem (Uhc
->MemPool
, Uhc
->SyncIntQh
, sizeof (UHCI_QH_SW
));
178 if (Uhc
->CtrlQh
!= NULL
) {
179 UsbHcFreeMem (Uhc
->MemPool
, Uhc
->CtrlQh
, sizeof (UHCI_QH_SW
));
182 if (Uhc
->BulkQh
!= NULL
) {
183 UsbHcFreeMem (Uhc
->MemPool
, Uhc
->BulkQh
, sizeof (UHCI_QH_SW
));
186 Uhc
->FrameBase
= NULL
;
187 Uhc
->SyncIntQh
= NULL
;
194 Convert the poll rate to the maxium 2^n that is smaller
197 @param Interval The poll rate to convert.
199 @return The converted poll rate.
203 UhciConvertPollRate (
209 ASSERT (Interval
!= 0);
212 // Find the index (1 based) of the highest non-zero bit
216 while (Interval
!= 0) {
221 return (UINTN
)1 << (BitCount
- 1);
226 Link a queue head (for asynchronous interrupt transfer) to
229 @param FrameBase The base of the frame list.
230 @param Qh The queue head to link into.
236 UhciLinkQhToFrameList (
245 ASSERT ((FrameBase
!= NULL
) && (Qh
!= NULL
));
247 for (Index
= 0; Index
< UHCI_FRAME_NUM
; Index
+= Qh
->Interval
) {
249 // First QH can't be NULL because we always keep static queue
250 // heads on the frame list
252 ASSERT (!LINK_TERMINATED (FrameBase
[Index
]));
253 Next
= UHCI_ADDR (FrameBase
[Index
]);
257 // Now, insert the queue head (Qh) into this frame:
258 // 1. Find a queue head with the same poll interval, just insert
259 // Qh after this queue head, then we are done.
261 // 2. Find the position to insert the queue head into:
262 // Previous head's interval is bigger than Qh's
263 // Next head's interval is less than Qh's
264 // Then, insert the Qh between then
266 // This method is very much the same as that used by EHCI.
267 // Because each QH's interval is round down to 2^n, poll
270 while (Next
->Interval
> Qh
->Interval
) {
275 ASSERT (Next
!= NULL
);
278 // The entry may have been linked into the frame by early insertation.
279 // For example: if insert a Qh with Qh.Interval == 4, and there is a Qh
280 // with Qh.Interval == 8 on the frame. If so, we are done with this frame.
281 // It isn't necessary to compare all the QH with the same interval to
282 // Qh. This is because if there is other QH with the same interval, Qh
283 // should has been inserted after that at FrameBase[0] and at FrameBase[0] it is
284 // impossible (Next == Qh)
290 if (Next
->Interval
== Qh
->Interval
) {
292 // If there is a QH with the same interval, it locates at
293 // FrameBase[0], and we can simply insert it after this QH. We
296 ASSERT ((Index
== 0) && (Qh
->NextQh
== NULL
));
304 Qh
->QhHw
.HorizonLink
= Prev
->QhHw
.HorizonLink
;
305 Prev
->QhHw
.HorizonLink
= QH_HLINK (Qh
, FALSE
);
310 // OK, find the right position, insert it in. If Qh's next
311 // link has already been set, it is in position. This is
312 // guarranted by 2^n polling interval.
314 if (Qh
->NextQh
== NULL
) {
316 Qh
->QhHw
.HorizonLink
= QH_HLINK (Next
, FALSE
);
320 FrameBase
[Index
] = QH_HLINK (Qh
, FALSE
);
323 Prev
->QhHw
.HorizonLink
= QH_HLINK (Qh
, FALSE
);
330 Unlink QH from the frame list is easier: find all
331 the precedence node, and pointer there next to QhSw's
334 @param FrameBase The base address of the frame list.
335 @param Qh The queue head to unlink.
341 UhciUnlinkQhFromFrameList (
350 ASSERT ((FrameBase
!= NULL
) && (Qh
!= NULL
));
352 for (Index
= 0; Index
< UHCI_FRAME_NUM
; Index
+= Qh
->Interval
) {
354 // Frame link can't be NULL because we always keep static
355 // queue heads on the frame list
357 ASSERT (!LINK_TERMINATED (FrameBase
[Index
]));
358 This
= UHCI_ADDR (FrameBase
[Index
]);
362 // Walk through the frame's QH list to find the
363 // queue head to remove
365 while ((This
!= NULL
) && (This
!= Qh
)) {
371 // Qh may have already been unlinked from this frame
380 // Qh is the first entry in the frame
382 FrameBase
[Index
] = Qh
->QhHw
.HorizonLink
;
384 Prev
->NextQh
= Qh
->NextQh
;
385 Prev
->QhHw
.HorizonLink
= Qh
->QhHw
.HorizonLink
;
394 @param Uhc This UHCI device.
395 @param Td UHCI_TD_SW to check.
396 @param IsLow Is Low Speed Device.
397 @param QhResult Return the result of this TD list.
399 @return Whether the TD's result is finialized.
407 OUT UHCI_QH_RESULT
*QhResult
418 // Initialize the data toggle to that of the first
419 // TD. The next toggle to use is either:
420 // 1. first TD's toggle if no TD is executed OK
421 // 2. the next toggle of last executed-OK TD
423 QhResult
->Result
= EFI_USB_NOERROR
;
424 QhResult
->NextToggle
= (UINT8
)Td
->TdHw
.DataToggle
;
425 QhResult
->Complete
= 0;
429 State
= (UINT8
)TdHw
->Status
;
432 // UHCI will set STALLED bit when it abort the execution
433 // of TD list. There are several reasons:
434 // 1. BABBLE error happened
435 // 2. Received a STALL response
436 // 3. Error count decreased to zero.
438 // It also set CRC/Timeout/NAK/Buffer Error/BitStuff Error
439 // bits when corresponding conditions happen. But these
440 // conditions are not deadly, that is a TD can successfully
441 // completes even these bits are set. But it is likely that
442 // upper layer won't distinguish these condtions. So, only
443 // set these bits when TD is actually halted.
445 if ((State
& USBTD_STALLED
) != 0) {
446 if ((State
& USBTD_BABBLE
) != 0) {
447 QhResult
->Result
|= EFI_USB_ERR_BABBLE
;
449 } else if (TdHw
->ErrorCount
!= 0) {
450 QhResult
->Result
|= EFI_USB_ERR_STALL
;
453 if ((State
& USBTD_CRC
) != 0) {
454 QhResult
->Result
|= EFI_USB_ERR_CRC
;
457 if ((State
& USBTD_BUFFERR
) != 0) {
458 QhResult
->Result
|= EFI_USB_ERR_BUFFER
;
461 if ((Td
->TdHw
.Status
& USBTD_BITSTUFF
) != 0) {
462 QhResult
->Result
|= EFI_USB_ERR_BITSTUFF
;
465 if (TdHw
->ErrorCount
== 0) {
466 QhResult
->Result
|= EFI_USB_ERR_TIMEOUT
;
472 } else if ((State
& USBTD_ACTIVE
) != 0) {
474 // The TD is still active, no need to check further.
476 QhResult
->Result
|= EFI_USB_ERR_NOTEXECUTE
;
483 // Update the next data toggle, it is always the
484 // next to the last known-good TD's data toggle if
485 // any TD is executed OK
487 QhResult
->NextToggle
= (UINT8
) (1 - (UINT8
)TdHw
->DataToggle
);
490 // This TD is finished OK or met short packet read. Update the
491 // transfer length if it isn't a SETUP.
493 Len
= (TdHw
->ActualLen
+ 1) & 0x7FF;
495 if (TdHw
->PidCode
!= SETUP_PACKET_ID
) {
496 QhResult
->Complete
+= Len
;
500 // Short packet condition for full speed input TD, also
501 // terminate the transfer
503 if (!IsLow
&& (TdHw
->ShortPacket
== 1) && (Len
< Td
->DataLen
)) {
504 DEBUG ((EFI_D_INFO
, "UhciCheckTdStatus: short packet read occured\n"));
516 // Check whether HC is halted. Don't move this up. It must be
517 // called after data toggle is successfully updated.
519 if (!UhciIsHcWorking (Uhc
->PciIo
)) {
520 QhResult
->Result
|= EFI_USB_ERR_SYSTEM
;
525 Uhc
->PciIo
->Flush (Uhc
->PciIo
);
528 UhciAckAllInterrupt (Uhc
);
534 Check the result of the transfer.
536 @param Uhc The UHCI device.
537 @param Qh The queue head of the transfer.
538 @param Td The first TDs of the transfer.
539 @param TimeOut TimeOut value in milliseconds.
540 @param IsLow Is Low Speed Device.
541 @param QhResult The variable to return result.
543 @retval EFI_SUCCESS The transfer finished with success.
544 @retval EFI_DEVICE_ERROR Transfer failed.
548 UhciExecuteTransfer (
554 OUT UHCI_QH_RESULT
*QhResult
563 Status
= EFI_SUCCESS
;
564 Delay
= (TimeOut
* UHC_1_MILLISECOND
/ UHC_SYNC_POLL_INTERVAL
) + 1;
566 for (Index
= 0; Index
< Delay
; Index
++) {
567 Finished
= UhciCheckTdStatus (Uhc
, Td
, IsLow
, QhResult
);
570 // Transfer is OK or some error occured (TD inactive)
576 gBS
->Stall (UHC_SYNC_POLL_INTERVAL
);
580 DEBUG ((EFI_D_ERROR
, "UhciExecuteTransfer: execution not finished for %dms\n", (UINT32
)TimeOut
));
584 Status
= EFI_TIMEOUT
;
586 } else if (QhResult
->Result
!= EFI_USB_NOERROR
) {
587 DEBUG ((EFI_D_ERROR
, "UhciExecuteTransfer: execution failed with result %x\n", QhResult
->Result
));
591 Status
= EFI_DEVICE_ERROR
;
599 Update Async Request, QH and TDs.
601 @param AsyncReq The UHCI asynchronous transfer to update.
602 @param Result Transfer reslut.
603 @param NextToggle The toggle of next data.
610 IN UHCI_ASYNC_REQUEST
*AsyncReq
,
620 FirstTd
= AsyncReq
->FirstTd
;
622 if (Result
== EFI_USB_NOERROR
) {
624 // The last transfer succeeds. Then we need to update
625 // the Qh and Td for next round of transfer.
626 // 1. Update the TD's data toggle
627 // 2. Activate all the TDs
628 // 3. Link the TD to the queue head again since during
629 // execution, queue head's TD pointer is changed by
632 for (Td
= FirstTd
; Td
!= NULL
; Td
= Td
->NextTd
) {
633 Td
->TdHw
.DataToggle
= NextToggle
;
635 Td
->TdHw
.Status
|= USBTD_ACTIVE
;
638 UhciLinkTdToQh (Qh
, FirstTd
);
645 Create Async Request node, and Link to List.
647 @param Uhc The UHCI device.
648 @param Qh The queue head of the transfer.
649 @param FirstTd First TD of the transfer.
650 @param DevAddr Device Address.
651 @param EndPoint EndPoint Address.
652 @param DataLen Data length.
653 @param Interval Polling Interval when inserted to frame list.
654 @param Mapping Mapping value.
655 @param Data Data buffer, unmapped.
656 @param Callback Callback after interrupt transfeer.
657 @param Context Callback Context passed as function parameter.
658 @param IsLow Is Low Speed.
660 @retval EFI_SUCCESS An asynchronous transfer is created.
661 @retval EFI_INVALID_PARAMETER Paremeter is error.
662 @retval EFI_OUT_OF_RESOURCES Failed because of resource shortage.
669 IN UHCI_TD_SW
*FirstTd
,
676 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback
,
681 UHCI_ASYNC_REQUEST
*AsyncReq
;
683 AsyncReq
= AllocatePool (sizeof (UHCI_ASYNC_REQUEST
));
685 if (AsyncReq
== NULL
) {
686 return EFI_OUT_OF_RESOURCES
;
690 // Fill Request field. Data is allocated host memory, not mapped
692 AsyncReq
->Signature
= UHCI_ASYNC_INT_SIGNATURE
;
693 AsyncReq
->DevAddr
= DevAddr
;
694 AsyncReq
->EndPoint
= EndPoint
;
695 AsyncReq
->DataLen
= DataLen
;
696 AsyncReq
->Interval
= UhciConvertPollRate(Interval
);
697 AsyncReq
->Mapping
= Mapping
;
698 AsyncReq
->Data
= Data
;
699 AsyncReq
->Callback
= Callback
;
700 AsyncReq
->Context
= Context
;
702 AsyncReq
->FirstTd
= FirstTd
;
703 AsyncReq
->IsLow
= IsLow
;
706 // Insert the new interrupt transfer to the head of the list.
707 // The interrupt transfer's monitor function scans the whole
708 // list from head to tail. The new interrupt transfer MUST be
709 // added to the head of the list.
711 InsertHeadList (&(Uhc
->AsyncIntList
), &(AsyncReq
->Link
));
718 Free an asynchronous request's resource such as memory.
720 @param Uhc The UHCI device.
721 @param AsyncReq The asynchronous request to free.
729 IN UHCI_ASYNC_REQUEST
*AsyncReq
732 ASSERT ((Uhc
!= NULL
) && (AsyncReq
!= NULL
));
734 UhciDestoryTds (Uhc
, AsyncReq
->FirstTd
);
735 UsbHcFreeMem (Uhc
->MemPool
, AsyncReq
->QhSw
, sizeof (UHCI_QH_SW
));
737 if (AsyncReq
->Mapping
!= NULL
) {
738 Uhc
->PciIo
->Unmap (Uhc
->PciIo
, AsyncReq
->Mapping
);
741 if (AsyncReq
->Data
!= NULL
) {
742 gBS
->FreePool (AsyncReq
->Data
);
745 gBS
->FreePool (AsyncReq
);
750 Unlink an asynchronous request's from UHC's asynchronus list.
751 also remove the queue head from the frame list. If FreeNow,
752 release its resource also. Otherwise, add the request to the
753 UHC's recycle list to wait for a while before release the memory.
754 Until then, hardware won't hold point to the request.
756 @param Uhc The UHCI device.
757 @param AsyncReq The asynchronous request to free.
758 @param FreeNow If TRUE, free the resource immediately, otherwise
759 add the request to recycle wait list.
767 IN UHCI_ASYNC_REQUEST
*AsyncReq
,
771 ASSERT ((Uhc
!= NULL
) && (AsyncReq
!= NULL
));
773 RemoveEntryList (&(AsyncReq
->Link
));
774 UhciUnlinkQhFromFrameList (Uhc
->FrameBase
, AsyncReq
->QhSw
);
777 UhciFreeAsyncReq (Uhc
, AsyncReq
);
780 // To sychronize with hardware, mark the queue head as inactive
781 // then add AsyncReq to UHC's recycle list
783 AsyncReq
->QhSw
->QhHw
.VerticalLink
= QH_VLINK (NULL
, TRUE
);
784 AsyncReq
->Recycle
= Uhc
->RecycleWait
;
785 Uhc
->RecycleWait
= AsyncReq
;
791 Delete Async Interrupt QH and TDs.
793 @param Uhc The UHCI device.
794 @param DevAddr Device Address.
795 @param EndPoint EndPoint Address.
796 @param Toggle The next data toggle to use.
798 @retval EFI_SUCCESS The request is deleted.
799 @retval EFI_INVALID_PARAMETER Paremeter is error.
800 @retval EFI_NOT_FOUND The asynchronous isn't found.
812 UHCI_ASYNC_REQUEST
*AsyncReq
;
813 UHCI_QH_RESULT QhResult
;
817 Status
= EFI_SUCCESS
;
820 // If no asynchronous interrupt transaction exists
822 if (IsListEmpty (&(Uhc
->AsyncIntList
))) {
827 // Find the asynchronous transfer to this device/endpoint pair
830 Link
= Uhc
->AsyncIntList
.ForwardLink
;
833 AsyncReq
= UHCI_ASYNC_INT_FROM_LINK (Link
);
834 Link
= Link
->ForwardLink
;
836 if ((AsyncReq
->DevAddr
== DevAddr
) && (AsyncReq
->EndPoint
== EndPoint
)) {
841 } while (Link
!= &(Uhc
->AsyncIntList
));
844 return EFI_NOT_FOUND
;
848 // Check the result of the async transfer then update it
849 // to get the next data toggle to use.
851 UhciCheckTdStatus (Uhc
, AsyncReq
->FirstTd
, AsyncReq
->IsLow
, &QhResult
);
852 *Toggle
= QhResult
.NextToggle
;
855 // Don't release the request now, keep it to synchronize with hardware.
857 UhciUnlinkAsyncReq (Uhc
, AsyncReq
, FALSE
);
863 Recycle the asynchronouse request. When a queue head
864 is unlinked from frame list, host controller hardware
865 may still hold a cached pointer to it. To synchronize
866 with hardware, the request is released in two steps:
867 first it is linked to the UHC's RecycleWait list. At
868 the next time UhciMonitorAsyncReqList is fired, it is
869 moved to UHC's Recylelist. Then, at another timer
870 activation, all the requests on Recycle list is freed.
871 This guarrantes that each unlink queue head keeps
872 existing for at least 50ms, far enough for the hardware
875 @param Uhc The UHCI device.
881 UhciRecycleAsyncReq (
885 UHCI_ASYNC_REQUEST
*Req
;
886 UHCI_ASYNC_REQUEST
*Next
;
890 while (Req
!= NULL
) {
892 UhciFreeAsyncReq (Uhc
, Req
);
896 Uhc
->Recycle
= Uhc
->RecycleWait
;
897 Uhc
->RecycleWait
= NULL
;
903 Release all the asynchronous transfers on the lsit.
905 @param Uhc The UHCI device.
911 UhciFreeAllAsyncReq (
916 UHCI_ASYNC_REQUEST
*AsyncReq
;
919 // Call UhciRecycleAsyncReq twice. The requests on Recycle
920 // will be released at the first call; The requests on
921 // RecycleWait will be released at the second call.
923 UhciRecycleAsyncReq (Uhc
);
924 UhciRecycleAsyncReq (Uhc
);
926 Head
= &(Uhc
->AsyncIntList
);
928 if (IsListEmpty (Head
)) {
932 while (!IsListEmpty (Head
)) {
933 AsyncReq
= UHCI_ASYNC_INT_FROM_LINK (Head
->ForwardLink
);
934 UhciUnlinkAsyncReq (Uhc
, AsyncReq
, TRUE
);
940 Interrupt transfer periodic check handler.
942 @param Event The event of the time.
943 @param Context Context of the event, pointer to USB_HC_DEV.
949 UhciMonitorAsyncReqList (
954 UHCI_ASYNC_REQUEST
*AsyncReq
;
959 UHCI_QH_RESULT QhResult
;
961 Uhc
= (USB_HC_DEV
*) Context
;
964 // Recycle the asynchronous requests expired, and promote
965 // requests waiting to be recycled the next time when this
968 UhciRecycleAsyncReq (Uhc
);
970 if (IsListEmpty (&(Uhc
->AsyncIntList
))) {
975 // This loop must be delete safe
977 Link
= Uhc
->AsyncIntList
.ForwardLink
;
980 AsyncReq
= UHCI_ASYNC_INT_FROM_LINK (Link
);
981 Link
= Link
->ForwardLink
;
983 Finished
= UhciCheckTdStatus (Uhc
, AsyncReq
->FirstTd
, AsyncReq
->IsLow
, &QhResult
);
990 // Copy the data to temporary buffer if there are some
991 // data transferred. We may have zero-length packet
995 if (QhResult
.Complete
!= 0) {
996 Data
= AllocatePool (QhResult
.Complete
);
1002 CopyMem (Data
, AsyncReq
->FirstTd
->Data
, QhResult
.Complete
);
1005 UhciUpdateAsyncReq (AsyncReq
, QhResult
.Result
, QhResult
.NextToggle
);
1008 // Now, either transfer is SUCCESS or met errors since
1009 // we have skipped to next transfer earlier if current
1010 // transfer is still active.
1012 if (QhResult
.Result
== EFI_USB_NOERROR
) {
1013 AsyncReq
->Callback (Data
, QhResult
.Complete
, AsyncReq
->Context
, QhResult
.Result
);
1016 // Leave error recovery to its related device driver.
1017 // A common case of the error recovery is to re-submit
1018 // the interrupt transfer. When an interrupt transfer
1019 // is re-submitted, its position in the linked list is
1020 // changed. It is inserted to the head of the linked
1021 // list, while this function scans the whole list from
1022 // head to tail. Thus, the re-submitted interrupt transfer's
1023 // callback function will not be called again in this round.
1025 AsyncReq
->Callback (NULL
, 0, AsyncReq
->Context
, QhResult
.Result
);
1029 gBS
->FreePool (Data
);
1031 } while (Link
!= &(Uhc
->AsyncIntList
));