3 The EHCI register operation routines.
5 Copyright (c) 2007 - 2009, Intel Corporation
6 All rights reserved. This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 Create Frame List Structure.
22 @param Uhc UHCI device.
24 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
25 @retval EFI_UNSUPPORTED Map memory fail.
26 @retval EFI_SUCCESS Success.
34 EFI_PHYSICAL_ADDRESS MappedAddr
;
42 EFI_PHYSICAL_ADDRESS PhyAddr
;
45 // The Frame List is a common buffer that will be
46 // accessed by both the cpu and the usb bus master
47 // at the same time. The Frame List ocupies 4K bytes,
48 // and must be aligned on 4-Kbyte boundaries.
51 Pages
= EFI_SIZE_TO_PAGES (Bytes
);
53 Status
= Uhc
->PciIo
->AllocateBuffer (
62 if (EFI_ERROR (Status
)) {
63 return EFI_OUT_OF_RESOURCES
;
66 Status
= Uhc
->PciIo
->Map (
68 EfiPciIoOperationBusMasterCommonBuffer
,
75 if (EFI_ERROR (Status
) || (Bytes
!= 4096)) {
76 Status
= EFI_UNSUPPORTED
;
80 Uhc
->FrameBase
= (UINT32
*) (UINTN
) Buffer
; // Cpu memory address
81 Uhc
->FrameBasePciMemAddr
= (UINT32
*) (UINTN
) MappedAddr
; // Pci memory address
82 Uhc
->FrameMapping
= Mapping
;
85 // Allocate the QH used by sync interrupt/control/bulk transfer.
86 // FS ctrl/bulk queue head is set to loopback so additional BW
87 // can be reclaimed. Notice, LS don't support bulk transfer and
88 // also doesn't support BW reclamation.
90 Uhc
->SyncIntQh
= UhciCreateQh (Uhc
, 1);
91 Uhc
->CtrlQh
= UhciCreateQh (Uhc
, 1);
92 Uhc
->BulkQh
= UhciCreateQh (Uhc
, 1);
94 if ((Uhc
->SyncIntQh
== NULL
) || (Uhc
->CtrlQh
== NULL
) || (Uhc
->BulkQh
== NULL
)) {
95 Uhc
->PciIo
->Unmap (Uhc
->PciIo
, Mapping
);
96 Status
= EFI_OUT_OF_RESOURCES
;
103 // Link the three together: SyncIntQh->CtrlQh->BulkQh <---------+
104 // Each frame entry is linked to this sequence of QH. These QH
105 // will remain on the schedul, never got removed
107 Len
= sizeof (UHCI_QH_HW
);
108 Status
= Uhc
->PciIo
->Map (
110 EfiPciIoOperationBusMasterRead
,
116 ASSERT (!EFI_ERROR (Status
));
118 Uhc
->SyncIntQh
->QhHw
.HorizonLink
= QH_HLINK (PhyAddr
, FALSE
);
119 Uhc
->SyncIntQh
->NextQh
= Uhc
->CtrlQh
;
121 Status
= Uhc
->PciIo
->Map (
123 EfiPciIoOperationBusMasterRead
,
129 ASSERT (!EFI_ERROR (Status
));
131 Uhc
->CtrlQh
->QhHw
.HorizonLink
= QH_HLINK (PhyAddr
, FALSE
);
132 Uhc
->CtrlQh
->NextQh
= Uhc
->BulkQh
;
135 // Some old platform such as Intel's Tiger 4 has a difficult time
136 // in supporting the full speed bandwidth reclamation in the previous
137 // mentioned form. Most new platforms don't suffer it.
139 Uhc
->BulkQh
->QhHw
.HorizonLink
= QH_HLINK (PhyAddr
, FALSE
);
141 Uhc
->BulkQh
->NextQh
= NULL
;
143 Len
= sizeof (UHCI_QH_HW
);
144 Status
= Uhc
->PciIo
->Map (
146 EfiPciIoOperationBusMasterRead
,
152 ASSERT (!EFI_ERROR (Status
));
154 for (Index
= 0; Index
< UHCI_FRAME_NUM
; Index
++) {
155 Uhc
->FrameBase
[Index
] = QH_HLINK (Uhc
->SyncIntQh
, FALSE
);
156 Uhc
->FrameBasePciMemAddr
[Index
] = QH_HLINK (PhyAddr
, FALSE
);
160 // Tell the Host Controller where the Frame List lies,
161 // by set the Frame List Base Address Register.
163 UhciSetFrameListBaseAddr (Uhc
->PciIo
, (VOID
*) (Uhc
->FrameBasePciMemAddr
));
167 if (Uhc
->SyncIntQh
!= NULL
) {
168 UsbHcFreeMem (Uhc
->MemPool
, Uhc
->SyncIntQh
, sizeof (UHCI_QH_SW
));
171 if (Uhc
->CtrlQh
!= NULL
) {
172 UsbHcFreeMem (Uhc
->MemPool
, Uhc
->CtrlQh
, sizeof (UHCI_QH_SW
));
175 if (Uhc
->BulkQh
!= NULL
) {
176 UsbHcFreeMem (Uhc
->MemPool
, Uhc
->BulkQh
, sizeof (UHCI_QH_SW
));
179 Uhc
->PciIo
->FreeBuffer (Uhc
->PciIo
, Pages
, Buffer
);
185 Destory FrameList buffer.
187 @param Uhc The UHCI device.
191 UhciDestoryFrameList (
196 // Unmap the common buffer for framelist entry,
197 // and free the common buffer.
198 // Uhci's frame list occupy 4k memory.
200 Uhc
->PciIo
->Unmap (Uhc
->PciIo
, Uhc
->FrameMapping
);
202 Uhc
->PciIo
->FreeBuffer (
204 EFI_SIZE_TO_PAGES (4096),
205 (VOID
*) Uhc
->FrameBase
208 if (Uhc
->SyncIntQh
!= NULL
) {
209 UsbHcFreeMem (Uhc
->MemPool
, Uhc
->SyncIntQh
, sizeof (UHCI_QH_SW
));
212 if (Uhc
->CtrlQh
!= NULL
) {
213 UsbHcFreeMem (Uhc
->MemPool
, Uhc
->CtrlQh
, sizeof (UHCI_QH_SW
));
216 if (Uhc
->BulkQh
!= NULL
) {
217 UsbHcFreeMem (Uhc
->MemPool
, Uhc
->BulkQh
, sizeof (UHCI_QH_SW
));
220 Uhc
->FrameBase
= NULL
;
221 Uhc
->FrameBasePciMemAddr
= NULL
;
222 Uhc
->SyncIntQh
= NULL
;
229 Convert the poll rate to the maxium 2^n that is smaller
232 @param Interval The poll rate to convert.
234 @return The converted poll rate.
238 UhciConvertPollRate (
244 ASSERT (Interval
!= 0);
247 // Find the index (1 based) of the highest non-zero bit
251 while (Interval
!= 0) {
256 return (UINTN
)1 << (BitCount
- 1);
261 Link a queue head (for asynchronous interrupt transfer) to
264 @param Uhc The UHCI device.
265 @param Qh The queue head to link into.
269 UhciLinkQhToFrameList (
278 EFI_PHYSICAL_ADDRESS PhyAddr
;
279 EFI_PHYSICAL_ADDRESS QhPciAddr
;
283 ASSERT ((Uhc
->FrameBase
!= NULL
) && (Qh
!= NULL
));
285 Len
= sizeof (UHCI_QH_HW
);
286 Status
= Uhc
->PciIo
->Map (
288 EfiPciIoOperationBusMasterRead
,
294 ASSERT (!EFI_ERROR (Status
));
296 for (Index
= 0; Index
< UHCI_FRAME_NUM
; Index
+= Qh
->Interval
) {
298 // First QH can't be NULL because we always keep static queue
299 // heads on the frame list
301 ASSERT (!LINK_TERMINATED (Uhc
->FrameBase
[Index
]));
302 Next
= UHCI_ADDR (Uhc
->FrameBase
[Index
]);
306 // Now, insert the queue head (Qh) into this frame:
307 // 1. Find a queue head with the same poll interval, just insert
308 // Qh after this queue head, then we are done.
310 // 2. Find the position to insert the queue head into:
311 // Previous head's interval is bigger than Qh's
312 // Next head's interval is less than Qh's
313 // Then, insert the Qh between then
315 // This method is very much the same as that used by EHCI.
316 // Because each QH's interval is round down to 2^n, poll
319 while (Next
->Interval
> Qh
->Interval
) {
322 ASSERT (Next
!= NULL
);
326 // The entry may have been linked into the frame by early insertation.
327 // For example: if insert a Qh with Qh.Interval == 4, and there is a Qh
328 // with Qh.Interval == 8 on the frame. If so, we are done with this frame.
329 // It isn't necessary to compare all the QH with the same interval to
330 // Qh. This is because if there is other QH with the same interval, Qh
331 // should has been inserted after that at FrameBase[0] and at FrameBase[0] it is
332 // impossible (Next == Qh)
338 if (Next
->Interval
== Qh
->Interval
) {
340 // If there is a QH with the same interval, it locates at
341 // FrameBase[0], and we can simply insert it after this QH. We
344 ASSERT ((Index
== 0) && (Qh
->NextQh
== NULL
));
352 Qh
->QhHw
.HorizonLink
= Prev
->QhHw
.HorizonLink
;
354 Prev
->QhHw
.HorizonLink
= QH_HLINK (QhPciAddr
, FALSE
);
359 // OK, find the right position, insert it in. If Qh's next
360 // link has already been set, it is in position. This is
361 // guarranted by 2^n polling interval.
363 if (Qh
->NextQh
== NULL
) {
366 Len
= sizeof (UHCI_QH_HW
);
367 Status
= Uhc
->PciIo
->Map (
369 EfiPciIoOperationBusMasterRead
,
375 ASSERT (!EFI_ERROR (Status
));
377 Qh
->QhHw
.HorizonLink
= QH_HLINK (PhyAddr
, FALSE
);
381 Uhc
->FrameBase
[Index
] = QH_HLINK (Qh
, FALSE
);
382 Uhc
->FrameBasePciMemAddr
[Index
] = QH_HLINK (QhPciAddr
, FALSE
);
385 Prev
->QhHw
.HorizonLink
= QH_HLINK (QhPciAddr
, FALSE
);
392 Unlink QH from the frame list is easier: find all
393 the precedence node, and pointer there next to QhSw's
396 @param Uhc The UHCI device.
397 @param Qh The queue head to unlink.
401 UhciUnlinkQhFromFrameList (
410 ASSERT ((Uhc
->FrameBase
!= NULL
) && (Qh
!= NULL
));
412 for (Index
= 0; Index
< UHCI_FRAME_NUM
; Index
+= Qh
->Interval
) {
414 // Frame link can't be NULL because we always keep static
415 // queue heads on the frame list
417 ASSERT (!LINK_TERMINATED (Uhc
->FrameBase
[Index
]));
418 This
= UHCI_ADDR (Uhc
->FrameBase
[Index
]);
422 // Walk through the frame's QH list to find the
423 // queue head to remove
425 while ((This
!= NULL
) && (This
!= Qh
)) {
431 // Qh may have already been unlinked from this frame
440 // Qh is the first entry in the frame
442 Uhc
->FrameBase
[Index
] = (UINT32
)(UINTN
)Qh
->NextQh
;
443 Uhc
->FrameBasePciMemAddr
[Index
] = Qh
->QhHw
.HorizonLink
;
445 Prev
->NextQh
= Qh
->NextQh
;
446 Prev
->QhHw
.HorizonLink
= Qh
->QhHw
.HorizonLink
;
455 @param Uhc This UHCI device.
456 @param Td UHCI_TD_SW to check.
457 @param IsLow Is Low Speed Device.
458 @param QhResult Return the result of this TD list.
460 @return Whether the TD's result is finialized.
468 OUT UHCI_QH_RESULT
*QhResult
479 // Initialize the data toggle to that of the first
480 // TD. The next toggle to use is either:
481 // 1. first TD's toggle if no TD is executed OK
482 // 2. the next toggle of last executed-OK TD
484 QhResult
->Result
= EFI_USB_NOERROR
;
485 QhResult
->NextToggle
= (UINT8
)Td
->TdHw
.DataToggle
;
486 QhResult
->Complete
= 0;
490 State
= (UINT8
)TdHw
->Status
;
493 // UHCI will set STALLED bit when it abort the execution
494 // of TD list. There are several reasons:
495 // 1. BABBLE error happened
496 // 2. Received a STALL response
497 // 3. Error count decreased to zero.
499 // It also set CRC/Timeout/NAK/Buffer Error/BitStuff Error
500 // bits when corresponding conditions happen. But these
501 // conditions are not deadly, that is a TD can successfully
502 // completes even these bits are set. But it is likely that
503 // upper layer won't distinguish these condtions. So, only
504 // set these bits when TD is actually halted.
506 if ((State
& USBTD_STALLED
) != 0) {
507 if ((State
& USBTD_BABBLE
) != 0) {
508 QhResult
->Result
|= EFI_USB_ERR_BABBLE
;
510 } else if (TdHw
->ErrorCount
!= 0) {
511 QhResult
->Result
|= EFI_USB_ERR_STALL
;
514 if ((State
& USBTD_CRC
) != 0) {
515 QhResult
->Result
|= EFI_USB_ERR_CRC
;
518 if ((State
& USBTD_BUFFERR
) != 0) {
519 QhResult
->Result
|= EFI_USB_ERR_BUFFER
;
522 if ((Td
->TdHw
.Status
& USBTD_BITSTUFF
) != 0) {
523 QhResult
->Result
|= EFI_USB_ERR_BITSTUFF
;
526 if (TdHw
->ErrorCount
== 0) {
527 QhResult
->Result
|= EFI_USB_ERR_TIMEOUT
;
533 } else if ((State
& USBTD_ACTIVE
) != 0) {
535 // The TD is still active, no need to check further.
537 QhResult
->Result
|= EFI_USB_ERR_NOTEXECUTE
;
544 // Update the next data toggle, it is always the
545 // next to the last known-good TD's data toggle if
546 // any TD is executed OK
548 QhResult
->NextToggle
= (UINT8
) (1 - (UINT8
)TdHw
->DataToggle
);
551 // This TD is finished OK or met short packet read. Update the
552 // transfer length if it isn't a SETUP.
554 Len
= (TdHw
->ActualLen
+ 1) & 0x7FF;
556 if (TdHw
->PidCode
!= SETUP_PACKET_ID
) {
557 QhResult
->Complete
+= Len
;
561 // Short packet condition for full speed input TD, also
562 // terminate the transfer
564 if (!IsLow
&& (TdHw
->ShortPacket
== 1) && (Len
< Td
->DataLen
)) {
565 DEBUG ((EFI_D_INFO
, "UhciCheckTdStatus: short packet read occured\n"));
577 // Check whether HC is halted. Don't move this up. It must be
578 // called after data toggle is successfully updated.
580 if (!UhciIsHcWorking (Uhc
->PciIo
)) {
581 QhResult
->Result
|= EFI_USB_ERR_SYSTEM
;
586 Uhc
->PciIo
->Flush (Uhc
->PciIo
);
589 UhciAckAllInterrupt (Uhc
);
595 Check the result of the transfer.
597 @param Uhc The UHCI device.
598 @param Qh The queue head of the transfer.
599 @param Td The first TDs of the transfer.
600 @param TimeOut TimeOut value in milliseconds.
601 @param IsLow Is Low Speed Device.
602 @param QhResult The variable to return result.
604 @retval EFI_SUCCESS The transfer finished with success.
605 @retval EFI_DEVICE_ERROR Transfer failed.
609 UhciExecuteTransfer (
615 OUT UHCI_QH_RESULT
*QhResult
624 Status
= EFI_SUCCESS
;
625 Delay
= (TimeOut
* UHC_1_MILLISECOND
/ UHC_SYNC_POLL_INTERVAL
) + 1;
627 for (Index
= 0; Index
< Delay
; Index
++) {
628 Finished
= UhciCheckTdStatus (Uhc
, Td
, IsLow
, QhResult
);
631 // Transfer is OK or some error occured (TD inactive)
637 gBS
->Stall (UHC_SYNC_POLL_INTERVAL
);
641 DEBUG ((EFI_D_ERROR
, "UhciExecuteTransfer: execution not finished for %dms\n", (UINT32
)TimeOut
));
645 Status
= EFI_TIMEOUT
;
647 } else if (QhResult
->Result
!= EFI_USB_NOERROR
) {
648 DEBUG ((EFI_D_ERROR
, "UhciExecuteTransfer: execution failed with result %x\n", QhResult
->Result
));
652 Status
= EFI_DEVICE_ERROR
;
660 Update Async Request, QH and TDs.
662 @param Uhc The UHCI device.
663 @param AsyncReq The UHCI asynchronous transfer to update.
664 @param Result Transfer reslut.
665 @param NextToggle The toggle of next data.
671 IN UHCI_ASYNC_REQUEST
*AsyncReq
,
681 FirstTd
= AsyncReq
->FirstTd
;
683 if (Result
== EFI_USB_NOERROR
) {
685 // The last transfer succeeds. Then we need to update
686 // the Qh and Td for next round of transfer.
687 // 1. Update the TD's data toggle
688 // 2. Activate all the TDs
689 // 3. Link the TD to the queue head again since during
690 // execution, queue head's TD pointer is changed by
693 for (Td
= FirstTd
; Td
!= NULL
; Td
= Td
->NextTd
) {
694 Td
->TdHw
.DataToggle
= NextToggle
;
696 Td
->TdHw
.Status
|= USBTD_ACTIVE
;
699 UhciLinkTdToQh (Uhc
, Qh
, FirstTd
);
706 Create Async Request node, and Link to List.
708 @param Uhc The UHCI device.
709 @param Qh The queue head of the transfer.
710 @param FirstTd First TD of the transfer.
711 @param DevAddr Device Address.
712 @param EndPoint EndPoint Address.
713 @param DataLen Data length.
714 @param Interval Polling Interval when inserted to frame list.
715 @param Mapping Mapping value.
716 @param Data Data buffer, unmapped.
717 @param Callback Callback after interrupt transfeer.
718 @param Context Callback Context passed as function parameter.
719 @param IsLow Is Low Speed.
721 @retval EFI_SUCCESS An asynchronous transfer is created.
722 @retval EFI_INVALID_PARAMETER Paremeter is error.
723 @retval EFI_OUT_OF_RESOURCES Failed because of resource shortage.
730 IN UHCI_TD_SW
*FirstTd
,
737 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback
,
742 UHCI_ASYNC_REQUEST
*AsyncReq
;
744 AsyncReq
= AllocatePool (sizeof (UHCI_ASYNC_REQUEST
));
746 if (AsyncReq
== NULL
) {
747 return EFI_OUT_OF_RESOURCES
;
751 // Fill Request field. Data is allocated host memory, not mapped
753 AsyncReq
->Signature
= UHCI_ASYNC_INT_SIGNATURE
;
754 AsyncReq
->DevAddr
= DevAddr
;
755 AsyncReq
->EndPoint
= EndPoint
;
756 AsyncReq
->DataLen
= DataLen
;
757 AsyncReq
->Interval
= UhciConvertPollRate(Interval
);
758 AsyncReq
->Mapping
= Mapping
;
759 AsyncReq
->Data
= Data
;
760 AsyncReq
->Callback
= Callback
;
761 AsyncReq
->Context
= Context
;
763 AsyncReq
->FirstTd
= FirstTd
;
764 AsyncReq
->IsLow
= IsLow
;
767 // Insert the new interrupt transfer to the head of the list.
768 // The interrupt transfer's monitor function scans the whole
769 // list from head to tail. The new interrupt transfer MUST be
770 // added to the head of the list.
772 InsertHeadList (&(Uhc
->AsyncIntList
), &(AsyncReq
->Link
));
779 Free an asynchronous request's resource such as memory.
781 @param Uhc The UHCI device.
782 @param AsyncReq The asynchronous request to free.
788 IN UHCI_ASYNC_REQUEST
*AsyncReq
791 ASSERT ((Uhc
!= NULL
) && (AsyncReq
!= NULL
));
793 UhciDestoryTds (Uhc
, AsyncReq
->FirstTd
);
794 UsbHcFreeMem (Uhc
->MemPool
, AsyncReq
->QhSw
, sizeof (UHCI_QH_SW
));
796 if (AsyncReq
->Mapping
!= NULL
) {
797 Uhc
->PciIo
->Unmap (Uhc
->PciIo
, AsyncReq
->Mapping
);
800 if (AsyncReq
->Data
!= NULL
) {
801 gBS
->FreePool (AsyncReq
->Data
);
804 gBS
->FreePool (AsyncReq
);
809 Unlink an asynchronous request's from UHC's asynchronus list.
810 also remove the queue head from the frame list. If FreeNow,
811 release its resource also. Otherwise, add the request to the
812 UHC's recycle list to wait for a while before release the memory.
813 Until then, hardware won't hold point to the request.
815 @param Uhc The UHCI device.
816 @param AsyncReq The asynchronous request to free.
817 @param FreeNow If TRUE, free the resource immediately, otherwise
818 add the request to recycle wait list.
824 IN UHCI_ASYNC_REQUEST
*AsyncReq
,
828 ASSERT ((Uhc
!= NULL
) && (AsyncReq
!= NULL
));
830 RemoveEntryList (&(AsyncReq
->Link
));
831 UhciUnlinkQhFromFrameList (Uhc
, AsyncReq
->QhSw
);
834 UhciFreeAsyncReq (Uhc
, AsyncReq
);
837 // To sychronize with hardware, mark the queue head as inactive
838 // then add AsyncReq to UHC's recycle list
840 AsyncReq
->QhSw
->QhHw
.VerticalLink
= QH_VLINK (NULL
, TRUE
);
841 AsyncReq
->Recycle
= Uhc
->RecycleWait
;
842 Uhc
->RecycleWait
= AsyncReq
;
848 Delete Async Interrupt QH and TDs.
850 @param Uhc The UHCI device.
851 @param DevAddr Device Address.
852 @param EndPoint EndPoint Address.
853 @param Toggle The next data toggle to use.
855 @retval EFI_SUCCESS The request is deleted.
856 @retval EFI_INVALID_PARAMETER Paremeter is error.
857 @retval EFI_NOT_FOUND The asynchronous isn't found.
869 UHCI_ASYNC_REQUEST
*AsyncReq
;
870 UHCI_QH_RESULT QhResult
;
874 Status
= EFI_SUCCESS
;
877 // If no asynchronous interrupt transaction exists
879 if (IsListEmpty (&(Uhc
->AsyncIntList
))) {
884 // Find the asynchronous transfer to this device/endpoint pair
887 Link
= Uhc
->AsyncIntList
.ForwardLink
;
890 AsyncReq
= UHCI_ASYNC_INT_FROM_LINK (Link
);
891 Link
= Link
->ForwardLink
;
893 if ((AsyncReq
->DevAddr
== DevAddr
) && (AsyncReq
->EndPoint
== EndPoint
)) {
898 } while (Link
!= &(Uhc
->AsyncIntList
));
901 return EFI_NOT_FOUND
;
905 // Check the result of the async transfer then update it
906 // to get the next data toggle to use.
908 UhciCheckTdStatus (Uhc
, AsyncReq
->FirstTd
, AsyncReq
->IsLow
, &QhResult
);
909 *Toggle
= QhResult
.NextToggle
;
912 // Don't release the request now, keep it to synchronize with hardware.
914 UhciUnlinkAsyncReq (Uhc
, AsyncReq
, FALSE
);
920 Recycle the asynchronouse request. When a queue head
921 is unlinked from frame list, host controller hardware
922 may still hold a cached pointer to it. To synchronize
923 with hardware, the request is released in two steps:
924 first it is linked to the UHC's RecycleWait list. At
925 the next time UhciMonitorAsyncReqList is fired, it is
926 moved to UHC's Recylelist. Then, at another timer
927 activation, all the requests on Recycle list is freed.
928 This guarrantes that each unlink queue head keeps
929 existing for at least 50ms, far enough for the hardware
932 @param Uhc The UHCI device.
936 UhciRecycleAsyncReq (
940 UHCI_ASYNC_REQUEST
*Req
;
941 UHCI_ASYNC_REQUEST
*Next
;
945 while (Req
!= NULL
) {
947 UhciFreeAsyncReq (Uhc
, Req
);
951 Uhc
->Recycle
= Uhc
->RecycleWait
;
952 Uhc
->RecycleWait
= NULL
;
958 Release all the asynchronous transfers on the lsit.
960 @param Uhc The UHCI device.
964 UhciFreeAllAsyncReq (
969 UHCI_ASYNC_REQUEST
*AsyncReq
;
972 // Call UhciRecycleAsyncReq twice. The requests on Recycle
973 // will be released at the first call; The requests on
974 // RecycleWait will be released at the second call.
976 UhciRecycleAsyncReq (Uhc
);
977 UhciRecycleAsyncReq (Uhc
);
979 Head
= &(Uhc
->AsyncIntList
);
981 if (IsListEmpty (Head
)) {
985 while (!IsListEmpty (Head
)) {
986 AsyncReq
= UHCI_ASYNC_INT_FROM_LINK (Head
->ForwardLink
);
987 UhciUnlinkAsyncReq (Uhc
, AsyncReq
, TRUE
);
993 Interrupt transfer periodic check handler.
995 @param Event The event of the time.
996 @param Context Context of the event, pointer to USB_HC_DEV.
1001 UhciMonitorAsyncReqList (
1006 UHCI_ASYNC_REQUEST
*AsyncReq
;
1011 UHCI_QH_RESULT QhResult
;
1013 Uhc
= (USB_HC_DEV
*) Context
;
1016 // Recycle the asynchronous requests expired, and promote
1017 // requests waiting to be recycled the next time when this
1020 UhciRecycleAsyncReq (Uhc
);
1022 if (IsListEmpty (&(Uhc
->AsyncIntList
))) {
1027 // This loop must be delete safe
1029 Link
= Uhc
->AsyncIntList
.ForwardLink
;
1032 AsyncReq
= UHCI_ASYNC_INT_FROM_LINK (Link
);
1033 Link
= Link
->ForwardLink
;
1035 Finished
= UhciCheckTdStatus (Uhc
, AsyncReq
->FirstTd
, AsyncReq
->IsLow
, &QhResult
);
1042 // Copy the data to temporary buffer if there are some
1043 // data transferred. We may have zero-length packet
1047 if (QhResult
.Complete
!= 0) {
1048 Data
= AllocatePool (QhResult
.Complete
);
1054 CopyMem (Data
, AsyncReq
->FirstTd
->Data
, QhResult
.Complete
);
1057 UhciUpdateAsyncReq (Uhc
, AsyncReq
, QhResult
.Result
, QhResult
.NextToggle
);
1060 // Now, either transfer is SUCCESS or met errors since
1061 // we have skipped to next transfer earlier if current
1062 // transfer is still active.
1064 if (QhResult
.Result
== EFI_USB_NOERROR
) {
1065 AsyncReq
->Callback (Data
, QhResult
.Complete
, AsyncReq
->Context
, QhResult
.Result
);
1068 // Leave error recovery to its related device driver.
1069 // A common case of the error recovery is to re-submit
1070 // the interrupt transfer. When an interrupt transfer
1071 // is re-submitted, its position in the linked list is
1072 // changed. It is inserted to the head of the linked
1073 // list, while this function scans the whole list from
1074 // head to tail. Thus, the re-submitted interrupt transfer's
1075 // callback function will not be called again in this round.
1077 AsyncReq
->Callback (NULL
, 0, AsyncReq
->Context
, QhResult
.Result
);
1081 gBS
->FreePool (Data
);
1083 } while (Link
!= &(Uhc
->AsyncIntList
));