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1 /** @file
2 Private Header file for Usb Host Controller PEIM
3
4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions
8 of the BSD License which accompanies this distribution. The
9 full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _RECOVERY_UHC_H_
18 #define _RECOVERY_UHC_H_
19
20
21 #include <PiPei.h>
22
23 #include <Ppi/UsbController.h>
24 #include <Ppi/UsbHostController.h>
25 #include <Ppi/IoMmu.h>
26 #include <Ppi/EndOfPeiPhase.h>
27
28 #include <Library/DebugLib.h>
29 #include <Library/PeimEntryPoint.h>
30 #include <Library/PeiServicesLib.h>
31 #include <Library/BaseMemoryLib.h>
32 #include <Library/TimerLib.h>
33 #include <Library/IoLib.h>
34 #include <Library/PeiServicesLib.h>
35
36 #define USB_SLOW_SPEED_DEVICE 0x01
37 #define USB_FULL_SPEED_DEVICE 0x02
38
39 //
40 // One memory block uses 16 page
41 //
42 #define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 16
43
44 #define USBCMD 0 /* Command Register Offset 00-01h */
45 #define USBCMD_RS BIT0 /* Run/Stop */
46 #define USBCMD_HCRESET BIT1 /* Host reset */
47 #define USBCMD_GRESET BIT2 /* Global reset */
48 #define USBCMD_EGSM BIT3 /* Global Suspend Mode */
49 #define USBCMD_FGR BIT4 /* Force Global Resume */
50 #define USBCMD_SWDBG BIT5 /* SW Debug mode */
51 #define USBCMD_CF BIT6 /* Config Flag (sw only) */
52 #define USBCMD_MAXP BIT7 /* Max Packet (0 = 32, 1 = 64) */
53
54 /* Status register */
55 #define USBSTS 2 /* Status Register Offset 02-03h */
56 #define USBSTS_USBINT BIT0 /* Interrupt due to IOC */
57 #define USBSTS_ERROR BIT1 /* Interrupt due to error */
58 #define USBSTS_RD BIT2 /* Resume Detect */
59 #define USBSTS_HSE BIT3 /* Host System Error - basically PCI problems */
60 #define USBSTS_HCPE BIT4 /* Host Controller Process Error - the scripts were buggy */
61 #define USBSTS_HCH BIT5 /* HC Halted */
62
63 /* Interrupt enable register */
64 #define USBINTR 4 /* Interrupt Enable Register 04-05h */
65 #define USBINTR_TIMEOUT BIT0 /* Timeout/CRC error enable */
66 #define USBINTR_RESUME BIT1 /* Resume interrupt enable */
67 #define USBINTR_IOC BIT2 /* Interrupt On Complete enable */
68 #define USBINTR_SP BIT3 /* Short packet interrupt enable */
69
70 /* Frame Number Register Offset 06-08h */
71 #define USBFRNUM 6
72
73 /* Frame List Base Address Register Offset 08-0Bh */
74 #define USBFLBASEADD 8
75
76 /* Start of Frame Modify Register Offset 0Ch */
77 #define USBSOF 0x0c
78
79 /* USB port status and control registers */
80 #define USBPORTSC1 0x10 /*Port 1 offset 10-11h */
81 #define USBPORTSC2 0x12 /*Port 2 offset 12-13h */
82
83 #define USBPORTSC_CCS BIT0 /* Current Connect Status ("device present") */
84 #define USBPORTSC_CSC BIT1 /* Connect Status Change */
85 #define USBPORTSC_PED BIT2 /* Port Enable / Disable */
86 #define USBPORTSC_PEDC BIT3 /* Port Enable / Disable Change */
87 #define USBPORTSC_LSL BIT4 /* Line Status Low bit*/
88 #define USBPORTSC_LSH BIT5 /* Line Status High bit*/
89 #define USBPORTSC_RD BIT6 /* Resume Detect */
90 #define USBPORTSC_LSDA BIT8 /* Low Speed Device Attached */
91 #define USBPORTSC_PR BIT9 /* Port Reset */
92 #define USBPORTSC_SUSP BIT12 /* Suspend */
93
94 #define SETUP_PACKET_ID 0x2D
95 #define INPUT_PACKET_ID 0x69
96 #define OUTPUT_PACKET_ID 0xE1
97 #define ERROR_PACKET_ID 0x55
98
99 #define STALL_1_MICRO_SECOND 1
100 #define STALL_1_MILLI_SECOND 1000
101
102
103 #pragma pack(1)
104
105 typedef struct {
106 UINT32 FrameListPtrTerminate : 1;
107 UINT32 FrameListPtrQSelect : 1;
108 UINT32 FrameListRsvd : 2;
109 UINT32 FrameListPtr : 28;
110 } FRAMELIST_ENTRY;
111
112 typedef struct {
113 UINT32 QHHorizontalTerminate : 1;
114 UINT32 QHHorizontalQSelect : 1;
115 UINT32 QHHorizontalRsvd : 2;
116 UINT32 QHHorizontalPtr : 28;
117 UINT32 QHVerticalTerminate : 1;
118 UINT32 QHVerticalQSelect : 1;
119 UINT32 QHVerticalRsvd : 2;
120 UINT32 QHVerticalPtr : 28;
121 } QUEUE_HEAD;
122
123 typedef struct {
124 QUEUE_HEAD QueueHead;
125 UINT32 Reserved1;
126 UINT32 Reserved2;
127 VOID *PtrNext;
128 VOID *PtrDown;
129 VOID *Reserved3;
130 UINT32 Reserved4;
131 } QH_STRUCT;
132
133 typedef struct {
134 UINT32 TDLinkPtrTerminate : 1;
135 UINT32 TDLinkPtrQSelect : 1;
136 UINT32 TDLinkPtrDepthSelect : 1;
137 UINT32 TDLinkPtrRsvd : 1;
138 UINT32 TDLinkPtr : 28;
139 UINT32 TDStatusActualLength : 11;
140 UINT32 TDStatusRsvd : 5;
141 UINT32 TDStatus : 8;
142 UINT32 TDStatusIOC : 1;
143 UINT32 TDStatusIOS : 1;
144 UINT32 TDStatusLS : 1;
145 UINT32 TDStatusErr : 2;
146 UINT32 TDStatusSPD : 1;
147 UINT32 TDStatusRsvd2 : 2;
148 UINT32 TDTokenPID : 8;
149 UINT32 TDTokenDevAddr : 7;
150 UINT32 TDTokenEndPt : 4;
151 UINT32 TDTokenDataToggle : 1;
152 UINT32 TDTokenRsvd : 1;
153 UINT32 TDTokenMaxLen : 11;
154 UINT32 TDBufferPtr;
155 } TD;
156
157 typedef struct {
158 TD TDData;
159 UINT8 *PtrTDBuffer;
160 VOID *PtrNextTD;
161 VOID *PtrNextQH;
162 UINT16 TDBufferLength;
163 UINT16 Reserved;
164 } TD_STRUCT;
165
166 #pragma pack()
167
168 typedef struct _MEMORY_MANAGE_HEADER MEMORY_MANAGE_HEADER;
169
170 struct _MEMORY_MANAGE_HEADER {
171 UINT8 *BitArrayPtr;
172 UINTN BitArraySizeInBytes;
173 UINT8 *MemoryBlockPtr;
174 UINTN MemoryBlockSizeInBytes;
175 MEMORY_MANAGE_HEADER *Next;
176 };
177
178 #define USB_UHC_DEV_SIGNATURE SIGNATURE_32 ('p', 'u', 'h', 'c')
179 typedef struct {
180 UINTN Signature;
181 PEI_USB_HOST_CONTROLLER_PPI UsbHostControllerPpi;
182 EDKII_IOMMU_PPI *IoMmu;
183 EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
184 //
185 // EndOfPei callback is used to stop the UHC DMA operation
186 // after exit PEI phase.
187 //
188 EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;
189
190 UINT32 UsbHostControllerBaseAddress;
191 FRAMELIST_ENTRY *FrameListEntry;
192 QH_STRUCT *ConfigQH;
193 QH_STRUCT *BulkQH;
194 //
195 // Header1 used for QH,TD memory blocks management
196 //
197 MEMORY_MANAGE_HEADER *Header1;
198
199 } USB_UHC_DEV;
200
201 #define PEI_RECOVERY_USB_UHC_DEV_FROM_UHCI_THIS(a) CR (a, USB_UHC_DEV, UsbHostControllerPpi, USB_UHC_DEV_SIGNATURE)
202 #define PEI_RECOVERY_USB_UHC_DEV_FROM_THIS_NOTIFY(a) CR (a, USB_UHC_DEV, EndOfPeiNotifyList, USB_UHC_DEV_SIGNATURE)
203
204 /**
205 Submits control transfer to a target USB device.
206
207 @param PeiServices The pointer of EFI_PEI_SERVICES.
208 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.
209 @param DeviceAddress The target device address.
210 @param DeviceSpeed Target device speed.
211 @param MaximumPacketLength Maximum packet size the default control transfer
212 endpoint is capable of sending or receiving.
213 @param Request USB device request to send.
214 @param TransferDirection Specifies the data direction for the data stage.
215 @param Data Data buffer to be transmitted or received from USB device.
216 @param DataLength The size (in bytes) of the data buffer.
217 @param TimeOut Indicates the maximum timeout, in millisecond.
218 @param TransferResult Return the result of this control transfer.
219
220 @retval EFI_SUCCESS Transfer was completed successfully.
221 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resources.
222 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
223 @retval EFI_TIMEOUT Transfer failed due to timeout.
224 @retval EFI_DEVICE_ERROR Transfer failed due to host controller or device error.
225
226 **/
227 EFI_STATUS
228 EFIAPI
229 UhcControlTransfer (
230 IN EFI_PEI_SERVICES **PeiServices,
231 IN PEI_USB_HOST_CONTROLLER_PPI * This,
232 IN UINT8 DeviceAddress,
233 IN UINT8 DeviceSpeed,
234 IN UINT8 MaximumPacketLength,
235 IN EFI_USB_DEVICE_REQUEST * Request,
236 IN EFI_USB_DATA_DIRECTION TransferDirection,
237 IN OUT VOID *Data OPTIONAL,
238 IN OUT UINTN *DataLength OPTIONAL,
239 IN UINTN TimeOut,
240 OUT UINT32 *TransferResult
241 );
242
243 /**
244 Submits bulk transfer to a bulk endpoint of a USB device.
245
246 @param PeiServices The pointer of EFI_PEI_SERVICES.
247 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.
248 @param DeviceAddress Target device address.
249 @param EndPointAddress Endpoint number and its direction in bit 7.
250 @param MaximumPacketLength Maximum packet size the endpoint is capable of
251 sending or receiving.
252 @param Data Array of pointers to the buffers of data to transmit
253 from or receive into.
254 @param DataLength The lenght of the data buffer.
255 @param DataToggle On input, the initial data toggle for the transfer;
256 On output, it is updated to to next data toggle to use of
257 the subsequent bulk transfer.
258 @param TimeOut Indicates the maximum time, in millisecond, which the
259 transfer is allowed to complete.
260 @param TransferResult A pointer to the detailed result information of the
261 bulk transfer.
262
263 @retval EFI_SUCCESS The transfer was completed successfully.
264 @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.
265 @retval EFI_INVALID_PARAMETER Parameters are invalid.
266 @retval EFI_TIMEOUT The transfer failed due to timeout.
267 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
268
269 **/
270 EFI_STATUS
271 EFIAPI
272 UhcBulkTransfer (
273 IN EFI_PEI_SERVICES **PeiServices,
274 IN PEI_USB_HOST_CONTROLLER_PPI *This,
275 IN UINT8 DeviceAddress,
276 IN UINT8 EndPointAddress,
277 IN UINT8 MaximumPacketLength,
278 IN OUT VOID *Data,
279 IN OUT UINTN *DataLength,
280 IN OUT UINT8 *DataToggle,
281 IN UINTN TimeOut,
282 OUT UINT32 *TransferResult
283 );
284
285 /**
286 Retrieves the number of root hub ports.
287
288 @param[in] PeiServices The pointer to the PEI Services Table.
289 @param[in] This The pointer to this instance of the
290 PEI_USB_HOST_CONTROLLER_PPI.
291 @param[out] PortNumber The pointer to the number of the root hub ports.
292
293 @retval EFI_SUCCESS The port number was retrieved successfully.
294 @retval EFI_INVALID_PARAMETER PortNumber is NULL.
295
296 **/
297 EFI_STATUS
298 EFIAPI
299 UhcGetRootHubPortNumber (
300 IN EFI_PEI_SERVICES **PeiServices,
301 IN PEI_USB_HOST_CONTROLLER_PPI *This,
302 OUT UINT8 *PortNumber
303 );
304
305 /**
306 Retrieves the current status of a USB root hub port.
307
308 @param PeiServices The pointer of EFI_PEI_SERVICES.
309 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.
310 @param PortNumber The root hub port to retrieve the state from.
311 @param PortStatus Variable to receive the port state.
312
313 @retval EFI_SUCCESS The status of the USB root hub port specified.
314 by PortNumber was returned in PortStatus.
315 @retval EFI_INVALID_PARAMETER PortNumber is invalid.
316
317 **/
318 EFI_STATUS
319 EFIAPI
320 UhcGetRootHubPortStatus (
321 IN EFI_PEI_SERVICES **PeiServices,
322 IN PEI_USB_HOST_CONTROLLER_PPI *This,
323 IN UINT8 PortNumber,
324 OUT EFI_USB_PORT_STATUS *PortStatus
325 );
326
327 /**
328 Sets a feature for the specified root hub port.
329
330 @param PeiServices The pointer of EFI_PEI_SERVICES
331 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI
332 @param PortNumber Root hub port to set.
333 @param PortFeature Feature to set.
334
335 @retval EFI_SUCCESS The feature specified by PortFeature was set.
336 @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.
337 @retval EFI_TIMEOUT The time out occurred.
338
339 **/
340 EFI_STATUS
341 EFIAPI
342 UhcSetRootHubPortFeature (
343 IN EFI_PEI_SERVICES **PeiServices,
344 IN PEI_USB_HOST_CONTROLLER_PPI *This,
345 IN UINT8 PortNumber,
346 IN EFI_USB_PORT_FEATURE PortFeature
347 );
348
349 /**
350 Clears a feature for the specified root hub port.
351
352 @param PeiServices The pointer of EFI_PEI_SERVICES.
353 @param This The pointer of PEI_USB_HOST_CONTROLLER_PPI.
354 @param PortNumber Specifies the root hub port whose feature
355 is requested to be cleared.
356 @param PortFeature Indicates the feature selector associated with the
357 feature clear request.
358
359 @retval EFI_SUCCESS The feature specified by PortFeature was cleared
360 for the USB root hub port specified by PortNumber.
361 @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.
362
363 **/
364 EFI_STATUS
365 EFIAPI
366 UhcClearRootHubPortFeature (
367 IN EFI_PEI_SERVICES **PeiServices,
368 IN PEI_USB_HOST_CONTROLLER_PPI *This,
369 IN UINT8 PortNumber,
370 IN EFI_USB_PORT_FEATURE PortFeature
371 );
372
373 /**
374 Initialize UHCI.
375
376 @param UhcDev UHCI Device.
377
378 @retval EFI_SUCCESS UHCI successfully initialized.
379 @retval EFI_OUT_OF_RESOURCES Resource can not be allocated.
380
381 **/
382 EFI_STATUS
383 InitializeUsbHC (
384 IN USB_UHC_DEV *UhcDev
385 );
386
387 /**
388 Create Frame List Structure.
389
390 @param UhcDev UHCI device.
391
392 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
393 @retval EFI_SUCCESS Success.
394
395 **/
396 EFI_STATUS
397 CreateFrameList (
398 USB_UHC_DEV *UhcDev
399 );
400
401 /**
402 Read a 16bit width data from Uhc HC IO space register.
403
404 @param UhcDev The UHCI device.
405 @param Port The IO space address of the register.
406
407 @retval the register content read.
408
409 **/
410 UINT16
411 USBReadPortW (
412 IN USB_UHC_DEV *UhcDev,
413 IN UINT32 Port
414 );
415
416 /**
417 Write a 16bit width data into Uhc HC IO space register.
418
419 @param UhcDev The UHCI device.
420 @param Port The IO space address of the register.
421 @param Data The data written into the register.
422
423 **/
424 VOID
425 USBWritePortW (
426 IN USB_UHC_DEV *UhcDev,
427 IN UINT32 Port,
428 IN UINT16 Data
429 );
430
431 /**
432 Write a 32bit width data into Uhc HC IO space register.
433
434 @param UhcDev The UHCI device.
435 @param Port The IO space address of the register.
436 @param Data The data written into the register.
437
438 **/
439 VOID
440 USBWritePortDW (
441 IN USB_UHC_DEV *UhcDev,
442 IN UINT32 Port,
443 IN UINT32 Data
444 );
445
446 /**
447 Clear the content of UHCI's Status Register.
448
449 @param UhcDev The UHCI device.
450 @param StatusAddr The IO space address of the register.
451
452 **/
453 VOID
454 ClearStatusReg (
455 IN USB_UHC_DEV *UhcDev,
456 IN UINT32 StatusAddr
457 );
458
459 /**
460 Check whether the host controller operates well.
461
462 @param UhcDev The UHCI device.
463 @param StatusRegAddr The io address of status register.
464
465 @retval TRUE Host controller is working.
466 @retval FALSE Host controller is halted or system error.
467
468 **/
469 BOOLEAN
470 IsStatusOK (
471 IN USB_UHC_DEV *UhcDev,
472 IN UINT32 StatusRegAddr
473 );
474
475 /**
476 Set Frame List Base Address.
477
478 @param UhcDev The UHCI device.
479 @param FrameListRegAddr The address of frame list register.
480 @param Addr The address of frame list table.
481
482 **/
483 VOID
484 SetFrameListBaseAddress (
485 IN USB_UHC_DEV *UhcDev,
486 IN UINT32 FrameListRegAddr,
487 IN UINT32 Addr
488 );
489
490 /**
491 Create QH and initialize.
492
493 @param UhcDev The UHCI device.
494 @param PtrQH Place to store QH_STRUCT pointer.
495
496 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
497 @retval EFI_SUCCESS Success.
498
499 **/
500 EFI_STATUS
501 CreateQH (
502 IN USB_UHC_DEV *UhcDev,
503 OUT QH_STRUCT **PtrQH
504 );
505
506 /**
507 Set the horizontal link pointer in QH.
508
509 @param PtrQH Place to store QH_STRUCT pointer.
510 @param PtrNext Place to the next QH_STRUCT.
511
512 **/
513 VOID
514 SetQHHorizontalLinkPtr (
515 IN QH_STRUCT *PtrQH,
516 IN VOID *PtrNext
517 );
518
519 /**
520 Set a QH or TD horizontally to be connected with a specific QH.
521
522 @param PtrQH Place to store QH_STRUCT pointer.
523 @param IsQH Specify QH or TD is connected.
524
525 **/
526 VOID
527 SetQHHorizontalQHorTDSelect (
528 IN QH_STRUCT *PtrQH,
529 IN BOOLEAN IsQH
530 );
531
532 /**
533 Set the horizontal validor bit in QH.
534
535 @param PtrQH Place to store QH_STRUCT pointer.
536 @param IsValid Specify the horizontal linker is valid or not.
537
538 **/
539 VOID
540 SetQHHorizontalValidorInvalid (
541 IN QH_STRUCT *PtrQH,
542 IN BOOLEAN IsValid
543 );
544
545 /**
546 Set the vertical link pointer in QH.
547
548 @param PtrQH Place to store QH_STRUCT pointer.
549 @param PtrNext Place to the next QH_STRUCT.
550
551 **/
552 VOID
553 SetQHVerticalLinkPtr (
554 IN QH_STRUCT *PtrQH,
555 IN VOID *PtrNext
556 );
557
558 /**
559 Set a QH or TD vertically to be connected with a specific QH.
560
561 @param PtrQH Place to store QH_STRUCT pointer.
562 @param IsQH Specify QH or TD is connected.
563
564 **/
565 VOID
566 SetQHVerticalQHorTDSelect (
567 IN QH_STRUCT *PtrQH,
568 IN BOOLEAN IsQH
569 );
570
571 /**
572 Set the vertical validor bit in QH.
573
574 @param PtrQH Place to store QH_STRUCT pointer.
575 @param IsValid Specify the vertical linker is valid or not.
576
577 **/
578 VOID
579 SetQHVerticalValidorInvalid (
580 IN QH_STRUCT *PtrQH,
581 IN BOOLEAN IsValid
582 );
583
584
585 /**
586 Allocate TD or QH Struct.
587
588 @param UhcDev The UHCI device.
589 @param Size The size of allocation.
590 @param PtrStruct Place to store TD_STRUCT pointer.
591
592 @return EFI_SUCCESS Allocate successfully.
593 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
594
595 **/
596 EFI_STATUS
597 AllocateTDorQHStruct (
598 IN USB_UHC_DEV *UhcDev,
599 IN UINT32 Size,
600 OUT VOID **PtrStruct
601 );
602
603 /**
604 Create a TD Struct.
605
606 @param UhcDev The UHCI device.
607 @param PtrTD Place to store TD_STRUCT pointer.
608
609 @return EFI_SUCCESS Allocate successfully.
610 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
611
612 **/
613 EFI_STATUS
614 CreateTD (
615 IN USB_UHC_DEV *UhcDev,
616 OUT TD_STRUCT **PtrTD
617 );
618
619 /**
620 Generate Setup Stage TD.
621
622 @param UhcDev The UHCI device.
623 @param DevAddr Device address.
624 @param Endpoint Endpoint number.
625 @param DeviceSpeed Device Speed.
626 @param DevRequest CPU memory address of request structure buffer to transfer.
627 @param RequestPhy PCI memory address of request structure buffer to transfer.
628 @param RequestLen Request length.
629 @param PtrTD TD_STRUCT generated.
630
631 @return EFI_SUCCESS Generate setup stage TD successfully.
632 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
633
634 **/
635 EFI_STATUS
636 GenSetupStageTD (
637 IN USB_UHC_DEV *UhcDev,
638 IN UINT8 DevAddr,
639 IN UINT8 Endpoint,
640 IN UINT8 DeviceSpeed,
641 IN UINT8 *DevRequest,
642 IN UINT8 *RequestPhy,
643 IN UINT8 RequestLen,
644 OUT TD_STRUCT **PtrTD
645 );
646
647 /**
648 Generate Data Stage TD.
649
650 @param UhcDev The UHCI device.
651 @param DevAddr Device address.
652 @param Endpoint Endpoint number.
653 @param PtrData CPU memory address of user data buffer to transfer.
654 @param DataPhy PCI memory address of user data buffer to transfer.
655 @param Len Data length.
656 @param PktID PacketID.
657 @param Toggle Data toggle value.
658 @param DeviceSpeed Device Speed.
659 @param PtrTD TD_STRUCT generated.
660
661 @return EFI_SUCCESS Generate data stage TD successfully.
662 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
663
664 **/
665 EFI_STATUS
666 GenDataTD (
667 IN USB_UHC_DEV *UhcDev,
668 IN UINT8 DevAddr,
669 IN UINT8 Endpoint,
670 IN UINT8 *PtrData,
671 IN UINT8 *DataPhy,
672 IN UINT8 Len,
673 IN UINT8 PktID,
674 IN UINT8 Toggle,
675 IN UINT8 DeviceSpeed,
676 OUT TD_STRUCT **PtrTD
677 );
678
679 /**
680 Generate Status Stage TD.
681
682 @param UhcDev The UHCI device.
683 @param DevAddr Device address.
684 @param Endpoint Endpoint number.
685 @param PktID PacketID.
686 @param DeviceSpeed Device Speed.
687 @param PtrTD TD_STRUCT generated.
688
689 @return EFI_SUCCESS Generate status stage TD successfully.
690 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resource.
691
692 **/
693 EFI_STATUS
694 CreateStatusTD (
695 IN USB_UHC_DEV *UhcDev,
696 IN UINT8 DevAddr,
697 IN UINT8 Endpoint,
698 IN UINT8 PktID,
699 IN UINT8 DeviceSpeed,
700 OUT TD_STRUCT **PtrTD
701 );
702
703 /**
704 Set the link pointer validor bit in TD.
705
706 @param PtrTDStruct Place to store TD_STRUCT pointer.
707 @param IsValid Specify the linker pointer is valid or not.
708
709 **/
710 VOID
711 SetTDLinkPtrValidorInvalid (
712 IN TD_STRUCT *PtrTDStruct,
713 IN BOOLEAN IsValid
714 );
715
716 /**
717 Set the Link Pointer pointing to a QH or TD.
718
719 @param PtrTDStruct Place to store TD_STRUCT pointer.
720 @param IsQH Specify QH or TD is connected.
721
722 **/
723 VOID
724 SetTDLinkPtrQHorTDSelect (
725 IN TD_STRUCT *PtrTDStruct,
726 IN BOOLEAN IsQH
727 );
728
729 /**
730 Set the traverse is depth-first or breadth-first.
731
732 @param PtrTDStruct Place to store TD_STRUCT pointer.
733 @param IsDepth Specify the traverse is depth-first or breadth-first.
734
735 **/
736 VOID
737 SetTDLinkPtrDepthorBreadth (
738 IN TD_STRUCT *PtrTDStruct,
739 IN BOOLEAN IsDepth
740 );
741
742 /**
743 Set TD Link Pointer in TD.
744
745 @param PtrTDStruct Place to store TD_STRUCT pointer.
746 @param PtrNext Place to the next TD_STRUCT.
747
748 **/
749 VOID
750 SetTDLinkPtr (
751 IN TD_STRUCT *PtrTDStruct,
752 IN VOID *PtrNext
753 );
754
755 /**
756 Get TD Link Pointer.
757
758 @param PtrTDStruct Place to store TD_STRUCT pointer.
759
760 @retval Get TD Link Pointer in TD.
761
762 **/
763 VOID*
764 GetTDLinkPtr (
765 IN TD_STRUCT *PtrTDStruct
766 );
767
768
769 /**
770 Enable/Disable short packet detection mechanism.
771
772 @param PtrTDStruct Place to store TD_STRUCT pointer.
773 @param IsEnable Enable or disable short packet detection mechanism.
774
775 **/
776 VOID
777 EnableorDisableTDShortPacket (
778 IN TD_STRUCT *PtrTDStruct,
779 IN BOOLEAN IsEnable
780 );
781
782 /**
783 Set the max error counter in TD.
784
785 @param PtrTDStruct Place to store TD_STRUCT pointer.
786 @param MaxErrors The number of allowable error.
787
788 **/
789 VOID
790 SetTDControlErrorCounter (
791 IN TD_STRUCT *PtrTDStruct,
792 IN UINT8 MaxErrors
793 );
794
795 /**
796 Set the TD is targeting a low-speed device or not.
797
798 @param PtrTDStruct Place to store TD_STRUCT pointer.
799 @param IsLowSpeedDevice Whether The device is low-speed.
800
801 **/
802 VOID
803 SetTDLoworFullSpeedDevice (
804 IN TD_STRUCT *PtrTDStruct,
805 IN BOOLEAN IsLowSpeedDevice
806 );
807
808 /**
809 Set the TD is isochronous transfer type or not.
810
811 @param PtrTDStruct Place to store TD_STRUCT pointer.
812 @param IsIsochronous Whether the transaction isochronous transfer type.
813
814 **/
815 VOID
816 SetTDControlIsochronousorNot (
817 IN TD_STRUCT *PtrTDStruct,
818 IN BOOLEAN IsIsochronous
819 );
820
821 /**
822 Set if UCHI should issue an interrupt on completion of the frame
823 in which this TD is executed
824
825 @param PtrTDStruct Place to store TD_STRUCT pointer.
826 @param IsSet Whether HC should issue an interrupt on completion.
827
828 **/
829 VOID
830 SetorClearTDControlIOC (
831 IN TD_STRUCT *PtrTDStruct,
832 IN BOOLEAN IsSet
833 );
834
835 /**
836 Set if the TD is active and can be executed.
837
838 @param PtrTDStruct Place to store TD_STRUCT pointer.
839 @param IsActive Whether the TD is active and can be executed.
840
841 **/
842 VOID
843 SetTDStatusActiveorInactive (
844 IN TD_STRUCT *PtrTDStruct,
845 IN BOOLEAN IsActive
846 );
847
848 /**
849 Specifies the maximum number of data bytes allowed for the transfer.
850
851 @param PtrTDStruct Place to store TD_STRUCT pointer.
852 @param MaxLen The maximum number of data bytes allowed.
853
854 @retval The allowed maximum number of data.
855 **/
856 UINT16
857 SetTDTokenMaxLength (
858 IN TD_STRUCT *PtrTDStruct,
859 IN UINT16 MaxLen
860 );
861
862 /**
863 Set the data toggle bit to DATA1.
864
865 @param PtrTDStruct Place to store TD_STRUCT pointer.
866
867 **/
868 VOID
869 SetTDTokenDataToggle1 (
870 IN TD_STRUCT *PtrTDStruct
871 );
872
873 /**
874 Set the data toggle bit to DATA0.
875
876 @param PtrTDStruct Place to store TD_STRUCT pointer.
877
878 **/
879 VOID
880 SetTDTokenDataToggle0 (
881 IN TD_STRUCT *PtrTDStruct
882 );
883
884 /**
885 Set EndPoint Number the TD is targeting at.
886
887 @param PtrTDStruct Place to store TD_STRUCT pointer.
888 @param EndPoint The Endport number of the target.
889
890 **/
891 VOID
892 SetTDTokenEndPoint (
893 IN TD_STRUCT *PtrTDStruct,
894 IN UINTN EndPoint
895 );
896
897 /**
898 Set Device Address the TD is targeting at.
899
900 @param PtrTDStruct Place to store TD_STRUCT pointer.
901 @param DevAddr The Device Address of the target.
902
903 **/
904 VOID
905 SetTDTokenDeviceAddress (
906 IN TD_STRUCT *PtrTDStruct,
907 IN UINTN DevAddr
908 );
909
910 /**
911 Set Packet Identification the TD is targeting at.
912
913 @param PtrTDStruct Place to store TD_STRUCT pointer.
914 @param PacketID The Packet Identification of the target.
915
916 **/
917 VOID
918 SetTDTokenPacketID (
919 IN TD_STRUCT *PtrTDStruct,
920 IN UINT8 PacketID
921 );
922
923 /**
924 Set the beginning address of the data buffer that will be used
925 during the transaction.
926
927 @param PtrTDStruct Place to store TD_STRUCT pointer.
928
929 **/
930 VOID
931 SetTDDataBuffer (
932 IN TD_STRUCT *PtrTDStruct
933 );
934
935 /**
936 Detect whether the TD is active.
937
938 @param PtrTDStruct Place to store TD_STRUCT pointer.
939
940 @retval The TD is active or not.
941
942 **/
943 BOOLEAN
944 IsTDStatusActive (
945 IN TD_STRUCT *PtrTDStruct
946 );
947
948 /**
949 Detect whether the TD is stalled.
950
951 @param PtrTDStruct Place to store TD_STRUCT pointer.
952
953 @retval The TD is stalled or not.
954
955 **/
956 BOOLEAN
957 IsTDStatusStalled (
958 IN TD_STRUCT *PtrTDStruct
959 );
960
961 /**
962 Detect whether Data Buffer Error is happened.
963
964 @param PtrTDStruct Place to store TD_STRUCT pointer.
965
966 @retval The Data Buffer Error is happened or not.
967
968 **/
969 BOOLEAN
970 IsTDStatusBufferError (
971 IN TD_STRUCT *PtrTDStruct
972 );
973
974 /**
975 Detect whether Babble Error is happened.
976
977 @param PtrTDStruct Place to store TD_STRUCT pointer.
978
979 @retval The Babble Error is happened or not.
980
981 **/
982 BOOLEAN
983 IsTDStatusBabbleError (
984 IN TD_STRUCT *PtrTDStruct
985 );
986
987 /**
988 Detect whether NAK is received.
989
990 @param PtrTDStruct Place to store TD_STRUCT pointer.
991
992 @retval The NAK is received or not.
993
994 **/
995 BOOLEAN
996 IsTDStatusNAKReceived (
997 IN TD_STRUCT *PtrTDStruct
998 );
999
1000 /**
1001 Detect whether CRC/Time Out Error is encountered.
1002
1003 @param PtrTDStruct Place to store TD_STRUCT pointer.
1004
1005 @retval The CRC/Time Out Error is encountered or not.
1006
1007 **/
1008 BOOLEAN
1009 IsTDStatusCRCTimeOutError (
1010 IN TD_STRUCT *PtrTDStruct
1011 );
1012
1013 /**
1014 Detect whether Bitstuff Error is received.
1015
1016 @param PtrTDStruct Place to store TD_STRUCT pointer.
1017
1018 @retval The Bitstuff Error is received or not.
1019
1020 **/
1021 BOOLEAN
1022 IsTDStatusBitStuffError (
1023 IN TD_STRUCT *PtrTDStruct
1024 );
1025
1026 /**
1027 Retrieve the actual number of bytes that were tansferred.
1028
1029 @param PtrTDStruct Place to store TD_STRUCT pointer.
1030
1031 @retval The actual number of bytes that were tansferred.
1032
1033 **/
1034 UINT16
1035 GetTDStatusActualLength (
1036 IN TD_STRUCT *PtrTDStruct
1037 );
1038
1039 /**
1040 Retrieve the information of whether the Link Pointer field is valid or not.
1041
1042 @param PtrTDStruct Place to store TD_STRUCT pointer.
1043
1044 @retval The linker pointer field is valid or not.
1045
1046 **/
1047 BOOLEAN
1048 GetTDLinkPtrValidorInvalid (
1049 IN TD_STRUCT *PtrTDStruct
1050 );
1051
1052 /**
1053 Count TD Number from PtrFirstTD.
1054
1055 @param PtrFirstTD Place to store TD_STRUCT pointer.
1056
1057 @retval The queued TDs number.
1058
1059 **/
1060 UINTN
1061 CountTDsNumber (
1062 IN TD_STRUCT *PtrFirstTD
1063 );
1064
1065 /**
1066 Link TD To QH.
1067
1068 @param PtrQH Place to store QH_STRUCT pointer.
1069 @param PtrTD Place to store TD_STRUCT pointer.
1070
1071 **/
1072 VOID
1073 LinkTDToQH (
1074 IN QH_STRUCT *PtrQH,
1075 IN TD_STRUCT *PtrTD
1076 );
1077
1078 /**
1079 Link TD To TD.
1080
1081 @param PtrPreTD Place to store TD_STRUCT pointer.
1082 @param PtrTD Place to store TD_STRUCT pointer.
1083
1084 **/
1085 VOID
1086 LinkTDToTD (
1087 IN TD_STRUCT *PtrPreTD,
1088 IN TD_STRUCT *PtrTD
1089 );
1090
1091 /**
1092 Execute Control Transfer.
1093
1094 @param UhcDev The UCHI device.
1095 @param PtrTD A pointer to TD_STRUCT data.
1096 @param ActualLen Actual transfer Length.
1097 @param TimeOut TimeOut value.
1098 @param TransferResult Transfer Result.
1099
1100 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1101 @return EFI_TIMEOUT The transfer failed due to time out.
1102 @return EFI_SUCCESS The transfer finished OK.
1103
1104 **/
1105 EFI_STATUS
1106 ExecuteControlTransfer (
1107 IN USB_UHC_DEV *UhcDev,
1108 IN TD_STRUCT *PtrTD,
1109 OUT UINTN *ActualLen,
1110 IN UINTN TimeOut,
1111 OUT UINT32 *TransferResult
1112 );
1113
1114 /**
1115 Execute Bulk Transfer.
1116
1117 @param UhcDev The UCHI device.
1118 @param PtrTD A pointer to TD_STRUCT data.
1119 @param ActualLen Actual transfer Length.
1120 @param DataToggle DataToggle value.
1121 @param TimeOut TimeOut value.
1122 @param TransferResult Transfer Result.
1123
1124 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1125 @return EFI_TIMEOUT The transfer failed due to time out.
1126 @return EFI_SUCCESS The transfer finished OK.
1127
1128 **/
1129 EFI_STATUS
1130 ExecBulkTransfer (
1131 IN USB_UHC_DEV *UhcDev,
1132 IN TD_STRUCT *PtrTD,
1133 IN OUT UINTN *ActualLen,
1134 IN UINT8 *DataToggle,
1135 IN UINTN TimeOut,
1136 OUT UINT32 *TransferResult
1137 );
1138
1139 /**
1140 Delete Queued TDs.
1141
1142 @param UhcDev The UCHI device.
1143 @param PtrFirstTD Place to store TD_STRUCT pointer.
1144
1145 **/
1146 VOID
1147 DeleteQueuedTDs (
1148 IN USB_UHC_DEV *UhcDev,
1149 IN TD_STRUCT *PtrFirstTD
1150 );
1151
1152 /**
1153 Check TDs Results.
1154
1155 @param PtrTD A pointer to TD_STRUCT data.
1156 @param Result The result to return.
1157 @param ErrTDPos The Error TD position.
1158 @param ActualTransferSize Actual transfer size.
1159
1160 @retval The TD is executed successfully or not.
1161
1162 **/
1163 BOOLEAN
1164 CheckTDsResults (
1165 IN TD_STRUCT *PtrTD,
1166 OUT UINT32 *Result,
1167 OUT UINTN *ErrTDPos,
1168 OUT UINTN *ActualTransferSize
1169 );
1170
1171 /**
1172 Create Memory Block.
1173
1174 @param UhcDev The UCHI device.
1175 @param MemoryHeader The Pointer to allocated memory block.
1176 @param MemoryBlockSizeInPages The page size of memory block to be allocated.
1177
1178 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
1179 @retval EFI_SUCCESS Success.
1180
1181 **/
1182 EFI_STATUS
1183 CreateMemoryBlock (
1184 IN USB_UHC_DEV *UhcDev,
1185 OUT MEMORY_MANAGE_HEADER **MemoryHeader,
1186 IN UINTN MemoryBlockSizeInPages
1187 );
1188
1189 /**
1190 Initialize UHCI memory management.
1191
1192 @param UhcDev The UCHI device.
1193
1194 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
1195 @retval EFI_SUCCESS Success.
1196
1197 **/
1198 EFI_STATUS
1199 InitializeMemoryManagement (
1200 IN USB_UHC_DEV *UhcDev
1201 );
1202
1203 /**
1204 Initialize UHCI memory management.
1205
1206 @param UhcDev The UCHI device.
1207 @param Pool Buffer pointer to store the buffer pointer.
1208 @param AllocSize The size of the pool to be allocated.
1209
1210 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
1211 @retval EFI_SUCCESS Success.
1212
1213 **/
1214 EFI_STATUS
1215 UhcAllocatePool (
1216 IN USB_UHC_DEV *UhcDev,
1217 OUT UINT8 **Pool,
1218 IN UINTN AllocSize
1219 );
1220
1221 /**
1222 Alloc Memory In MemoryBlock.
1223
1224 @param MemoryHeader The pointer to memory manage header.
1225 @param Pool Buffer pointer to store the buffer pointer.
1226 @param NumberOfMemoryUnit The size of the pool to be allocated.
1227
1228 @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources.
1229 @retval EFI_SUCCESS Success.
1230
1231 **/
1232 EFI_STATUS
1233 AllocMemInMemoryBlock (
1234 IN MEMORY_MANAGE_HEADER *MemoryHeader,
1235 OUT VOID **Pool,
1236 IN UINTN NumberOfMemoryUnit
1237 );
1238
1239 /**
1240 Uhci Free Pool.
1241
1242 @param UhcDev The UHCI device.
1243 @param Pool A pointer to store the buffer address.
1244 @param AllocSize The size of the pool to be freed.
1245
1246 **/
1247 VOID
1248 UhcFreePool (
1249 IN USB_UHC_DEV *UhcDev,
1250 IN UINT8 *Pool,
1251 IN UINTN AllocSize
1252 );
1253
1254 /**
1255 Insert a new memory header into list.
1256
1257 @param MemoryHeader A pointer to the memory header list.
1258 @param NewMemoryHeader A new memory header to be inserted into the list.
1259
1260 **/
1261 VOID
1262 InsertMemoryHeaderToList (
1263 IN MEMORY_MANAGE_HEADER *MemoryHeader,
1264 IN MEMORY_MANAGE_HEADER *NewMemoryHeader
1265 );
1266
1267
1268 /**
1269 Map address of request structure buffer.
1270
1271 @param Uhc The UHCI device.
1272 @param Request The user request buffer.
1273 @param MappedAddr Mapped address of request.
1274 @param Map Identificaion of this mapping to return.
1275
1276 @return EFI_SUCCESS Success.
1277 @return EFI_DEVICE_ERROR Fail to map the user request.
1278
1279 **/
1280 EFI_STATUS
1281 UhciMapUserRequest (
1282 IN USB_UHC_DEV *Uhc,
1283 IN OUT VOID *Request,
1284 OUT UINT8 **MappedAddr,
1285 OUT VOID **Map
1286 );
1287
1288 /**
1289 Map address of user data buffer.
1290
1291 @param Uhc The UHCI device.
1292 @param Direction Direction of the data transfer.
1293 @param Data The user data buffer.
1294 @param Len Length of the user data.
1295 @param PktId Packet identificaion.
1296 @param MappedAddr Mapped address to return.
1297 @param Map Identificaion of this mapping to return.
1298
1299 @return EFI_SUCCESS Success.
1300 @return EFI_DEVICE_ERROR Fail to map the user data.
1301
1302 **/
1303 EFI_STATUS
1304 UhciMapUserData (
1305 IN USB_UHC_DEV *Uhc,
1306 IN EFI_USB_DATA_DIRECTION Direction,
1307 IN VOID *Data,
1308 IN OUT UINTN *Len,
1309 OUT UINT8 *PktId,
1310 OUT UINT8 **MappedAddr,
1311 OUT VOID **Map
1312 );
1313
1314 /**
1315 Provides the controller-specific addresses required to access system memory from a
1316 DMA bus master.
1317
1318 @param IoMmu Pointer to IOMMU PPI.
1319 @param Operation Indicates if the bus master is going to read or write to system memory.
1320 @param HostAddress The system memory address to map to the PCI controller.
1321 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
1322 that were mapped.
1323 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
1324 access the hosts HostAddress.
1325 @param Mapping A resulting value to pass to Unmap().
1326
1327 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
1328 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
1329 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1330 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1331 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
1332
1333 **/
1334 EFI_STATUS
1335 IoMmuMap (
1336 IN EDKII_IOMMU_PPI *IoMmu,
1337 IN EDKII_IOMMU_OPERATION Operation,
1338 IN VOID *HostAddress,
1339 IN OUT UINTN *NumberOfBytes,
1340 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
1341 OUT VOID **Mapping
1342 );
1343
1344 /**
1345 Completes the Map() operation and releases any corresponding resources.
1346
1347 @param IoMmu Pointer to IOMMU PPI.
1348 @param Mapping The mapping value returned from Map().
1349
1350 **/
1351 VOID
1352 IoMmuUnmap (
1353 IN EDKII_IOMMU_PPI *IoMmu,
1354 IN VOID *Mapping
1355 );
1356
1357 /**
1358 Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
1359 OperationBusMasterCommonBuffer64 mapping.
1360
1361 @param IoMmu Pointer to IOMMU PPI.
1362 @param Pages The number of pages to allocate.
1363 @param HostAddress A pointer to store the base system memory address of the
1364 allocated range.
1365 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
1366 access the hosts HostAddress.
1367 @param Mapping A resulting value to pass to Unmap().
1368
1369 @retval EFI_SUCCESS The requested memory pages were allocated.
1370 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
1371 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
1372 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1373 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
1374
1375 **/
1376 EFI_STATUS
1377 IoMmuAllocateBuffer (
1378 IN EDKII_IOMMU_PPI *IoMmu,
1379 IN UINTN Pages,
1380 OUT VOID **HostAddress,
1381 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
1382 OUT VOID **Mapping
1383 );
1384
1385
1386 /**
1387 Initialize IOMMU.
1388
1389 @param IoMmu Pointer to pointer to IOMMU PPI.
1390
1391 **/
1392 VOID
1393 IoMmuInit (
1394 OUT EDKII_IOMMU_PPI **IoMmu
1395 );
1396
1397 #endif