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1 /** @file
2
3 XHCI transfer scheduling routines.
4
5 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include "Xhci.h"
17
18 /**
19 Allocates a buffer of a certain pool type at a specified alignment.
20
21 Allocates the number bytes specified by AllocationSize of a certain pool type with an alignment
22 specified by Alignment. The allocated buffer is returned. If AllocationSize is 0, then a valid
23 buffer of 0 size is returned. If there is not enough memory at the specified alignment remaining
24 to satisfy the request, then NULL is returned.
25 If Alignment is not a power of two and Alignment is not zero, then ASSERT().
26
27 @param PoolType The type of pool to allocate.
28 @param AllocationSize The number of bytes to allocate.
29 @param Alignment The requested alignment of the allocation. Must be a power of two.
30 If Alignment is zero, then byte alignment is used.
31
32 @return A pointer to the allocated buffer or NULL if allocation fails.
33
34 **/
35 VOID *
36 InternalAllocateAlignedPool (
37 IN EFI_MEMORY_TYPE PoolType,
38 IN UINTN AllocationSize,
39 IN UINTN Alignment
40 )
41 {
42 VOID *RawAddress;
43 UINTN AlignedAddress;
44 UINTN AlignmentMask;
45 UINTN OverAllocationSize;
46 UINTN RealAllocationSize;
47 VOID **FreePointer;
48
49 //
50 // Alignment must be a power of two or zero.
51 //
52 ASSERT ((Alignment & (Alignment - 1)) == 0);
53
54 if (Alignment == 0) {
55 AlignmentMask = Alignment;
56 } else {
57 AlignmentMask = Alignment - 1;
58 }
59 //
60 // Calculate the extra memory size, over-allocate memory pool and get the aligned memory address.
61 //
62 OverAllocationSize = sizeof (RawAddress) + AlignmentMask;
63 RealAllocationSize = AllocationSize + OverAllocationSize;
64 //
65 // Make sure that AllocationSize plus OverAllocationSize does not overflow.
66 //
67 ASSERT (RealAllocationSize > AllocationSize);
68
69 RawAddress = NULL;
70 gBS->AllocatePool (PoolType, RealAllocationSize, &RawAddress);
71 if (RawAddress == NULL) {
72 return NULL;
73 }
74 AlignedAddress = ((UINTN) RawAddress + OverAllocationSize) & ~AlignmentMask;
75 //
76 // Save the original memory address just before the aligned address.
77 //
78 FreePointer = (VOID **)(AlignedAddress - sizeof (RawAddress));
79 *FreePointer = RawAddress;
80
81 return (VOID *) AlignedAddress;
82 }
83
84 /**
85 Allocates and zeros a buffer of a certain pool type at a specified alignment.
86
87 Allocates the number bytes specified by AllocationSize of a certain pool type with an alignment
88 specified by Alignment, clears the buffer with zeros, and returns a pointer to the allocated
89 buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there is not
90 enough memory at the specified alignment remaining to satisfy the request, then NULL is returned.
91 If Alignment is not a power of two and Alignment is not zero, then ASSERT().
92
93 @param PoolType The type of pool to allocate.
94 @param AllocationSize The number of bytes to allocate.
95 @param Alignment The requested alignment of the allocation. Must be a power of two.
96 If Alignment is zero, then byte alignment is used.
97
98 @return A pointer to the allocated buffer or NULL if allocation fails.
99
100 **/
101 VOID *
102 InternalAllocateAlignedZeroPool (
103 IN EFI_MEMORY_TYPE PoolType,
104 IN UINTN AllocationSize,
105 IN UINTN Alignment
106 )
107 {
108 VOID *Memory;
109 Memory = InternalAllocateAlignedPool (PoolType, AllocationSize, Alignment);
110 if (Memory != NULL) {
111 ZeroMem (Memory, AllocationSize);
112 }
113 return Memory;
114 }
115
116 /**
117 Allocates and zeros a buffer of type EfiBootServicesData at a specified alignment.
118
119 Allocates the number bytes specified by AllocationSize of type EfiBootServicesData with an
120 alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the
121 allocated buffer. If AllocationSize is 0, then a valid buffer of 0 size is returned. If there
122 is not enough memory at the specified alignment remaining to satisfy the request, then NULL is
123 returned.
124 If Alignment is not a power of two and Alignment is not zero, then ASSERT().
125
126 @param AllocationSize The number of bytes to allocate.
127 @param Alignment The requested alignment of the allocation. Must be a power of two.
128 If Alignment is zero, then byte alignment is used.
129
130 @return A pointer to the allocated buffer or NULL if allocation fails.
131
132 **/
133 VOID *
134 EFIAPI
135 AllocateAlignedZeroPool (
136 IN UINTN AllocationSize,
137 IN UINTN Alignment
138 )
139 {
140 return InternalAllocateAlignedZeroPool (EfiBootServicesData, AllocationSize, Alignment);
141 }
142
143 /**
144 Frees a buffer that was previously allocated with one of the aligned pool allocation functions
145 in the Memory Allocation Library.
146
147 Frees the buffer specified by Buffer. Buffer must have been allocated on a previous call to the
148 aligned pool allocation services of the Memory Allocation Library.
149 If Buffer was not allocated with an aligned pool allocation function in the Memory Allocation
150 Library, then ASSERT().
151
152 @param Buffer Pointer to the buffer to free.
153
154 **/
155 VOID
156 EFIAPI
157 FreeAlignedPool (
158 IN VOID *Buffer
159 )
160 {
161 VOID *RawAddress;
162 VOID **FreePointer;
163 EFI_STATUS Status;
164
165 //
166 // Get the pre-saved original address in the over-allocate pool.
167 //
168 FreePointer = (VOID **)((UINTN) Buffer - sizeof (RawAddress));
169 RawAddress = *FreePointer;
170
171 Status = gBS->FreePool (RawAddress);
172 ASSERT_EFI_ERROR (Status);
173 }
174
175 /**
176 Create a command transfer TRB to support XHCI command interfaces.
177
178 @param Xhc The XHCI device.
179 @param CmdTrb The cmd TRB to be executed.
180
181 @return Created URB or NULL.
182
183 **/
184 URB*
185 XhcCreateCmdTrb (
186 IN USB_XHCI_DEV *Xhc,
187 IN TRB *CmdTrb
188 )
189 {
190 URB *Urb;
191
192 Urb = AllocateZeroPool (sizeof (URB));
193 if (Urb == NULL) {
194 return NULL;
195 }
196
197 Urb->Signature = XHC_URB_SIG;
198
199 Urb->Ring = &Xhc->CmdRing;
200 XhcSyncTrsRing (Xhc, Urb->Ring);
201 Urb->TrbNum = 1;
202 Urb->TrbStart = Urb->Ring->RingEnqueue;
203 CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB));
204 Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;
205 Urb->TrbEnd = Urb->TrbStart;
206
207 Urb->EvtRing = &Xhc->CmdEventRing;
208 XhcSyncEventRing (Xhc, Urb->EvtRing);
209 Urb->EvtTrbStart = Urb->EvtRing->EventRingEnqueue;
210
211 return Urb;
212 }
213
214 /**
215 Execute a XHCI cmd TRB pointed by CmdTrb.
216
217 @param Xhc The XHCI device.
218 @param CmdTrb The cmd TRB to be executed.
219 @param TimeOut Indicates the maximum time, in millisecond, which the
220 transfer is allowed to complete.
221 @param EvtTrb The event TRB corresponding to the cmd TRB.
222
223 @retval EFI_SUCCESS The transfer was completed successfully.
224 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
225 @retval EFI_TIMEOUT The transfer failed due to timeout.
226 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
227
228 **/
229 EFI_STATUS
230 EFIAPI
231 XhcCmdTransfer (
232 IN USB_XHCI_DEV *Xhc,
233 IN TRB *CmdTrb,
234 IN UINTN TimeOut,
235 OUT TRB **EvtTrb
236 )
237 {
238 EFI_STATUS Status;
239 URB *Urb;
240
241 //
242 // Validate the parameters
243 //
244 if ((Xhc == NULL) || (CmdTrb == NULL)) {
245 return EFI_INVALID_PARAMETER;
246 }
247
248 Status = EFI_DEVICE_ERROR;
249
250 if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
251 DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: HC is halted\n"));
252 goto ON_EXIT;
253 }
254
255 //
256 // Create a new URB, then poll the execution status.
257 //
258 Urb = XhcCreateCmdTrb (Xhc, CmdTrb);
259
260 if (Urb == NULL) {
261 DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: failed to create URB\n"));
262 Status = EFI_OUT_OF_RESOURCES;
263 goto ON_EXIT;
264 }
265
266 ASSERT (Urb->EvtRing == &Xhc->CmdEventRing);
267
268 Status = XhcExecTransfer (Xhc, TRUE, Urb, TimeOut);
269 *EvtTrb = Urb->EvtTrbStart;
270
271 if (Urb->Result == EFI_USB_NOERROR) {
272 Status = EFI_SUCCESS;
273 }
274
275 FreePool (Urb);
276
277 ON_EXIT:
278 return Status;
279 }
280
281 /**
282 Create a new URB for a new transaction.
283
284 @param Xhc The XHCI device
285 @param DevAddr The device address
286 @param EpAddr Endpoint addrress
287 @param DevSpeed The device speed
288 @param MaxPacket The max packet length of the endpoint
289 @param Type The transaction type
290 @param Request The standard USB request for control transfer
291 @param Data The user data to transfer
292 @param DataLen The length of data buffer
293 @param Callback The function to call when data is transferred
294 @param Context The context to the callback
295
296 @return Created URB or NULL
297
298 **/
299 URB*
300 XhcCreateUrb (
301 IN USB_XHCI_DEV *Xhc,
302 IN UINT8 DevAddr,
303 IN UINT8 EpAddr,
304 IN UINT8 DevSpeed,
305 IN UINTN MaxPacket,
306 IN UINTN Type,
307 IN EFI_USB_DEVICE_REQUEST *Request,
308 IN VOID *Data,
309 IN UINTN DataLen,
310 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
311 IN VOID *Context
312 )
313 {
314 USB_ENDPOINT *Ep;
315 EFI_STATUS Status;
316 URB *Urb;
317
318 Urb = AllocateZeroPool (sizeof (URB));
319 if (Urb == NULL) {
320 return NULL;
321 }
322
323 Urb->Signature = XHC_URB_SIG;
324 InitializeListHead (&Urb->UrbList);
325
326 Ep = &Urb->Ep;
327 Ep->DevAddr = DevAddr;
328 Ep->EpAddr = (UINT8)(EpAddr & 0x0F);
329 Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
330 Ep->DevSpeed = DevSpeed;
331 Ep->MaxPacket = MaxPacket;
332 Ep->Type = Type;
333
334 Urb->Request = Request;
335 Urb->Data = Data;
336 Urb->DataLen = DataLen;
337 Urb->Callback = Callback;
338 Urb->Context = Context;
339
340 Status = XhcCreateTransferTrb (Xhc, Urb);
341
342 return Urb;
343 }
344
345 /**
346 Create a transfer TRB.
347
348 @param Xhc The XHCI device
349 @param Urb The urb used to construct the transfer TRB.
350
351 @return Created TRB or NULL
352
353 **/
354 EFI_STATUS
355 XhcCreateTransferTrb (
356 IN USB_XHCI_DEV *Xhc,
357 IN URB *Urb
358 )
359 {
360 DEVICE_CONTEXT *OutputDevContxt;
361 TRANSFER_RING *EPRing;
362 UINT8 EPType;
363 UINT8 SlotId;
364 UINT8 Dci;
365 TRB *TrbStart;
366 UINTN TotalLen;
367 UINTN Len;
368 UINTN TrbNum;
369
370 SlotId = XhcDevAddrToSlotId(Urb->Ep.DevAddr);
371 Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
372 EPRing = (TRANSFER_RING *)(UINTN) UsbDevContext[SlotId].EndpointTransferRing[Dci-1];
373 Urb->Ring = EPRing;
374 OutputDevContxt = (DEVICE_CONTEXT *)(UINTN) Xhc->DCBAA[SlotId];
375 EPType = (UINT8) OutputDevContxt->EP[Dci-1].EPType;
376
377 //
378 // Construct the TRB
379 //
380 XhcSyncTrsRing (Xhc, EPRing);
381 Urb->TrbStart = EPRing->RingEnqueue;
382 switch (EPType) {
383 case ED_CONTROL_BIDIR:
384 Urb->EvtRing = &Xhc->CtrlTrEventRing;
385 XhcSyncEventRing (Xhc, Urb->EvtRing);
386 Urb->EvtTrbStart = Urb->EvtRing->EventRingEnqueue;
387 //
388 // For control transfer, create SETUP_STAGE_TRB first.
389 //
390 TrbStart = EPRing->RingEnqueue;
391 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->bmRequestType = Urb->Request->RequestType;
392 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->bRequest = Urb->Request->Request;
393 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->wValue = Urb->Request->Value;
394 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->wIndex = Urb->Request->Index;
395 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->wLength = Urb->Request->Length;
396 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->Lenth = 8;
397 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->IntTarget = Urb->EvtRing->EventInterrupter;
398 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->IOC = 1;
399 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->IDT = 1;
400 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->Type = TRB_TYPE_SETUP_STAGE;
401 if (Urb->Ep.Direction == EfiUsbDataIn) {
402 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->TRT = 3;
403 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
404 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->TRT = 2;
405 } else {
406 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->TRT = 0;
407 }
408 //
409 // Update the cycle bit
410 //
411 ((TRANSFER_TRB_CONTROL_SETUP *) TrbStart)->CycleBit = EPRing->RingPCS & BIT0;
412 Urb->TrbNum++;
413
414 //
415 // For control transfer, create DATA_STAGE_TRB.
416 //
417 if (Urb->DataLen > 0) {
418 XhcSyncTrsRing (Xhc, EPRing);
419 TrbStart = EPRing->RingEnqueue;
420 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->TRBPtrLo = XHC_LOW_32BIT(Urb->Data);
421 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->TRBPtrHi = XHC_HIGH_32BIT(Urb->Data);
422 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->Lenth = (UINT32) Urb->DataLen;
423 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->TDSize = 0;
424 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->IntTarget = Urb->EvtRing->EventInterrupter;
425 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->ISP = 1;
426 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->IOC = 1;
427 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->IDT = 0;
428 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->CH = 0;
429 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->Type = TRB_TYPE_DATA_STAGE;
430 if (Urb->Ep.Direction == EfiUsbDataIn) {
431 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->DIR = 1;
432 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
433 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->DIR = 0;
434 } else {
435 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->DIR = 0;
436 }
437 //
438 // Update the cycle bit
439 //
440 ((TRANSFER_TRB_CONTROL_DATA *) TrbStart)->CycleBit = EPRing->RingPCS & BIT0;
441 Urb->TrbNum++;
442 }
443 //
444 // For control transfer, create STATUS_STAGE_TRB.
445 // Get the pointer to next TRB for status stage use
446 //
447 XhcSyncTrsRing (Xhc, EPRing);
448 TrbStart = EPRing->RingEnqueue;
449 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->IntTarget = Urb->EvtRing->EventInterrupter;
450 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->IOC = 1;
451 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->CH = 0;
452 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->Type = TRB_TYPE_STATUS_STAGE;
453 if (Urb->Ep.Direction == EfiUsbDataIn) {
454 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->DIR = 0;
455 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
456 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->DIR = 1;
457 } else {
458 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->DIR = 0;
459 }
460 //
461 // Update the cycle bit
462 //
463 ((TRANSFER_TRB_CONTROL_STATUS *) TrbStart)->CycleBit = EPRing->RingPCS & BIT0;
464 //
465 // Update the enqueue pointer
466 //
467 XhcSyncTrsRing (Xhc, EPRing);
468 Urb->TrbNum++;
469 Urb->TrbEnd = TrbStart;
470
471 break;
472
473 case ED_BULK_OUT:
474 case ED_BULK_IN:
475 Urb->EvtRing = &Xhc->BulkTrEventRing;
476 XhcSyncEventRing (Xhc, Urb->EvtRing);
477 Urb->EvtTrbStart = Urb->EvtRing->EventRingEnqueue;
478
479 TotalLen = 0;
480 Len = 0;
481 TrbNum = 0;
482 TrbStart = EPRing->RingEnqueue;
483 while (TotalLen < Urb->DataLen) {
484 if ((TotalLen + 0x10000) >= Urb->DataLen) {
485 Len = Urb->DataLen - TotalLen;
486 } else {
487 Len = 0x10000;
488 }
489 TrbStart = EPRing->RingEnqueue;
490 ((TRANSFER_TRB_NORMAL *) TrbStart)->TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen);
491 ((TRANSFER_TRB_NORMAL *) TrbStart)->TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen);
492 ((TRANSFER_TRB_NORMAL *) TrbStart)->Lenth = (UINT32) Len;
493 ((TRANSFER_TRB_NORMAL *) TrbStart)->TDSize = 0;
494 ((TRANSFER_TRB_NORMAL *) TrbStart)->IntTarget = Urb->EvtRing->EventInterrupter;
495 ((TRANSFER_TRB_NORMAL *) TrbStart)->ISP = 1;
496 ((TRANSFER_TRB_NORMAL *) TrbStart)->IOC = 1;
497 ((TRANSFER_TRB_NORMAL *) TrbStart)->Type = TRB_TYPE_NORMAL;
498 //
499 // Update the cycle bit
500 //
501 ((TRANSFER_TRB_NORMAL *) TrbStart)->CycleBit = EPRing->RingPCS & BIT0;
502
503 XhcSyncTrsRing (Xhc, EPRing);
504 TrbNum++;
505 TotalLen += Len;
506 }
507
508 Urb->TrbNum = TrbNum;
509 Urb->TrbEnd = TrbStart;
510 break;
511
512 case ED_INTERRUPT_OUT:
513 case ED_INTERRUPT_IN:
514 if (Urb->Ep.Type == XHC_INT_TRANSFER_ASYNC) {
515 Urb->EvtRing = &Xhc->AsynIntTrEventRing;
516 } else if(Urb->Ep.Type == XHC_INT_TRANSFER_SYNC){
517 Urb->EvtRing = &Xhc->IntTrEventRing;
518 } else {
519 DEBUG ((EFI_D_ERROR, "EP Interrupt type error!\n"));
520 ASSERT(FALSE);
521 }
522 XhcSyncEventRing (Xhc, Urb->EvtRing);
523 Urb->EvtTrbStart = Urb->EvtRing->EventRingEnqueue;
524
525 TotalLen = 0;
526 Len = 0;
527 TrbNum = 0;
528 TrbStart = EPRing->RingEnqueue;
529 while (TotalLen < Urb->DataLen) {
530 if ((TotalLen + 0x10000) >= Urb->DataLen) {
531 Len = Urb->DataLen - TotalLen;
532 } else {
533 Len = 0x10000;
534 }
535 TrbStart = EPRing->RingEnqueue;
536 ((TRANSFER_TRB_NORMAL *) TrbStart)->TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen);
537 ((TRANSFER_TRB_NORMAL *) TrbStart)->TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen);
538 ((TRANSFER_TRB_NORMAL *) TrbStart)->Lenth = (UINT32) Len;
539 ((TRANSFER_TRB_NORMAL *) TrbStart)->TDSize = 0;
540 ((TRANSFER_TRB_NORMAL *) TrbStart)->IntTarget = Urb->EvtRing->EventInterrupter;
541 ((TRANSFER_TRB_NORMAL *) TrbStart)->ISP = 1;
542 ((TRANSFER_TRB_NORMAL *) TrbStart)->IOC = 1;
543 ((TRANSFER_TRB_NORMAL *) TrbStart)->Type = TRB_TYPE_NORMAL;
544 //
545 // Update the cycle bit
546 //
547 ((TRANSFER_TRB_NORMAL *) TrbStart)->CycleBit = EPRing->RingPCS & BIT0;
548
549 XhcSyncTrsRing (Xhc, EPRing);
550 TrbNum++;
551 TotalLen += Len;
552 }
553
554 Urb->TrbNum = TrbNum;
555 Urb->TrbEnd = TrbStart;
556 break;
557
558 default:
559 DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));
560 ASSERT (FALSE);
561 break;
562 }
563
564 return EFI_SUCCESS;
565 }
566
567
568 /**
569 Initialize the XHCI host controller for schedule.
570
571 @param Xhc The XHCI device to be initialized.
572
573 **/
574 VOID
575 XhcInitSched (
576 IN USB_XHCI_DEV *Xhc
577 )
578 {
579 VOID *Dcbaa;
580 UINT64 CmdRing;
581 UINTN Entries;
582 UINT32 MaxScratchpadBufs;
583 UINT64 *ScratchBuf;
584 UINT64 *ScratchEntryBuf;
585 UINT32 Index;
586
587 //
588 // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)
589 // to enable the device slots that system software is going to use.
590 //
591 Xhc->MaxSlotsEn = Xhc->HcSParams1.Data.MaxSlots;
592 ASSERT (Xhc->MaxSlotsEn >= 1 && Xhc->MaxSlotsEn <= 255);
593 XhcWriteOpReg (Xhc, XHC_CONFIG_OFFSET, Xhc->MaxSlotsEn);
594
595 //
596 // The Device Context Base Address Array entry associated with each allocated Device Slot
597 // shall contain a 64-bit pointer to the base of the associated Device Context.
598 // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
599 // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
600 //
601 Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);
602 Dcbaa = AllocateAlignedZeroPool(Entries, 64);
603 ASSERT (Dcbaa != NULL);
604
605 //
606 // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.
607 // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run
608 // mode (Run/Stop(R/S) ='1').
609 //
610 MaxScratchpadBufs = ((Xhc->HcSParams2.Data.ScratchBufHi) << 5) | (Xhc->HcSParams2.Data.ScratchBufLo);
611 Xhc->MaxScratchpadBufs = MaxScratchpadBufs;
612 ASSERT (MaxScratchpadBufs <= 1023);
613 if (MaxScratchpadBufs != 0) {
614 ScratchBuf = AllocateAlignedZeroPool(MaxScratchpadBufs * sizeof (UINT64), Xhc->PageSize);
615 ASSERT (ScratchBuf != NULL);
616 Xhc->ScratchBuf = ScratchBuf;
617
618 for (Index = 0; Index < MaxScratchpadBufs; Index++) {
619 ScratchEntryBuf = AllocateAlignedZeroPool(Xhc->PageSize, Xhc->PageSize);
620 *ScratchBuf++ = (UINT64)(UINTN)ScratchEntryBuf;
621 }
622
623 //
624 // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
625 // Device Context Base Address Array points to the Scratchpad Buffer Array.
626 //
627 *(UINT64 *)Dcbaa = (UINT64)(UINTN)Xhc->ScratchBuf;
628 }
629
630 //
631 // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with
632 // a 64-bit address pointing to where the Device Context Base Address Array is located.
633 //
634 Xhc->DCBAA = (UINT64 *)(UINTN)Dcbaa;
635 XhcWriteOpReg64 (Xhc, XHC_DCBAAP_OFFSET, (UINT64)(UINTN)Xhc->DCBAA);
636 DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));
637
638 //
639 // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
640 // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.
641 // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall
642 // always be '0'.
643 //
644 CreateTransferRing (Xhc, CMD_RING_TRB_NUMBER, &Xhc->CmdRing);
645 //
646 // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a
647 // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
648 // So we set RCS as inverted PCS init value to let Command Ring empty
649 //
650 CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
651 ASSERT ((CmdRing & 0x3F) == 0);
652 CmdRing |= XHC_CRCR_RCS;
653 XhcWriteOpReg64 (Xhc, XHC_CRCR_OFFSET, CmdRing);
654
655 DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0));
656
657 //
658 // Disable the 'interrupter enable' bit in USB_CMD
659 // and clear IE & IP bit in all Interrupter X Management Registers.
660 //
661 XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_INTE);
662 for (Index = 0; Index < (UINT16)(Xhc->HcSParams1.Data.MaxIntrs); Index++) {
663 XhcClearRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IE);
664 XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IP);
665 }
666
667 //
668 // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
669 //
670 CreateEventRing (Xhc, CMD_INTER, &Xhc->CmdEventRing);
671 CreateEventRing (Xhc, CTRL_INTER, &Xhc->CtrlTrEventRing);
672 CreateEventRing (Xhc, BULK_INTER, &Xhc->BulkTrEventRing);
673 CreateEventRing (Xhc, INT_INTER, &Xhc->IntTrEventRing);
674 CreateEventRing (Xhc, INT_INTER_ASYNC, &Xhc->AsynIntTrEventRing);
675 }
676
677 /**
678 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
679 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
680 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
681 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
682 Stopped to the Running state.
683
684 @param Xhc The XHCI device.
685 @param Urb The urb which makes the endpoint halted.
686
687 @retval EFI_SUCCESS The recovery is successful.
688 @retval Others Failed to recovery halted endpoint.
689
690 **/
691 EFI_STATUS
692 EFIAPI
693 XhcRecoverHaltedEndpoint (
694 IN USB_XHCI_DEV *Xhc,
695 IN URB *Urb
696 )
697 {
698 EFI_STATUS Status;
699 EVT_TRB_COMMAND *EvtTrb;
700 CMD_TRB_RESET_ED CmdTrbResetED;
701 CMD_SET_TR_DEQ CmdSetTRDeq;
702 UINT8 Dci;
703 UINT8 SlotId;
704
705 Status = EFI_SUCCESS;
706 SlotId = XhcDevAddrToSlotId(Urb->Ep.DevAddr);
707 Dci = XhcEndpointToDci(Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
708
709 DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));
710
711 //
712 // 1) Send Reset endpoint command to transit from halt to stop state
713 //
714 ZeroMem (&CmdTrbResetED, sizeof (CmdTrbResetED));
715 CmdTrbResetED.CycleBit = 1;
716 CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;
717 CmdTrbResetED.EDID = Dci;
718 CmdTrbResetED.SlotId = SlotId;
719 Status = XhcCmdTransfer (
720 Xhc,
721 (TRB *) (UINTN) &CmdTrbResetED,
722 XHC_GENERIC_TIMEOUT,
723 (TRB **) (UINTN) &EvtTrb
724 );
725 ASSERT (!EFI_ERROR(Status));
726
727 //
728 // 2)Set dequeue pointer
729 //
730 ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
731 CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (Urb->Ring->RingEnqueue) | Urb->Ring->RingPCS;
732 CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (Urb->Ring->RingEnqueue);
733 CmdSetTRDeq.CycleBit = 1;
734 CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;
735 CmdSetTRDeq.Endpoint = Dci;
736 CmdSetTRDeq.SlotId = SlotId;
737 Status = XhcCmdTransfer (
738 Xhc,
739 (TRB *) (UINTN) &CmdSetTRDeq,
740 XHC_GENERIC_TIMEOUT,
741 (TRB **) (UINTN) &EvtTrb
742 );
743 ASSERT (!EFI_ERROR(Status));
744
745 //
746 // 3)Ring the doorbell to transit from stop to active
747 //
748 XhcRingDoorBell (Xhc, SlotId, Dci);
749
750 return Status;
751 }
752
753 /**
754 Create XHCI event ring.
755
756 @param Xhc The XHCI device.
757 @param EventInterrupter The interrupter of event.
758 @param EventRing The created event ring.
759
760 **/
761 VOID
762 CreateEventRing (
763 IN USB_XHCI_DEV *Xhc,
764 IN UINT8 EventInterrupter,
765 OUT EVENT_RING *EventRing
766 )
767 {
768 VOID *Buf;
769 EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;
770
771 ASSERT (EventRing != NULL);
772
773 Buf = AllocateAlignedZeroPool(sizeof (TRB) * EVENT_RING_TRB_NUMBER, 64);
774 ASSERT (Buf != NULL);
775 ASSERT (((UINTN) Buf & 0x3F) == 0);
776
777 EventRing->EventRingSeg0 = Buf;
778 EventRing->EventInterrupter = EventInterrupter;
779 EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;
780 EventRing->EventRingDequeue = (TRB *) EventRing->EventRingSeg0;
781 EventRing->EventRingEnqueue = (TRB *) EventRing->EventRingSeg0;
782 //
783 // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
784 // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
785 //
786 EventRing->EventRingCCS = 1;
787
788 Buf = AllocateAlignedZeroPool(sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER, 64);
789 ASSERT (Buf != NULL);
790 ASSERT (((UINTN) Buf & 0x3F) == 0);
791
792 ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;
793 EventRing->ERSTBase = ERSTBase;
794 ERSTBase->PtrLo = XHC_LOW_32BIT (EventRing->EventRingSeg0);
795 ERSTBase->PtrHi = XHC_HIGH_32BIT (EventRing->EventRingSeg0);
796 ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;
797
798 //
799 // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)
800 //
801 XhcWriteRuntimeReg (
802 Xhc,
803 XHC_ERSTSZ_OFFSET + (32 * EventRing->EventInterrupter),
804 ERST_NUMBER
805 );
806 //
807 // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)
808 //
809 XhcWriteRuntimeReg64 (
810 Xhc,
811 XHC_ERDP_OFFSET + (32 * EventRing->EventInterrupter),
812 (UINT64)(UINTN)EventRing->EventRingDequeue
813 );
814 //
815 // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)
816 //
817 XhcWriteRuntimeReg64 (
818 Xhc,
819 XHC_ERSTBA_OFFSET + (32 * EventRing->EventInterrupter),
820 (UINT64)(UINTN)ERSTBase
821 );
822 //
823 // Need set IMAN IE bit to enble the ring interrupt
824 //
825 XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (32 * EventRing->EventInterrupter), XHC_IMAN_IE);
826 }
827
828 /**
829 Create XHCI transfer ring.
830
831 @param Xhc The XHCI device.
832 @param TrbNum The number of TRB in the ring.
833 @param TransferRing The created transfer ring.
834
835 **/
836 VOID
837 CreateTransferRing (
838 IN USB_XHCI_DEV *Xhc,
839 IN UINTN TrbNum,
840 OUT TRANSFER_RING *TransferRing
841 )
842 {
843 VOID *Buf;
844 LNK_TRB *EndTrb;
845
846 Buf = AllocateAlignedZeroPool(sizeof (TRB) * TrbNum, 64);
847 ASSERT (Buf != NULL);
848 ASSERT (((UINTN) Buf & 0x3F) == 0);
849
850 TransferRing->RingSeg0 = Buf;
851 TransferRing->TrbNumber = TrbNum;
852 TransferRing->RingEnqueue = (TRB *) TransferRing->RingSeg0;
853 TransferRing->RingDequeue = (TRB *) TransferRing->RingSeg0;
854 TransferRing->RingPCS = 1;
855 //
856 // 4.9.2 Transfer Ring Management
857 // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
858 // point to the first TRB in the ring.
859 //
860 EndTrb = (LNK_TRB*) ((UINTN)Buf + sizeof (TRB) * (TrbNum - 1));
861 EndTrb->Type = TRB_TYPE_LINK;
862 EndTrb->PtrLo = XHC_LOW_32BIT (Buf);
863 EndTrb->PtrHi = XHC_HIGH_32BIT (Buf);
864 //
865 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
866 //
867 EndTrb->TC = 1;
868 //
869 // Set Cycle bit as other TRB PCS init value
870 //
871 EndTrb->CycleBit = 0;
872 }
873
874 /**
875 Free XHCI event ring.
876
877 @param Xhc The XHCI device.
878 @param EventRing The event ring to be freed.
879
880 **/
881 EFI_STATUS
882 EFIAPI
883 XhcFreeEventRing (
884 IN USB_XHCI_DEV *Xhc,
885 IN EVENT_RING *EventRing
886 )
887 {
888 UINT8 Index;
889 EVENT_RING_SEG_TABLE_ENTRY *TablePtr;
890 VOID *RingBuf;
891 EVENT_RING_SEG_TABLE_ENTRY *EventRingPtr;
892 UINTN InterrupterTarget;
893
894 if(EventRing->EventRingSeg0 == NULL) {
895 return EFI_SUCCESS;
896 }
897
898 InterrupterTarget = EventRing->EventInterrupter;
899 //
900 // Get the Event Ring Segment Table base address
901 //
902 TablePtr = (EVENT_RING_SEG_TABLE_ENTRY *)(EventRing->ERSTBase);
903
904 //
905 // Get all the TRBs Ring and release
906 //
907 for (Index = 0; Index < ERST_NUMBER; Index++) {
908 EventRingPtr = TablePtr + Index;
909 RingBuf = (VOID *)(UINTN)(EventRingPtr->PtrLo | ((UINT64)EventRingPtr->PtrHi << 32));
910
911 if(RingBuf != NULL) {
912 FreeAlignedPool (RingBuf);
913 ZeroMem (EventRingPtr, sizeof (EVENT_RING_SEG_TABLE_ENTRY));
914 }
915 }
916
917 FreeAlignedPool (TablePtr);
918 return EFI_SUCCESS;
919 }
920
921 /**
922 Free the resouce allocated at initializing schedule.
923
924 @param Xhc The XHCI device.
925
926 **/
927 VOID
928 XhcFreeSched (
929 IN USB_XHCI_DEV *Xhc
930 )
931 {
932 UINT32 Index;
933
934 if (Xhc->ScratchBuf != NULL) {
935 for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {
936 FreeAlignedPool ((VOID*)(UINTN)*Xhc->ScratchBuf++);
937 }
938 }
939
940 if (Xhc->DCBAA != NULL) {
941 FreeAlignedPool (Xhc->DCBAA);
942 Xhc->DCBAA = NULL;
943 }
944
945 if (Xhc->CmdRing.RingSeg0 != NULL){
946 FreeAlignedPool (Xhc->CmdRing.RingSeg0);
947 Xhc->CmdRing.RingSeg0 = NULL;
948 }
949 XhcFreeEventRing (Xhc,&Xhc->CmdEventRing);
950 XhcFreeEventRing (Xhc,&Xhc->CtrlTrEventRing);
951 XhcFreeEventRing (Xhc,&Xhc->BulkTrEventRing);
952 XhcFreeEventRing (Xhc,&Xhc->AsynIntTrEventRing);
953 XhcFreeEventRing (Xhc,&Xhc->IntTrEventRing);
954 }
955
956 /**
957 Check if it is ring TRB.
958
959 @param Ring The transfer ring
960 @param Trb The TRB to check if it's in the transfer ring
961
962 @retval TRUE It is in the ring
963 @retval FALSE It is not in the ring
964
965 **/
966 BOOLEAN
967 IsTransferRingTrb (
968 IN TRANSFER_RING *Ring,
969 IN TRB *Trb
970 )
971 {
972 BOOLEAN Flag;
973 TRB *Trb1;
974 UINTN Index;
975
976 Trb1 = Ring->RingSeg0;
977 Flag = FALSE;
978
979 ASSERT (Ring->TrbNumber == CMD_RING_TRB_NUMBER || Ring->TrbNumber == TR_RING_TRB_NUMBER);
980
981 for (Index = 0; Index < Ring->TrbNumber; Index++) {
982 if (Trb == Trb1) {
983 Flag = TRUE;
984 break;
985 }
986 Trb1++;
987 }
988
989 return Flag;
990 }
991
992 /**
993 Check the URB's execution result and update the URB's
994 result accordingly.
995
996 @param Xhc The XHCI device.
997 @param Urb The URB to check result.
998
999 @return Whether the result of URB transfer is finialized.
1000
1001 **/
1002 EFI_STATUS
1003 XhcCheckUrbResult (
1004 IN USB_XHCI_DEV *Xhc,
1005 IN URB *Urb
1006 )
1007 {
1008 BOOLEAN StartDone;
1009 BOOLEAN EndDone;
1010 EVT_TRB_TRANSFER *EvtTrb;
1011 TRB *TRBPtr;
1012 UINTN Index;
1013 UINT8 TRBType;
1014 EFI_STATUS Status;
1015
1016 ASSERT ((Xhc != NULL) && (Urb != NULL));
1017
1018 Urb->Completed = 0;
1019 Urb->Result = EFI_USB_NOERROR;
1020 Status = EFI_SUCCESS;
1021 EvtTrb = NULL;
1022
1023 if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {
1024 Urb->Result |= EFI_USB_ERR_SYSTEM;
1025 Status = EFI_DEVICE_ERROR;
1026 goto EXIT;
1027 }
1028
1029 //
1030 // Restore the EventRingDequeue and poll the transfer event ring from beginning
1031 //
1032 StartDone = FALSE;
1033 EndDone = FALSE;
1034 Urb->EvtRing->EventRingDequeue = Urb->EvtTrbStart;
1035 for (Index = 0; Index < Urb->EvtRing->TrbNumber; Index++) {
1036 XhcSyncEventRing (Xhc, Urb->EvtRing);
1037 Status = XhcCheckNewEvent (Xhc, Urb->EvtRing, ((TRB **)&EvtTrb));
1038 if (Status == EFI_NOT_READY) {
1039 Urb->Result |= EFI_USB_ERR_TIMEOUT;
1040 goto EXIT;
1041 }
1042
1043 TRBPtr = (TRB *)(UINTN)(EvtTrb->TRBPtrLo | (UINT64) EvtTrb->TRBPtrHi << 32);
1044
1045 switch (EvtTrb->Completcode) {
1046 case TRB_COMPLETION_STALL_ERROR:
1047 Urb->Result |= EFI_USB_ERR_STALL;
1048 Status = EFI_DEVICE_ERROR;
1049 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completcode = %x\n",EvtTrb->Completcode));
1050 goto EXIT;
1051 break;
1052
1053 case TRB_COMPLETION_BABBLE_ERROR:
1054 Urb->Result |= EFI_USB_ERR_BABBLE;
1055 Status = EFI_DEVICE_ERROR;
1056 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completcode = %x\n",EvtTrb->Completcode));
1057 goto EXIT;
1058 break;
1059
1060 case TRB_COMPLETION_DATA_BUFFER_ERROR:
1061 Urb->Result |= EFI_USB_ERR_BUFFER;
1062 Status = EFI_DEVICE_ERROR;
1063 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completcode = %x\n",EvtTrb->Completcode));
1064 goto EXIT;
1065 break;
1066
1067 case TRB_COMPLETION_USB_TRANSACTION_ERROR:
1068 Urb->Result |= EFI_USB_ERR_TIMEOUT;
1069 Status = EFI_DEVICE_ERROR;
1070 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completcode = %x\n",EvtTrb->Completcode));
1071 goto EXIT;
1072 break;
1073
1074 case TRB_COMPLETION_SHORT_PACKET:
1075 case TRB_COMPLETION_SUCCESS:
1076 if (IsTransferRingTrb (Urb->Ring, TRBPtr)) {
1077 if (EvtTrb->Completcode == TRB_COMPLETION_SHORT_PACKET) {
1078 DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: short packet happens!\n"));
1079 }
1080 TRBType = (UINT8) (TRBPtr->Type);
1081 if ((TRBType == TRB_TYPE_DATA_STAGE) ||
1082 (TRBType == TRB_TYPE_NORMAL) ||
1083 (TRBType == TRB_TYPE_ISOCH)) {
1084 Urb->Completed += (Urb->DataLen - EvtTrb->Lenth);
1085 }
1086 }
1087 Status = EFI_SUCCESS;
1088 break;
1089
1090 default:
1091 DEBUG ((EFI_D_ERROR, "Transfer Default Error Occur! Completcode = 0x%x!\n",EvtTrb->Completcode));
1092 Urb->Result |= EFI_USB_ERR_TIMEOUT;
1093 Status = EFI_DEVICE_ERROR;
1094 goto EXIT;
1095 break;
1096 }
1097
1098 //
1099 // Only check first and end Trb event address
1100 //
1101 if (TRBPtr == Urb->TrbStart) {
1102 StartDone = TRUE;
1103 }
1104
1105 if (TRBPtr == Urb->TrbEnd) {
1106 EndDone = TRUE;
1107 }
1108
1109 if (StartDone && EndDone) {
1110 break;
1111 }
1112 }
1113
1114 EXIT:
1115 return Status;
1116 }
1117
1118
1119 /**
1120 Execute the transfer by polling the URB. This is a synchronous operation.
1121
1122 @param Xhc The XHCI device.
1123 @param CmdTransfer The executed URB is for cmd transfer or not.
1124 @param Urb The URB to execute.
1125 @param TimeOut The time to wait before abort, in millisecond.
1126
1127 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
1128 @return EFI_TIMEOUT The transfer failed due to time out.
1129 @return EFI_SUCCESS The transfer finished OK.
1130
1131 **/
1132 EFI_STATUS
1133 XhcExecTransfer (
1134 IN USB_XHCI_DEV *Xhc,
1135 IN BOOLEAN CmdTransfer,
1136 IN URB *Urb,
1137 IN UINTN TimeOut
1138 )
1139 {
1140 EFI_STATUS Status;
1141 UINTN Index;
1142 UINTN Loop;
1143 UINT8 SlotId;
1144 UINT8 Dci;
1145
1146 if (CmdTransfer) {
1147 SlotId = 0;
1148 Dci = 0;
1149 } else {
1150 SlotId = XhcDevAddrToSlotId(Urb->Ep.DevAddr);
1151 Dci = XhcEndpointToDci(Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
1152 }
1153
1154 Status = EFI_SUCCESS;
1155 Loop = (TimeOut * XHC_1_MILLISECOND / XHC_SYNC_POLL_INTERVAL) + 1;
1156 if (TimeOut == 0) {
1157 Loop = 0xFFFFFFFF;
1158 }
1159
1160 XhcRingDoorBell (Xhc, SlotId, Dci);
1161
1162 for (Index = 0; Index < Loop; Index++) {
1163 Status = XhcCheckUrbResult (Xhc, Urb);
1164 if ((Status != EFI_NOT_READY)) {
1165 break;
1166 }
1167 gBS->Stall (XHC_SYNC_POLL_INTERVAL);
1168 }
1169
1170 return Status;
1171 }
1172
1173 /**
1174 Delete a single asynchronous interrupt transfer for
1175 the device and endpoint.
1176
1177 @param Xhc The XHCI device.
1178 @param DevAddr The address of the target device.
1179 @param EpNum The endpoint of the target.
1180
1181 @retval EFI_SUCCESS An asynchronous transfer is removed.
1182 @retval EFI_NOT_FOUND No transfer for the device is found.
1183
1184 **/
1185 EFI_STATUS
1186 XhciDelAsyncIntTransfer (
1187 IN USB_XHCI_DEV *Xhc,
1188 IN UINT8 DevAddr,
1189 IN UINT8 EpNum
1190 )
1191 {
1192 LIST_ENTRY *Entry;
1193 LIST_ENTRY *Next;
1194 URB *Urb;
1195 EFI_USB_DATA_DIRECTION Direction;
1196 BOOLEAN Found;
1197
1198 Direction = ((EpNum & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
1199 EpNum &= 0x0F;
1200
1201 Found = FALSE;
1202 Urb = NULL;
1203
1204 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1205 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1206 if ((Urb->Ep.DevAddr == DevAddr) &&
1207 (Urb->Ep.EpAddr == EpNum) &&
1208 (Urb->Ep.Direction == Direction)) {
1209 RemoveEntryList (&Urb->UrbList);
1210 FreePool (Urb->Data);
1211 FreePool (Urb);
1212 return EFI_SUCCESS;
1213 }
1214 }
1215
1216 return EFI_NOT_FOUND;
1217 }
1218
1219 /**
1220 Remove all the asynchronous interrutp transfers.
1221
1222 @param Xhc The XHCI device.
1223
1224 **/
1225 VOID
1226 XhciDelAllAsyncIntTransfers (
1227 IN USB_XHCI_DEV *Xhc
1228 )
1229 {
1230 LIST_ENTRY *Entry;
1231 LIST_ENTRY *Next;
1232 URB *Urb;
1233
1234 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1235 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1236 RemoveEntryList (&Urb->UrbList);
1237 FreePool (Urb->Data);
1238 FreePool (Urb);
1239 }
1240 }
1241
1242 /**
1243 Update the queue head for next round of asynchronous transfer
1244
1245 @param Xhc The XHCI device.
1246 @param Urb The URB to update
1247
1248 **/
1249 VOID
1250 XhcUpdateAsyncRequest (
1251 IN USB_XHCI_DEV* Xhc,
1252 IN URB *Urb
1253 )
1254 {
1255 EFI_STATUS Status;
1256
1257 if (Urb->Result == EFI_USB_NOERROR) {
1258 Status = XhcCreateTransferTrb (Xhc, Urb);
1259 ASSERT_EFI_ERROR (Status);
1260 Status = RingIntTransferDoorBell (Xhc, Urb);
1261 ASSERT_EFI_ERROR (Status);
1262 }
1263 }
1264
1265
1266 /**
1267 Interrupt transfer periodic check handler.
1268
1269 @param Event Interrupt event.
1270 @param Context Pointer to USB_XHCI_DEV.
1271
1272 **/
1273 VOID
1274 EFIAPI
1275 XhcMonitorAsyncRequests (
1276 IN EFI_EVENT Event,
1277 IN VOID *Context
1278 )
1279 {
1280 USB_XHCI_DEV *Xhc;
1281 LIST_ENTRY *Entry;
1282 LIST_ENTRY *Next;
1283 UINT8 *ProcBuf;
1284 URB *Urb;
1285 UINT8 SlotId;
1286 EFI_STATUS Status;
1287 EFI_TPL OldTpl;
1288
1289 OldTpl = gBS->RaiseTPL (XHC_TPL);
1290
1291 Xhc = (USB_XHCI_DEV*) Context;
1292
1293 EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
1294 Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
1295
1296 //
1297 // Make sure that the device is available before every check.
1298 //
1299 SlotId = XhcDevAddrToSlotId(Urb->Ep.DevAddr);
1300 if (SlotId == 0) {
1301 continue;
1302 }
1303
1304 //
1305 // Check the result of URB execution. If it is still
1306 // active, check the next one.
1307 //
1308 Status = XhcCheckUrbResult (Xhc, Urb);
1309
1310 if (Status == EFI_NOT_READY) {
1311 continue;
1312 }
1313
1314 //
1315 // Allocate a buffer then copy the transferred data for user.
1316 // If failed to allocate the buffer, update the URB for next
1317 // round of transfer. Ignore the data of this round.
1318 //
1319 ProcBuf = NULL;
1320 if (Urb->Result == EFI_USB_NOERROR) {
1321 ASSERT (Urb->Completed <= Urb->DataLen);
1322
1323 ProcBuf = AllocatePool (Urb->Completed);
1324
1325 if (ProcBuf == NULL) {
1326 XhcUpdateAsyncRequest (Xhc, Urb);
1327 continue;
1328 }
1329
1330 CopyMem (ProcBuf, Urb->Data, Urb->Completed);
1331 }
1332
1333 XhcUpdateAsyncRequest (Xhc, Urb);
1334
1335 //
1336 // Leave error recovery to its related device driver. A
1337 // common case of the error recovery is to re-submit the
1338 // interrupt transfer which is linked to the head of the
1339 // list. This function scans from head to tail. So the
1340 // re-submitted interrupt transfer's callback function
1341 // will not be called again in this round. Don't touch this
1342 // URB after the callback, it may have been removed by the
1343 // callback.
1344 //
1345 if (Urb->Callback != NULL) {
1346 //
1347 // Restore the old TPL, USB bus maybe connect device in
1348 // his callback. Some drivers may has a lower TPL restriction.
1349 //
1350 gBS->RestoreTPL (OldTpl);
1351 (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);
1352 OldTpl = gBS->RaiseTPL (XHC_TPL);
1353 }
1354
1355 if (ProcBuf != NULL) {
1356 gBS->FreePool (ProcBuf);
1357 }
1358 }
1359 gBS->RestoreTPL (OldTpl);
1360 }
1361
1362 /**
1363 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
1364
1365 @param Xhc The XHCI device.
1366 @param ParentRouteChart The route string pointed to the parent device if it exists.
1367 @param Port The port to be polled.
1368 @param PortState The port state.
1369
1370 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
1371 @retval Others Should not appear.
1372
1373 **/
1374 EFI_STATUS
1375 EFIAPI
1376 XhcPollPortStatusChange (
1377 IN USB_XHCI_DEV* Xhc,
1378 IN USB_DEV_ROUTE ParentRouteChart,
1379 IN UINT8 Port,
1380 IN EFI_USB_PORT_STATUS *PortState
1381 )
1382 {
1383 EFI_STATUS Status;
1384 UINT8 Speed;
1385 UINT8 SlotId;
1386 USB_DEV_ROUTE RouteChart;
1387
1388 Status = EFI_SUCCESS;
1389
1390 if (ParentRouteChart.Dword == 0) {
1391 RouteChart.Field.RouteString = 0;
1392 RouteChart.Field.RootPortNum = Port + 1;
1393 RouteChart.Field.TierNum = 1;
1394 } else {
1395 if(Port < 14) {
1396 RouteChart.Field.RouteString = ParentRouteChart.Field.RouteString | (Port << (4 * (ParentRouteChart.Field.TierNum - 1)));
1397 } else {
1398 RouteChart.Field.RouteString = ParentRouteChart.Field.RouteString | (15 << (4 * (ParentRouteChart.Field.TierNum - 1)));
1399 }
1400 RouteChart.Field.RootPortNum = ParentRouteChart.Field.RootPortNum;
1401 RouteChart.Field.TierNum = ParentRouteChart.Field.TierNum + 1;
1402 }
1403
1404 if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&
1405 ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {
1406 //
1407 // Has a device attached, Identify device speed after port is enabled.
1408 //
1409 Speed = EFI_USB_SPEED_FULL;
1410 if ((PortState->PortStatus & USB_PORT_STAT_LOW_SPEED) != 0) {
1411 Speed = EFI_USB_SPEED_LOW;
1412 } else if ((PortState->PortStatus & USB_PORT_STAT_HIGH_SPEED) != 0) {
1413 Speed = EFI_USB_SPEED_HIGH;
1414 } else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {
1415 Speed = EFI_USB_SPEED_SUPER;
1416 }
1417 //
1418 // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
1419 //
1420 SlotId = XhcRouteStringToSlotId (RouteChart);
1421 if (SlotId == 0) {
1422 Status = XhcInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);
1423 ASSERT_EFI_ERROR (Status);
1424 }
1425 } else if ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) == 0) {
1426 //
1427 // Device is detached. Disable the allocated device slot and release resource.
1428 //
1429 SlotId = XhcRouteStringToSlotId (RouteChart);
1430 if (SlotId != 0) {
1431 Status = XhcDisableSlotCmd (Xhc, SlotId);
1432 ASSERT_EFI_ERROR (Status);
1433 }
1434 }
1435 return Status;
1436 }
1437
1438
1439 /**
1440 Calculate the device context index by endpoint address and direction.
1441
1442 @param EpAddr The target endpoint number.
1443 @param Direction The direction of the target endpoint.
1444
1445 @return The device context index of endpoint.
1446
1447 **/
1448 UINT8
1449 XhcEndpointToDci (
1450 IN UINT8 EpAddr,
1451 IN UINT8 Direction
1452 )
1453 {
1454 UINT8 Index;
1455
1456 if (EpAddr == 0) {
1457 return 1;
1458 } else {
1459 Index = (UINT8) (2 * EpAddr);
1460 if (Direction == EfiUsbDataIn) {
1461 Index += 1;
1462 }
1463 return Index;
1464 }
1465 }
1466
1467 /**
1468 Find out the slot id according to device address assigned by XHCI's Address_Device cmd.
1469
1470 @param DevAddr The device address of the target device.
1471
1472 @return The slot id used by the device.
1473
1474 **/
1475 UINT8
1476 XhcDevAddrToSlotId (
1477 IN UINT8 DevAddr
1478 )
1479 {
1480 UINT8 Index;
1481
1482 for (Index = 0; Index < 255; Index++) {
1483 if (UsbDevContext[Index + 1].Enabled &&
1484 (UsbDevContext[Index + 1].SlotId != 0) &&
1485 (UsbDevContext[Index + 1].XhciDevAddr == DevAddr)) {
1486 break;
1487 }
1488 }
1489
1490 if (Index == 255) {
1491 return 0;
1492 }
1493
1494 return UsbDevContext[Index + 1].SlotId;
1495 }
1496
1497 /**
1498 Find out the actual device address according to the requested device address from UsbBus.
1499
1500 @param BusDevAddr The requested device address by UsbBus upper driver.
1501
1502 @return The actual device address assigned to the device.
1503
1504 **/
1505 UINT8
1506 EFIAPI
1507 XhcBusDevAddrToSlotId (
1508 IN UINT8 BusDevAddr
1509 )
1510 {
1511 UINT8 Index;
1512
1513 for (Index = 0; Index < 255; Index++) {
1514 if (UsbDevContext[Index + 1].Enabled &&
1515 (UsbDevContext[Index + 1].SlotId != 0) &&
1516 (UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {
1517 break;
1518 }
1519 }
1520
1521 if (Index == 255) {
1522 return 0;
1523 }
1524
1525 return UsbDevContext[Index + 1].SlotId;
1526 }
1527
1528 /**
1529 Find out the slot id according to the device's route string.
1530
1531 @param RouteString The route string described the device location.
1532
1533 @return The slot id used by the device.
1534
1535 **/
1536 UINT8
1537 EFIAPI
1538 XhcRouteStringToSlotId (
1539 IN USB_DEV_ROUTE RouteString
1540 )
1541 {
1542 UINT8 Index;
1543
1544 for (Index = 0; Index < 255; Index++) {
1545 if (UsbDevContext[Index + 1].Enabled &&
1546 (UsbDevContext[Index + 1].SlotId != 0) &&
1547 (UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {
1548 break;
1549 }
1550 }
1551
1552 if (Index == 255) {
1553 return 0;
1554 }
1555
1556 return UsbDevContext[Index + 1].SlotId;
1557 }
1558
1559 /**
1560 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1561
1562 @param Xhc The XHCI device.
1563 @param EvtRing The event ring to sync.
1564
1565 @retval EFI_SUCCESS The event ring is synchronized successfully.
1566
1567 **/
1568 EFI_STATUS
1569 EFIAPI
1570 XhcSyncEventRing (
1571 IN USB_XHCI_DEV *Xhc,
1572 IN EVENT_RING *EvtRing
1573 )
1574 {
1575 UINTN Index;
1576 TRB *EvtTrb1;
1577 TRB *EvtTrb2;
1578 TRB *XhcDequeue;
1579
1580 ASSERT (EvtRing != NULL);
1581
1582 //
1583 // Calculate the EventRingEnqueue and EventRingCCS.
1584 // Note: only support single Segment
1585 //
1586 EvtTrb1 = EvtRing->EventRingSeg0;
1587 EvtTrb2 = EvtRing->EventRingSeg0;
1588
1589 for (Index = 0; Index < EvtRing->TrbNumber; Index++) {
1590 if (EvtTrb1->CycleBit != EvtTrb2->CycleBit) {
1591 break;
1592 }
1593 EvtTrb1++;
1594 }
1595
1596 if (Index < EvtRing->TrbNumber) {
1597 EvtRing->EventRingEnqueue = EvtTrb1;
1598 EvtRing->EventRingCCS = (EvtTrb2->CycleBit) ? 1 : 0;
1599 } else {
1600 EvtRing->EventRingEnqueue = EvtTrb2;
1601 EvtRing->EventRingCCS = (EvtTrb2->CycleBit) ? 0 : 1;
1602 }
1603
1604 //
1605 // Apply the EventRingDequeue to Xhc
1606 //
1607 XhcDequeue = (TRB *)(UINTN) XhcReadRuntimeReg64 (
1608 Xhc,
1609 XHC_ERDP_OFFSET + (32 * EvtRing->EventInterrupter)
1610 );
1611
1612 if (((UINT64)(UINTN)XhcDequeue & (~0x0F)) != ((UINT64)(UINTN)EvtRing->EventRingDequeue & (~0x0F))) {
1613 XhcWriteRuntimeReg64 (
1614 Xhc,
1615 XHC_ERDP_OFFSET + (32 * EvtRing->EventInterrupter),
1616 (UINT64)(UINTN)EvtRing->EventRingDequeue | BIT3
1617 );
1618 }
1619
1620 return EFI_SUCCESS;
1621 }
1622
1623 /**
1624 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1625
1626 @param Xhc The XHCI device.
1627 @param TrsRing The transfer ring to sync.
1628
1629 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1630
1631 **/
1632 EFI_STATUS
1633 EFIAPI
1634 XhcSyncTrsRing (
1635 IN USB_XHCI_DEV *Xhc,
1636 IN TRANSFER_RING *TrsRing
1637 )
1638 {
1639 UINTN Index;
1640 TRB *TrsTrb;
1641
1642 ASSERT (TrsRing != NULL);
1643 //
1644 // Calculate the latest RingEnqueue and RingPCS
1645 //
1646 TrsTrb = TrsRing->RingEnqueue;
1647 ASSERT (TrsTrb != NULL);
1648
1649 for (Index = 0; Index < TrsRing->TrbNumber; Index++) {
1650 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {
1651 break;
1652 }
1653 TrsTrb++;
1654 if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {
1655 ASSERT (((LNK_TRB*)TrsTrb)->TC != 0);
1656 //
1657 // set cycle bit in Link TRB as normal
1658 //
1659 ((LNK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;
1660 //
1661 // Toggle PCS maintained by software
1662 //
1663 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;
1664 TrsTrb = (TRB*)(UINTN)((TrsTrb->Dword1 | ((UINT64)TrsTrb->Dword2 << 32)) & ~0x0F);
1665 }
1666 }
1667
1668 ASSERT (Index != TrsRing->TrbNumber);
1669
1670 if (TrsTrb != TrsRing->RingEnqueue) {
1671 TrsRing->RingEnqueue = TrsTrb;
1672 }
1673
1674 //
1675 // Clear the Trb context for enqueue, but reserve the PCS bit
1676 //
1677 TrsTrb->Dword1 = 0;
1678 TrsTrb->Dword2 = 0;
1679 TrsTrb->Dword3 = 0;
1680 TrsTrb->RsvdZ1 = 0;
1681 TrsTrb->Type = 0;
1682 TrsTrb->RsvdZ2 = 0;
1683
1684 return EFI_SUCCESS;
1685 }
1686
1687 /**
1688 Check if there is a new generated event.
1689
1690 @param Xhc The XHCI device.
1691 @param EvtRing The event ring to check.
1692 @param NewEvtTrb The new event TRB found.
1693
1694 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1695 @retval EFI_NOT_READY The event ring has no new event.
1696
1697 **/
1698 EFI_STATUS
1699 EFIAPI
1700 XhcCheckNewEvent (
1701 IN USB_XHCI_DEV *Xhc,
1702 IN EVENT_RING *EvtRing,
1703 OUT TRB **NewEvtTrb
1704 )
1705 {
1706 EFI_STATUS Status;
1707 TRB *EvtTrb;
1708
1709 ASSERT (EvtRing != NULL);
1710
1711 EvtTrb = EvtRing->EventRingDequeue;
1712 *NewEvtTrb = EvtRing->EventRingDequeue;
1713
1714 if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {
1715 return EFI_NOT_READY;
1716 }
1717
1718 Status = EFI_SUCCESS;
1719
1720 if (((EvtTrb->Dword3 >> 24) & 0xFF) != TRB_COMPLETION_SUCCESS) {
1721 Status = EFI_DEVICE_ERROR;
1722 }
1723
1724 EvtRing->EventRingDequeue++;
1725 //
1726 // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
1727 //
1728 if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB) * EvtRing->TrbNumber)) {
1729 EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;
1730 }
1731
1732 return Status;
1733 }
1734
1735 /**
1736 Ring the door bell to notify XHCI there is a transaction to be executed.
1737
1738 @param Xhc The XHCI device.
1739 @param SlotId The slot id of the target device.
1740 @param Dci The device context index of the target slot or endpoint.
1741
1742 @retval EFI_SUCCESS Successfully ring the door bell.
1743
1744 **/
1745 EFI_STATUS
1746 EFIAPI
1747 XhcRingDoorBell (
1748 IN USB_XHCI_DEV *Xhc,
1749 IN UINT8 SlotId,
1750 IN UINT8 Dci
1751 )
1752 {
1753 if (SlotId == 0) {
1754 XhcWriteDoorBellReg (Xhc, 0, 0);
1755 } else {
1756 XhcWriteDoorBellReg (Xhc, SlotId * sizeof (UINT32), Dci);
1757 }
1758
1759 return EFI_SUCCESS;
1760 }
1761
1762 /**
1763 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
1764
1765 @param Xhc The XHCI device.
1766 @param Urb The URB to be rung.
1767
1768 @retval EFI_SUCCESS Successfully ring the door bell.
1769
1770 **/
1771 EFI_STATUS
1772 RingIntTransferDoorBell (
1773 IN USB_XHCI_DEV *Xhc,
1774 IN URB *Urb
1775 )
1776 {
1777 UINT8 SlotId;
1778 UINT8 Dci;
1779
1780 SlotId = XhcDevAddrToSlotId(Urb->Ep.DevAddr);
1781 Dci = XhcEndpointToDci(Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
1782 XhcRingDoorBell (Xhc, SlotId, Dci);
1783 return EFI_SUCCESS;
1784 }
1785
1786 /**
1787 Assign and initialize the device slot for a new device.
1788
1789 @param Xhc The XHCI device.
1790 @param ParentRouteChart The route string pointed to the parent device.
1791 @param ParentPort The port at which the device is located.
1792 @param RouteChart The route string pointed to the device.
1793 @param DeviceSpeed The device speed.
1794
1795 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1796
1797 **/
1798 EFI_STATUS
1799 EFIAPI
1800 XhcInitializeDeviceSlot (
1801 IN USB_XHCI_DEV *Xhc,
1802 IN USB_DEV_ROUTE ParentRouteChart,
1803 IN UINT16 ParentPort,
1804 IN USB_DEV_ROUTE RouteChart,
1805 IN UINT8 DeviceSpeed
1806 )
1807 {
1808 EFI_STATUS Status;
1809 EVT_TRB_COMMAND *EvtTrb;
1810 INPUT_CONTEXT *InputContext;
1811 DEVICE_CONTEXT *OutputDevContxt;
1812 TRANSFER_RING *EndpointTransferRing;
1813 CMD_TRB_ADDR_DEV CmdTrbAddr;
1814 UINT8 DeviceAddress;
1815 CMD_TRB_EN_SLOT CmdTrb;
1816 UINT8 SlotId;
1817 UINT8 ParentSlotId;
1818 DEVICE_CONTEXT *ParentDeviceContext;
1819
1820 ZeroMem (&CmdTrb, sizeof (CMD_TRB_EN_SLOT));
1821 CmdTrb.CycleBit = 1;
1822 CmdTrb.Type = TRB_TYPE_EN_SLOT;
1823
1824 Status = XhcCmdTransfer (
1825 Xhc,
1826 (TRB *) (UINTN) &CmdTrb,
1827 XHC_GENERIC_TIMEOUT,
1828 (TRB **) (UINTN) &EvtTrb
1829 );
1830 ASSERT_EFI_ERROR (Status);
1831 ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);
1832 DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));
1833 SlotId = (UINT8)EvtTrb->SlotId;
1834 ASSERT (SlotId != 0);
1835
1836 ZeroMem (&UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));
1837 UsbDevContext[SlotId].Enabled = TRUE;
1838 UsbDevContext[SlotId].SlotId = SlotId;
1839 UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;
1840 UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;
1841
1842 //
1843 // 4.3.3 Device Slot Initialization
1844 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
1845 //
1846 InputContext = AllocateAlignedZeroPool(sizeof (INPUT_CONTEXT), 64);
1847 ASSERT (InputContext != NULL);
1848 ASSERT (((UINTN) InputContext & 0x3F) == 0);
1849
1850 UsbDevContext[SlotId].InputContext = (VOID *) InputContext;
1851
1852 //
1853 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
1854 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
1855 // Context are affected by the command.
1856 //
1857 InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);
1858
1859 //
1860 // 3) Initialize the Input Slot Context data structure
1861 //
1862 InputContext->Slot.RouteStr = RouteChart.Field.RouteString;
1863 InputContext->Slot.Speed = DeviceSpeed + 1;
1864 InputContext->Slot.ContextEntries = 1;
1865 InputContext->Slot.RootHubPortNum = RouteChart.Field.RootPortNum;
1866
1867 if (RouteChart.Field.RouteString) {
1868 //
1869 // The device is behind of hub device.
1870 //
1871 ParentSlotId = XhcRouteStringToSlotId(ParentRouteChart);
1872 ASSERT (ParentSlotId != 0);
1873 //
1874 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
1875 //
1876 ParentDeviceContext = (DEVICE_CONTEXT *)UsbDevContext[ParentSlotId].OutputDevContxt;
1877 if ((ParentDeviceContext->Slot.TTPortNum == 0) &&
1878 (ParentDeviceContext->Slot.TTHubSlotId == 0)) {
1879 if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {
1880 //
1881 // Full/Low device attached to High speed hub port that isolates the high speed signaling
1882 // environment from Full/Low speed signaling environment for a device
1883 //
1884 InputContext->Slot.TTPortNum = ParentPort;
1885 InputContext->Slot.TTHubSlotId = ParentSlotId;
1886 }
1887 } else {
1888 //
1889 // Inherit the TT parameters from parent device.
1890 //
1891 InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;
1892 InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;
1893 //
1894 // If the device is a High speed device then down the speed to be the same as its parent Hub
1895 //
1896 if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
1897 InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;
1898 }
1899 }
1900 }
1901
1902 //
1903 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
1904 //
1905 EndpointTransferRing = AllocateAlignedZeroPool(sizeof (TRANSFER_RING), 64);
1906 UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;
1907 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)UsbDevContext[SlotId].EndpointTransferRing[0]);
1908 //
1909 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
1910 //
1911 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;
1912
1913 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
1914 InputContext->EP[0].MaxPacketSize = 512;
1915 } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {
1916 InputContext->EP[0].MaxPacketSize = 64;
1917 } else {
1918 InputContext->EP[0].MaxPacketSize = 8;
1919 }
1920 //
1921 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
1922 // 1KB, and Bulk and Isoch endpoints 3KB.
1923 //
1924 InputContext->EP[0].AverageTRBLength = 8;
1925 InputContext->EP[0].MaxBurstSize = 0;
1926 InputContext->EP[0].Interval = 0;
1927 InputContext->EP[0].MaxPStreams = 0;
1928 InputContext->EP[0].Mult = 0;
1929 InputContext->EP[0].CErr = 3;
1930
1931 //
1932 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
1933 //
1934 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0) | BIT0;
1935 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0);
1936
1937 //
1938 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
1939 //
1940 OutputDevContxt = AllocateAlignedZeroPool(sizeof (DEVICE_CONTEXT), 64);
1941 ASSERT (OutputDevContxt != NULL);
1942 ASSERT (((UINTN) OutputDevContxt & 0x3F) == 0);
1943
1944 UsbDevContext[SlotId].OutputDevContxt = OutputDevContxt;
1945 //
1946 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
1947 // a pointer to the Output Device Context data structure (6.2.1).
1948 //
1949 Xhc->DCBAA[SlotId] = (UINT64) (UINTN) OutputDevContxt;
1950
1951 //
1952 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
1953 // Context data structure described above.
1954 //
1955 ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
1956 CmdTrbAddr.PtrLo = XHC_LOW_32BIT (UsbDevContext[SlotId].InputContext);
1957 CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (UsbDevContext[SlotId].InputContext);
1958 CmdTrbAddr.CycleBit = 1;
1959 CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;
1960 CmdTrbAddr.SlotId = UsbDevContext[SlotId].SlotId;
1961 Status = XhcCmdTransfer (
1962 Xhc,
1963 (TRB *) (UINTN) &CmdTrbAddr,
1964 XHC_GENERIC_TIMEOUT,
1965 (TRB **) (UINTN) &EvtTrb
1966 );
1967 ASSERT (!EFI_ERROR(Status));
1968
1969 DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputDevContxt)->Slot.DeviceAddress;
1970 DEBUG ((EFI_D_INFO, " Address %d assigned succeefully\n", DeviceAddress));
1971
1972 UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;
1973
1974 return Status;
1975 }
1976
1977 /**
1978 Disable the specified device slot.
1979
1980 @param Xhc The XHCI device.
1981 @param SlotId The slot id to be disabled.
1982
1983 @retval EFI_SUCCESS Successfully disable the device slot.
1984
1985 **/
1986 EFI_STATUS
1987 EFIAPI
1988 XhcDisableSlotCmd (
1989 IN USB_XHCI_DEV *Xhc,
1990 IN UINT8 SlotId
1991 )
1992 {
1993 EFI_STATUS Status;
1994 TRB *EvtTrb;
1995 CMD_TRB_DIS_SLOT CmdTrbDisSlot;
1996 UINT8 Index;
1997 VOID *RingSeg;
1998
1999 //
2000 // Disable the device slots occupied by these devices on its downstream ports.
2001 // Entry 0 is reserved.
2002 //
2003 for (Index = 0; Index < 255; Index++) {
2004 if (!UsbDevContext[Index + 1].Enabled ||
2005 (UsbDevContext[Index + 1].SlotId == 0) ||
2006 (UsbDevContext[Index + 1].ParentRouteString.Dword != UsbDevContext[SlotId].RouteString.Dword)) {
2007 continue;
2008 }
2009
2010 Status = XhcDisableSlotCmd (Xhc, UsbDevContext[Index + 1].SlotId);
2011
2012 if (EFI_ERROR (Status)) {
2013 DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));
2014 UsbDevContext[Index + 1].SlotId = 0;
2015 }
2016 }
2017
2018 //
2019 // Construct the disable slot command
2020 //
2021 DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));
2022
2023 ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));
2024 CmdTrbDisSlot.CycleBit = 1;
2025 CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;
2026 CmdTrbDisSlot.SlotId = SlotId;
2027 Status = XhcCmdTransfer (
2028 Xhc,
2029 (TRB *) (UINTN) &CmdTrbDisSlot,
2030 XHC_GENERIC_TIMEOUT,
2031 (TRB **) (UINTN) &EvtTrb
2032 );
2033 ASSERT_EFI_ERROR(Status);
2034 //
2035 // Free the slot's device context entry
2036 //
2037 Xhc->DCBAA[SlotId] = 0;
2038
2039 //
2040 // Free the slot related data structure
2041 //
2042 for (Index = 0; Index < 31; Index++) {
2043 if (UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {
2044 RingSeg = ((TRANSFER_RING *)(UINTN)UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;
2045 if (RingSeg != NULL) {
2046 FreeAlignedPool(RingSeg);
2047 }
2048 FreeAlignedPool(UsbDevContext[SlotId].EndpointTransferRing[Index]);
2049 }
2050 }
2051
2052 for (Index = 0; Index < UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {
2053 if (UsbDevContext[SlotId].ConfDesc[Index] != NULL) {
2054 FreePool (UsbDevContext[SlotId].ConfDesc[Index]);
2055 }
2056 }
2057
2058 if (UsbDevContext[SlotId].InputContext != NULL) {
2059 FreeAlignedPool (UsbDevContext[SlotId].InputContext);
2060 }
2061
2062 if (UsbDevContext[SlotId].OutputDevContxt != NULL) {
2063 FreeAlignedPool (UsbDevContext[SlotId].OutputDevContxt);
2064 }
2065 //
2066 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
2067 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
2068 // remove urb from XHCI's asynchronous transfer list.
2069 //
2070 UsbDevContext[SlotId].Enabled = FALSE;
2071
2072 return Status;
2073 }
2074
2075 /**
2076 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
2077
2078 @param Xhc The XHCI device.
2079 @param SlotId The slot id to be configured.
2080 @param DeviceSpeed The device's speed.
2081 @param ConfigDesc The pointer to the usb device configuration descriptor.
2082
2083 @retval EFI_SUCCESS Successfully configure all the device endpoints.
2084
2085 **/
2086 EFI_STATUS
2087 EFIAPI
2088 XhcSetConfigCmd (
2089 IN USB_XHCI_DEV *Xhc,
2090 IN UINT8 SlotId,
2091 IN UINT8 DeviceSpeed,
2092 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
2093 )
2094 {
2095 EFI_STATUS Status;
2096
2097 USB_INTERFACE_DESCRIPTOR *IfDesc;
2098 USB_ENDPOINT_DESCRIPTOR *EpDesc;
2099 UINT8 Index;
2100 UINTN NumEp;
2101 UINTN EpIndex;
2102 UINT8 EpAddr;
2103 UINT8 Direction;
2104 UINT8 Dci;
2105 UINT8 MaxDci;
2106 UINT32 PhyAddr;
2107 UINT8 Interval;
2108
2109 TRANSFER_RING *EndpointTransferRing;
2110 CMD_CFG_ED CmdTrbCfgEP;
2111 INPUT_CONTEXT *InputContext;
2112 DEVICE_CONTEXT *OutputDevContxt;
2113 EVT_TRB_COMMAND *EvtTrb;
2114 //
2115 // 4.6.6 Configure Endpoint
2116 //
2117 InputContext = UsbDevContext[SlotId].InputContext;
2118 OutputDevContxt = UsbDevContext[SlotId].OutputDevContxt;
2119 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
2120 CopyMem (&InputContext->Slot, &OutputDevContxt->Slot, sizeof (SLOT_CONTEXT));
2121
2122 ASSERT (ConfigDesc != NULL);
2123
2124 MaxDci = 0;
2125
2126 IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);
2127 for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {
2128 while (IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) {
2129 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
2130 }
2131
2132 NumEp = IfDesc->NumEndpoints;
2133
2134 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);
2135 for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {
2136 while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {
2137 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2138 }
2139
2140 EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);
2141 Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);
2142
2143 Dci = XhcEndpointToDci (EpAddr, Direction);
2144 if (Dci > MaxDci) {
2145 MaxDci = Dci;
2146 }
2147
2148 InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);
2149 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;
2150
2151 if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2152 //
2153 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
2154 //
2155 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2156 } else {
2157 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2158 }
2159
2160 switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {
2161 case USB_ENDPOINT_BULK:
2162 if (Direction == EfiUsbDataIn) {
2163 InputContext->EP[Dci-1].CErr = 3;
2164 InputContext->EP[Dci-1].EPType = ED_BULK_IN;
2165 } else {
2166 InputContext->EP[Dci-1].CErr = 3;
2167 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
2168 }
2169
2170 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2171 if (UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2172 EndpointTransferRing = AllocateAlignedZeroPool(sizeof (TRANSFER_RING), 64);
2173 UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2174 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2175 }
2176
2177 break;
2178 case USB_ENDPOINT_ISO:
2179 if (Direction == EfiUsbDataIn) {
2180 InputContext->EP[Dci-1].CErr = 0;
2181 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
2182 } else {
2183 InputContext->EP[Dci-1].CErr = 0;
2184 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
2185 }
2186 break;
2187 case USB_ENDPOINT_INTERRUPT:
2188 if (Direction == EfiUsbDataIn) {
2189 InputContext->EP[Dci-1].CErr = 3;
2190 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
2191 } else {
2192 InputContext->EP[Dci-1].CErr = 3;
2193 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
2194 }
2195 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2196 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
2197 //
2198 // Get the bInterval from descriptor and init the the interval field of endpoint context
2199 //
2200 if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {
2201 Interval = EpDesc->Interval;
2202 //
2203 // BUGBUG: Hard code the interval to MAX
2204 //
2205 InputContext->EP[Dci-1].Interval = 6;
2206 } else if (DeviceSpeed == EFI_USB_SPEED_SUPER) {
2207 Interval = EpDesc->Interval;
2208 InputContext->EP[Dci-1].Interval = 0x0F;
2209 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
2210 InputContext->EP[Dci-1].MaxESITPayload = 0x0002;
2211 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
2212 InputContext->EP[Dci-1].CErr = 3;
2213 }
2214
2215 if (UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {
2216 EndpointTransferRing = AllocateAlignedZeroPool(sizeof (TRANSFER_RING), 64);
2217 UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
2218 CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
2219 }
2220 break;
2221
2222 case USB_ENDPOINT_CONTROL:
2223 default:
2224 ASSERT (0);
2225 break;
2226 }
2227
2228 PhyAddr = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);
2229 PhyAddr &= ~(0x0F);
2230 PhyAddr |= ((TRANSFER_RING *)(UINTN)UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
2231 InputContext->EP[Dci-1].PtrLo = PhyAddr;
2232 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);
2233
2234 EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);
2235 }
2236 IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);
2237 }
2238
2239 InputContext->InputControlContext.Dword2 |= BIT0;
2240 InputContext->Slot.ContextEntries = MaxDci;
2241 //
2242 // configure endpoint
2243 //
2244 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
2245 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);
2246 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);
2247 CmdTrbCfgEP.CycleBit = 1;
2248 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
2249 CmdTrbCfgEP.SlotId = UsbDevContext[SlotId].SlotId;
2250 DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));
2251 Status = XhcCmdTransfer (
2252 Xhc,
2253 (TRB *) (UINTN) &CmdTrbCfgEP,
2254 XHC_GENERIC_TIMEOUT,
2255 (TRB **) (UINTN) &EvtTrb
2256 );
2257 ASSERT_EFI_ERROR(Status);
2258
2259 return Status;
2260 }
2261
2262 /**
2263 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
2264
2265 @param Xhc The XHCI device.
2266 @param SlotId The slot id to be evaluated.
2267 @param MaxPacketSize The max packet size supported by the device control transfer.
2268
2269 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
2270
2271 **/
2272 EFI_STATUS
2273 EFIAPI
2274 XhcEvaluateContext (
2275 IN USB_XHCI_DEV *Xhc,
2276 IN UINT8 SlotId,
2277 IN UINT32 MaxPacketSize
2278 )
2279 {
2280 EFI_STATUS Status;
2281 CMD_TRB_EVALU_CONTX CmdTrbEvalu;
2282 EVT_TRB_COMMAND *EvtTrb;
2283 INPUT_CONTEXT *InputContext;
2284
2285 ASSERT (UsbDevContext[SlotId].SlotId != 0);
2286
2287 //
2288 // 4.6.7 Evaluate Context
2289 //
2290 InputContext = UsbDevContext[SlotId].InputContext;
2291 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
2292
2293 InputContext->InputControlContext.Dword2 |= BIT1;
2294 InputContext->EP[0].MaxPacketSize = MaxPacketSize;
2295
2296 ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
2297 CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (InputContext);
2298 CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (InputContext);
2299 CmdTrbEvalu.CycleBit = 1;
2300 CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;
2301 CmdTrbEvalu.SlotId = UsbDevContext[SlotId].SlotId;
2302 DEBUG ((EFI_D_INFO, "Evaluate context\n"));
2303 Status = XhcCmdTransfer (
2304 Xhc,
2305 (TRB *) (UINTN) &CmdTrbEvalu,
2306 XHC_GENERIC_TIMEOUT,
2307 (TRB **) (UINTN) &EvtTrb
2308 );
2309 ASSERT (!EFI_ERROR(Status));
2310
2311 return Status;
2312 }
2313
2314 /**
2315 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
2316
2317 @param Xhc The XHCI device.
2318 @param SlotId The slot id to be configured.
2319 @param PortNum The total number of downstream port supported by the hub.
2320 @param TTT The TT think time of the hub device.
2321 @param MTT The multi-TT of the hub device.
2322
2323 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
2324
2325 **/
2326 EFI_STATUS
2327 XhcConfigHubContext (
2328 IN USB_XHCI_DEV *Xhc,
2329 IN UINT8 SlotId,
2330 IN UINT8 PortNum,
2331 IN UINT8 TTT,
2332 IN UINT8 MTT
2333 )
2334 {
2335 EFI_STATUS Status;
2336
2337 EVT_TRB_COMMAND *EvtTrb;
2338 INPUT_CONTEXT *InputContext;
2339 DEVICE_CONTEXT *OutputDevContxt;
2340 CMD_CFG_ED CmdTrbCfgEP;
2341
2342 ASSERT (UsbDevContext[SlotId].SlotId != 0);
2343 InputContext = UsbDevContext[SlotId].InputContext;
2344 OutputDevContxt = UsbDevContext[SlotId].OutputDevContxt;
2345
2346 //
2347 // 4.6.7 Evaluate Context
2348 //
2349 ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
2350
2351 InputContext->InputControlContext.Dword2 |= BIT0;
2352
2353 //
2354 // Copy the slot context from OutputContext to Input context
2355 //
2356 CopyMem(&(InputContext->Slot), &(OutputDevContxt->Slot), sizeof (SLOT_CONTEXT));
2357 InputContext->Slot.Hub = 1;
2358 InputContext->Slot.PortNum = PortNum;
2359 InputContext->Slot.TTT = TTT;
2360 InputContext->Slot.MTT = MTT;
2361
2362 ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
2363 CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);
2364 CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);
2365 CmdTrbCfgEP.CycleBit = 1;
2366 CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;
2367 CmdTrbCfgEP.SlotId = UsbDevContext[SlotId].SlotId;
2368 DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));
2369 Status = XhcCmdTransfer (
2370 Xhc,
2371 (TRB *) (UINTN) &CmdTrbCfgEP,
2372 XHC_GENERIC_TIMEOUT,
2373 (TRB **) (UINTN) &EvtTrb
2374 );
2375 ASSERT (!EFI_ERROR(Status));
2376
2377 return Status;
2378 }
2379
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