931c7efa0c283160f1168788e0b3a569945beb19
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciSched.h
1 /** @file
2
3 This file contains the definition for XHCI host controller schedule routines.
4
5 Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #ifndef _EFI_XHCI_SCHED_H_
17 #define _EFI_XHCI_SCHED_H_
18
19 #define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
20
21 //
22 // Transfer types, used in URB to identify the transfer type
23 //
24 #define XHC_CTRL_TRANSFER 0x01
25 #define XHC_BULK_TRANSFER 0x02
26 #define XHC_INT_TRANSFER_SYNC 0x04
27 #define XHC_INT_TRANSFER_ASYNC 0x08
28 #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10
29
30 //
31 // 6.4.6 TRB Types
32 //
33 #define TRB_TYPE_NORMAL 1
34 #define TRB_TYPE_SETUP_STAGE 2
35 #define TRB_TYPE_DATA_STAGE 3
36 #define TRB_TYPE_STATUS_STAGE 4
37 #define TRB_TYPE_ISOCH 5
38 #define TRB_TYPE_LINK 6
39 #define TRB_TYPE_EVENT_DATA 7
40 #define TRB_TYPE_NO_OP 8
41 #define TRB_TYPE_EN_SLOT 9
42 #define TRB_TYPE_DIS_SLOT 10
43 #define TRB_TYPE_ADDRESS_DEV 11
44 #define TRB_TYPE_CON_ENDPOINT 12
45 #define TRB_TYPE_EVALU_CONTXT 13
46 #define TRB_TYPE_RESET_ENDPOINT 14
47 #define TRB_TYPE_STOP_ENDPOINT 15
48 #define TRB_TYPE_SET_TR_DEQUE 16
49 #define TRB_TYPE_RESET_DEV 17
50 #define TRB_TYPE_GET_PORT_BANW 21
51 #define TRB_TYPE_FORCE_HEADER 22
52 #define TRB_TYPE_NO_OP_COMMAND 23
53 #define TRB_TYPE_TRANS_EVENT 32
54 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
55 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
56 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
57 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
58 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
59
60 //
61 // Endpoint Type (EP Type).
62 //
63 #define ED_NOT_VALID 0
64 #define ED_ISOCH_OUT 1
65 #define ED_BULK_OUT 2
66 #define ED_INTERRUPT_OUT 3
67 #define ED_CONTROL_BIDIR 4
68 #define ED_ISOCH_IN 5
69 #define ED_BULK_IN 6
70 #define ED_INTERRUPT_IN 7
71
72 //
73 // 6.4.5 TRB Completion Codes
74 //
75 #define TRB_COMPLETION_INVALID 0
76 #define TRB_COMPLETION_SUCCESS 1
77 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
78 #define TRB_COMPLETION_BABBLE_ERROR 3
79 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
80 #define TRB_COMPLETION_TRB_ERROR 5
81 #define TRB_COMPLETION_STALL_ERROR 6
82 #define TRB_COMPLETION_SHORT_PACKET 13
83
84 //
85 // The topology string used to present usb device location
86 //
87 typedef struct _USB_DEV_TOPOLOGY {
88 //
89 // The tier concatenation of down stream port.
90 //
91 UINT32 RouteString:20;
92 //
93 // The root port number of the chain.
94 //
95 UINT32 RootPortNum:8;
96 //
97 // The Tier the device reside.
98 //
99 UINT32 TierNum:4;
100 } USB_DEV_TOPOLOGY;
101
102 //
103 // USB Device's RouteChart
104 //
105 typedef union _USB_DEV_ROUTE {
106 UINT32 Dword;
107 USB_DEV_TOPOLOGY Route;
108 } USB_DEV_ROUTE;
109
110 //
111 // Endpoint address and its capabilities
112 //
113 typedef struct _USB_ENDPOINT {
114 //
115 // Store logical device address assigned by UsbBus
116 // It's because some XHCI host controllers may assign the same physcial device
117 // address for those devices inserted at different root port.
118 //
119 UINT8 BusAddr;
120 UINT8 DevAddr;
121 UINT8 EpAddr;
122 EFI_USB_DATA_DIRECTION Direction;
123 UINT8 DevSpeed;
124 UINTN MaxPacket;
125 UINTN Type;
126 } USB_ENDPOINT;
127
128 //
129 // TRB Template
130 //
131 typedef struct _TRB_TEMPLATE {
132 UINT32 Parameter1;
133
134 UINT32 Parameter2;
135
136 UINT32 Status;
137
138 UINT32 CycleBit:1;
139 UINT32 RsvdZ1:9;
140 UINT32 Type:6;
141 UINT32 Control:16;
142 } TRB_TEMPLATE;
143
144 typedef struct _TRANSFER_RING {
145 VOID *RingSeg0;
146 UINTN TrbNumber;
147 TRB_TEMPLATE *RingEnqueue;
148 TRB_TEMPLATE *RingDequeue;
149 UINT32 RingPCS;
150 } TRANSFER_RING;
151
152 typedef struct _EVENT_RING {
153 VOID *ERSTBase;
154 VOID *EventRingSeg0;
155 UINTN TrbNumber;
156 TRB_TEMPLATE *EventRingEnqueue;
157 TRB_TEMPLATE *EventRingDequeue;
158 UINT32 EventRingCCS;
159 } EVENT_RING;
160
161 //
162 // URB (Usb Request Block) contains information for all kinds of
163 // usb requests.
164 //
165 typedef struct _URB {
166 UINT32 Signature;
167 LIST_ENTRY UrbList;
168 //
169 // Usb Device URB related information
170 //
171 USB_ENDPOINT Ep;
172 EFI_USB_DEVICE_REQUEST *Request;
173 VOID *Data;
174 UINTN DataLen;
175 VOID *DataPhy;
176 VOID *DataMap;
177 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
178 VOID *Context;
179 //
180 // Execute result
181 //
182 UINT32 Result;
183 //
184 // completed data length
185 //
186 UINTN Completed;
187 //
188 // Command/Tranfer Ring info
189 //
190 TRANSFER_RING *Ring;
191 TRB_TEMPLATE *TrbStart;
192 TRB_TEMPLATE *TrbEnd;
193 UINTN TrbNum;
194 BOOLEAN StartDone;
195 BOOLEAN EndDone;
196 BOOLEAN Finished;
197
198 TRB_TEMPLATE *EvtTrb;
199 } URB;
200
201 //
202 // 6.5 Event Ring Segment Table
203 // The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime
204 // expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the
205 // Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table
206 // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
207 //
208 typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
209 UINT32 PtrLo;
210 UINT32 PtrHi;
211 UINT32 RingTrbSize:16;
212 UINT32 RsvdZ1:16;
213 UINT32 RsvdZ2;
214 } EVENT_RING_SEG_TABLE_ENTRY;
215
216 //
217 // 6.4.1.1 Normal TRB
218 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
219 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
220 // Rings, and to define the Data stage information for Control Transfer Rings.
221 //
222 typedef struct _TRANSFER_TRB_NORMAL {
223 UINT32 TRBPtrLo;
224
225 UINT32 TRBPtrHi;
226
227 UINT32 Length:17;
228 UINT32 TDSize:5;
229 UINT32 IntTarget:10;
230
231 UINT32 CycleBit:1;
232 UINT32 ENT:1;
233 UINT32 ISP:1;
234 UINT32 NS:1;
235 UINT32 CH:1;
236 UINT32 IOC:1;
237 UINT32 IDT:1;
238 UINT32 RsvdZ1:2;
239 UINT32 BEI:1;
240 UINT32 Type:6;
241 UINT32 RsvdZ2:16;
242 } TRANSFER_TRB_NORMAL;
243
244 //
245 // 6.4.1.2.1 Setup Stage TRB
246 // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
247 //
248 typedef struct _TRANSFER_TRB_CONTROL_SETUP {
249 UINT32 bmRequestType:8;
250 UINT32 bRequest:8;
251 UINT32 wValue:16;
252
253 UINT32 wIndex:16;
254 UINT32 wLength:16;
255
256 UINT32 Length:17;
257 UINT32 RsvdZ1:5;
258 UINT32 IntTarget:10;
259
260 UINT32 CycleBit:1;
261 UINT32 RsvdZ2:4;
262 UINT32 IOC:1;
263 UINT32 IDT:1;
264 UINT32 RsvdZ3:3;
265 UINT32 Type:6;
266 UINT32 TRT:2;
267 UINT32 RsvdZ4:14;
268 } TRANSFER_TRB_CONTROL_SETUP;
269
270 //
271 // 6.4.1.2.2 Data Stage TRB
272 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
273 //
274 typedef struct _TRANSFER_TRB_CONTROL_DATA {
275 UINT32 TRBPtrLo;
276
277 UINT32 TRBPtrHi;
278
279 UINT32 Length:17;
280 UINT32 TDSize:5;
281 UINT32 IntTarget:10;
282
283 UINT32 CycleBit:1;
284 UINT32 ENT:1;
285 UINT32 ISP:1;
286 UINT32 NS:1;
287 UINT32 CH:1;
288 UINT32 IOC:1;
289 UINT32 IDT:1;
290 UINT32 RsvdZ1:3;
291 UINT32 Type:6;
292 UINT32 DIR:1;
293 UINT32 RsvdZ2:15;
294 } TRANSFER_TRB_CONTROL_DATA;
295
296 //
297 // 6.4.1.2.2 Data Stage TRB
298 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
299 //
300 typedef struct _TRANSFER_TRB_CONTROL_STATUS {
301 UINT32 RsvdZ1;
302 UINT32 RsvdZ2;
303
304 UINT32 RsvdZ3:22;
305 UINT32 IntTarget:10;
306
307 UINT32 CycleBit:1;
308 UINT32 ENT:1;
309 UINT32 RsvdZ4:2;
310 UINT32 CH:1;
311 UINT32 IOC:1;
312 UINT32 RsvdZ5:4;
313 UINT32 Type:6;
314 UINT32 DIR:1;
315 UINT32 RsvdZ6:15;
316 } TRANSFER_TRB_CONTROL_STATUS;
317
318 //
319 // 6.4.2.1 Transfer Event TRB
320 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
321 // for more information on the use and operation of Transfer Events.
322 //
323 typedef struct _EVT_TRB_TRANSFER {
324 UINT32 TRBPtrLo;
325
326 UINT32 TRBPtrHi;
327
328 UINT32 Length:24;
329 UINT32 Completecode:8;
330
331 UINT32 CycleBit:1;
332 UINT32 RsvdZ1:1;
333 UINT32 ED:1;
334 UINT32 RsvdZ2:7;
335 UINT32 Type:6;
336 UINT32 EndpointId:5;
337 UINT32 RsvdZ3:3;
338 UINT32 SlotId:8;
339 } EVT_TRB_TRANSFER;
340
341 //
342 // 6.4.2.2 Command Completion Event TRB
343 // A Command Completion Event TRB shall be generated by the xHC when a command completes on the
344 // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
345 //
346 typedef struct _EVT_TRB_COMMAND_COMPLETION {
347 UINT32 TRBPtrLo;
348
349 UINT32 TRBPtrHi;
350
351 UINT32 RsvdZ2:24;
352 UINT32 Completecode:8;
353
354 UINT32 CycleBit:1;
355 UINT32 RsvdZ3:9;
356 UINT32 Type:6;
357 UINT32 VFID:8;
358 UINT32 SlotId:8;
359 } EVT_TRB_COMMAND_COMPLETION;
360
361 typedef union _TRB {
362 TRB_TEMPLATE TrbTemplate;
363 TRANSFER_TRB_NORMAL TrbNormal;
364 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
365 TRANSFER_TRB_CONTROL_DATA TrbCtrData;
366 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
367 } TRB;
368
369 //
370 // 6.4.3.1 No Op Command TRB
371 // The No Op Command TRB provides a simple means for verifying the operation of the Command Ring
372 // mechanisms offered by the xHCI.
373 //
374 typedef struct _CMD_TRB_NO_OP {
375 UINT32 RsvdZ0;
376 UINT32 RsvdZ1;
377 UINT32 RsvdZ2;
378
379 UINT32 CycleBit:1;
380 UINT32 RsvdZ3:9;
381 UINT32 Type:6;
382 UINT32 RsvdZ4:16;
383 } CMD_TRB_NO_OP;
384
385 //
386 // 6.4.3.2 Enable Slot Command TRB
387 // The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the
388 // selected slot to the host in a Command Completion Event.
389 //
390 typedef struct _CMD_TRB_ENABLE_SLOT {
391 UINT32 RsvdZ0;
392 UINT32 RsvdZ1;
393 UINT32 RsvdZ2;
394
395 UINT32 CycleBit:1;
396 UINT32 RsvdZ3:9;
397 UINT32 Type:6;
398 UINT32 RsvdZ4:16;
399 } CMD_TRB_ENABLE_SLOT;
400
401 //
402 // 6.4.3.3 Disable Slot Command TRB
403 // The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any
404 // internal xHC resources assigned to the slot.
405 //
406 typedef struct _CMD_TRB_DISABLE_SLOT {
407 UINT32 RsvdZ0;
408 UINT32 RsvdZ1;
409 UINT32 RsvdZ2;
410
411 UINT32 CycleBit:1;
412 UINT32 RsvdZ3:9;
413 UINT32 Type:6;
414 UINT32 RsvdZ4:8;
415 UINT32 SlotId:8;
416 } CMD_TRB_DISABLE_SLOT;
417
418 //
419 // 6.4.3.4 Address Device Command TRB
420 // The Address Device Command TRB transitions the selected Device Context from the Default to the
421 // Addressed state and causes the xHC to select an address for the USB device in the Default State and
422 // issue a SET_ADDRESS request to the USB device.
423 //
424 typedef struct _CMD_TRB_ADDRESS_DEVICE {
425 UINT32 PtrLo;
426
427 UINT32 PtrHi;
428
429 UINT32 RsvdZ1;
430
431 UINT32 CycleBit:1;
432 UINT32 RsvdZ2:8;
433 UINT32 BSR:1;
434 UINT32 Type:6;
435 UINT32 RsvdZ3:8;
436 UINT32 SlotId:8;
437 } CMD_TRB_ADDRESS_DEVICE;
438
439 //
440 // 6.4.3.5 Configure Endpoint Command TRB
441 // The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the
442 // endpoints selected by the command.
443 //
444 typedef struct _CMD_TRB_CONFIG_ENDPOINT {
445 UINT32 PtrLo;
446
447 UINT32 PtrHi;
448
449 UINT32 RsvdZ1;
450
451 UINT32 CycleBit:1;
452 UINT32 RsvdZ2:8;
453 UINT32 DC:1;
454 UINT32 Type:6;
455 UINT32 RsvdZ3:8;
456 UINT32 SlotId:8;
457 } CMD_TRB_CONFIG_ENDPOINT;
458
459 //
460 // 6.4.3.6 Evaluate Context Command TRB
461 // The Evaluate Context Command TRB is used by system software to inform the xHC that the selected
462 // Context data structures in the Device Context have been modified by system software and that the xHC
463 // shall evaluate any changes
464 //
465 typedef struct _CMD_TRB_EVALUATE_CONTEXT {
466 UINT32 PtrLo;
467
468 UINT32 PtrHi;
469
470 UINT32 RsvdZ1;
471
472 UINT32 CycleBit:1;
473 UINT32 RsvdZ2:9;
474 UINT32 Type:6;
475 UINT32 RsvdZ3:8;
476 UINT32 SlotId:8;
477 } CMD_TRB_EVALUATE_CONTEXT;
478
479 //
480 // 6.4.3.7 Reset Endpoint Command TRB
481 // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
482 //
483 typedef struct _CMD_TRB_RESET_ENDPOINT {
484 UINT32 RsvdZ0;
485 UINT32 RsvdZ1;
486 UINT32 RsvdZ2;
487
488 UINT32 CycleBit:1;
489 UINT32 RsvdZ3:8;
490 UINT32 TSP:1;
491 UINT32 Type:6;
492 UINT32 EDID:5;
493 UINT32 RsvdZ4:3;
494 UINT32 SlotId:8;
495 } CMD_TRB_RESET_ENDPOINT;
496
497 //
498 // 6.4.3.8 Stop Endpoint Command TRB
499 // The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a
500 // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
501 //
502 typedef struct _CMD_TRB_STOP_ENDPOINT {
503 UINT32 RsvdZ0;
504 UINT32 RsvdZ1;
505 UINT32 RsvdZ2;
506
507 UINT32 CycleBit:1;
508 UINT32 RsvdZ3:9;
509 UINT32 Type:6;
510 UINT32 EDID:5;
511 UINT32 RsvdZ4:2;
512 UINT32 SP:1;
513 UINT32 SlotId:8;
514 } CMD_TRB_STOP_ENDPOINT;
515
516 //
517 // 6.4.3.9 Set TR Dequeue Pointer Command TRB
518 // The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue
519 // Pointer and DCS fields of an Endpoint or Stream Context.
520 //
521 typedef struct _CMD_SET_TR_DEQ_POINTER {
522 UINT32 PtrLo;
523
524 UINT32 PtrHi;
525
526 UINT32 RsvdZ1:16;
527 UINT32 StreamID:16;
528
529 UINT32 CycleBit:1;
530 UINT32 RsvdZ2:9;
531 UINT32 Type:6;
532 UINT32 Endpoint:5;
533 UINT32 RsvdZ3:3;
534 UINT32 SlotId:8;
535 } CMD_SET_TR_DEQ_POINTER;
536
537 //
538 // 6.4.4.1 Link TRB
539 // A Link TRB provides support for non-contiguous TRB Rings.
540 //
541 typedef struct _LINK_TRB {
542 UINT32 PtrLo;
543
544 UINT32 PtrHi;
545
546 UINT32 RsvdZ1:22;
547 UINT32 InterTarget:10;
548
549 UINT32 CycleBit:1;
550 UINT32 TC:1;
551 UINT32 RsvdZ2:2;
552 UINT32 CH:1;
553 UINT32 IOC:1;
554 UINT32 RsvdZ3:4;
555 UINT32 Type:6;
556 UINT32 RsvdZ4:16;
557 } LINK_TRB;
558
559 //
560 // 6.2.2 Slot Context
561 //
562 typedef struct _SLOT_CONTEXT {
563 UINT32 RouteString:20;
564 UINT32 Speed:4;
565 UINT32 RsvdZ1:1;
566 UINT32 MTT:1;
567 UINT32 Hub:1;
568 UINT32 ContextEntries:5;
569
570 UINT32 MaxExitLatency:16;
571 UINT32 RootHubPortNum:8;
572 UINT32 PortNum:8;
573
574 UINT32 TTHubSlotId:8;
575 UINT32 TTPortNum:8;
576 UINT32 TTT:2;
577 UINT32 RsvdZ2:4;
578 UINT32 InterTarget:10;
579
580 UINT32 DeviceAddress:8;
581 UINT32 RsvdZ3:19;
582 UINT32 SlotState:5;
583
584 UINT32 RsvdZ4;
585 UINT32 RsvdZ5;
586 UINT32 RsvdZ6;
587 UINT32 RsvdZ7;
588 } SLOT_CONTEXT;
589
590 typedef struct _SLOT_CONTEXT_64 {
591 UINT32 RouteString:20;
592 UINT32 Speed:4;
593 UINT32 RsvdZ1:1;
594 UINT32 MTT:1;
595 UINT32 Hub:1;
596 UINT32 ContextEntries:5;
597
598 UINT32 MaxExitLatency:16;
599 UINT32 RootHubPortNum:8;
600 UINT32 PortNum:8;
601
602 UINT32 TTHubSlotId:8;
603 UINT32 TTPortNum:8;
604 UINT32 TTT:2;
605 UINT32 RsvdZ2:4;
606 UINT32 InterTarget:10;
607
608 UINT32 DeviceAddress:8;
609 UINT32 RsvdZ3:19;
610 UINT32 SlotState:5;
611
612 UINT32 RsvdZ4;
613 UINT32 RsvdZ5;
614 UINT32 RsvdZ6;
615 UINT32 RsvdZ7;
616
617 UINT32 RsvdZ8;
618 UINT32 RsvdZ9;
619 UINT32 RsvdZ10;
620 UINT32 RsvdZ11;
621
622 UINT32 RsvdZ12;
623 UINT32 RsvdZ13;
624 UINT32 RsvdZ14;
625 UINT32 RsvdZ15;
626
627 } SLOT_CONTEXT_64;
628
629
630 //
631 // 6.2.3 Endpoint Context
632 //
633 typedef struct _ENDPOINT_CONTEXT {
634 UINT32 EPState:3;
635 UINT32 RsvdZ1:5;
636 UINT32 Mult:2;
637 UINT32 MaxPStreams:5;
638 UINT32 LSA:1;
639 UINT32 Interval:8;
640 UINT32 RsvdZ2:8;
641
642 UINT32 RsvdZ3:1;
643 UINT32 CErr:2;
644 UINT32 EPType:3;
645 UINT32 RsvdZ4:1;
646 UINT32 HID:1;
647 UINT32 MaxBurstSize:8;
648 UINT32 MaxPacketSize:16;
649
650 UINT32 PtrLo;
651
652 UINT32 PtrHi;
653
654 UINT32 AverageTRBLength:16;
655 UINT32 MaxESITPayload:16;
656
657 UINT32 RsvdZ5;
658 UINT32 RsvdZ6;
659 UINT32 RsvdZ7;
660 } ENDPOINT_CONTEXT;
661
662 typedef struct _ENDPOINT_CONTEXT_64 {
663 UINT32 EPState:3;
664 UINT32 RsvdZ1:5;
665 UINT32 Mult:2;
666 UINT32 MaxPStreams:5;
667 UINT32 LSA:1;
668 UINT32 Interval:8;
669 UINT32 RsvdZ2:8;
670
671 UINT32 RsvdZ3:1;
672 UINT32 CErr:2;
673 UINT32 EPType:3;
674 UINT32 RsvdZ4:1;
675 UINT32 HID:1;
676 UINT32 MaxBurstSize:8;
677 UINT32 MaxPacketSize:16;
678
679 UINT32 PtrLo;
680
681 UINT32 PtrHi;
682
683 UINT32 AverageTRBLength:16;
684 UINT32 MaxESITPayload:16;
685
686 UINT32 RsvdZ5;
687 UINT32 RsvdZ6;
688 UINT32 RsvdZ7;
689
690 UINT32 RsvdZ8;
691 UINT32 RsvdZ9;
692 UINT32 RsvdZ10;
693 UINT32 RsvdZ11;
694
695 UINT32 RsvdZ12;
696 UINT32 RsvdZ13;
697 UINT32 RsvdZ14;
698 UINT32 RsvdZ15;
699
700 } ENDPOINT_CONTEXT_64;
701
702
703 //
704 // 6.2.5.1 Input Control Context
705 //
706 typedef struct _INPUT_CONTRL_CONTEXT {
707 UINT32 Dword1;
708 UINT32 Dword2;
709 UINT32 RsvdZ1;
710 UINT32 RsvdZ2;
711 UINT32 RsvdZ3;
712 UINT32 RsvdZ4;
713 UINT32 RsvdZ5;
714 UINT32 RsvdZ6;
715 } INPUT_CONTRL_CONTEXT;
716
717 typedef struct _INPUT_CONTRL_CONTEXT_64 {
718 UINT32 Dword1;
719 UINT32 Dword2;
720 UINT32 RsvdZ1;
721 UINT32 RsvdZ2;
722 UINT32 RsvdZ3;
723 UINT32 RsvdZ4;
724 UINT32 RsvdZ5;
725 UINT32 RsvdZ6;
726 UINT32 RsvdZ7;
727 UINT32 RsvdZ8;
728 UINT32 RsvdZ9;
729 UINT32 RsvdZ10;
730 UINT32 RsvdZ11;
731 UINT32 RsvdZ12;
732 UINT32 RsvdZ13;
733 UINT32 RsvdZ14;
734 } INPUT_CONTRL_CONTEXT_64;
735
736 //
737 // 6.2.1 Device Context
738 //
739 typedef struct _DEVICE_CONTEXT {
740 SLOT_CONTEXT Slot;
741 ENDPOINT_CONTEXT EP[31];
742 } DEVICE_CONTEXT;
743
744 typedef struct _DEVICE_CONTEXT_64 {
745 SLOT_CONTEXT_64 Slot;
746 ENDPOINT_CONTEXT_64 EP[31];
747 } DEVICE_CONTEXT_64;
748
749 //
750 // 6.2.5 Input Context
751 //
752 typedef struct _INPUT_CONTEXT {
753 INPUT_CONTRL_CONTEXT InputControlContext;
754 SLOT_CONTEXT Slot;
755 ENDPOINT_CONTEXT EP[31];
756 } INPUT_CONTEXT;
757
758 typedef struct _INPUT_CONTEXT_64 {
759 INPUT_CONTRL_CONTEXT_64 InputControlContext;
760 SLOT_CONTEXT_64 Slot;
761 ENDPOINT_CONTEXT_64 EP[31];
762 } INPUT_CONTEXT_64;
763
764
765 /**
766 Initialize the XHCI host controller for schedule.
767
768 @param Xhc The XHCI Instance to be initialized.
769
770 **/
771 VOID
772 XhcInitSched (
773 IN USB_XHCI_INSTANCE *Xhc
774 );
775
776 /**
777 Free the resouce allocated at initializing schedule.
778
779 @param Xhc The XHCI Instance.
780
781 **/
782 VOID
783 XhcFreeSched (
784 IN USB_XHCI_INSTANCE *Xhc
785 );
786
787 /**
788 Ring the door bell to notify XHCI there is a transaction to be executed through URB.
789
790 @param Xhc The XHCI Instance.
791 @param Urb The URB to be rung.
792
793 @retval EFI_SUCCESS Successfully ring the door bell.
794
795 **/
796 EFI_STATUS
797 RingIntTransferDoorBell (
798 IN USB_XHCI_INSTANCE *Xhc,
799 IN URB *Urb
800 );
801
802 /**
803 Execute the transfer by polling the URB. This is a synchronous operation.
804
805 @param Xhc The XHCI Instance.
806 @param CmdTransfer The executed URB is for cmd transfer or not.
807 @param Urb The URB to execute.
808 @param Timeout The time to wait before abort, in millisecond.
809
810 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
811 @return EFI_TIMEOUT The transfer failed due to time out.
812 @return EFI_SUCCESS The transfer finished OK.
813
814 **/
815 EFI_STATUS
816 XhcExecTransfer (
817 IN USB_XHCI_INSTANCE *Xhc,
818 IN BOOLEAN CmdTransfer,
819 IN URB *Urb,
820 IN UINTN Timeout
821 );
822
823 /**
824 Delete a single asynchronous interrupt transfer for
825 the device and endpoint.
826
827 @param Xhc The XHCI Instance.
828 @param BusAddr The logical device address assigned by UsbBus driver.
829 @param EpNum The endpoint of the target.
830
831 @retval EFI_SUCCESS An asynchronous transfer is removed.
832 @retval EFI_NOT_FOUND No transfer for the device is found.
833
834 **/
835 EFI_STATUS
836 XhciDelAsyncIntTransfer (
837 IN USB_XHCI_INSTANCE *Xhc,
838 IN UINT8 BusAddr,
839 IN UINT8 EpNum
840 );
841
842 /**
843 Remove all the asynchronous interrupt transfers.
844
845 @param Xhc The XHCI Instance.
846
847 **/
848 VOID
849 XhciDelAllAsyncIntTransfers (
850 IN USB_XHCI_INSTANCE *Xhc
851 );
852
853 /**
854 Set Bios Ownership
855
856 @param Xhc The XHCI Instance.
857
858 **/
859 VOID
860 XhcSetBiosOwnership (
861 IN USB_XHCI_INSTANCE *Xhc
862 );
863
864 /**
865 Clear Bios Ownership
866
867 @param Xhc The XHCI Instance.
868
869 **/
870 VOID
871 XhcClearBiosOwnership (
872 IN USB_XHCI_INSTANCE *Xhc
873 );
874
875 /**
876 Find out the slot id according to the device's route string.
877
878 @param Xhc The XHCI Instance.
879 @param RouteString The route string described the device location.
880
881 @return The slot id used by the device.
882
883 **/
884 UINT8
885 EFIAPI
886 XhcRouteStringToSlotId (
887 IN USB_XHCI_INSTANCE *Xhc,
888 IN USB_DEV_ROUTE RouteString
889 );
890
891 /**
892 Calculate the device context index by endpoint address and direction.
893
894 @param EpAddr The target endpoint number.
895 @param Direction The direction of the target endpoint.
896
897 @return The device context index of endpoint.
898
899 **/
900 UINT8
901 XhcEndpointToDci (
902 IN UINT8 EpAddr,
903 IN UINT8 Direction
904 );
905
906 /**
907 Ring the door bell to notify XHCI there is a transaction to be executed.
908
909 @param Xhc The XHCI Instance.
910 @param SlotId The slot id of the target device.
911 @param Dci The device context index of the target slot or endpoint.
912
913 @retval EFI_SUCCESS Successfully ring the door bell.
914
915 **/
916 EFI_STATUS
917 EFIAPI
918 XhcRingDoorBell (
919 IN USB_XHCI_INSTANCE *Xhc,
920 IN UINT8 SlotId,
921 IN UINT8 Dci
922 );
923
924 /**
925 Interrupt transfer periodic check handler.
926
927 @param Event Interrupt event.
928 @param Context Pointer to USB_XHCI_INSTANCE.
929
930 **/
931 VOID
932 EFIAPI
933 XhcMonitorAsyncRequests (
934 IN EFI_EVENT Event,
935 IN VOID *Context
936 );
937
938 /**
939 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
940
941 @param Xhc The XHCI Instance.
942 @param ParentRouteChart The route string pointed to the parent device if it exists.
943 @param Port The port to be polled.
944 @param PortState The port state.
945
946 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
947 @retval Others Should not appear.
948
949 **/
950 EFI_STATUS
951 EFIAPI
952 XhcPollPortStatusChange (
953 IN USB_XHCI_INSTANCE *Xhc,
954 IN USB_DEV_ROUTE ParentRouteChart,
955 IN UINT8 Port,
956 IN EFI_USB_PORT_STATUS *PortState
957 );
958
959 /**
960 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
961
962 @param Xhc The XHCI Instance.
963 @param SlotId The slot id to be configured.
964 @param PortNum The total number of downstream port supported by the hub.
965 @param TTT The TT think time of the hub device.
966 @param MTT The multi-TT of the hub device.
967
968 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
969
970 **/
971 EFI_STATUS
972 XhcConfigHubContext (
973 IN USB_XHCI_INSTANCE *Xhc,
974 IN UINT8 SlotId,
975 IN UINT8 PortNum,
976 IN UINT8 TTT,
977 IN UINT8 MTT
978 );
979
980
981 /**
982 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
983
984 @param Xhc The XHCI Instance.
985 @param SlotId The slot id to be configured.
986 @param PortNum The total number of downstream port supported by the hub.
987 @param TTT The TT think time of the hub device.
988 @param MTT The multi-TT of the hub device.
989
990 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
991
992 **/
993 EFI_STATUS
994 XhcConfigHubContext64 (
995 IN USB_XHCI_INSTANCE *Xhc,
996 IN UINT8 SlotId,
997 IN UINT8 PortNum,
998 IN UINT8 TTT,
999 IN UINT8 MTT
1000 );
1001
1002
1003 /**
1004 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1005
1006 @param Xhc The XHCI Instance.
1007 @param SlotId The slot id to be configured.
1008 @param DeviceSpeed The device's speed.
1009 @param ConfigDesc The pointer to the usb device configuration descriptor.
1010
1011 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1012
1013 **/
1014 EFI_STATUS
1015 EFIAPI
1016 XhcSetConfigCmd (
1017 IN USB_XHCI_INSTANCE *Xhc,
1018 IN UINT8 SlotId,
1019 IN UINT8 DeviceSpeed,
1020 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1021 );
1022
1023
1024 /**
1025 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1026
1027 @param Xhc The XHCI Instance.
1028 @param SlotId The slot id to be configured.
1029 @param DeviceSpeed The device's speed.
1030 @param ConfigDesc The pointer to the usb device configuration descriptor.
1031
1032 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1033
1034 **/
1035 EFI_STATUS
1036 EFIAPI
1037 XhcSetConfigCmd64 (
1038 IN USB_XHCI_INSTANCE *Xhc,
1039 IN UINT8 SlotId,
1040 IN UINT8 DeviceSpeed,
1041 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
1042 );
1043
1044 /**
1045 Set interface through XHCI's Configure_Endpoint cmd.
1046
1047 @param Xhc The XHCI Instance.
1048 @param SlotId The slot id to be configured.
1049 @param DeviceSpeed The device's speed.
1050 @param ConfigDesc The pointer to the usb device configuration descriptor.
1051 @param Request USB device request to send.
1052
1053 @retval EFI_SUCCESS Successfully set interface.
1054
1055 **/
1056 EFI_STATUS
1057 EFIAPI
1058 XhcSetInterface (
1059 IN USB_XHCI_INSTANCE *Xhc,
1060 IN UINT8 SlotId,
1061 IN UINT8 DeviceSpeed,
1062 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
1063 IN EFI_USB_DEVICE_REQUEST *Request
1064 );
1065
1066 /**
1067 Set interface through XHCI's Configure_Endpoint cmd.
1068
1069 @param Xhc The XHCI Instance.
1070 @param SlotId The slot id to be configured.
1071 @param DeviceSpeed The device's speed.
1072 @param ConfigDesc The pointer to the usb device configuration descriptor.
1073 @param Request USB device request to send.
1074
1075 @retval EFI_SUCCESS Successfully set interface.
1076
1077 **/
1078 EFI_STATUS
1079 EFIAPI
1080 XhcSetInterface64 (
1081 IN USB_XHCI_INSTANCE *Xhc,
1082 IN UINT8 SlotId,
1083 IN UINT8 DeviceSpeed,
1084 IN USB_CONFIG_DESCRIPTOR *ConfigDesc,
1085 IN EFI_USB_DEVICE_REQUEST *Request
1086 );
1087
1088 /**
1089 Find out the actual device address according to the requested device address from UsbBus.
1090
1091 @param Xhc The XHCI Instance.
1092 @param BusDevAddr The requested device address by UsbBus upper driver.
1093
1094 @return The actual device address assigned to the device.
1095
1096 **/
1097 UINT8
1098 EFIAPI
1099 XhcBusDevAddrToSlotId (
1100 IN USB_XHCI_INSTANCE *Xhc,
1101 IN UINT8 BusDevAddr
1102 );
1103
1104 /**
1105 Assign and initialize the device slot for a new device.
1106
1107 @param Xhc The XHCI Instance.
1108 @param ParentRouteChart The route string pointed to the parent device.
1109 @param ParentPort The port at which the device is located.
1110 @param RouteChart The route string pointed to the device.
1111 @param DeviceSpeed The device speed.
1112
1113 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1114
1115 **/
1116 EFI_STATUS
1117 EFIAPI
1118 XhcInitializeDeviceSlot (
1119 IN USB_XHCI_INSTANCE *Xhc,
1120 IN USB_DEV_ROUTE ParentRouteChart,
1121 IN UINT16 ParentPort,
1122 IN USB_DEV_ROUTE RouteChart,
1123 IN UINT8 DeviceSpeed
1124 );
1125
1126 /**
1127 Assign and initialize the device slot for a new device.
1128
1129 @param Xhc The XHCI Instance.
1130 @param ParentRouteChart The route string pointed to the parent device.
1131 @param ParentPort The port at which the device is located.
1132 @param RouteChart The route string pointed to the device.
1133 @param DeviceSpeed The device speed.
1134
1135 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1136
1137 **/
1138 EFI_STATUS
1139 EFIAPI
1140 XhcInitializeDeviceSlot64 (
1141 IN USB_XHCI_INSTANCE *Xhc,
1142 IN USB_DEV_ROUTE ParentRouteChart,
1143 IN UINT16 ParentPort,
1144 IN USB_DEV_ROUTE RouteChart,
1145 IN UINT8 DeviceSpeed
1146 );
1147
1148 /**
1149 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1150
1151 @param Xhc The XHCI Instance.
1152 @param SlotId The slot id to be evaluated.
1153 @param MaxPacketSize The max packet size supported by the device control transfer.
1154
1155 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1156
1157 **/
1158 EFI_STATUS
1159 EFIAPI
1160 XhcEvaluateContext (
1161 IN USB_XHCI_INSTANCE *Xhc,
1162 IN UINT8 SlotId,
1163 IN UINT32 MaxPacketSize
1164 );
1165
1166
1167 /**
1168 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1169
1170 @param Xhc The XHCI Instance.
1171 @param SlotId The slot id to be evaluated.
1172 @param MaxPacketSize The max packet size supported by the device control transfer.
1173
1174 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1175
1176 **/
1177 EFI_STATUS
1178 EFIAPI
1179 XhcEvaluateContext64 (
1180 IN USB_XHCI_INSTANCE *Xhc,
1181 IN UINT8 SlotId,
1182 IN UINT32 MaxPacketSize
1183 );
1184
1185
1186 /**
1187 Disable the specified device slot.
1188
1189 @param Xhc The XHCI Instance.
1190 @param SlotId The slot id to be disabled.
1191
1192 @retval EFI_SUCCESS Successfully disable the device slot.
1193
1194 **/
1195 EFI_STATUS
1196 EFIAPI
1197 XhcDisableSlotCmd (
1198 IN USB_XHCI_INSTANCE *Xhc,
1199 IN UINT8 SlotId
1200 );
1201
1202
1203 /**
1204 Disable the specified device slot.
1205
1206 @param Xhc The XHCI Instance.
1207 @param SlotId The slot id to be disabled.
1208
1209 @retval EFI_SUCCESS Successfully disable the device slot.
1210
1211 **/
1212 EFI_STATUS
1213 EFIAPI
1214 XhcDisableSlotCmd64 (
1215 IN USB_XHCI_INSTANCE *Xhc,
1216 IN UINT8 SlotId
1217 );
1218
1219
1220 /**
1221 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1222
1223 @param Xhc The XHCI Instance.
1224 @param TrsRing The transfer ring to sync.
1225
1226 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1227
1228 **/
1229 EFI_STATUS
1230 EFIAPI
1231 XhcSyncTrsRing (
1232 IN USB_XHCI_INSTANCE *Xhc,
1233 TRANSFER_RING *TrsRing
1234 );
1235
1236 /**
1237 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1238
1239 @param Xhc The XHCI Instance.
1240 @param EvtRing The event ring to sync.
1241
1242 @retval EFI_SUCCESS The event ring is synchronized successfully.
1243
1244 **/
1245 EFI_STATUS
1246 EFIAPI
1247 XhcSyncEventRing (
1248 IN USB_XHCI_INSTANCE *Xhc,
1249 EVENT_RING *EvtRing
1250 );
1251
1252 /**
1253 Check if there is a new generated event.
1254
1255 @param Xhc The XHCI Instance.
1256 @param EvtRing The event ring to check.
1257 @param NewEvtTrb The new event TRB found.
1258
1259 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1260 @retval EFI_NOT_READY The event ring has no new event.
1261
1262 **/
1263 EFI_STATUS
1264 EFIAPI
1265 XhcCheckNewEvent (
1266 IN USB_XHCI_INSTANCE *Xhc,
1267 IN EVENT_RING *EvtRing,
1268 OUT TRB_TEMPLATE **NewEvtTrb
1269 );
1270
1271 /**
1272 Create XHCI transfer ring.
1273
1274 @param Xhc The XHCI Instance.
1275 @param TrbNum The number of TRB in the ring.
1276 @param TransferRing The created transfer ring.
1277
1278 **/
1279 VOID
1280 CreateTransferRing (
1281 IN USB_XHCI_INSTANCE *Xhc,
1282 IN UINTN TrbNum,
1283 OUT TRANSFER_RING *TransferRing
1284 );
1285
1286 /**
1287 Create XHCI event ring.
1288
1289 @param Xhc The XHCI Instance.
1290 @param EventRing The created event ring.
1291
1292 **/
1293 VOID
1294 CreateEventRing (
1295 IN USB_XHCI_INSTANCE *Xhc,
1296 OUT EVENT_RING *EventRing
1297 );
1298
1299 /**
1300 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
1301 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
1302 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
1303 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
1304 Stopped to the Running state.
1305
1306 @param Xhc The XHCI Instance.
1307 @param Urb The urb which makes the endpoint halted.
1308
1309 @retval EFI_SUCCESS The recovery is successful.
1310 @retval Others Failed to recovery halted endpoint.
1311
1312 **/
1313 EFI_STATUS
1314 EFIAPI
1315 XhcRecoverHaltedEndpoint (
1316 IN USB_XHCI_INSTANCE *Xhc,
1317 IN URB *Urb
1318 );
1319
1320 /**
1321 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer
1322 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to
1323 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running
1324 state.
1325
1326 @param Xhc The XHCI Instance.
1327 @param Urb The urb which doesn't get completed in a specified timeout range.
1328
1329 @retval EFI_SUCCESS The dequeuing of the TDs is successful.
1330 @retval Others Failed to stop the endpoint and dequeue the TDs.
1331
1332 **/
1333 EFI_STATUS
1334 EFIAPI
1335 XhcDequeueTrbFromEndpoint (
1336 IN USB_XHCI_INSTANCE *Xhc,
1337 IN URB *Urb
1338 );
1339
1340 /**
1341 Stop endpoint through XHCI's Stop_Endpoint cmd.
1342
1343 @param Xhc The XHCI Instance.
1344 @param SlotId The slot id to be configured.
1345 @param Dci The device context index of endpoint.
1346
1347 @retval EFI_SUCCESS Stop endpoint successfully.
1348 @retval Others Failed to stop endpoint.
1349
1350 **/
1351 EFI_STATUS
1352 EFIAPI
1353 XhcStopEndpoint (
1354 IN USB_XHCI_INSTANCE *Xhc,
1355 IN UINT8 SlotId,
1356 IN UINT8 Dci
1357 );
1358
1359 /**
1360 Reset endpoint through XHCI's Reset_Endpoint cmd.
1361
1362 @param Xhc The XHCI Instance.
1363 @param SlotId The slot id to be configured.
1364 @param Dci The device context index of endpoint.
1365
1366 @retval EFI_SUCCESS Reset endpoint successfully.
1367 @retval Others Failed to reset endpoint.
1368
1369 **/
1370 EFI_STATUS
1371 EFIAPI
1372 XhcResetEndpoint (
1373 IN USB_XHCI_INSTANCE *Xhc,
1374 IN UINT8 SlotId,
1375 IN UINT8 Dci
1376 );
1377
1378 /**
1379 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.
1380
1381 @param Xhc The XHCI Instance.
1382 @param SlotId The slot id to be configured.
1383 @param Dci The device context index of endpoint.
1384 @param Urb The dequeue pointer of the transfer ring specified
1385 by the urb to be updated.
1386
1387 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.
1388 @retval Others Failed to set transfer ring dequeue pointer.
1389
1390 **/
1391 EFI_STATUS
1392 EFIAPI
1393 XhcSetTrDequeuePointer (
1394 IN USB_XHCI_INSTANCE *Xhc,
1395 IN UINT8 SlotId,
1396 IN UINT8 Dci,
1397 IN URB *Urb
1398 );
1399
1400 /**
1401 Create a new URB for a new transaction.
1402
1403 @param Xhc The XHCI Instance
1404 @param DevAddr The device address
1405 @param EpAddr Endpoint addrress
1406 @param DevSpeed The device speed
1407 @param MaxPacket The max packet length of the endpoint
1408 @param Type The transaction type
1409 @param Request The standard USB request for control transfer
1410 @param Data The user data to transfer
1411 @param DataLen The length of data buffer
1412 @param Callback The function to call when data is transferred
1413 @param Context The context to the callback
1414
1415 @return Created URB or NULL
1416
1417 **/
1418 URB*
1419 XhcCreateUrb (
1420 IN USB_XHCI_INSTANCE *Xhc,
1421 IN UINT8 DevAddr,
1422 IN UINT8 EpAddr,
1423 IN UINT8 DevSpeed,
1424 IN UINTN MaxPacket,
1425 IN UINTN Type,
1426 IN EFI_USB_DEVICE_REQUEST *Request,
1427 IN VOID *Data,
1428 IN UINTN DataLen,
1429 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
1430 IN VOID *Context
1431 );
1432
1433 /**
1434 Free an allocated URB.
1435
1436 @param Xhc The XHCI device.
1437 @param Urb The URB to free.
1438
1439 **/
1440 VOID
1441 XhcFreeUrb (
1442 IN USB_XHCI_INSTANCE *Xhc,
1443 IN URB *Urb
1444 );
1445
1446 /**
1447 Create a transfer TRB.
1448
1449 @param Xhc The XHCI Instance
1450 @param Urb The urb used to construct the transfer TRB.
1451
1452 @return Created TRB or NULL
1453
1454 **/
1455 EFI_STATUS
1456 XhcCreateTransferTrb (
1457 IN USB_XHCI_INSTANCE *Xhc,
1458 IN URB *Urb
1459 );
1460
1461 #endif