MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h

   1 /** @file
   2 Private Header file for Usb Host Controller PEIM
   3
   4 Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef _RECOVERY_XHC_H_
  11 #define _RECOVERY_XHC_H_
  12
  13 #include <PiPei.h>
  14
  15 #include <Ppi/UsbController.h>
  16 #include <Ppi/Usb2HostController.h>
  17 #include <Ppi/IoMmu.h>
  18 #include <Ppi/EndOfPeiPhase.h>
  19
  20 #include <Library/DebugLib.h>
  21 #include <Library/PeimEntryPoint.h>
  22 #include <Library/PeiServicesLib.h>
  23 #include <Library/BaseMemoryLib.h>
  24 #include <Library/TimerLib.h>
  25 #include <Library/IoLib.h>
  26 #include <Library/MemoryAllocationLib.h>
  27
  28 typedef struct _PEI_XHC_DEV      PEI_XHC_DEV;
  29 typedef struct _USB_DEV_CONTEXT  USB_DEV_CONTEXT;
  30
  31 #include "UsbHcMem.h"
  32 #include "XhciReg.h"
  33 #include "XhciSched.h"
  34
  35 #define CMD_RING_TRB_NUMBER    0x100
  36 #define TR_RING_TRB_NUMBER     0x100
  37 #define ERST_NUMBER            0x01
  38 #define EVENT_RING_TRB_NUMBER  0x200
  39
  40 #define XHC_1_MICROSECOND  1
  41 #define XHC_1_MILLISECOND  (1000 * XHC_1_MICROSECOND)
  42 #define XHC_1_SECOND       (1000 * XHC_1_MILLISECOND)
  43
  44 //
  45 // XHC reset timeout experience values.
  46 // The unit is millisecond, setting it as 1s.
  47 //
  48 #define XHC_RESET_TIMEOUT  (1000)
  49
  50 //
  51 // TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.
  52 // The unit is microsecond, setting it as 10ms.
  53 //
  54 #define XHC_RESET_RECOVERY_DELAY  (10 * 1000)
  55
  56 //
  57 // Wait for root port state stable.
  58 //
  59 #define XHC_ROOT_PORT_STATE_STABLE  (200 * XHC_1_MILLISECOND)
  60
  61 //
  62 // XHC generic timeout experience values.
  63 // The unit is millisecond, setting it as 10s.
  64 //
  65 #define XHC_GENERIC_TIMEOUT  (10 * 1000)
  66
  67 #define XHC_LOW_32BIT(Addr64)      ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
  68 #define XHC_HIGH_32BIT(Addr64)     ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
  69 #define XHC_BIT_IS_SET(Data, Bit)  ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
  70
  71 #define XHC_REG_BIT_IS_SET(XHC, Offset, Bit) \
  72           (XHC_BIT_IS_SET(XhcPeiReadOpReg ((XHC), (Offset)), (Bit)))
  73
  74 #define USB_DESC_TYPE_HUB              0x29
  75 #define USB_DESC_TYPE_HUB_SUPER_SPEED  0x2a
  76
  77 //
  78 // The RequestType in EFI_USB_DEVICE_REQUEST is composed of
  79 // three fields: One bit direction, 2 bit type, and 5 bit
  80 // target.
  81 //
  82 #define USB_REQUEST_TYPE(Dir, Type, Target) \
  83           ((UINT8)((((Dir) == EfiUsbDataIn ? 0x01 : 0) << 7) | (Type) | (Target)))
  84
  85 struct _USB_DEV_CONTEXT {
  86   //
  87   // Whether this entry in UsbDevContext array is used or not.
  88   //
  89   BOOLEAN          Enabled;
  90   //
  91   // The slot id assigned to the new device through XHCI's Enable_Slot cmd.
  92   //
  93   UINT8            SlotId;
  94   //
  95   // The route string presented an attached usb device.
  96   //
  97   USB_DEV_ROUTE    RouteString;
  98   //
  99   // The route string of parent device if it exists. Otherwise it's zero.
 100   //
 101   USB_DEV_ROUTE    ParentRouteString;
 102   //
 103   // The actual device address assigned by XHCI through Address_Device command.
 104   //
 105   UINT8            XhciDevAddr;
 106   //
 107   // The requested device address from UsbBus driver through Set_Address standard usb request.
 108   // As XHCI spec replaces this request with Address_Device command, we have to record the
 109   // requested device address and establish a mapping relationship with the actual device address.
 110   // Then UsbBus driver just need to be aware of the requested device address to access usb device
 111   // through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual
 112   // device address and access the actual device.
 113   //
 114   UINT8                        BusDevAddr;
 115   //
 116   // The pointer to the input device context.
 117   //
 118   VOID                         *InputContext;
 119   //
 120   // The pointer to the output device context.
 121   //
 122   VOID                         *OutputContext;
 123   //
 124   // The transfer queue for every endpoint.
 125   //
 126   VOID                         *EndpointTransferRing[31];
 127   //
 128   // The device descriptor which is stored to support XHCI's Evaluate_Context cmd.
 129   //
 130   EFI_USB_DEVICE_DESCRIPTOR    DevDesc;
 131   //
 132   // As a usb device may include multiple configuration descriptors, we dynamically allocate an array
 133   // to store them.
 134   // Note that every configuration descriptor stored here includes those lower level descriptors,
 135   // such as Interface descriptor, Endpoint descriptor, and so on.
 136   // These information is used to support XHCI's Config_Endpoint cmd.
 137   //
 138   EFI_USB_CONFIG_DESCRIPTOR    **ConfDesc;
 139 };
 140
 141 #define USB_XHC_DEV_SIGNATURE  SIGNATURE_32 ('x', 'h', 'c', 'i')
 142
 143 struct _PEI_XHC_DEV {
 144   UINTN                           Signature;
 145   PEI_USB2_HOST_CONTROLLER_PPI    Usb2HostControllerPpi;
 146   EFI_PEI_PPI_DESCRIPTOR          PpiDescriptor;
 147   UINT32                          UsbHostControllerBaseAddress;
 148   USBHC_MEM_POOL                  *MemPool;
 149
 150   //
 151   // EndOfPei callback is used to stop the XHC DMA operation
 152   // after exit PEI phase.
 153   //
 154   EFI_PEI_NOTIFY_DESCRIPTOR       EndOfPeiNotifyList;
 155
 156   //
 157   // XHCI configuration data
 158   //
 159   UINT8                           CapLength;      ///< Capability Register Length
 160   XHC_HCSPARAMS1                  HcSParams1;     ///< Structural Parameters 1
 161   XHC_HCSPARAMS2                  HcSParams2;     ///< Structural Parameters 2
 162   XHC_HCCPARAMS                   HcCParams;      ///< Capability Parameters
 163   UINT32                          DBOff;          ///< Doorbell Offset
 164   UINT32                          RTSOff;         ///< Runtime Register Space Offset
 165   UINT32                          PageSize;
 166   UINT32                          MaxScratchpadBufs;
 167   UINT64                          *ScratchBuf;
 168   VOID                            *ScratchMap;
 169   UINT64                          *ScratchEntry;
 170   UINTN                           *ScratchEntryMap;
 171   UINT64                          *DCBAA;
 172   UINT32                          MaxSlotsEn;
 173   //
 174   // Cmd Transfer Ring
 175   //
 176   TRANSFER_RING                   CmdRing;
 177   //
 178   // EventRing
 179   //
 180   EVENT_RING                      EventRing;
 181
 182   //
 183   // Store device contexts managed by XHCI device
 184   // The array supports up to 255 devices, entry 0 is reserved and should not be used.
 185   //
 186   USB_DEV_CONTEXT                 UsbDevContext[256];
 187 };
 188
 189 #define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a)         CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)
 190 #define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(a)  CR (a, PEI_XHC_DEV, EndOfPeiNotifyList, USB_XHC_DEV_SIGNATURE)
 191
 192 /**
 193   Initialize the memory management pool for the host controller.
 194
 195   @return Pointer to the allocated memory pool or NULL if failed.
 196
 197 **/
 198 USBHC_MEM_POOL *
 199 UsbHcInitMemPool (
 200   VOID
 201   )
 202 ;
 203
 204 /**
 205   Release the memory management pool.
 206
 207   @param  Pool          The USB memory pool to free.
 208
 209 **/
 210 VOID
 211 UsbHcFreeMemPool (
 212   IN USBHC_MEM_POOL  *Pool
 213   )
 214 ;
 215
 216 /**
 217   Allocate some memory from the host controller's memory pool
 218   which can be used to communicate with host controller.
 219
 220   @param  Pool          The host controller's memory pool.
 221   @param  Size          Size of the memory to allocate.
 222
 223   @return The allocated memory or NULL.
 224
 225 **/
 226 VOID *
 227 UsbHcAllocateMem (
 228   IN USBHC_MEM_POOL  *Pool,
 229   IN UINTN           Size
 230   )
 231 ;
 232
 233 /**
 234   Free the allocated memory back to the memory pool.
 235
 236   @param  Pool          The memory pool of the host controller.
 237   @param  Mem           The memory to free.
 238   @param  Size          The size of the memory to free.
 239
 240 **/
 241 VOID
 242 UsbHcFreeMem (
 243   IN USBHC_MEM_POOL  *Pool,
 244   IN VOID            *Mem,
 245   IN UINTN           Size
 246   )
 247 ;
 248
 249 /**
 250   Initialize IOMMU.
 251 **/
 252 VOID
 253 IoMmuInit (
 254   VOID
 255   );
 256
 257 /**
 258   Provides the controller-specific addresses required to access system memory from a
 259   DMA bus master.
 260
 261   @param  Operation             Indicates if the bus master is going to read or write to system memory.
 262   @param  HostAddress           The system memory address to map to the PCI controller.
 263   @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes
 264                                 that were mapped.
 265   @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to
 266                                 access the hosts HostAddress.
 267   @param  Mapping               A resulting value to pass to Unmap().
 268
 269   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
 270   @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
 271   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 272   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 273   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
 274
 275 **/
 276 EFI_STATUS
 277 IoMmuMap (
 278   IN  EDKII_IOMMU_OPERATION  Operation,
 279   IN  VOID                   *HostAddress,
 280   IN  OUT UINTN              *NumberOfBytes,
 281   OUT EFI_PHYSICAL_ADDRESS   *DeviceAddress,
 282   OUT VOID                   **Mapping
 283   );
 284
 285 /**
 286   Completes the Map() operation and releases any corresponding resources.
 287
 288   @param  Mapping               The mapping value returned from Map().
 289
 290   @retval EFI_SUCCESS           The range was unmapped.
 291   @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
 292   @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.
 293 **/
 294 EFI_STATUS
 295 IoMmuUnmap (
 296   IN VOID  *Mapping
 297   );
 298
 299 /**
 300   Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
 301   OperationBusMasterCommonBuffer64 mapping.
 302
 303   @param  Pages                 The number of pages to allocate.
 304   @param  HostAddress           A pointer to store the base system memory address of the
 305                                 allocated range.
 306   @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to
 307                                 access the hosts HostAddress.
 308   @param  Mapping               A resulting value to pass to Unmap().
 309
 310   @retval EFI_SUCCESS           The requested memory pages were allocated.
 311   @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
 312                                 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
 313   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 314   @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
 315
 316 **/
 317 EFI_STATUS
 318 IoMmuAllocateBuffer (
 319   IN UINTN                  Pages,
 320   OUT VOID                  **HostAddress,
 321   OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,
 322   OUT VOID                  **Mapping
 323   );
 324
 325 /**
 326   Frees memory that was allocated with AllocateBuffer().
 327
 328   @param  Pages                 The number of pages to free.
 329   @param  HostAddress           The base system memory address of the allocated range.
 330   @param  Mapping               The mapping value returned from Map().
 331
 332   @retval EFI_SUCCESS           The requested memory pages were freed.
 333   @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
 334                                 was not allocated with AllocateBuffer().
 335
 336 **/
 337 EFI_STATUS
 338 IoMmuFreeBuffer (
 339   IN UINTN  Pages,
 340   IN VOID   *HostAddress,
 341   IN VOID   *Mapping
 342   );
 343
 344 /**
 345   Allocates aligned pages that are suitable for an OperationBusMasterCommonBuffer or
 346   OperationBusMasterCommonBuffer64 mapping.
 347
 348   @param  Pages                 The number of pages to allocate.
 349   @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
 350   @param  HostAddress           A pointer to store the base system memory address of the
 351                                 allocated range.
 352   @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to
 353                                 access the hosts HostAddress.
 354   @param  Mapping               A resulting value to pass to Unmap().
 355
 356   @retval EFI_SUCCESS           The requested memory pages were allocated.
 357   @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
 358                                 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
 359   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 360   @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
 361
 362 **/
 363 EFI_STATUS
 364 IoMmuAllocateAlignedBuffer (
 365   IN UINTN                  Pages,
 366   IN UINTN                  Alignment,
 367   OUT VOID                  **HostAddress,
 368   OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,
 369   OUT VOID                  **Mapping
 370   );
 371
 372 #endif