2 PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid
3 which is used to enable recovery function from USB Drivers.
5 Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions
9 of the BSD License which accompanies this distribution. The
10 full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 Create a command transfer TRB to support XHCI command interfaces.
23 @param Xhc The XHCI device.
24 @param CmdTrb The cmd TRB to be executed.
26 @return Created URB or NULL.
32 IN TRB_TEMPLATE
*CmdTrb
37 Urb
= AllocateZeroPool (sizeof (URB
));
42 Urb
->Signature
= XHC_URB_SIG
;
44 Urb
->Ring
= &Xhc
->CmdRing
;
45 XhcPeiSyncTrsRing (Xhc
, Urb
->Ring
);
47 Urb
->TrbStart
= Urb
->Ring
->RingEnqueue
;
48 CopyMem (Urb
->TrbStart
, CmdTrb
, sizeof (TRB_TEMPLATE
));
49 Urb
->TrbStart
->CycleBit
= Urb
->Ring
->RingPCS
& BIT0
;
50 Urb
->TrbEnd
= Urb
->TrbStart
;
56 Execute a XHCI cmd TRB pointed by CmdTrb.
58 @param Xhc The XHCI device.
59 @param CmdTrb The cmd TRB to be executed.
60 @param Timeout Indicates the maximum time, in millisecond, which the
61 transfer is allowed to complete.
62 @param EvtTrb The event TRB corresponding to the cmd TRB.
64 @retval EFI_SUCCESS The transfer was completed successfully.
65 @retval EFI_INVALID_PARAMETER Some parameters are invalid.
66 @retval EFI_TIMEOUT The transfer failed due to timeout.
67 @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.
73 IN TRB_TEMPLATE
*CmdTrb
,
75 OUT TRB_TEMPLATE
**EvtTrb
82 // Validate the parameters
84 if ((Xhc
== NULL
) || (CmdTrb
== NULL
)) {
85 return EFI_INVALID_PARAMETER
;
88 Status
= EFI_DEVICE_ERROR
;
90 if (XhcPeiIsHalt (Xhc
) || XhcPeiIsSysError (Xhc
)) {
91 DEBUG ((EFI_D_ERROR
, "XhcPeiCmdTransfer: HC is halted or has system error\n"));
96 // Create a new URB, then poll the execution status.
98 Urb
= XhcPeiCreateCmdTrb (Xhc
, CmdTrb
);
100 DEBUG ((EFI_D_ERROR
, "XhcPeiCmdTransfer: failed to create URB\n"));
101 Status
= EFI_OUT_OF_RESOURCES
;
105 Status
= XhcPeiExecTransfer (Xhc
, TRUE
, Urb
, Timeout
);
106 *EvtTrb
= Urb
->EvtTrb
;
108 if (Urb
->Result
== EFI_USB_NOERROR
) {
109 Status
= EFI_SUCCESS
;
112 XhcPeiFreeUrb (Xhc
, Urb
);
119 Create a new URB for a new transaction.
121 @param Xhc The XHCI device
122 @param BusAddr The logical device address assigned by UsbBus driver
123 @param EpAddr Endpoint addrress
124 @param DevSpeed The device speed
125 @param MaxPacket The max packet length of the endpoint
126 @param Type The transaction type
127 @param Request The standard USB request for control transfer
128 @param Data The user data to transfer
129 @param DataLen The length of data buffer
130 @param Callback The function to call when data is transferred
131 @param Context The context to the callback
133 @return Created URB or NULL
144 IN EFI_USB_DEVICE_REQUEST
*Request
,
147 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback
,
155 Urb
= AllocateZeroPool (sizeof (URB
));
160 Urb
->Signature
= XHC_URB_SIG
;
163 Ep
->BusAddr
= BusAddr
;
164 Ep
->EpAddr
= (UINT8
) (EpAddr
& 0x0F);
165 Ep
->Direction
= ((EpAddr
& 0x80) != 0) ? EfiUsbDataIn
: EfiUsbDataOut
;
166 Ep
->DevSpeed
= DevSpeed
;
167 Ep
->MaxPacket
= MaxPacket
;
170 Urb
->Request
= Request
;
172 Urb
->DataLen
= DataLen
;
173 Urb
->Callback
= Callback
;
174 Urb
->Context
= Context
;
176 Status
= XhcPeiCreateTransferTrb (Xhc
, Urb
);
177 if (EFI_ERROR (Status
)) {
178 DEBUG ((EFI_D_ERROR
, "XhcPeiCreateUrb: XhcPeiCreateTransferTrb Failed, Status = %r\n", Status
));
187 Free an allocated URB.
189 @param Xhc The XHCI device.
190 @param Urb The URB to free.
199 if ((Xhc
== NULL
) || (Urb
== NULL
)) {
207 Create a transfer TRB.
209 @param Xhc The XHCI device
210 @param Urb The urb used to construct the transfer TRB.
212 @return Created TRB or NULL
216 XhcPeiCreateTransferTrb (
222 TRANSFER_RING
*EPRing
;
231 SlotId
= XhcPeiBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
233 return EFI_DEVICE_ERROR
;
236 Urb
->Finished
= FALSE
;
237 Urb
->StartDone
= FALSE
;
238 Urb
->EndDone
= FALSE
;
240 Urb
->Result
= EFI_USB_NOERROR
;
242 Dci
= XhcPeiEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
243 EPRing
= (TRANSFER_RING
*) (UINTN
) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1];
245 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
246 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
247 EPType
= (UINT8
) ((DEVICE_CONTEXT
*)OutputContext
)->EP
[Dci
-1].EPType
;
249 EPType
= (UINT8
) ((DEVICE_CONTEXT_64
*)OutputContext
)->EP
[Dci
-1].EPType
;
252 Urb
->DataPhy
= Urb
->Data
;
257 XhcPeiSyncTrsRing (Xhc
, EPRing
);
258 Urb
->TrbStart
= EPRing
->RingEnqueue
;
260 case ED_CONTROL_BIDIR
:
262 // For control transfer, create SETUP_STAGE_TRB first.
264 TrbStart
= (TRB
*) (UINTN
) EPRing
->RingEnqueue
;
265 TrbStart
->TrbCtrSetup
.bmRequestType
= Urb
->Request
->RequestType
;
266 TrbStart
->TrbCtrSetup
.bRequest
= Urb
->Request
->Request
;
267 TrbStart
->TrbCtrSetup
.wValue
= Urb
->Request
->Value
;
268 TrbStart
->TrbCtrSetup
.wIndex
= Urb
->Request
->Index
;
269 TrbStart
->TrbCtrSetup
.wLength
= Urb
->Request
->Length
;
270 TrbStart
->TrbCtrSetup
.Length
= 8;
271 TrbStart
->TrbCtrSetup
.IntTarget
= 0;
272 TrbStart
->TrbCtrSetup
.IOC
= 1;
273 TrbStart
->TrbCtrSetup
.IDT
= 1;
274 TrbStart
->TrbCtrSetup
.Type
= TRB_TYPE_SETUP_STAGE
;
275 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
276 TrbStart
->TrbCtrSetup
.TRT
= 3;
277 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
278 TrbStart
->TrbCtrSetup
.TRT
= 2;
280 TrbStart
->TrbCtrSetup
.TRT
= 0;
283 // Update the cycle bit
285 TrbStart
->TrbCtrSetup
.CycleBit
= EPRing
->RingPCS
& BIT0
;
289 // For control transfer, create DATA_STAGE_TRB.
291 if (Urb
->DataLen
> 0) {
292 XhcPeiSyncTrsRing (Xhc
, EPRing
);
293 TrbStart
= (TRB
*) (UINTN
) EPRing
->RingEnqueue
;
294 TrbStart
->TrbCtrData
.TRBPtrLo
= XHC_LOW_32BIT (Urb
->DataPhy
);
295 TrbStart
->TrbCtrData
.TRBPtrHi
= XHC_HIGH_32BIT (Urb
->DataPhy
);
296 TrbStart
->TrbCtrData
.Length
= (UINT32
) Urb
->DataLen
;
297 TrbStart
->TrbCtrData
.TDSize
= 0;
298 TrbStart
->TrbCtrData
.IntTarget
= 0;
299 TrbStart
->TrbCtrData
.ISP
= 1;
300 TrbStart
->TrbCtrData
.IOC
= 1;
301 TrbStart
->TrbCtrData
.IDT
= 0;
302 TrbStart
->TrbCtrData
.CH
= 0;
303 TrbStart
->TrbCtrData
.Type
= TRB_TYPE_DATA_STAGE
;
304 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
305 TrbStart
->TrbCtrData
.DIR = 1;
306 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
307 TrbStart
->TrbCtrData
.DIR = 0;
309 TrbStart
->TrbCtrData
.DIR = 0;
312 // Update the cycle bit
314 TrbStart
->TrbCtrData
.CycleBit
= EPRing
->RingPCS
& BIT0
;
318 // For control transfer, create STATUS_STAGE_TRB.
319 // Get the pointer to next TRB for status stage use
321 XhcPeiSyncTrsRing (Xhc
, EPRing
);
322 TrbStart
= (TRB
*) (UINTN
) EPRing
->RingEnqueue
;
323 TrbStart
->TrbCtrStatus
.IntTarget
= 0;
324 TrbStart
->TrbCtrStatus
.IOC
= 1;
325 TrbStart
->TrbCtrStatus
.CH
= 0;
326 TrbStart
->TrbCtrStatus
.Type
= TRB_TYPE_STATUS_STAGE
;
327 if (Urb
->Ep
.Direction
== EfiUsbDataIn
) {
328 TrbStart
->TrbCtrStatus
.DIR = 0;
329 } else if (Urb
->Ep
.Direction
== EfiUsbDataOut
) {
330 TrbStart
->TrbCtrStatus
.DIR = 1;
332 TrbStart
->TrbCtrStatus
.DIR = 0;
335 // Update the cycle bit
337 TrbStart
->TrbCtrStatus
.CycleBit
= EPRing
->RingPCS
& BIT0
;
339 // Update the enqueue pointer
341 XhcPeiSyncTrsRing (Xhc
, EPRing
);
343 Urb
->TrbEnd
= (TRB_TEMPLATE
*) (UINTN
) TrbStart
;
352 TrbStart
= (TRB
*) (UINTN
) EPRing
->RingEnqueue
;
353 while (TotalLen
< Urb
->DataLen
) {
354 if ((TotalLen
+ 0x10000) >= Urb
->DataLen
) {
355 Len
= Urb
->DataLen
- TotalLen
;
359 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
360 TrbStart
->TrbNormal
.TRBPtrLo
= XHC_LOW_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
361 TrbStart
->TrbNormal
.TRBPtrHi
= XHC_HIGH_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
362 TrbStart
->TrbNormal
.Length
= (UINT32
) Len
;
363 TrbStart
->TrbNormal
.TDSize
= 0;
364 TrbStart
->TrbNormal
.IntTarget
= 0;
365 TrbStart
->TrbNormal
.ISP
= 1;
366 TrbStart
->TrbNormal
.IOC
= 1;
367 TrbStart
->TrbNormal
.Type
= TRB_TYPE_NORMAL
;
369 // Update the cycle bit
371 TrbStart
->TrbNormal
.CycleBit
= EPRing
->RingPCS
& BIT0
;
373 XhcPeiSyncTrsRing (Xhc
, EPRing
);
378 Urb
->TrbNum
= TrbNum
;
379 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
382 case ED_INTERRUPT_OUT
:
383 case ED_INTERRUPT_IN
:
387 TrbStart
= (TRB
*) (UINTN
) EPRing
->RingEnqueue
;
388 while (TotalLen
< Urb
->DataLen
) {
389 if ((TotalLen
+ 0x10000) >= Urb
->DataLen
) {
390 Len
= Urb
->DataLen
- TotalLen
;
394 TrbStart
= (TRB
*)(UINTN
)EPRing
->RingEnqueue
;
395 TrbStart
->TrbNormal
.TRBPtrLo
= XHC_LOW_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
396 TrbStart
->TrbNormal
.TRBPtrHi
= XHC_HIGH_32BIT((UINT8
*) Urb
->DataPhy
+ TotalLen
);
397 TrbStart
->TrbNormal
.Length
= (UINT32
) Len
;
398 TrbStart
->TrbNormal
.TDSize
= 0;
399 TrbStart
->TrbNormal
.IntTarget
= 0;
400 TrbStart
->TrbNormal
.ISP
= 1;
401 TrbStart
->TrbNormal
.IOC
= 1;
402 TrbStart
->TrbNormal
.Type
= TRB_TYPE_NORMAL
;
404 // Update the cycle bit
406 TrbStart
->TrbNormal
.CycleBit
= EPRing
->RingPCS
& BIT0
;
408 XhcPeiSyncTrsRing (Xhc
, EPRing
);
413 Urb
->TrbNum
= TrbNum
;
414 Urb
->TrbEnd
= (TRB_TEMPLATE
*)(UINTN
)TrbStart
;
418 DEBUG ((EFI_D_INFO
, "Not supported EPType 0x%x!\n",EPType
));
427 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
428 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
429 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
430 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
431 Stopped to the Running state.
433 @param Xhc The XHCI device.
434 @param Urb The urb which makes the endpoint halted.
436 @retval EFI_SUCCESS The recovery is successful.
437 @retval Others Failed to recovery halted endpoint.
441 XhcPeiRecoverHaltedEndpoint (
447 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
448 CMD_TRB_RESET_ENDPOINT CmdTrbResetED
;
449 CMD_SET_TR_DEQ_POINTER CmdSetTRDeq
;
452 EFI_PHYSICAL_ADDRESS PhyAddr
;
454 Status
= EFI_SUCCESS
;
455 SlotId
= XhcPeiBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
457 return EFI_DEVICE_ERROR
;
459 Dci
= XhcPeiEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
) (Urb
->Ep
.Direction
));
461 DEBUG ((EFI_D_INFO
, "XhcPeiRecoverHaltedEndpoint: Recovery Halted Slot = %x, Dci = %x\n", SlotId
, Dci
));
464 // 1) Send Reset endpoint command to transit from halt to stop state
466 ZeroMem (&CmdTrbResetED
, sizeof (CmdTrbResetED
));
467 CmdTrbResetED
.CycleBit
= 1;
468 CmdTrbResetED
.Type
= TRB_TYPE_RESET_ENDPOINT
;
469 CmdTrbResetED
.EDID
= Dci
;
470 CmdTrbResetED
.SlotId
= SlotId
;
471 Status
= XhcPeiCmdTransfer (
473 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbResetED
,
475 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
477 if (EFI_ERROR(Status
)) {
478 DEBUG ((EFI_D_ERROR
, "XhcPeiRecoverHaltedEndpoint: Reset Endpoint Failed, Status = %r\n", Status
));
483 // 2) Set dequeue pointer
485 ZeroMem (&CmdSetTRDeq
, sizeof (CmdSetTRDeq
));
486 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Urb
->Ring
->RingEnqueue
, sizeof (CMD_SET_TR_DEQ_POINTER
));
487 CmdSetTRDeq
.PtrLo
= XHC_LOW_32BIT (PhyAddr
) | Urb
->Ring
->RingPCS
;
488 CmdSetTRDeq
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
489 CmdSetTRDeq
.CycleBit
= 1;
490 CmdSetTRDeq
.Type
= TRB_TYPE_SET_TR_DEQUE
;
491 CmdSetTRDeq
.Endpoint
= Dci
;
492 CmdSetTRDeq
.SlotId
= SlotId
;
493 Status
= XhcPeiCmdTransfer (
495 (TRB_TEMPLATE
*) (UINTN
) &CmdSetTRDeq
,
497 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
499 if (EFI_ERROR(Status
)) {
500 DEBUG ((EFI_D_ERROR
, "XhcPeiRecoverHaltedEndpoint: Set Dequeue Pointer Failed, Status = %r\n", Status
));
505 // 3) Ring the doorbell to transit from stop to active
507 XhcPeiRingDoorBell (Xhc
, SlotId
, Dci
);
514 Check if the Trb is a transaction of the URB.
516 @param Trb The TRB to be checked
517 @param Urb The transfer ring to be checked.
519 @retval TRUE It is a transaction of the URB.
520 @retval FALSE It is not any transaction of the URB.
524 XhcPeiIsTransferRingTrb (
525 IN TRB_TEMPLATE
*Trb
,
529 TRB_TEMPLATE
*CheckedTrb
;
532 CheckedTrb
= Urb
->Ring
->RingSeg0
;
534 ASSERT (Urb
->Ring
->TrbNumber
== CMD_RING_TRB_NUMBER
|| Urb
->Ring
->TrbNumber
== TR_RING_TRB_NUMBER
);
536 for (Index
= 0; Index
< Urb
->Ring
->TrbNumber
; Index
++) {
537 if (Trb
== CheckedTrb
) {
547 Check the URB's execution result and update the URB's
550 @param Xhc The XHCI device.
551 @param Urb The URB to check result.
553 @return Whether the result of URB transfer is finialized.
557 XhcPeiCheckUrbResult (
562 EVT_TRB_TRANSFER
*EvtTrb
;
563 TRB_TEMPLATE
*TRBPtr
;
571 EFI_PHYSICAL_ADDRESS PhyAddr
;
573 ASSERT ((Xhc
!= NULL
) && (Urb
!= NULL
));
575 Status
= EFI_SUCCESS
;
583 if (XhcPeiIsHalt (Xhc
) || XhcPeiIsSysError (Xhc
)) {
584 Urb
->Result
|= EFI_USB_ERR_SYSTEM
;
585 Status
= EFI_DEVICE_ERROR
;
590 // Traverse the event ring to find out all new events from the previous check.
592 XhcPeiSyncEventRing (Xhc
, &Xhc
->EventRing
);
593 for (Index
= 0; Index
< Xhc
->EventRing
.TrbNumber
; Index
++) {
594 Status
= XhcPeiCheckNewEvent (Xhc
, &Xhc
->EventRing
, ((TRB_TEMPLATE
**) &EvtTrb
));
595 if (Status
== EFI_NOT_READY
) {
597 // All new events are handled, return directly.
603 // Only handle COMMAND_COMPLETETION_EVENT and TRANSFER_EVENT.
605 if ((EvtTrb
->Type
!= TRB_TYPE_COMMAND_COMPLT_EVENT
) && (EvtTrb
->Type
!= TRB_TYPE_TRANS_EVENT
)) {
610 // Need convert pci device address to host address
612 PhyAddr
= (EFI_PHYSICAL_ADDRESS
) (EvtTrb
->TRBPtrLo
| LShiftU64 ((UINT64
) EvtTrb
->TRBPtrHi
, 32));
613 TRBPtr
= (TRB_TEMPLATE
*) (UINTN
) UsbHcGetHostAddrForPciAddr (Xhc
->MemPool
, (VOID
*) (UINTN
) PhyAddr
, sizeof (TRB_TEMPLATE
));
616 // Update the status of Urb according to the finished event regardless of whether
617 // the urb is current checked one or in the XHCI's async transfer list.
618 // This way is used to avoid that those completed async transfer events don't get
619 // handled in time and are flushed by newer coming events.
621 if (XhcPeiIsTransferRingTrb (TRBPtr
, Urb
)) {
627 switch (EvtTrb
->Completecode
) {
628 case TRB_COMPLETION_STALL_ERROR
:
629 CheckedUrb
->Result
|= EFI_USB_ERR_STALL
;
630 CheckedUrb
->Finished
= TRUE
;
631 DEBUG ((EFI_D_ERROR
, "XhcPeiCheckUrbResult: STALL_ERROR! Completecode = %x\n", EvtTrb
->Completecode
));
634 case TRB_COMPLETION_BABBLE_ERROR
:
635 CheckedUrb
->Result
|= EFI_USB_ERR_BABBLE
;
636 CheckedUrb
->Finished
= TRUE
;
637 DEBUG ((EFI_D_ERROR
, "XhcPeiCheckUrbResult: BABBLE_ERROR! Completecode = %x\n", EvtTrb
->Completecode
));
640 case TRB_COMPLETION_DATA_BUFFER_ERROR
:
641 CheckedUrb
->Result
|= EFI_USB_ERR_BUFFER
;
642 CheckedUrb
->Finished
= TRUE
;
643 DEBUG ((EFI_D_ERROR
, "XhcPeiCheckUrbResult: ERR_BUFFER! Completecode = %x\n", EvtTrb
->Completecode
));
646 case TRB_COMPLETION_USB_TRANSACTION_ERROR
:
647 CheckedUrb
->Result
|= EFI_USB_ERR_TIMEOUT
;
648 CheckedUrb
->Finished
= TRUE
;
649 DEBUG ((EFI_D_ERROR
, "XhcPeiCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n", EvtTrb
->Completecode
));
652 case TRB_COMPLETION_SHORT_PACKET
:
653 case TRB_COMPLETION_SUCCESS
:
654 if (EvtTrb
->Completecode
== TRB_COMPLETION_SHORT_PACKET
) {
655 DEBUG ((EFI_D_ERROR
, "XhcPeiCheckUrbResult: short packet happens!\n"));
658 TRBType
= (UINT8
) (TRBPtr
->Type
);
659 if ((TRBType
== TRB_TYPE_DATA_STAGE
) ||
660 (TRBType
== TRB_TYPE_NORMAL
) ||
661 (TRBType
== TRB_TYPE_ISOCH
)) {
662 CheckedUrb
->Completed
+= (CheckedUrb
->DataLen
- EvtTrb
->Length
);
668 DEBUG ((EFI_D_ERROR
, "XhcPeiCheckUrbResult: Transfer Default Error Occur! Completecode = 0x%x!\n", EvtTrb
->Completecode
));
669 CheckedUrb
->Result
|= EFI_USB_ERR_TIMEOUT
;
670 CheckedUrb
->Finished
= TRUE
;
675 // Only check first and end Trb event address
677 if (TRBPtr
== CheckedUrb
->TrbStart
) {
678 CheckedUrb
->StartDone
= TRUE
;
681 if (TRBPtr
== CheckedUrb
->TrbEnd
) {
682 CheckedUrb
->EndDone
= TRUE
;
685 if (CheckedUrb
->StartDone
&& CheckedUrb
->EndDone
) {
686 CheckedUrb
->Finished
= TRUE
;
687 CheckedUrb
->EvtTrb
= (TRB_TEMPLATE
*) EvtTrb
;
694 // Advance event ring to last available entry
696 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
697 // So divide it to two 32-bytes width register access.
699 Low
= XhcPeiReadRuntimeReg (Xhc
, XHC_ERDP_OFFSET
);
700 High
= XhcPeiReadRuntimeReg (Xhc
, XHC_ERDP_OFFSET
+ 4);
701 XhcDequeue
= (UINT64
) (LShiftU64((UINT64
) High
, 32) | Low
);
703 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->EventRing
.EventRingDequeue
, sizeof (TRB_TEMPLATE
));
705 if ((XhcDequeue
& (~0x0F)) != (PhyAddr
& (~0x0F))) {
707 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
708 // So divide it to two 32-bytes width register access.
710 XhcPeiWriteRuntimeReg (Xhc
, XHC_ERDP_OFFSET
, XHC_LOW_32BIT (PhyAddr
) | BIT3
);
711 XhcPeiWriteRuntimeReg (Xhc
, XHC_ERDP_OFFSET
+ 4, XHC_HIGH_32BIT (PhyAddr
));
718 Execute the transfer by polling the URB. This is a synchronous operation.
720 @param Xhc The XHCI device.
721 @param CmdTransfer The executed URB is for cmd transfer or not.
722 @param Urb The URB to execute.
723 @param Timeout The time to wait before abort, in millisecond.
725 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
726 @return EFI_TIMEOUT The transfer failed due to time out.
727 @return EFI_SUCCESS The transfer finished OK.
733 IN BOOLEAN CmdTransfer
,
748 SlotId
= XhcPeiBusDevAddrToSlotId (Xhc
, Urb
->Ep
.BusAddr
);
750 return EFI_DEVICE_ERROR
;
752 Dci
= XhcPeiEndpointToDci (Urb
->Ep
.EpAddr
, (UINT8
)(Urb
->Ep
.Direction
));
755 Status
= EFI_SUCCESS
;
756 Loop
= Timeout
* XHC_1_MILLISECOND
;
761 XhcPeiRingDoorBell (Xhc
, SlotId
, Dci
);
763 for (Index
= 0; Index
< Loop
; Index
++) {
764 Status
= XhcPeiCheckUrbResult (Xhc
, Urb
);
768 MicroSecondDelay (XHC_1_MICROSECOND
);
772 Urb
->Result
= EFI_USB_ERR_TIMEOUT
;
779 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
781 @param Xhc The XHCI device.
782 @param ParentRouteChart The route string pointed to the parent device if it exists.
783 @param Port The port to be polled.
784 @param PortState The port state.
786 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
787 @retval Others Should not appear.
791 XhcPeiPollPortStatusChange (
793 IN USB_DEV_ROUTE ParentRouteChart
,
795 IN EFI_USB_PORT_STATUS
*PortState
801 USB_DEV_ROUTE RouteChart
;
803 DEBUG ((EFI_D_INFO
, "XhcPeiPollPortStatusChange: PortChangeStatus: %x PortStatus: %x\n", PortState
->PortChangeStatus
, PortState
->PortStatus
));
805 Status
= EFI_SUCCESS
;
807 if ((PortState
->PortChangeStatus
& (USB_PORT_STAT_C_CONNECTION
| USB_PORT_STAT_C_ENABLE
| USB_PORT_STAT_C_OVERCURRENT
| USB_PORT_STAT_C_RESET
)) == 0) {
811 if (ParentRouteChart
.Dword
== 0) {
812 RouteChart
.Route
.RouteString
= 0;
813 RouteChart
.Route
.RootPortNum
= Port
+ 1;
814 RouteChart
.Route
.TierNum
= 1;
817 RouteChart
.Route
.RouteString
= ParentRouteChart
.Route
.RouteString
| (Port
<< (4 * (ParentRouteChart
.Route
.TierNum
- 1)));
819 RouteChart
.Route
.RouteString
= ParentRouteChart
.Route
.RouteString
| (15 << (4 * (ParentRouteChart
.Route
.TierNum
- 1)));
821 RouteChart
.Route
.RootPortNum
= ParentRouteChart
.Route
.RootPortNum
;
822 RouteChart
.Route
.TierNum
= ParentRouteChart
.Route
.TierNum
+ 1;
825 SlotId
= XhcPeiRouteStringToSlotId (Xhc
, RouteChart
);
827 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
828 Status
= XhcPeiDisableSlotCmd (Xhc
, SlotId
);
830 Status
= XhcPeiDisableSlotCmd64 (Xhc
, SlotId
);
834 if (((PortState
->PortStatus
& USB_PORT_STAT_ENABLE
) != 0) &&
835 ((PortState
->PortStatus
& USB_PORT_STAT_CONNECTION
) != 0)) {
837 // Has a device attached, Identify device speed after port is enabled.
839 Speed
= EFI_USB_SPEED_FULL
;
840 if ((PortState
->PortStatus
& USB_PORT_STAT_LOW_SPEED
) != 0) {
841 Speed
= EFI_USB_SPEED_LOW
;
842 } else if ((PortState
->PortStatus
& USB_PORT_STAT_HIGH_SPEED
) != 0) {
843 Speed
= EFI_USB_SPEED_HIGH
;
844 } else if ((PortState
->PortStatus
& USB_PORT_STAT_SUPER_SPEED
) != 0) {
845 Speed
= EFI_USB_SPEED_SUPER
;
848 // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.
850 SlotId
= XhcPeiRouteStringToSlotId (Xhc
, RouteChart
);
851 if ((SlotId
== 0) && ((PortState
->PortChangeStatus
& USB_PORT_STAT_C_RESET
) != 0)) {
852 if (Xhc
->HcCParams
.Data
.Csz
== 0) {
853 Status
= XhcPeiInitializeDeviceSlot (Xhc
, ParentRouteChart
, Port
, RouteChart
, Speed
);
855 Status
= XhcPeiInitializeDeviceSlot64 (Xhc
, ParentRouteChart
, Port
, RouteChart
, Speed
);
864 Calculate the device context index by endpoint address and direction.
866 @param EpAddr The target endpoint number.
867 @param Direction The direction of the target endpoint.
869 @return The device context index of endpoint.
873 XhcPeiEndpointToDci (
875 IN EFI_USB_DATA_DIRECTION Direction
880 ASSERT (EpAddr
<= 15);
885 Index
= (UINT8
) (2 * EpAddr
);
886 if (Direction
== EfiUsbDataIn
) {
894 Find out the actual device address according to the requested device address from UsbBus.
896 @param Xhc The XHCI device.
897 @param BusDevAddr The requested device address by UsbBus upper driver.
899 @return The actual device address assigned to the device.
903 XhcPeiBusDevAddrToSlotId (
910 for (Index
= 0; Index
< 255; Index
++) {
911 if (Xhc
->UsbDevContext
[Index
+ 1].Enabled
&&
912 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
!= 0) &&
913 (Xhc
->UsbDevContext
[Index
+ 1].BusDevAddr
== BusDevAddr
)) {
922 return Xhc
->UsbDevContext
[Index
+ 1].SlotId
;
926 Find out the slot id according to the device's route string.
928 @param Xhc The XHCI device.
929 @param RouteString The route string described the device location.
931 @return The slot id used by the device.
935 XhcPeiRouteStringToSlotId (
937 IN USB_DEV_ROUTE RouteString
942 for (Index
= 0; Index
< 255; Index
++) {
943 if (Xhc
->UsbDevContext
[Index
+ 1].Enabled
&&
944 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
!= 0) &&
945 (Xhc
->UsbDevContext
[Index
+ 1].RouteString
.Dword
== RouteString
.Dword
)) {
954 return Xhc
->UsbDevContext
[Index
+ 1].SlotId
;
958 Ring the door bell to notify XHCI there is a transaction to be executed.
960 @param Xhc The XHCI device.
961 @param SlotId The slot id of the target device.
962 @param Dci The device context index of the target slot or endpoint.
973 XhcPeiWriteDoorBellReg (Xhc
, 0, 0);
975 XhcPeiWriteDoorBellReg (Xhc
, SlotId
* sizeof (UINT32
), Dci
);
980 Assign and initialize the device slot for a new device.
982 @param Xhc The XHCI device.
983 @param ParentRouteChart The route string pointed to the parent device.
984 @param ParentPort The port at which the device is located.
985 @param RouteChart The route string pointed to the device.
986 @param DeviceSpeed The device speed.
988 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
989 @retval Others Fail to initialize device slot.
993 XhcPeiInitializeDeviceSlot (
995 IN USB_DEV_ROUTE ParentRouteChart
,
996 IN UINT16 ParentPort
,
997 IN USB_DEV_ROUTE RouteChart
,
1002 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
1003 INPUT_CONTEXT
*InputContext
;
1004 DEVICE_CONTEXT
*OutputContext
;
1005 TRANSFER_RING
*EndpointTransferRing
;
1006 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr
;
1007 UINT8 DeviceAddress
;
1008 CMD_TRB_ENABLE_SLOT CmdTrb
;
1011 DEVICE_CONTEXT
*ParentDeviceContext
;
1012 EFI_PHYSICAL_ADDRESS PhyAddr
;
1014 ZeroMem (&CmdTrb
, sizeof (CMD_TRB_ENABLE_SLOT
));
1015 CmdTrb
.CycleBit
= 1;
1016 CmdTrb
.Type
= TRB_TYPE_EN_SLOT
;
1018 Status
= XhcPeiCmdTransfer (
1020 (TRB_TEMPLATE
*) (UINTN
) &CmdTrb
,
1021 XHC_GENERIC_TIMEOUT
,
1022 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
1024 if (EFI_ERROR (Status
)) {
1025 DEBUG ((EFI_D_ERROR
, "XhcPeiInitializeDeviceSlot: Enable Slot Failed, Status = %r\n", Status
));
1028 ASSERT (EvtTrb
->SlotId
<= Xhc
->MaxSlotsEn
);
1029 DEBUG ((EFI_D_INFO
, "XhcPeiInitializeDeviceSlot: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb
->SlotId
));
1030 SlotId
= (UINT8
) EvtTrb
->SlotId
;
1031 ASSERT (SlotId
!= 0);
1033 ZeroMem (&Xhc
->UsbDevContext
[SlotId
], sizeof (USB_DEV_CONTEXT
));
1034 Xhc
->UsbDevContext
[SlotId
].Enabled
= TRUE
;
1035 Xhc
->UsbDevContext
[SlotId
].SlotId
= SlotId
;
1036 Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
= RouteChart
.Dword
;
1037 Xhc
->UsbDevContext
[SlotId
].ParentRouteString
.Dword
= ParentRouteChart
.Dword
;
1040 // 4.3.3 Device Slot Initialization
1041 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
1043 InputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (INPUT_CONTEXT
));
1044 ASSERT (InputContext
!= NULL
);
1045 ASSERT (((UINTN
) InputContext
& 0x3F) == 0);
1046 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
1048 Xhc
->UsbDevContext
[SlotId
].InputContext
= (VOID
*) InputContext
;
1051 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
1052 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
1053 // Context are affected by the command.
1055 InputContext
->InputControlContext
.Dword2
|= (BIT0
| BIT1
);
1058 // 3) Initialize the Input Slot Context data structure
1060 InputContext
->Slot
.RouteString
= RouteChart
.Route
.RouteString
;
1061 InputContext
->Slot
.Speed
= DeviceSpeed
+ 1;
1062 InputContext
->Slot
.ContextEntries
= 1;
1063 InputContext
->Slot
.RootHubPortNum
= RouteChart
.Route
.RootPortNum
;
1065 if (RouteChart
.Route
.RouteString
!= 0) {
1067 // The device is behind of hub device.
1069 ParentSlotId
= XhcPeiRouteStringToSlotId (Xhc
, ParentRouteChart
);
1070 ASSERT (ParentSlotId
!= 0);
1072 // If the Full/Low device attached to a High Speed Hub, init the TTPortNum and TTHubSlotId field of slot context
1074 ParentDeviceContext
= (DEVICE_CONTEXT
*) Xhc
->UsbDevContext
[ParentSlotId
].OutputContext
;
1075 if ((ParentDeviceContext
->Slot
.TTPortNum
== 0) &&
1076 (ParentDeviceContext
->Slot
.TTHubSlotId
== 0)) {
1077 if ((ParentDeviceContext
->Slot
.Speed
== (EFI_USB_SPEED_HIGH
+ 1)) && (DeviceSpeed
< EFI_USB_SPEED_HIGH
)) {
1079 // Full/Low device attached to High speed hub port that isolates the high speed signaling
1080 // environment from Full/Low speed signaling environment for a device
1082 InputContext
->Slot
.TTPortNum
= ParentPort
;
1083 InputContext
->Slot
.TTHubSlotId
= ParentSlotId
;
1087 // Inherit the TT parameters from parent device.
1089 InputContext
->Slot
.TTPortNum
= ParentDeviceContext
->Slot
.TTPortNum
;
1090 InputContext
->Slot
.TTHubSlotId
= ParentDeviceContext
->Slot
.TTHubSlotId
;
1092 // If the device is a High speed device then down the speed to be the same as its parent Hub
1094 if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
1095 InputContext
->Slot
.Speed
= ParentDeviceContext
->Slot
.Speed
;
1101 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
1103 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
1104 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0] = EndpointTransferRing
;
1105 XhcPeiCreateTransferRing (Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0]);
1107 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
1109 InputContext
->EP
[0].EPType
= ED_CONTROL_BIDIR
;
1111 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
1112 InputContext
->EP
[0].MaxPacketSize
= 512;
1113 } else if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
1114 InputContext
->EP
[0].MaxPacketSize
= 64;
1116 InputContext
->EP
[0].MaxPacketSize
= 8;
1119 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
1120 // 1KB, and Bulk and Isoch endpoints 3KB.
1122 InputContext
->EP
[0].AverageTRBLength
= 8;
1123 InputContext
->EP
[0].MaxBurstSize
= 0;
1124 InputContext
->EP
[0].Interval
= 0;
1125 InputContext
->EP
[0].MaxPStreams
= 0;
1126 InputContext
->EP
[0].Mult
= 0;
1127 InputContext
->EP
[0].CErr
= 3;
1130 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
1132 PhyAddr
= UsbHcGetPciAddrForHostAddr (
1134 ((TRANSFER_RING
*) (UINTN
) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0])->RingSeg0
,
1135 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
1137 InputContext
->EP
[0].PtrLo
= XHC_LOW_32BIT (PhyAddr
) | BIT0
;
1138 InputContext
->EP
[0].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
1141 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
1143 OutputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (DEVICE_CONTEXT
));
1144 ASSERT (OutputContext
!= NULL
);
1145 ASSERT (((UINTN
) OutputContext
& 0x3F) == 0);
1146 ZeroMem (OutputContext
, sizeof (DEVICE_CONTEXT
));
1148 Xhc
->UsbDevContext
[SlotId
].OutputContext
= OutputContext
;
1150 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
1151 // a pointer to the Output Device Context data structure (6.2.1).
1153 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, OutputContext
, sizeof (DEVICE_CONTEXT
));
1155 // Fill DCBAA with PCI device address
1157 Xhc
->DCBAA
[SlotId
] = (UINT64
) (UINTN
) PhyAddr
;
1160 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
1161 // Context data structure described above.
1163 ZeroMem (&CmdTrbAddr
, sizeof (CmdTrbAddr
));
1164 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT
));
1165 CmdTrbAddr
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
1166 CmdTrbAddr
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
1167 CmdTrbAddr
.CycleBit
= 1;
1168 CmdTrbAddr
.Type
= TRB_TYPE_ADDRESS_DEV
;
1169 CmdTrbAddr
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
1170 Status
= XhcPeiCmdTransfer (
1172 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbAddr
,
1173 XHC_GENERIC_TIMEOUT
,
1174 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
1176 if (!EFI_ERROR (Status
)) {
1177 DeviceAddress
= (UINT8
) OutputContext
->Slot
.DeviceAddress
;
1178 DEBUG ((EFI_D_INFO
, "XhcPeiInitializeDeviceSlot: Address %d assigned successfully\n", DeviceAddress
));
1179 Xhc
->UsbDevContext
[SlotId
].XhciDevAddr
= DeviceAddress
;
1182 DEBUG ((EFI_D_INFO
, "XhcPeiInitializeDeviceSlot: Enable Slot, Status = %r\n", Status
));
1187 Assign and initialize the device slot for a new device.
1189 @param Xhc The XHCI device.
1190 @param ParentRouteChart The route string pointed to the parent device.
1191 @param ParentPort The port at which the device is located.
1192 @param RouteChart The route string pointed to the device.
1193 @param DeviceSpeed The device speed.
1195 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1196 @retval Others Fail to initialize device slot.
1200 XhcPeiInitializeDeviceSlot64 (
1201 IN PEI_XHC_DEV
*Xhc
,
1202 IN USB_DEV_ROUTE ParentRouteChart
,
1203 IN UINT16 ParentPort
,
1204 IN USB_DEV_ROUTE RouteChart
,
1205 IN UINT8 DeviceSpeed
1209 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
1210 INPUT_CONTEXT_64
*InputContext
;
1211 DEVICE_CONTEXT_64
*OutputContext
;
1212 TRANSFER_RING
*EndpointTransferRing
;
1213 CMD_TRB_ADDRESS_DEVICE CmdTrbAddr
;
1214 UINT8 DeviceAddress
;
1215 CMD_TRB_ENABLE_SLOT CmdTrb
;
1218 DEVICE_CONTEXT_64
*ParentDeviceContext
;
1219 EFI_PHYSICAL_ADDRESS PhyAddr
;
1221 ZeroMem (&CmdTrb
, sizeof (CMD_TRB_ENABLE_SLOT
));
1222 CmdTrb
.CycleBit
= 1;
1223 CmdTrb
.Type
= TRB_TYPE_EN_SLOT
;
1225 Status
= XhcPeiCmdTransfer (
1227 (TRB_TEMPLATE
*) (UINTN
) &CmdTrb
,
1228 XHC_GENERIC_TIMEOUT
,
1229 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
1231 if (EFI_ERROR (Status
)) {
1232 DEBUG ((EFI_D_ERROR
, "XhcPeiInitializeDeviceSlot64: Enable Slot Failed, Status = %r\n", Status
));
1235 ASSERT (EvtTrb
->SlotId
<= Xhc
->MaxSlotsEn
);
1236 DEBUG ((EFI_D_INFO
, "XhcPeiInitializeDeviceSlot64: Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb
->SlotId
));
1237 SlotId
= (UINT8
)EvtTrb
->SlotId
;
1238 ASSERT (SlotId
!= 0);
1240 ZeroMem (&Xhc
->UsbDevContext
[SlotId
], sizeof (USB_DEV_CONTEXT
));
1241 Xhc
->UsbDevContext
[SlotId
].Enabled
= TRUE
;
1242 Xhc
->UsbDevContext
[SlotId
].SlotId
= SlotId
;
1243 Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
= RouteChart
.Dword
;
1244 Xhc
->UsbDevContext
[SlotId
].ParentRouteString
.Dword
= ParentRouteChart
.Dword
;
1247 // 4.3.3 Device Slot Initialization
1248 // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.
1250 InputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (INPUT_CONTEXT_64
));
1251 ASSERT (InputContext
!= NULL
);
1252 ASSERT (((UINTN
) InputContext
& 0x3F) == 0);
1253 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
1255 Xhc
->UsbDevContext
[SlotId
].InputContext
= (VOID
*) InputContext
;
1258 // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1
1259 // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input
1260 // Context are affected by the command.
1262 InputContext
->InputControlContext
.Dword2
|= (BIT0
| BIT1
);
1265 // 3) Initialize the Input Slot Context data structure
1267 InputContext
->Slot
.RouteString
= RouteChart
.Route
.RouteString
;
1268 InputContext
->Slot
.Speed
= DeviceSpeed
+ 1;
1269 InputContext
->Slot
.ContextEntries
= 1;
1270 InputContext
->Slot
.RootHubPortNum
= RouteChart
.Route
.RootPortNum
;
1272 if (RouteChart
.Route
.RouteString
!= 0) {
1274 // The device is behind of hub device.
1276 ParentSlotId
= XhcPeiRouteStringToSlotId (Xhc
, ParentRouteChart
);
1277 ASSERT (ParentSlotId
!= 0);
1279 //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context
1281 ParentDeviceContext
= (DEVICE_CONTEXT_64
*) Xhc
->UsbDevContext
[ParentSlotId
].OutputContext
;
1282 if ((ParentDeviceContext
->Slot
.TTPortNum
== 0) &&
1283 (ParentDeviceContext
->Slot
.TTHubSlotId
== 0)) {
1284 if ((ParentDeviceContext
->Slot
.Speed
== (EFI_USB_SPEED_HIGH
+ 1)) && (DeviceSpeed
< EFI_USB_SPEED_HIGH
)) {
1286 // Full/Low device attached to High speed hub port that isolates the high speed signaling
1287 // environment from Full/Low speed signaling environment for a device
1289 InputContext
->Slot
.TTPortNum
= ParentPort
;
1290 InputContext
->Slot
.TTHubSlotId
= ParentSlotId
;
1294 // Inherit the TT parameters from parent device.
1296 InputContext
->Slot
.TTPortNum
= ParentDeviceContext
->Slot
.TTPortNum
;
1297 InputContext
->Slot
.TTHubSlotId
= ParentDeviceContext
->Slot
.TTHubSlotId
;
1299 // If the device is a High speed device then down the speed to be the same as its parent Hub
1301 if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
1302 InputContext
->Slot
.Speed
= ParentDeviceContext
->Slot
.Speed
;
1308 // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.
1310 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
1311 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0] = EndpointTransferRing
;
1312 XhcPeiCreateTransferRing(Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0]);
1314 // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).
1316 InputContext
->EP
[0].EPType
= ED_CONTROL_BIDIR
;
1318 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
1319 InputContext
->EP
[0].MaxPacketSize
= 512;
1320 } else if (DeviceSpeed
== EFI_USB_SPEED_HIGH
) {
1321 InputContext
->EP
[0].MaxPacketSize
= 64;
1323 InputContext
->EP
[0].MaxPacketSize
= 8;
1326 // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints
1327 // 1KB, and Bulk and Isoch endpoints 3KB.
1329 InputContext
->EP
[0].AverageTRBLength
= 8;
1330 InputContext
->EP
[0].MaxBurstSize
= 0;
1331 InputContext
->EP
[0].Interval
= 0;
1332 InputContext
->EP
[0].MaxPStreams
= 0;
1333 InputContext
->EP
[0].Mult
= 0;
1334 InputContext
->EP
[0].CErr
= 3;
1337 // Init the DCS(dequeue cycle state) as the transfer ring's CCS
1339 PhyAddr
= UsbHcGetPciAddrForHostAddr (
1341 ((TRANSFER_RING
*) (UINTN
) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[0])->RingSeg0
,
1342 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
1344 InputContext
->EP
[0].PtrLo
= XHC_LOW_32BIT (PhyAddr
) | BIT0
;
1345 InputContext
->EP
[0].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
1348 // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.
1350 OutputContext
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (DEVICE_CONTEXT_64
));
1351 ASSERT (OutputContext
!= NULL
);
1352 ASSERT (((UINTN
) OutputContext
& 0x3F) == 0);
1353 ZeroMem (OutputContext
, sizeof (DEVICE_CONTEXT_64
));
1355 Xhc
->UsbDevContext
[SlotId
].OutputContext
= OutputContext
;
1357 // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
1358 // a pointer to the Output Device Context data structure (6.2.1).
1360 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, OutputContext
, sizeof (DEVICE_CONTEXT_64
));
1362 // Fill DCBAA with PCI device address
1364 Xhc
->DCBAA
[SlotId
] = (UINT64
) (UINTN
) PhyAddr
;
1367 // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
1368 // Context data structure described above.
1370 ZeroMem (&CmdTrbAddr
, sizeof (CmdTrbAddr
));
1371 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT_64
));
1372 CmdTrbAddr
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
1373 CmdTrbAddr
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
1374 CmdTrbAddr
.CycleBit
= 1;
1375 CmdTrbAddr
.Type
= TRB_TYPE_ADDRESS_DEV
;
1376 CmdTrbAddr
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
1377 Status
= XhcPeiCmdTransfer (
1379 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbAddr
,
1380 XHC_GENERIC_TIMEOUT
,
1381 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
1383 if (!EFI_ERROR (Status
)) {
1384 DeviceAddress
= (UINT8
) OutputContext
->Slot
.DeviceAddress
;
1385 DEBUG ((EFI_D_INFO
, "XhcPeiInitializeDeviceSlot64: Address %d assigned successfully\n", DeviceAddress
));
1386 Xhc
->UsbDevContext
[SlotId
].XhciDevAddr
= DeviceAddress
;
1389 DEBUG ((EFI_D_INFO
, "XhcPeiInitializeDeviceSlot64: Enable Slot, Status = %r\n", Status
));
1395 Disable the specified device slot.
1397 @param Xhc The XHCI device.
1398 @param SlotId The slot id to be disabled.
1400 @retval EFI_SUCCESS Successfully disable the device slot.
1404 XhcPeiDisableSlotCmd (
1405 IN PEI_XHC_DEV
*Xhc
,
1410 TRB_TEMPLATE
*EvtTrb
;
1411 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot
;
1416 // Disable the device slots occupied by these devices on its downstream ports.
1417 // Entry 0 is reserved.
1419 for (Index
= 0; Index
< 255; Index
++) {
1420 if (!Xhc
->UsbDevContext
[Index
+ 1].Enabled
||
1421 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
== 0) ||
1422 (Xhc
->UsbDevContext
[Index
+ 1].ParentRouteString
.Dword
!= Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
)) {
1426 Status
= XhcPeiDisableSlotCmd (Xhc
, Xhc
->UsbDevContext
[Index
+ 1].SlotId
);
1428 if (EFI_ERROR (Status
)) {
1429 DEBUG ((EFI_D_ERROR
, "XhcPeiDisableSlotCmd: failed to disable child, ignore error\n"));
1430 Xhc
->UsbDevContext
[Index
+ 1].SlotId
= 0;
1435 // Construct the disable slot command
1437 DEBUG ((EFI_D_INFO
, "XhcPeiDisableSlotCmd: Disable device slot %d!\n", SlotId
));
1439 ZeroMem (&CmdTrbDisSlot
, sizeof (CmdTrbDisSlot
));
1440 CmdTrbDisSlot
.CycleBit
= 1;
1441 CmdTrbDisSlot
.Type
= TRB_TYPE_DIS_SLOT
;
1442 CmdTrbDisSlot
.SlotId
= SlotId
;
1443 Status
= XhcPeiCmdTransfer (
1445 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbDisSlot
,
1446 XHC_GENERIC_TIMEOUT
,
1447 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
1449 if (EFI_ERROR (Status
)) {
1450 DEBUG ((EFI_D_ERROR
, "XhcPeiDisableSlotCmd: Disable Slot Command Failed, Status = %r\n", Status
));
1454 // Free the slot's device context entry
1456 Xhc
->DCBAA
[SlotId
] = 0;
1459 // Free the slot related data structure
1461 for (Index
= 0; Index
< 31; Index
++) {
1462 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] != NULL
) {
1463 RingSeg
= ((TRANSFER_RING
*) (UINTN
) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
])->RingSeg0
;
1464 if (RingSeg
!= NULL
) {
1465 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
1467 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
]);
1468 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] = NULL
;
1472 for (Index
= 0; Index
< Xhc
->UsbDevContext
[SlotId
].DevDesc
.NumConfigurations
; Index
++) {
1473 if (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
] != NULL
) {
1474 FreePool (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
]);
1478 if (Xhc
->UsbDevContext
[SlotId
].InputContext
!= NULL
) {
1479 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT
));
1482 if (Xhc
->UsbDevContext
[SlotId
].OutputContext
!= NULL
) {
1483 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].OutputContext
, sizeof (DEVICE_CONTEXT
));
1486 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
1487 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
1488 // remove urb from XHCI's asynchronous transfer list.
1490 Xhc
->UsbDevContext
[SlotId
].Enabled
= FALSE
;
1491 Xhc
->UsbDevContext
[SlotId
].SlotId
= 0;
1493 DEBUG ((EFI_D_INFO
, "XhcPeiDisableSlotCmd: Disable Slot Command, Status = %r\n", Status
));
1498 Disable the specified device slot.
1500 @param Xhc The XHCI device.
1501 @param SlotId The slot id to be disabled.
1503 @retval EFI_SUCCESS Successfully disable the device slot.
1507 XhcPeiDisableSlotCmd64 (
1508 IN PEI_XHC_DEV
*Xhc
,
1513 TRB_TEMPLATE
*EvtTrb
;
1514 CMD_TRB_DISABLE_SLOT CmdTrbDisSlot
;
1519 // Disable the device slots occupied by these devices on its downstream ports.
1520 // Entry 0 is reserved.
1522 for (Index
= 0; Index
< 255; Index
++) {
1523 if (!Xhc
->UsbDevContext
[Index
+ 1].Enabled
||
1524 (Xhc
->UsbDevContext
[Index
+ 1].SlotId
== 0) ||
1525 (Xhc
->UsbDevContext
[Index
+ 1].ParentRouteString
.Dword
!= Xhc
->UsbDevContext
[SlotId
].RouteString
.Dword
)) {
1529 Status
= XhcPeiDisableSlotCmd64 (Xhc
, Xhc
->UsbDevContext
[Index
+ 1].SlotId
);
1531 if (EFI_ERROR (Status
)) {
1532 DEBUG ((EFI_D_ERROR
, "XhcPeiDisableSlotCmd64: failed to disable child, ignore error\n"));
1533 Xhc
->UsbDevContext
[Index
+ 1].SlotId
= 0;
1538 // Construct the disable slot command
1540 DEBUG ((EFI_D_INFO
, "XhcPeiDisableSlotCmd64: Disable device slot %d!\n", SlotId
));
1542 ZeroMem (&CmdTrbDisSlot
, sizeof (CmdTrbDisSlot
));
1543 CmdTrbDisSlot
.CycleBit
= 1;
1544 CmdTrbDisSlot
.Type
= TRB_TYPE_DIS_SLOT
;
1545 CmdTrbDisSlot
.SlotId
= SlotId
;
1546 Status
= XhcPeiCmdTransfer (
1548 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbDisSlot
,
1549 XHC_GENERIC_TIMEOUT
,
1550 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
1552 if (EFI_ERROR (Status
)) {
1553 DEBUG ((EFI_D_ERROR
, "XhcPeiDisableSlotCmd64: Disable Slot Command Failed, Status = %r\n", Status
));
1557 // Free the slot's device context entry
1559 Xhc
->DCBAA
[SlotId
] = 0;
1562 // Free the slot related data structure
1564 for (Index
= 0; Index
< 31; Index
++) {
1565 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] != NULL
) {
1566 RingSeg
= ((TRANSFER_RING
*) (UINTN
) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
])->RingSeg0
;
1567 if (RingSeg
!= NULL
) {
1568 UsbHcFreeMem (Xhc
->MemPool
, RingSeg
, sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
);
1570 FreePool (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
]);
1571 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Index
] = NULL
;
1575 for (Index
= 0; Index
< Xhc
->UsbDevContext
[SlotId
].DevDesc
.NumConfigurations
; Index
++) {
1576 if (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
] != NULL
) {
1577 FreePool (Xhc
->UsbDevContext
[SlotId
].ConfDesc
[Index
]);
1581 if (Xhc
->UsbDevContext
[SlotId
].InputContext
!= NULL
) {
1582 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].InputContext
, sizeof (INPUT_CONTEXT_64
));
1585 if (Xhc
->UsbDevContext
[SlotId
].OutputContext
!= NULL
) {
1586 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->UsbDevContext
[SlotId
].OutputContext
, sizeof (DEVICE_CONTEXT_64
));
1589 // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established
1590 // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to
1591 // remove urb from XHCI's asynchronous transfer list.
1593 Xhc
->UsbDevContext
[SlotId
].Enabled
= FALSE
;
1594 Xhc
->UsbDevContext
[SlotId
].SlotId
= 0;
1596 DEBUG ((EFI_D_INFO
, "XhcPeiDisableSlotCmd64: Disable Slot Command, Status = %r\n", Status
));
1601 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1603 @param Xhc The XHCI device.
1604 @param SlotId The slot id to be configured.
1605 @param DeviceSpeed The device's speed.
1606 @param ConfigDesc The pointer to the usb device configuration descriptor.
1608 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1612 XhcPeiSetConfigCmd (
1613 IN PEI_XHC_DEV
*Xhc
,
1615 IN UINT8 DeviceSpeed
,
1616 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
1620 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
1621 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
1626 EFI_USB_DATA_DIRECTION Direction
;
1629 EFI_PHYSICAL_ADDRESS PhyAddr
;
1632 TRANSFER_RING
*EndpointTransferRing
;
1633 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
1634 INPUT_CONTEXT
*InputContext
;
1635 DEVICE_CONTEXT
*OutputContext
;
1636 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
1638 // 4.6.6 Configure Endpoint
1640 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
1641 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
1642 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
1643 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT
));
1645 ASSERT (ConfigDesc
!= NULL
);
1649 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*) (ConfigDesc
+ 1);
1650 for (Index
= 0; Index
< ConfigDesc
->NumInterfaces
; Index
++) {
1651 while ((IfDesc
->DescriptorType
!= USB_DESC_TYPE_INTERFACE
) || (IfDesc
->AlternateSetting
!= 0)) {
1652 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*) ((UINTN
) IfDesc
+ IfDesc
->Length
);
1655 NumEp
= IfDesc
->NumEndpoints
;
1657 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*) (IfDesc
+ 1);
1658 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
1659 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
1660 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*) ((UINTN
) EpDesc
+ EpDesc
->Length
);
1663 EpAddr
= (UINT8
) (EpDesc
->EndpointAddress
& 0x0F);
1664 Direction
= (UINT8
) ((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
1666 Dci
= XhcPeiEndpointToDci (EpAddr
, Direction
);
1671 InputContext
->InputControlContext
.Dword2
|= (BIT0
<< Dci
);
1672 InputContext
->EP
[Dci
-1].MaxPacketSize
= EpDesc
->MaxPacketSize
;
1674 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
1676 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
1678 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
1680 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
1683 switch (EpDesc
->Attributes
& USB_ENDPOINT_TYPE_MASK
) {
1684 case USB_ENDPOINT_BULK
:
1685 if (Direction
== EfiUsbDataIn
) {
1686 InputContext
->EP
[Dci
-1].CErr
= 3;
1687 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_IN
;
1689 InputContext
->EP
[Dci
-1].CErr
= 3;
1690 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_OUT
;
1693 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
1694 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
1695 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
1696 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
1697 XhcPeiCreateTransferRing (Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
1701 case USB_ENDPOINT_ISO
:
1702 if (Direction
== EfiUsbDataIn
) {
1703 InputContext
->EP
[Dci
-1].CErr
= 0;
1704 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_IN
;
1706 InputContext
->EP
[Dci
-1].CErr
= 0;
1707 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_OUT
;
1710 // Do not support isochronous transfer now.
1712 DEBUG ((EFI_D_INFO
, "XhcPeiSetConfigCmd: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
1713 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
1715 case USB_ENDPOINT_INTERRUPT
:
1716 if (Direction
== EfiUsbDataIn
) {
1717 InputContext
->EP
[Dci
-1].CErr
= 3;
1718 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_IN
;
1720 InputContext
->EP
[Dci
-1].CErr
= 3;
1721 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_OUT
;
1723 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
1724 InputContext
->EP
[Dci
-1].MaxESITPayload
= EpDesc
->MaxPacketSize
;
1726 // Get the bInterval from descriptor and init the interval field of endpoint context
1728 if ((DeviceSpeed
== EFI_USB_SPEED_FULL
) || (DeviceSpeed
== EFI_USB_SPEED_LOW
)) {
1729 Interval
= EpDesc
->Interval
;
1731 // Calculate through the bInterval field of Endpoint descriptor.
1733 ASSERT (Interval
!= 0);
1734 InputContext
->EP
[Dci
-1].Interval
= (UINT32
) HighBitSet32 ((UINT32
) Interval
) + 3;
1735 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
1736 Interval
= EpDesc
->Interval
;
1737 ASSERT (Interval
>= 1 && Interval
<= 16);
1739 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
1741 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
1744 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
1745 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
1746 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
1747 XhcPeiCreateTransferRing (Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
1751 case USB_ENDPOINT_CONTROL
:
1753 // Do not support control transfer now.
1755 DEBUG ((EFI_D_INFO
, "XhcPeiSetConfigCmd: Unsupport Control EP found, Transfer ring is not allocated.\n"));
1757 DEBUG ((EFI_D_INFO
, "XhcPeiSetConfigCmd: Unknown EP found, Transfer ring is not allocated.\n"));
1758 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
1762 PhyAddr
= UsbHcGetPciAddrForHostAddr (
1764 ((TRANSFER_RING
*) (UINTN
) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingSeg0
,
1765 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
1767 PhyAddr
&= ~((EFI_PHYSICAL_ADDRESS
)0x0F);
1768 PhyAddr
|= (EFI_PHYSICAL_ADDRESS
)((TRANSFER_RING
*) (UINTN
) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingPCS
;
1769 InputContext
->EP
[Dci
-1].PtrLo
= XHC_LOW_32BIT (PhyAddr
);
1770 InputContext
->EP
[Dci
-1].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
1772 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*) ((UINTN
) EpDesc
+ EpDesc
->Length
);
1774 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*) ((UINTN
) IfDesc
+ IfDesc
->Length
);
1777 InputContext
->InputControlContext
.Dword2
|= BIT0
;
1778 InputContext
->Slot
.ContextEntries
= MaxDci
;
1780 // configure endpoint
1782 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
1783 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
1784 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
1785 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
1786 CmdTrbCfgEP
.CycleBit
= 1;
1787 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
1788 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
1789 DEBUG ((EFI_D_INFO
, "XhcSetConfigCmd: Configure Endpoint\n"));
1790 Status
= XhcPeiCmdTransfer (
1792 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
1793 XHC_GENERIC_TIMEOUT
,
1794 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
1796 if (EFI_ERROR (Status
)) {
1797 DEBUG ((EFI_D_ERROR
, "XhcSetConfigCmd: Config Endpoint Failed, Status = %r\n", Status
));
1803 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
1805 @param Xhc The XHCI device.
1806 @param SlotId The slot id to be configured.
1807 @param DeviceSpeed The device's speed.
1808 @param ConfigDesc The pointer to the usb device configuration descriptor.
1810 @retval EFI_SUCCESS Successfully configure all the device endpoints.
1814 XhcPeiSetConfigCmd64 (
1815 IN PEI_XHC_DEV
*Xhc
,
1817 IN UINT8 DeviceSpeed
,
1818 IN USB_CONFIG_DESCRIPTOR
*ConfigDesc
1822 USB_INTERFACE_DESCRIPTOR
*IfDesc
;
1823 USB_ENDPOINT_DESCRIPTOR
*EpDesc
;
1828 EFI_USB_DATA_DIRECTION Direction
;
1831 EFI_PHYSICAL_ADDRESS PhyAddr
;
1834 TRANSFER_RING
*EndpointTransferRing
;
1835 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
1836 INPUT_CONTEXT_64
*InputContext
;
1837 DEVICE_CONTEXT_64
*OutputContext
;
1838 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
1840 // 4.6.6 Configure Endpoint
1842 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
1843 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
1844 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
1845 CopyMem (&InputContext
->Slot
, &OutputContext
->Slot
, sizeof (SLOT_CONTEXT_64
));
1847 ASSERT (ConfigDesc
!= NULL
);
1851 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*) (ConfigDesc
+ 1);
1852 for (Index
= 0; Index
< ConfigDesc
->NumInterfaces
; Index
++) {
1853 while ((IfDesc
->DescriptorType
!= USB_DESC_TYPE_INTERFACE
) || (IfDesc
->AlternateSetting
!= 0)) {
1854 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*) ((UINTN
) IfDesc
+ IfDesc
->Length
);
1857 NumEp
= IfDesc
->NumEndpoints
;
1859 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*) (IfDesc
+ 1);
1860 for (EpIndex
= 0; EpIndex
< NumEp
; EpIndex
++) {
1861 while (EpDesc
->DescriptorType
!= USB_DESC_TYPE_ENDPOINT
) {
1862 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*) ((UINTN
) EpDesc
+ EpDesc
->Length
);
1865 EpAddr
= (UINT8
) (EpDesc
->EndpointAddress
& 0x0F);
1866 Direction
= (UINT8
) ((EpDesc
->EndpointAddress
& 0x80) ? EfiUsbDataIn
: EfiUsbDataOut
);
1868 Dci
= XhcPeiEndpointToDci (EpAddr
, Direction
);
1874 InputContext
->InputControlContext
.Dword2
|= (BIT0
<< Dci
);
1875 InputContext
->EP
[Dci
-1].MaxPacketSize
= EpDesc
->MaxPacketSize
;
1877 if (DeviceSpeed
== EFI_USB_SPEED_SUPER
) {
1879 // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.
1881 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
1883 InputContext
->EP
[Dci
-1].MaxBurstSize
= 0x0;
1886 switch (EpDesc
->Attributes
& USB_ENDPOINT_TYPE_MASK
) {
1887 case USB_ENDPOINT_BULK
:
1888 if (Direction
== EfiUsbDataIn
) {
1889 InputContext
->EP
[Dci
-1].CErr
= 3;
1890 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_IN
;
1892 InputContext
->EP
[Dci
-1].CErr
= 3;
1893 InputContext
->EP
[Dci
-1].EPType
= ED_BULK_OUT
;
1896 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
1897 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
1898 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
1899 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
1900 XhcPeiCreateTransferRing (Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
1904 case USB_ENDPOINT_ISO
:
1905 if (Direction
== EfiUsbDataIn
) {
1906 InputContext
->EP
[Dci
-1].CErr
= 0;
1907 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_IN
;
1909 InputContext
->EP
[Dci
-1].CErr
= 0;
1910 InputContext
->EP
[Dci
-1].EPType
= ED_ISOCH_OUT
;
1913 // Do not support isochronous transfer now.
1915 DEBUG ((EFI_D_INFO
, "XhcPeiSetConfigCmd64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
1916 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
1918 case USB_ENDPOINT_INTERRUPT
:
1919 if (Direction
== EfiUsbDataIn
) {
1920 InputContext
->EP
[Dci
-1].CErr
= 3;
1921 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_IN
;
1923 InputContext
->EP
[Dci
-1].CErr
= 3;
1924 InputContext
->EP
[Dci
-1].EPType
= ED_INTERRUPT_OUT
;
1926 InputContext
->EP
[Dci
-1].AverageTRBLength
= 0x1000;
1927 InputContext
->EP
[Dci
-1].MaxESITPayload
= EpDesc
->MaxPacketSize
;
1929 // Get the bInterval from descriptor and init the the interval field of endpoint context
1931 if ((DeviceSpeed
== EFI_USB_SPEED_FULL
) || (DeviceSpeed
== EFI_USB_SPEED_LOW
)) {
1932 Interval
= EpDesc
->Interval
;
1934 // Calculate through the bInterval field of Endpoint descriptor.
1936 ASSERT (Interval
!= 0);
1937 InputContext
->EP
[Dci
-1].Interval
= (UINT32
) HighBitSet32( (UINT32
) Interval
) + 3;
1938 } else if ((DeviceSpeed
== EFI_USB_SPEED_HIGH
) || (DeviceSpeed
== EFI_USB_SPEED_SUPER
)) {
1939 Interval
= EpDesc
->Interval
;
1940 ASSERT (Interval
>= 1 && Interval
<= 16);
1942 // Refer to XHCI 1.0 spec section 6.2.3.6, table 61
1944 InputContext
->EP
[Dci
-1].Interval
= Interval
- 1;
1947 if (Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] == NULL
) {
1948 EndpointTransferRing
= AllocateZeroPool (sizeof (TRANSFER_RING
));
1949 Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1] = (VOID
*) EndpointTransferRing
;
1950 XhcPeiCreateTransferRing (Xhc
, TR_RING_TRB_NUMBER
, (TRANSFER_RING
*) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1]);
1954 case USB_ENDPOINT_CONTROL
:
1956 // Do not support control transfer now.
1958 DEBUG ((EFI_D_INFO
, "XhcPeiSetConfigCmd64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
1960 DEBUG ((EFI_D_INFO
, "XhcPeiSetConfigCmd64: Unknown EP found, Transfer ring is not allocated.\n"));
1961 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*)((UINTN
)EpDesc
+ EpDesc
->Length
);
1965 PhyAddr
= UsbHcGetPciAddrForHostAddr (
1967 ((TRANSFER_RING
*) (UINTN
) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingSeg0
,
1968 sizeof (TRB_TEMPLATE
) * TR_RING_TRB_NUMBER
1971 PhyAddr
&= ~((EFI_PHYSICAL_ADDRESS
)0x0F);
1972 PhyAddr
|= (EFI_PHYSICAL_ADDRESS
)((TRANSFER_RING
*) (UINTN
) Xhc
->UsbDevContext
[SlotId
].EndpointTransferRing
[Dci
-1])->RingPCS
;
1974 InputContext
->EP
[Dci
-1].PtrLo
= XHC_LOW_32BIT (PhyAddr
);
1975 InputContext
->EP
[Dci
-1].PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
1977 EpDesc
= (USB_ENDPOINT_DESCRIPTOR
*) ((UINTN
)EpDesc
+ EpDesc
->Length
);
1979 IfDesc
= (USB_INTERFACE_DESCRIPTOR
*) ((UINTN
)IfDesc
+ IfDesc
->Length
);
1982 InputContext
->InputControlContext
.Dword2
|= BIT0
;
1983 InputContext
->Slot
.ContextEntries
= MaxDci
;
1985 // configure endpoint
1987 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
1988 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
1989 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
1990 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
1991 CmdTrbCfgEP
.CycleBit
= 1;
1992 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
1993 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
1994 DEBUG ((EFI_D_INFO
, "XhcSetConfigCmd64: Configure Endpoint\n"));
1995 Status
= XhcPeiCmdTransfer (
1997 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
1998 XHC_GENERIC_TIMEOUT
,
1999 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2001 if (EFI_ERROR (Status
)) {
2002 DEBUG ((EFI_D_ERROR
, "XhcSetConfigCmd64: Config Endpoint Failed, Status = %r\n", Status
));
2010 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
2012 @param Xhc The XHCI device.
2013 @param SlotId The slot id to be evaluated.
2014 @param MaxPacketSize The max packet size supported by the device control transfer.
2016 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
2020 XhcPeiEvaluateContext (
2021 IN PEI_XHC_DEV
*Xhc
,
2023 IN UINT32 MaxPacketSize
2027 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu
;
2028 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2029 INPUT_CONTEXT
*InputContext
;
2030 EFI_PHYSICAL_ADDRESS PhyAddr
;
2032 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
2035 // 4.6.7 Evaluate Context
2037 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
2038 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
2040 InputContext
->InputControlContext
.Dword2
|= BIT1
;
2041 InputContext
->EP
[0].MaxPacketSize
= MaxPacketSize
;
2043 ZeroMem (&CmdTrbEvalu
, sizeof (CmdTrbEvalu
));
2044 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
2045 CmdTrbEvalu
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2046 CmdTrbEvalu
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2047 CmdTrbEvalu
.CycleBit
= 1;
2048 CmdTrbEvalu
.Type
= TRB_TYPE_EVALU_CONTXT
;
2049 CmdTrbEvalu
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2050 DEBUG ((EFI_D_INFO
, "XhcEvaluateContext: Evaluate context\n"));
2051 Status
= XhcPeiCmdTransfer (
2053 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbEvalu
,
2054 XHC_GENERIC_TIMEOUT
,
2055 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2057 if (EFI_ERROR (Status
)) {
2058 DEBUG ((EFI_D_ERROR
, "XhcEvaluateContext: Evaluate Context Failed, Status = %r\n", Status
));
2064 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
2066 @param Xhc The XHCI device.
2067 @param SlotId The slot id to be evaluated.
2068 @param MaxPacketSize The max packet size supported by the device control transfer.
2070 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
2074 XhcPeiEvaluateContext64 (
2075 IN PEI_XHC_DEV
*Xhc
,
2077 IN UINT32 MaxPacketSize
2081 CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu
;
2082 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2083 INPUT_CONTEXT_64
*InputContext
;
2084 EFI_PHYSICAL_ADDRESS PhyAddr
;
2086 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
2089 // 4.6.7 Evaluate Context
2091 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
2092 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
2094 InputContext
->InputControlContext
.Dword2
|= BIT1
;
2095 InputContext
->EP
[0].MaxPacketSize
= MaxPacketSize
;
2097 ZeroMem (&CmdTrbEvalu
, sizeof (CmdTrbEvalu
));
2098 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
2099 CmdTrbEvalu
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2100 CmdTrbEvalu
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2101 CmdTrbEvalu
.CycleBit
= 1;
2102 CmdTrbEvalu
.Type
= TRB_TYPE_EVALU_CONTXT
;
2103 CmdTrbEvalu
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2104 DEBUG ((EFI_D_INFO
, "XhcEvaluateContext64: Evaluate context 64\n"));
2105 Status
= XhcPeiCmdTransfer (
2107 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbEvalu
,
2108 XHC_GENERIC_TIMEOUT
,
2109 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2111 if (EFI_ERROR (Status
)) {
2112 DEBUG ((EFI_D_ERROR
, "XhcEvaluateContext64: Evaluate Context Failed, Status = %r\n", Status
));
2118 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
2120 @param Xhc The XHCI device.
2121 @param SlotId The slot id to be configured.
2122 @param PortNum The total number of downstream port supported by the hub.
2123 @param TTT The TT think time of the hub device.
2124 @param MTT The multi-TT of the hub device.
2126 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
2130 XhcPeiConfigHubContext (
2131 IN PEI_XHC_DEV
*Xhc
,
2139 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2140 INPUT_CONTEXT
*InputContext
;
2141 DEVICE_CONTEXT
*OutputContext
;
2142 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
2143 EFI_PHYSICAL_ADDRESS PhyAddr
;
2145 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
2146 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
2147 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
2150 // 4.6.7 Evaluate Context
2152 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT
));
2154 InputContext
->InputControlContext
.Dword2
|= BIT0
;
2157 // Copy the slot context from OutputContext to Input context
2159 CopyMem(&(InputContext
->Slot
), &(OutputContext
->Slot
), sizeof (SLOT_CONTEXT
));
2160 InputContext
->Slot
.Hub
= 1;
2161 InputContext
->Slot
.PortNum
= PortNum
;
2162 InputContext
->Slot
.TTT
= TTT
;
2163 InputContext
->Slot
.MTT
= MTT
;
2165 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
2166 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT
));
2167 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2168 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2169 CmdTrbCfgEP
.CycleBit
= 1;
2170 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
2171 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2172 DEBUG ((EFI_D_INFO
, "Configure Hub Slot Context\n"));
2173 Status
= XhcPeiCmdTransfer (
2175 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
2176 XHC_GENERIC_TIMEOUT
,
2177 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2179 if (EFI_ERROR (Status
)) {
2180 DEBUG ((EFI_D_ERROR
, "XhcConfigHubContext: Config Endpoint Failed, Status = %r\n", Status
));
2186 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
2188 @param Xhc The XHCI device.
2189 @param SlotId The slot id to be configured.
2190 @param PortNum The total number of downstream port supported by the hub.
2191 @param TTT The TT think time of the hub device.
2192 @param MTT The multi-TT of the hub device.
2194 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
2198 XhcPeiConfigHubContext64 (
2199 IN PEI_XHC_DEV
*Xhc
,
2207 EVT_TRB_COMMAND_COMPLETION
*EvtTrb
;
2208 INPUT_CONTEXT_64
*InputContext
;
2209 DEVICE_CONTEXT_64
*OutputContext
;
2210 CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP
;
2211 EFI_PHYSICAL_ADDRESS PhyAddr
;
2213 ASSERT (Xhc
->UsbDevContext
[SlotId
].SlotId
!= 0);
2214 InputContext
= Xhc
->UsbDevContext
[SlotId
].InputContext
;
2215 OutputContext
= Xhc
->UsbDevContext
[SlotId
].OutputContext
;
2218 // 4.6.7 Evaluate Context
2220 ZeroMem (InputContext
, sizeof (INPUT_CONTEXT_64
));
2222 InputContext
->InputControlContext
.Dword2
|= BIT0
;
2225 // Copy the slot context from OutputContext to Input context
2227 CopyMem(&(InputContext
->Slot
), &(OutputContext
->Slot
), sizeof (SLOT_CONTEXT_64
));
2228 InputContext
->Slot
.Hub
= 1;
2229 InputContext
->Slot
.PortNum
= PortNum
;
2230 InputContext
->Slot
.TTT
= TTT
;
2231 InputContext
->Slot
.MTT
= MTT
;
2233 ZeroMem (&CmdTrbCfgEP
, sizeof (CmdTrbCfgEP
));
2234 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, InputContext
, sizeof (INPUT_CONTEXT_64
));
2235 CmdTrbCfgEP
.PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2236 CmdTrbCfgEP
.PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2237 CmdTrbCfgEP
.CycleBit
= 1;
2238 CmdTrbCfgEP
.Type
= TRB_TYPE_CON_ENDPOINT
;
2239 CmdTrbCfgEP
.SlotId
= Xhc
->UsbDevContext
[SlotId
].SlotId
;
2240 DEBUG ((EFI_D_INFO
, "Configure Hub Slot Context 64\n"));
2241 Status
= XhcPeiCmdTransfer (
2243 (TRB_TEMPLATE
*) (UINTN
) &CmdTrbCfgEP
,
2244 XHC_GENERIC_TIMEOUT
,
2245 (TRB_TEMPLATE
**) (UINTN
) &EvtTrb
2247 if (EFI_ERROR (Status
)) {
2248 DEBUG ((EFI_D_ERROR
, "XhcConfigHubContext64: Config Endpoint Failed, Status = %r\n", Status
));
2254 Check if there is a new generated event.
2256 @param Xhc The XHCI device.
2257 @param EvtRing The event ring to check.
2258 @param NewEvtTrb The new event TRB found.
2260 @retval EFI_SUCCESS Found a new event TRB at the event ring.
2261 @retval EFI_NOT_READY The event ring has no new event.
2265 XhcPeiCheckNewEvent (
2266 IN PEI_XHC_DEV
*Xhc
,
2267 IN EVENT_RING
*EvtRing
,
2268 OUT TRB_TEMPLATE
**NewEvtTrb
2271 ASSERT (EvtRing
!= NULL
);
2273 *NewEvtTrb
= EvtRing
->EventRingDequeue
;
2275 if (EvtRing
->EventRingDequeue
== EvtRing
->EventRingEnqueue
) {
2276 return EFI_NOT_READY
;
2279 EvtRing
->EventRingDequeue
++;
2281 // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.
2283 if ((UINTN
) EvtRing
->EventRingDequeue
>= ((UINTN
) EvtRing
->EventRingSeg0
+ sizeof (TRB_TEMPLATE
) * EvtRing
->TrbNumber
)) {
2284 EvtRing
->EventRingDequeue
= EvtRing
->EventRingSeg0
;
2291 Synchronize the specified event ring to update the enqueue and dequeue pointer.
2293 @param Xhc The XHCI device.
2294 @param EvtRing The event ring to sync.
2296 @retval EFI_SUCCESS The event ring is synchronized successfully.
2300 XhcPeiSyncEventRing (
2301 IN PEI_XHC_DEV
*Xhc
,
2302 IN EVENT_RING
*EvtRing
2306 TRB_TEMPLATE
*EvtTrb
;
2308 ASSERT (EvtRing
!= NULL
);
2311 // Calculate the EventRingEnqueue and EventRingCCS.
2312 // Note: only support single Segment
2314 EvtTrb
= EvtRing
->EventRingDequeue
;
2316 for (Index
= 0; Index
< EvtRing
->TrbNumber
; Index
++) {
2317 if (EvtTrb
->CycleBit
!= EvtRing
->EventRingCCS
) {
2323 if ((UINTN
) EvtTrb
>= ((UINTN
) EvtRing
->EventRingSeg0
+ sizeof (TRB_TEMPLATE
) * EvtRing
->TrbNumber
)) {
2324 EvtTrb
= EvtRing
->EventRingSeg0
;
2325 EvtRing
->EventRingCCS
= (EvtRing
->EventRingCCS
) ? 0 : 1;
2329 if (Index
< EvtRing
->TrbNumber
) {
2330 EvtRing
->EventRingEnqueue
= EvtTrb
;
2339 Free XHCI event ring.
2341 @param Xhc The XHCI device.
2342 @param EventRing The event ring to be freed.
2346 XhcPeiFreeEventRing (
2347 IN PEI_XHC_DEV
*Xhc
,
2348 IN EVENT_RING
*EventRing
2351 if(EventRing
->EventRingSeg0
== NULL
) {
2356 // Free EventRing Segment 0
2358 UsbHcFreeMem (Xhc
->MemPool
, EventRing
->EventRingSeg0
, sizeof (TRB_TEMPLATE
) * EVENT_RING_TRB_NUMBER
);
2363 UsbHcFreeMem (Xhc
->MemPool
, EventRing
->ERSTBase
, sizeof (EVENT_RING_SEG_TABLE_ENTRY
) * ERST_NUMBER
);
2367 Create XHCI event ring.
2369 @param Xhc The XHCI device.
2370 @param EventRing The created event ring.
2374 XhcPeiCreateEventRing (
2375 IN PEI_XHC_DEV
*Xhc
,
2376 OUT EVENT_RING
*EventRing
2380 EVENT_RING_SEG_TABLE_ENTRY
*ERSTBase
;
2382 EFI_PHYSICAL_ADDRESS ERSTPhy
;
2383 EFI_PHYSICAL_ADDRESS DequeuePhy
;
2385 ASSERT (EventRing
!= NULL
);
2387 Size
= sizeof (TRB_TEMPLATE
) * EVENT_RING_TRB_NUMBER
;
2388 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, Size
);
2389 ASSERT (Buf
!= NULL
);
2390 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
2391 ZeroMem (Buf
, Size
);
2393 DequeuePhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Buf
, Size
);
2395 EventRing
->EventRingSeg0
= Buf
;
2396 EventRing
->TrbNumber
= EVENT_RING_TRB_NUMBER
;
2397 EventRing
->EventRingDequeue
= (TRB_TEMPLATE
*) EventRing
->EventRingSeg0
;
2398 EventRing
->EventRingEnqueue
= (TRB_TEMPLATE
*) EventRing
->EventRingSeg0
;
2401 // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
2402 // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.
2404 EventRing
->EventRingCCS
= 1;
2406 Size
= sizeof (EVENT_RING_SEG_TABLE_ENTRY
) * ERST_NUMBER
;
2407 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, Size
);
2408 ASSERT (Buf
!= NULL
);
2409 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
2410 ZeroMem (Buf
, Size
);
2412 ERSTBase
= (EVENT_RING_SEG_TABLE_ENTRY
*) Buf
;
2413 EventRing
->ERSTBase
= ERSTBase
;
2414 ERSTBase
->PtrLo
= XHC_LOW_32BIT (DequeuePhy
);
2415 ERSTBase
->PtrHi
= XHC_HIGH_32BIT (DequeuePhy
);
2416 ERSTBase
->RingTrbSize
= EVENT_RING_TRB_NUMBER
;
2418 ERSTPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Buf
, Size
);
2421 // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)
2423 XhcPeiWriteRuntimeReg (
2429 // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)
2431 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
2432 // So divide it to two 32-bytes width register access.
2434 XhcPeiWriteRuntimeReg (
2437 XHC_LOW_32BIT ((UINT64
) (UINTN
) DequeuePhy
)
2439 XhcPeiWriteRuntimeReg (
2441 XHC_ERDP_OFFSET
+ 4,
2442 XHC_HIGH_32BIT ((UINT64
) (UINTN
) DequeuePhy
)
2445 // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register (5.5.2.3.2)
2447 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
2448 // So divide it to two 32-bytes width register access.
2450 XhcPeiWriteRuntimeReg (
2453 XHC_LOW_32BIT ((UINT64
) (UINTN
) ERSTPhy
)
2455 XhcPeiWriteRuntimeReg (
2457 XHC_ERSTBA_OFFSET
+ 4,
2458 XHC_HIGH_32BIT ((UINT64
) (UINTN
) ERSTPhy
)
2461 // Need set IMAN IE bit to enable the ring interrupt
2463 XhcPeiSetRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
, XHC_IMAN_IE
);
2467 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
2469 @param Xhc The XHCI device.
2470 @param TrsRing The transfer ring to sync.
2472 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
2477 IN PEI_XHC_DEV
*Xhc
,
2478 IN TRANSFER_RING
*TrsRing
2482 TRB_TEMPLATE
*TrsTrb
;
2484 ASSERT (TrsRing
!= NULL
);
2486 // Calculate the latest RingEnqueue and RingPCS
2488 TrsTrb
= TrsRing
->RingEnqueue
;
2489 ASSERT (TrsTrb
!= NULL
);
2491 for (Index
= 0; Index
< TrsRing
->TrbNumber
; Index
++) {
2492 if (TrsTrb
->CycleBit
!= (TrsRing
->RingPCS
& BIT0
)) {
2496 if ((UINT8
) TrsTrb
->Type
== TRB_TYPE_LINK
) {
2497 ASSERT (((LINK_TRB
*) TrsTrb
)->TC
!= 0);
2499 // set cycle bit in Link TRB as normal
2501 ((LINK_TRB
*)TrsTrb
)->CycleBit
= TrsRing
->RingPCS
& BIT0
;
2503 // Toggle PCS maintained by software
2505 TrsRing
->RingPCS
= (TrsRing
->RingPCS
& BIT0
) ? 0 : 1;
2506 TrsTrb
= (TRB_TEMPLATE
*) TrsRing
->RingSeg0
; // Use host address
2510 ASSERT (Index
!= TrsRing
->TrbNumber
);
2512 if (TrsTrb
!= TrsRing
->RingEnqueue
) {
2513 TrsRing
->RingEnqueue
= TrsTrb
;
2517 // Clear the Trb context for enqueue, but reserve the PCS bit
2519 TrsTrb
->Parameter1
= 0;
2520 TrsTrb
->Parameter2
= 0;
2524 TrsTrb
->Control
= 0;
2530 Create XHCI transfer ring.
2532 @param Xhc The XHCI Device.
2533 @param TrbNum The number of TRB in the ring.
2534 @param TransferRing The created transfer ring.
2538 XhcPeiCreateTransferRing (
2539 IN PEI_XHC_DEV
*Xhc
,
2541 OUT TRANSFER_RING
*TransferRing
2546 EFI_PHYSICAL_ADDRESS PhyAddr
;
2548 Buf
= UsbHcAllocateMem (Xhc
->MemPool
, sizeof (TRB_TEMPLATE
) * TrbNum
);
2549 ASSERT (Buf
!= NULL
);
2550 ASSERT (((UINTN
) Buf
& 0x3F) == 0);
2551 ZeroMem (Buf
, sizeof (TRB_TEMPLATE
) * TrbNum
);
2553 TransferRing
->RingSeg0
= Buf
;
2554 TransferRing
->TrbNumber
= TrbNum
;
2555 TransferRing
->RingEnqueue
= (TRB_TEMPLATE
*) TransferRing
->RingSeg0
;
2556 TransferRing
->RingDequeue
= (TRB_TEMPLATE
*) TransferRing
->RingSeg0
;
2557 TransferRing
->RingPCS
= 1;
2559 // 4.9.2 Transfer Ring Management
2560 // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to
2561 // point to the first TRB in the ring.
2563 EndTrb
= (LINK_TRB
*) ((UINTN
) Buf
+ sizeof (TRB_TEMPLATE
) * (TrbNum
- 1));
2564 EndTrb
->Type
= TRB_TYPE_LINK
;
2565 PhyAddr
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Buf
, sizeof (TRB_TEMPLATE
) * TrbNum
);
2566 EndTrb
->PtrLo
= XHC_LOW_32BIT (PhyAddr
);
2567 EndTrb
->PtrHi
= XHC_HIGH_32BIT (PhyAddr
);
2569 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
2573 // Set Cycle bit as other TRB PCS init value
2575 EndTrb
->CycleBit
= 0;
2579 Initialize the XHCI host controller for schedule.
2581 @param Xhc The XHCI device to be initialized.
2590 EFI_PHYSICAL_ADDRESS DcbaaPhy
;
2592 EFI_PHYSICAL_ADDRESS CmdRingPhy
;
2593 UINT32 MaxScratchpadBufs
;
2595 EFI_PHYSICAL_ADDRESS ScratchPhy
;
2596 UINT64
*ScratchEntry
;
2597 EFI_PHYSICAL_ADDRESS ScratchEntryPhy
;
2602 // Initialize memory management.
2604 Xhc
->MemPool
= UsbHcInitMemPool ();
2605 ASSERT (Xhc
->MemPool
!= NULL
);
2608 // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)
2609 // to enable the device slots that system software is going to use.
2611 Xhc
->MaxSlotsEn
= Xhc
->HcSParams1
.Data
.MaxSlots
;
2612 ASSERT (Xhc
->MaxSlotsEn
>= 1 && Xhc
->MaxSlotsEn
<= 255);
2613 XhcPeiWriteOpReg (Xhc
, XHC_CONFIG_OFFSET
, (XhcPeiReadOpReg (Xhc
, XHC_CONFIG_OFFSET
) & ~XHC_CONFIG_MASK
) | Xhc
->MaxSlotsEn
);
2616 // The Device Context Base Address Array entry associated with each allocated Device Slot
2617 // shall contain a 64-bit pointer to the base of the associated Device Context.
2618 // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.
2619 // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.
2621 Size
= (Xhc
->MaxSlotsEn
+ 1) * sizeof (UINT64
);
2622 Dcbaa
= UsbHcAllocateMem (Xhc
->MemPool
, Size
);
2623 ASSERT (Dcbaa
!= NULL
);
2626 // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.
2627 // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run
2628 // mode (Run/Stop(R/S) ='1').
2630 MaxScratchpadBufs
= ((Xhc
->HcSParams2
.Data
.ScratchBufHi
) << 5) | (Xhc
->HcSParams2
.Data
.ScratchBufLo
);
2631 Xhc
->MaxScratchpadBufs
= MaxScratchpadBufs
;
2632 ASSERT (MaxScratchpadBufs
<= 1023);
2633 if (MaxScratchpadBufs
!= 0) {
2635 // Allocate the buffer to record the host address for each entry
2637 ScratchEntry
= AllocateZeroPool (sizeof (UINT64
) * MaxScratchpadBufs
);
2638 ASSERT (ScratchEntry
!= NULL
);
2639 Xhc
->ScratchEntry
= ScratchEntry
;
2642 Status
= UsbHcAllocateAlignedPages (
2643 EFI_SIZE_TO_PAGES (MaxScratchpadBufs
* sizeof (UINT64
)),
2645 (VOID
**) &ScratchBuf
,
2648 ASSERT_EFI_ERROR (Status
);
2650 ZeroMem (ScratchBuf
, MaxScratchpadBufs
* sizeof (UINT64
));
2651 Xhc
->ScratchBuf
= ScratchBuf
;
2654 // Allocate each scratch buffer
2656 for (Index
= 0; Index
< MaxScratchpadBufs
; Index
++) {
2657 ScratchEntryPhy
= 0;
2658 Status
= UsbHcAllocateAlignedPages (
2659 EFI_SIZE_TO_PAGES (Xhc
->PageSize
),
2661 (VOID
**) &ScratchEntry
[Index
],
2664 ASSERT_EFI_ERROR (Status
);
2665 ZeroMem ((VOID
*) (UINTN
) ScratchEntry
[Index
], Xhc
->PageSize
);
2667 // Fill with the PCI device address
2669 *ScratchBuf
++ = ScratchEntryPhy
;
2672 // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the
2673 // Device Context Base Address Array points to the Scratchpad Buffer Array.
2675 *(UINT64
*) Dcbaa
= (UINT64
) (UINTN
) ScratchPhy
;
2679 // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with
2680 // a 64-bit address pointing to where the Device Context Base Address Array is located.
2682 Xhc
->DCBAA
= (UINT64
*) (UINTN
) Dcbaa
;
2684 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
2685 // So divide it to two 32-bytes width register access.
2687 DcbaaPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Dcbaa
, Size
);
2688 XhcPeiWriteOpReg (Xhc
, XHC_DCBAAP_OFFSET
, XHC_LOW_32BIT (DcbaaPhy
));
2689 XhcPeiWriteOpReg (Xhc
, XHC_DCBAAP_OFFSET
+ 4, XHC_HIGH_32BIT (DcbaaPhy
));
2691 DEBUG ((EFI_D_INFO
, "XhcPeiInitSched:DCBAA=0x%x\n", Xhc
->DCBAA
));
2694 // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register
2695 // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.
2696 // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall
2699 XhcPeiCreateTransferRing (Xhc
, CMD_RING_TRB_NUMBER
, &Xhc
->CmdRing
);
2701 // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a
2702 // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.
2703 // So we set RCS as inverted PCS init value to let Command Ring empty
2705 CmdRingPhy
= UsbHcGetPciAddrForHostAddr (Xhc
->MemPool
, Xhc
->CmdRing
.RingSeg0
, sizeof (TRB_TEMPLATE
) * CMD_RING_TRB_NUMBER
);
2706 ASSERT ((CmdRingPhy
& 0x3F) == 0);
2707 CmdRingPhy
|= XHC_CRCR_RCS
;
2709 // Some 3rd party XHCI external cards don't support single 64-bytes width register access,
2710 // So divide it to two 32-bytes width register access.
2712 XhcPeiWriteOpReg (Xhc
, XHC_CRCR_OFFSET
, XHC_LOW_32BIT (CmdRingPhy
));
2713 XhcPeiWriteOpReg (Xhc
, XHC_CRCR_OFFSET
+ 4, XHC_HIGH_32BIT (CmdRingPhy
));
2715 DEBUG ((EFI_D_INFO
, "XhcPeiInitSched:XHC_CRCR=0x%x\n", Xhc
->CmdRing
.RingSeg0
));
2718 // Disable the 'interrupter enable' bit in USB_CMD
2719 // and clear IE & IP bit in all Interrupter X Management Registers.
2721 XhcPeiClearOpRegBit (Xhc
, XHC_USBCMD_OFFSET
, XHC_USBCMD_INTE
);
2722 for (Index
= 0; Index
< (UINT16
)(Xhc
->HcSParams1
.Data
.MaxIntrs
); Index
++) {
2723 XhcPeiClearRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
+ (Index
* 32), XHC_IMAN_IE
);
2724 XhcPeiSetRuntimeRegBit (Xhc
, XHC_IMAN_OFFSET
+ (Index
* 32), XHC_IMAN_IP
);
2728 // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
2730 XhcPeiCreateEventRing (Xhc
, &Xhc
->EventRing
);
2731 DEBUG ((EFI_D_INFO
, "XhcPeiInitSched:XHC_EVENTRING=0x%x\n", Xhc
->EventRing
.EventRingSeg0
));
2735 Free the resouce allocated at initializing schedule.
2737 @param Xhc The XHCI device.
2746 UINT64
*ScratchEntry
;
2748 if (Xhc
->ScratchBuf
!= NULL
) {
2749 ScratchEntry
= Xhc
->ScratchEntry
;
2750 for (Index
= 0; Index
< Xhc
->MaxScratchpadBufs
; Index
++) {
2752 // Free Scratchpad Buffers
2754 UsbHcFreeAlignedPages ((VOID
*) (UINTN
) ScratchEntry
[Index
], EFI_SIZE_TO_PAGES (Xhc
->PageSize
));
2757 // Free Scratchpad Buffer Array
2759 UsbHcFreeAlignedPages (Xhc
->ScratchBuf
, EFI_SIZE_TO_PAGES (Xhc
->MaxScratchpadBufs
* sizeof (UINT64
)));
2760 FreePool (Xhc
->ScratchEntry
);
2763 if (Xhc
->CmdRing
.RingSeg0
!= NULL
) {
2764 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->CmdRing
.RingSeg0
, sizeof (TRB_TEMPLATE
) * CMD_RING_TRB_NUMBER
);
2765 Xhc
->CmdRing
.RingSeg0
= NULL
;
2768 XhcPeiFreeEventRing (Xhc
,&Xhc
->EventRing
);
2770 if (Xhc
->DCBAA
!= NULL
) {
2771 UsbHcFreeMem (Xhc
->MemPool
, Xhc
->DCBAA
, (Xhc
->MaxSlotsEn
+ 1) * sizeof (UINT64
));
2776 // Free memory pool at last
2778 if (Xhc
->MemPool
!= NULL
) {
2779 UsbHcFreeMemPool (Xhc
->MemPool
);
2780 Xhc
->MemPool
= NULL
;