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MdeModulePkg XhciPei/UsbBusPei: Add XHCI recovery support.
[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhciSched.h
1 /** @file
2 Private Header file for Usb Host Controller PEIM
3
4 Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
5
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions
8 of the BSD License which accompanies this distribution. The
9 full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _EFI_PEI_XHCI_SCHED_H_
18 #define _EFI_PEI_XHCI_SCHED_H_
19
20 //
21 // Transfer types, used in URB to identify the transfer type
22 //
23 #define XHC_CTRL_TRANSFER 0x01
24 #define XHC_BULK_TRANSFER 0x02
25
26 //
27 // 6.4.6 TRB Types
28 //
29 #define TRB_TYPE_NORMAL 1
30 #define TRB_TYPE_SETUP_STAGE 2
31 #define TRB_TYPE_DATA_STAGE 3
32 #define TRB_TYPE_STATUS_STAGE 4
33 #define TRB_TYPE_ISOCH 5
34 #define TRB_TYPE_LINK 6
35 #define TRB_TYPE_EVENT_DATA 7
36 #define TRB_TYPE_NO_OP 8
37 #define TRB_TYPE_EN_SLOT 9
38 #define TRB_TYPE_DIS_SLOT 10
39 #define TRB_TYPE_ADDRESS_DEV 11
40 #define TRB_TYPE_CON_ENDPOINT 12
41 #define TRB_TYPE_EVALU_CONTXT 13
42 #define TRB_TYPE_RESET_ENDPOINT 14
43 #define TRB_TYPE_STOP_ENDPOINT 15
44 #define TRB_TYPE_SET_TR_DEQUE 16
45 #define TRB_TYPE_RESET_DEV 17
46 #define TRB_TYPE_GET_PORT_BANW 21
47 #define TRB_TYPE_FORCE_HEADER 22
48 #define TRB_TYPE_NO_OP_COMMAND 23
49 #define TRB_TYPE_TRANS_EVENT 32
50 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
51 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
52 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
53 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
54 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
55
56 //
57 // Endpoint Type (EP Type).
58 //
59 #define ED_NOT_VALID 0
60 #define ED_ISOCH_OUT 1
61 #define ED_BULK_OUT 2
62 #define ED_INTERRUPT_OUT 3
63 #define ED_CONTROL_BIDIR 4
64 #define ED_ISOCH_IN 5
65 #define ED_BULK_IN 6
66 #define ED_INTERRUPT_IN 7
67
68 //
69 // 6.4.5 TRB Completion Codes
70 //
71 #define TRB_COMPLETION_INVALID 0
72 #define TRB_COMPLETION_SUCCESS 1
73 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
74 #define TRB_COMPLETION_BABBLE_ERROR 3
75 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
76 #define TRB_COMPLETION_TRB_ERROR 5
77 #define TRB_COMPLETION_STALL_ERROR 6
78 #define TRB_COMPLETION_SHORT_PACKET 13
79
80 //
81 // The topology string used to present usb device location
82 //
83 typedef struct _USB_DEV_TOPOLOGY {
84 //
85 // The tier concatenation of down stream port.
86 //
87 UINT32 RouteString:20;
88 //
89 // The root port number of the chain.
90 //
91 UINT32 RootPortNum:8;
92 //
93 // The Tier the device reside.
94 //
95 UINT32 TierNum:4;
96 } USB_DEV_TOPOLOGY;
97
98 //
99 // USB Device's RouteChart
100 //
101 typedef union _USB_DEV_ROUTE {
102 UINT32 Dword;
103 USB_DEV_TOPOLOGY Route;
104 } USB_DEV_ROUTE;
105
106 //
107 // Endpoint address and its capabilities
108 //
109 typedef struct _USB_ENDPOINT {
110 //
111 // Store logical device address assigned by UsbBus
112 // It's because some XHCI host controllers may assign the same physcial device
113 // address for those devices inserted at different root port.
114 //
115 UINT8 BusAddr;
116 UINT8 DevAddr;
117 UINT8 EpAddr;
118 EFI_USB_DATA_DIRECTION Direction;
119 UINT8 DevSpeed;
120 UINTN MaxPacket;
121 UINTN Type;
122 } USB_ENDPOINT;
123
124 //
125 // TRB Template
126 //
127 typedef struct _TRB_TEMPLATE {
128 UINT32 Parameter1;
129
130 UINT32 Parameter2;
131
132 UINT32 Status;
133
134 UINT32 CycleBit:1;
135 UINT32 RsvdZ1:9;
136 UINT32 Type:6;
137 UINT32 Control:16;
138 } TRB_TEMPLATE;
139
140 typedef struct _TRANSFER_RING {
141 VOID *RingSeg0;
142 UINTN TrbNumber;
143 TRB_TEMPLATE *RingEnqueue;
144 TRB_TEMPLATE *RingDequeue;
145 UINT32 RingPCS;
146 } TRANSFER_RING;
147
148 typedef struct _EVENT_RING {
149 VOID *ERSTBase;
150 VOID *EventRingSeg0;
151 UINTN TrbNumber;
152 TRB_TEMPLATE *EventRingEnqueue;
153 TRB_TEMPLATE *EventRingDequeue;
154 UINT32 EventRingCCS;
155 } EVENT_RING;
156
157 #define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
158
159 //
160 // URB (Usb Request Block) contains information for all kinds of
161 // usb requests.
162 //
163 typedef struct _URB {
164 UINT32 Signature;
165 //
166 // Usb Device URB related information
167 //
168 USB_ENDPOINT Ep;
169 EFI_USB_DEVICE_REQUEST *Request;
170 VOID *Data;
171 UINTN DataLen;
172 VOID *DataPhy;
173 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
174 VOID *Context;
175 //
176 // Execute result
177 //
178 UINT32 Result;
179 //
180 // completed data length
181 //
182 UINTN Completed;
183 //
184 // Command/Tranfer Ring info
185 //
186 TRANSFER_RING *Ring;
187 TRB_TEMPLATE *TrbStart;
188 TRB_TEMPLATE *TrbEnd;
189 UINTN TrbNum;
190 BOOLEAN StartDone;
191 BOOLEAN EndDone;
192 BOOLEAN Finished;
193
194 TRB_TEMPLATE *EvtTrb;
195 } URB;
196
197 //
198 // 6.5 Event Ring Segment Table
199 // The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime
200 // expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the
201 // Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table
202 // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
203 //
204 typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
205 UINT32 PtrLo;
206 UINT32 PtrHi;
207 UINT32 RingTrbSize:16;
208 UINT32 RsvdZ1:16;
209 UINT32 RsvdZ2;
210 } EVENT_RING_SEG_TABLE_ENTRY;
211
212 //
213 // 6.4.1.1 Normal TRB
214 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
215 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
216 // Rings, and to define the Data stage information for Control Transfer Rings.
217 //
218 typedef struct _TRANSFER_TRB_NORMAL {
219 UINT32 TRBPtrLo;
220
221 UINT32 TRBPtrHi;
222
223 UINT32 Length:17;
224 UINT32 TDSize:5;
225 UINT32 IntTarget:10;
226
227 UINT32 CycleBit:1;
228 UINT32 ENT:1;
229 UINT32 ISP:1;
230 UINT32 NS:1;
231 UINT32 CH:1;
232 UINT32 IOC:1;
233 UINT32 IDT:1;
234 UINT32 RsvdZ1:2;
235 UINT32 BEI:1;
236 UINT32 Type:6;
237 UINT32 RsvdZ2:16;
238 } TRANSFER_TRB_NORMAL;
239
240 //
241 // 6.4.1.2.1 Setup Stage TRB
242 // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
243 //
244 typedef struct _TRANSFER_TRB_CONTROL_SETUP {
245 UINT32 bmRequestType:8;
246 UINT32 bRequest:8;
247 UINT32 wValue:16;
248
249 UINT32 wIndex:16;
250 UINT32 wLength:16;
251
252 UINT32 Length:17;
253 UINT32 RsvdZ1:5;
254 UINT32 IntTarget:10;
255
256 UINT32 CycleBit:1;
257 UINT32 RsvdZ2:4;
258 UINT32 IOC:1;
259 UINT32 IDT:1;
260 UINT32 RsvdZ3:3;
261 UINT32 Type:6;
262 UINT32 TRT:2;
263 UINT32 RsvdZ4:14;
264 } TRANSFER_TRB_CONTROL_SETUP;
265
266 //
267 // 6.4.1.2.2 Data Stage TRB
268 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
269 //
270 typedef struct _TRANSFER_TRB_CONTROL_DATA {
271 UINT32 TRBPtrLo;
272
273 UINT32 TRBPtrHi;
274
275 UINT32 Length:17;
276 UINT32 TDSize:5;
277 UINT32 IntTarget:10;
278
279 UINT32 CycleBit:1;
280 UINT32 ENT:1;
281 UINT32 ISP:1;
282 UINT32 NS:1;
283 UINT32 CH:1;
284 UINT32 IOC:1;
285 UINT32 IDT:1;
286 UINT32 RsvdZ1:3;
287 UINT32 Type:6;
288 UINT32 DIR:1;
289 UINT32 RsvdZ2:15;
290 } TRANSFER_TRB_CONTROL_DATA;
291
292 //
293 // 6.4.1.2.2 Data Stage TRB
294 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
295 //
296 typedef struct _TRANSFER_TRB_CONTROL_STATUS {
297 UINT32 RsvdZ1;
298 UINT32 RsvdZ2;
299
300 UINT32 RsvdZ3:22;
301 UINT32 IntTarget:10;
302
303 UINT32 CycleBit:1;
304 UINT32 ENT:1;
305 UINT32 RsvdZ4:2;
306 UINT32 CH:1;
307 UINT32 IOC:1;
308 UINT32 RsvdZ5:4;
309 UINT32 Type:6;
310 UINT32 DIR:1;
311 UINT32 RsvdZ6:15;
312 } TRANSFER_TRB_CONTROL_STATUS;
313
314 //
315 // 6.4.2.1 Transfer Event TRB
316 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
317 // for more information on the use and operation of Transfer Events.
318 //
319 typedef struct _EVT_TRB_TRANSFER {
320 UINT32 TRBPtrLo;
321
322 UINT32 TRBPtrHi;
323
324 UINT32 Length:24;
325 UINT32 Completecode:8;
326
327 UINT32 CycleBit:1;
328 UINT32 RsvdZ1:1;
329 UINT32 ED:1;
330 UINT32 RsvdZ2:7;
331 UINT32 Type:6;
332 UINT32 EndpointId:5;
333 UINT32 RsvdZ3:3;
334 UINT32 SlotId:8;
335 } EVT_TRB_TRANSFER;
336
337 //
338 // 6.4.2.2 Command Completion Event TRB
339 // A Command Completion Event TRB shall be generated by the xHC when a command completes on the
340 // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
341 //
342 typedef struct _EVT_TRB_COMMAND_COMPLETION {
343 UINT32 TRBPtrLo;
344
345 UINT32 TRBPtrHi;
346
347 UINT32 RsvdZ2:24;
348 UINT32 Completecode:8;
349
350 UINT32 CycleBit:1;
351 UINT32 RsvdZ3:9;
352 UINT32 Type:6;
353 UINT32 VFID:8;
354 UINT32 SlotId:8;
355 } EVT_TRB_COMMAND_COMPLETION;
356
357 typedef union _TRB {
358 TRB_TEMPLATE TrbTemplate;
359 TRANSFER_TRB_NORMAL TrbNormal;
360 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
361 TRANSFER_TRB_CONTROL_DATA TrbCtrData;
362 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
363 } TRB;
364
365 //
366 // 6.4.3.1 No Op Command TRB
367 // The No Op Command TRB provides a simple means for verifying the operation of the Command Ring
368 // mechanisms offered by the xHCI.
369 //
370 typedef struct _CMD_TRB_NO_OP {
371 UINT32 RsvdZ0;
372 UINT32 RsvdZ1;
373 UINT32 RsvdZ2;
374
375 UINT32 CycleBit:1;
376 UINT32 RsvdZ3:9;
377 UINT32 Type:6;
378 UINT32 RsvdZ4:16;
379 } CMD_TRB_NO_OP;
380
381 //
382 // 6.4.3.2 Enable Slot Command TRB
383 // The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the
384 // selected slot to the host in a Command Completion Event.
385 //
386 typedef struct _CMD_TRB_ENABLE_SLOT {
387 UINT32 RsvdZ0;
388 UINT32 RsvdZ1;
389 UINT32 RsvdZ2;
390
391 UINT32 CycleBit:1;
392 UINT32 RsvdZ3:9;
393 UINT32 Type:6;
394 UINT32 RsvdZ4:16;
395 } CMD_TRB_ENABLE_SLOT;
396
397 //
398 // 6.4.3.3 Disable Slot Command TRB
399 // The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any
400 // internal xHC resources assigned to the slot.
401 //
402 typedef struct _CMD_TRB_DISABLE_SLOT {
403 UINT32 RsvdZ0;
404 UINT32 RsvdZ1;
405 UINT32 RsvdZ2;
406
407 UINT32 CycleBit:1;
408 UINT32 RsvdZ3:9;
409 UINT32 Type:6;
410 UINT32 RsvdZ4:8;
411 UINT32 SlotId:8;
412 } CMD_TRB_DISABLE_SLOT;
413
414 //
415 // 6.4.3.4 Address Device Command TRB
416 // The Address Device Command TRB transitions the selected Device Context from the Default to the
417 // Addressed state and causes the xHC to select an address for the USB device in the Default State and
418 // issue a SET_ADDRESS request to the USB device.
419 //
420 typedef struct _CMD_TRB_ADDRESS_DEVICE {
421 UINT32 PtrLo;
422
423 UINT32 PtrHi;
424
425 UINT32 RsvdZ1;
426
427 UINT32 CycleBit:1;
428 UINT32 RsvdZ2:8;
429 UINT32 BSR:1;
430 UINT32 Type:6;
431 UINT32 RsvdZ3:8;
432 UINT32 SlotId:8;
433 } CMD_TRB_ADDRESS_DEVICE;
434
435 //
436 // 6.4.3.5 Configure Endpoint Command TRB
437 // The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the
438 // endpoints selected by the command.
439 //
440 typedef struct _CMD_TRB_CONFIG_ENDPOINT {
441 UINT32 PtrLo;
442
443 UINT32 PtrHi;
444
445 UINT32 RsvdZ1;
446
447 UINT32 CycleBit:1;
448 UINT32 RsvdZ2:8;
449 UINT32 DC:1;
450 UINT32 Type:6;
451 UINT32 RsvdZ3:8;
452 UINT32 SlotId:8;
453 } CMD_TRB_CONFIG_ENDPOINT;
454
455 //
456 // 6.4.3.6 Evaluate Context Command TRB
457 // The Evaluate Context Command TRB is used by system software to inform the xHC that the selected
458 // Context data structures in the Device Context have been modified by system software and that the xHC
459 // shall evaluate any changes
460 //
461 typedef struct _CMD_TRB_EVALUATE_CONTEXT {
462 UINT32 PtrLo;
463
464 UINT32 PtrHi;
465
466 UINT32 RsvdZ1;
467
468 UINT32 CycleBit:1;
469 UINT32 RsvdZ2:9;
470 UINT32 Type:6;
471 UINT32 RsvdZ3:8;
472 UINT32 SlotId:8;
473 } CMD_TRB_EVALUATE_CONTEXT;
474
475 //
476 // 6.4.3.7 Reset Endpoint Command TRB
477 // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
478 //
479 typedef struct _CMD_TRB_RESET_ENDPOINT {
480 UINT32 RsvdZ0;
481 UINT32 RsvdZ1;
482 UINT32 RsvdZ2;
483
484 UINT32 CycleBit:1;
485 UINT32 RsvdZ3:8;
486 UINT32 TSP:1;
487 UINT32 Type:6;
488 UINT32 EDID:5;
489 UINT32 RsvdZ4:3;
490 UINT32 SlotId:8;
491 } CMD_TRB_RESET_ENDPOINT;
492
493 //
494 // 6.4.3.8 Stop Endpoint Command TRB
495 // The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a
496 // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
497 //
498 typedef struct _CMD_TRB_STOP_ENDPOINT {
499 UINT32 RsvdZ0;
500 UINT32 RsvdZ1;
501 UINT32 RsvdZ2;
502
503 UINT32 CycleBit:1;
504 UINT32 RsvdZ3:9;
505 UINT32 Type:6;
506 UINT32 EDID:5;
507 UINT32 RsvdZ4:2;
508 UINT32 SP:1;
509 UINT32 SlotId:8;
510 } CMD_TRB_STOP_ENDPOINT;
511
512 //
513 // 6.4.3.9 Set TR Dequeue Pointer Command TRB
514 // The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue
515 // Pointer and DCS fields of an Endpoint or Stream Context.
516 //
517 typedef struct _CMD_SET_TR_DEQ_POINTER {
518 UINT32 PtrLo;
519
520 UINT32 PtrHi;
521
522 UINT32 RsvdZ1:16;
523 UINT32 StreamID:16;
524
525 UINT32 CycleBit:1;
526 UINT32 RsvdZ2:9;
527 UINT32 Type:6;
528 UINT32 Endpoint:5;
529 UINT32 RsvdZ3:3;
530 UINT32 SlotId:8;
531 } CMD_SET_TR_DEQ_POINTER;
532
533 //
534 // 6.4.4.1 Link TRB
535 // A Link TRB provides support for non-contiguous TRB Rings.
536 //
537 typedef struct _LINK_TRB {
538 UINT32 PtrLo;
539
540 UINT32 PtrHi;
541
542 UINT32 RsvdZ1:22;
543 UINT32 InterTarget:10;
544
545 UINT32 CycleBit:1;
546 UINT32 TC:1;
547 UINT32 RsvdZ2:2;
548 UINT32 CH:1;
549 UINT32 IOC:1;
550 UINT32 RsvdZ3:4;
551 UINT32 Type:6;
552 UINT32 RsvdZ4:16;
553 } LINK_TRB;
554
555 //
556 // 6.2.2 Slot Context
557 //
558 typedef struct _SLOT_CONTEXT {
559 UINT32 RouteString:20;
560 UINT32 Speed:4;
561 UINT32 RsvdZ1:1;
562 UINT32 MTT:1;
563 UINT32 Hub:1;
564 UINT32 ContextEntries:5;
565
566 UINT32 MaxExitLatency:16;
567 UINT32 RootHubPortNum:8;
568 UINT32 PortNum:8;
569
570 UINT32 TTHubSlotId:8;
571 UINT32 TTPortNum:8;
572 UINT32 TTT:2;
573 UINT32 RsvdZ2:4;
574 UINT32 InterTarget:10;
575
576 UINT32 DeviceAddress:8;
577 UINT32 RsvdZ3:19;
578 UINT32 SlotState:5;
579
580 UINT32 RsvdZ4;
581 UINT32 RsvdZ5;
582 UINT32 RsvdZ6;
583 UINT32 RsvdZ7;
584 } SLOT_CONTEXT;
585
586 typedef struct _SLOT_CONTEXT_64 {
587 UINT32 RouteString:20;
588 UINT32 Speed:4;
589 UINT32 RsvdZ1:1;
590 UINT32 MTT:1;
591 UINT32 Hub:1;
592 UINT32 ContextEntries:5;
593
594 UINT32 MaxExitLatency:16;
595 UINT32 RootHubPortNum:8;
596 UINT32 PortNum:8;
597
598 UINT32 TTHubSlotId:8;
599 UINT32 TTPortNum:8;
600 UINT32 TTT:2;
601 UINT32 RsvdZ2:4;
602 UINT32 InterTarget:10;
603
604 UINT32 DeviceAddress:8;
605 UINT32 RsvdZ3:19;
606 UINT32 SlotState:5;
607
608 UINT32 RsvdZ4;
609 UINT32 RsvdZ5;
610 UINT32 RsvdZ6;
611 UINT32 RsvdZ7;
612
613 UINT32 RsvdZ8;
614 UINT32 RsvdZ9;
615 UINT32 RsvdZ10;
616 UINT32 RsvdZ11;
617
618 UINT32 RsvdZ12;
619 UINT32 RsvdZ13;
620 UINT32 RsvdZ14;
621 UINT32 RsvdZ15;
622
623 } SLOT_CONTEXT_64;
624
625
626 //
627 // 6.2.3 Endpoint Context
628 //
629 typedef struct _ENDPOINT_CONTEXT {
630 UINT32 EPState:3;
631 UINT32 RsvdZ1:5;
632 UINT32 Mult:2;
633 UINT32 MaxPStreams:5;
634 UINT32 LSA:1;
635 UINT32 Interval:8;
636 UINT32 RsvdZ2:8;
637
638 UINT32 RsvdZ3:1;
639 UINT32 CErr:2;
640 UINT32 EPType:3;
641 UINT32 RsvdZ4:1;
642 UINT32 HID:1;
643 UINT32 MaxBurstSize:8;
644 UINT32 MaxPacketSize:16;
645
646 UINT32 PtrLo;
647
648 UINT32 PtrHi;
649
650 UINT32 AverageTRBLength:16;
651 UINT32 MaxESITPayload:16;
652
653 UINT32 RsvdZ5;
654 UINT32 RsvdZ6;
655 UINT32 RsvdZ7;
656 } ENDPOINT_CONTEXT;
657
658 typedef struct _ENDPOINT_CONTEXT_64 {
659 UINT32 EPState:3;
660 UINT32 RsvdZ1:5;
661 UINT32 Mult:2;
662 UINT32 MaxPStreams:5;
663 UINT32 LSA:1;
664 UINT32 Interval:8;
665 UINT32 RsvdZ2:8;
666
667 UINT32 RsvdZ3:1;
668 UINT32 CErr:2;
669 UINT32 EPType:3;
670 UINT32 RsvdZ4:1;
671 UINT32 HID:1;
672 UINT32 MaxBurstSize:8;
673 UINT32 MaxPacketSize:16;
674
675 UINT32 PtrLo;
676
677 UINT32 PtrHi;
678
679 UINT32 AverageTRBLength:16;
680 UINT32 MaxESITPayload:16;
681
682 UINT32 RsvdZ5;
683 UINT32 RsvdZ6;
684 UINT32 RsvdZ7;
685
686 UINT32 RsvdZ8;
687 UINT32 RsvdZ9;
688 UINT32 RsvdZ10;
689 UINT32 RsvdZ11;
690
691 UINT32 RsvdZ12;
692 UINT32 RsvdZ13;
693 UINT32 RsvdZ14;
694 UINT32 RsvdZ15;
695
696 } ENDPOINT_CONTEXT_64;
697
698
699 //
700 // 6.2.5.1 Input Control Context
701 //
702 typedef struct _INPUT_CONTRL_CONTEXT {
703 UINT32 Dword1;
704 UINT32 Dword2;
705 UINT32 RsvdZ1;
706 UINT32 RsvdZ2;
707 UINT32 RsvdZ3;
708 UINT32 RsvdZ4;
709 UINT32 RsvdZ5;
710 UINT32 RsvdZ6;
711 } INPUT_CONTRL_CONTEXT;
712
713 typedef struct _INPUT_CONTRL_CONTEXT_64 {
714 UINT32 Dword1;
715 UINT32 Dword2;
716 UINT32 RsvdZ1;
717 UINT32 RsvdZ2;
718 UINT32 RsvdZ3;
719 UINT32 RsvdZ4;
720 UINT32 RsvdZ5;
721 UINT32 RsvdZ6;
722 UINT32 RsvdZ7;
723 UINT32 RsvdZ8;
724 UINT32 RsvdZ9;
725 UINT32 RsvdZ10;
726 UINT32 RsvdZ11;
727 UINT32 RsvdZ12;
728 UINT32 RsvdZ13;
729 UINT32 RsvdZ14;
730 } INPUT_CONTRL_CONTEXT_64;
731
732 //
733 // 6.2.1 Device Context
734 //
735 typedef struct _DEVICE_CONTEXT {
736 SLOT_CONTEXT Slot;
737 ENDPOINT_CONTEXT EP[31];
738 } DEVICE_CONTEXT;
739
740 typedef struct _DEVICE_CONTEXT_64 {
741 SLOT_CONTEXT_64 Slot;
742 ENDPOINT_CONTEXT_64 EP[31];
743 } DEVICE_CONTEXT_64;
744
745 //
746 // 6.2.5 Input Context
747 //
748 typedef struct _INPUT_CONTEXT {
749 INPUT_CONTRL_CONTEXT InputControlContext;
750 SLOT_CONTEXT Slot;
751 ENDPOINT_CONTEXT EP[31];
752 } INPUT_CONTEXT;
753
754 typedef struct _INPUT_CONTEXT_64 {
755 INPUT_CONTRL_CONTEXT_64 InputControlContext;
756 SLOT_CONTEXT_64 Slot;
757 ENDPOINT_CONTEXT_64 EP[31];
758 } INPUT_CONTEXT_64;
759
760 /**
761 Execute the transfer by polling the URB. This is a synchronous operation.
762
763 @param Xhc The XHCI device.
764 @param CmdTransfer The executed URB is for cmd transfer or not.
765 @param Urb The URB to execute.
766 @param Timeout The time to wait before abort, in millisecond.
767
768 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
769 @return EFI_TIMEOUT The transfer failed due to time out.
770 @return EFI_SUCCESS The transfer finished OK.
771
772 **/
773 EFI_STATUS
774 XhcPeiExecTransfer (
775 IN PEI_XHC_DEV *Xhc,
776 IN BOOLEAN CmdTransfer,
777 IN URB *Urb,
778 IN UINTN Timeout
779 );
780
781 /**
782 Find out the actual device address according to the requested device address from UsbBus.
783
784 @param Xhc The XHCI device.
785 @param BusDevAddr The requested device address by UsbBus upper driver.
786
787 @return The actual device address assigned to the device.
788
789 **/
790 UINT8
791 XhcPeiBusDevAddrToSlotId (
792 IN PEI_XHC_DEV *Xhc,
793 IN UINT8 BusDevAddr
794 );
795
796 /**
797 Find out the slot id according to the device's route string.
798
799 @param Xhc The XHCI device.
800 @param RouteString The route string described the device location.
801
802 @return The slot id used by the device.
803
804 **/
805 UINT8
806 XhcPeiRouteStringToSlotId (
807 IN PEI_XHC_DEV *Xhc,
808 IN USB_DEV_ROUTE RouteString
809 );
810
811 /**
812 Calculate the device context index by endpoint address and direction.
813
814 @param EpAddr The target endpoint number.
815 @param Direction The direction of the target endpoint.
816
817 @return The device context index of endpoint.
818
819 **/
820 UINT8
821 XhcPeiEndpointToDci (
822 IN UINT8 EpAddr,
823 IN EFI_USB_DATA_DIRECTION Direction
824 );
825
826 /**
827 Ring the door bell to notify XHCI there is a transaction to be executed.
828
829 @param Xhc The XHCI device.
830 @param SlotId The slot id of the target device.
831 @param Dci The device context index of the target slot or endpoint.
832
833 **/
834 VOID
835 XhcPeiRingDoorBell (
836 IN PEI_XHC_DEV *Xhc,
837 IN UINT8 SlotId,
838 IN UINT8 Dci
839 );
840
841 /**
842 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
843
844 @param Xhc The XHCI device.
845 @param ParentRouteChart The route string pointed to the parent device if it exists.
846 @param Port The port to be polled.
847 @param PortState The port state.
848
849 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
850 @retval Others Should not appear.
851
852 **/
853 EFI_STATUS
854 XhcPeiPollPortStatusChange (
855 IN PEI_XHC_DEV *Xhc,
856 IN USB_DEV_ROUTE ParentRouteChart,
857 IN UINT8 Port,
858 IN EFI_USB_PORT_STATUS *PortState
859 );
860
861 /**
862 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
863
864 @param Xhc The XHCI device.
865 @param SlotId The slot id to be configured.
866 @param PortNum The total number of downstream port supported by the hub.
867 @param TTT The TT think time of the hub device.
868 @param MTT The multi-TT of the hub device.
869
870 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
871
872 **/
873 EFI_STATUS
874 XhcPeiConfigHubContext (
875 IN PEI_XHC_DEV *Xhc,
876 IN UINT8 SlotId,
877 IN UINT8 PortNum,
878 IN UINT8 TTT,
879 IN UINT8 MTT
880 );
881
882 /**
883 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
884
885 @param Xhc The XHCI device.
886 @param SlotId The slot id to be configured.
887 @param PortNum The total number of downstream port supported by the hub.
888 @param TTT The TT think time of the hub device.
889 @param MTT The multi-TT of the hub device.
890
891 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
892
893 **/
894 EFI_STATUS
895 XhcPeiConfigHubContext64 (
896 IN PEI_XHC_DEV *Xhc,
897 IN UINT8 SlotId,
898 IN UINT8 PortNum,
899 IN UINT8 TTT,
900 IN UINT8 MTT
901 );
902
903 /**
904 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
905
906 @param Xhc The XHCI device.
907 @param SlotId The slot id to be configured.
908 @param DeviceSpeed The device's speed.
909 @param ConfigDesc The pointer to the usb device configuration descriptor.
910
911 @retval EFI_SUCCESS Successfully configure all the device endpoints.
912
913 **/
914 EFI_STATUS
915 XhcPeiSetConfigCmd (
916 IN PEI_XHC_DEV *Xhc,
917 IN UINT8 SlotId,
918 IN UINT8 DeviceSpeed,
919 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
920 );
921
922 /**
923 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
924
925 @param Xhc The XHCI device.
926 @param SlotId The slot id to be configured.
927 @param DeviceSpeed The device's speed.
928 @param ConfigDesc The pointer to the usb device configuration descriptor.
929
930 @retval EFI_SUCCESS Successfully configure all the device endpoints.
931
932 **/
933 EFI_STATUS
934 XhcPeiSetConfigCmd64 (
935 IN PEI_XHC_DEV *Xhc,
936 IN UINT8 SlotId,
937 IN UINT8 DeviceSpeed,
938 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
939 );
940
941 /**
942 Assign and initialize the device slot for a new device.
943
944 @param Xhc The XHCI device.
945 @param ParentRouteChart The route string pointed to the parent device.
946 @param ParentPort The port at which the device is located.
947 @param RouteChart The route string pointed to the device.
948 @param DeviceSpeed The device speed.
949
950 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
951 @retval Others Fail to initialize device slot.
952
953 **/
954 EFI_STATUS
955 XhcPeiInitializeDeviceSlot (
956 IN PEI_XHC_DEV *Xhc,
957 IN USB_DEV_ROUTE ParentRouteChart,
958 IN UINT16 ParentPort,
959 IN USB_DEV_ROUTE RouteChart,
960 IN UINT8 DeviceSpeed
961 );
962
963 /**
964 Assign and initialize the device slot for a new device.
965
966 @param Xhc The XHCI device.
967 @param ParentRouteChart The route string pointed to the parent device.
968 @param ParentPort The port at which the device is located.
969 @param RouteChart The route string pointed to the device.
970 @param DeviceSpeed The device speed.
971
972 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
973 @retval Others Fail to initialize device slot.
974
975 **/
976 EFI_STATUS
977 XhcPeiInitializeDeviceSlot64 (
978 IN PEI_XHC_DEV *Xhc,
979 IN USB_DEV_ROUTE ParentRouteChart,
980 IN UINT16 ParentPort,
981 IN USB_DEV_ROUTE RouteChart,
982 IN UINT8 DeviceSpeed
983 );
984
985 /**
986 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
987
988 @param Xhc The XHCI device.
989 @param SlotId The slot id to be evaluated.
990 @param MaxPacketSize The max packet size supported by the device control transfer.
991
992 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
993
994 **/
995 EFI_STATUS
996 XhcPeiEvaluateContext (
997 IN PEI_XHC_DEV *Xhc,
998 IN UINT8 SlotId,
999 IN UINT32 MaxPacketSize
1000 );
1001
1002 /**
1003 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1004
1005 @param Xhc The XHCI device.
1006 @param SlotId The slot id to be evaluated.
1007 @param MaxPacketSize The max packet size supported by the device control transfer.
1008
1009 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1010
1011 **/
1012 EFI_STATUS
1013 XhcPeiEvaluateContext64 (
1014 IN PEI_XHC_DEV *Xhc,
1015 IN UINT8 SlotId,
1016 IN UINT32 MaxPacketSize
1017 );
1018
1019 /**
1020 Disable the specified device slot.
1021
1022 @param Xhc The XHCI device.
1023 @param SlotId The slot id to be disabled.
1024
1025 @retval EFI_SUCCESS Successfully disable the device slot.
1026
1027 **/
1028 EFI_STATUS
1029 XhcPeiDisableSlotCmd (
1030 IN PEI_XHC_DEV *Xhc,
1031 IN UINT8 SlotId
1032 );
1033
1034 /**
1035 Disable the specified device slot.
1036
1037 @param Xhc The XHCI device.
1038 @param SlotId The slot id to be disabled.
1039
1040 @retval EFI_SUCCESS Successfully disable the device slot.
1041
1042 **/
1043 EFI_STATUS
1044 XhcPeiDisableSlotCmd64 (
1045 IN PEI_XHC_DEV *Xhc,
1046 IN UINT8 SlotId
1047 );
1048
1049 /**
1050 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
1051 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
1052 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
1053 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
1054 Stopped to the Running state.
1055
1056 @param Xhc The XHCI device.
1057 @param Urb The urb which makes the endpoint halted.
1058
1059 @retval EFI_SUCCESS The recovery is successful.
1060 @retval Others Failed to recovery halted endpoint.
1061
1062 **/
1063 EFI_STATUS
1064 XhcPeiRecoverHaltedEndpoint (
1065 IN PEI_XHC_DEV *Xhc,
1066 IN URB *Urb
1067 );
1068
1069 /**
1070 Create a new URB for a new transaction.
1071
1072 @param Xhc The XHCI device
1073 @param DevAddr The device address
1074 @param EpAddr Endpoint addrress
1075 @param DevSpeed The device speed
1076 @param MaxPacket The max packet length of the endpoint
1077 @param Type The transaction type
1078 @param Request The standard USB request for control transfer
1079 @param Data The user data to transfer
1080 @param DataLen The length of data buffer
1081 @param Callback The function to call when data is transferred
1082 @param Context The context to the callback
1083
1084 @return Created URB or NULL
1085
1086 **/
1087 URB*
1088 XhcPeiCreateUrb (
1089 IN PEI_XHC_DEV *Xhc,
1090 IN UINT8 DevAddr,
1091 IN UINT8 EpAddr,
1092 IN UINT8 DevSpeed,
1093 IN UINTN MaxPacket,
1094 IN UINTN Type,
1095 IN EFI_USB_DEVICE_REQUEST *Request,
1096 IN VOID *Data,
1097 IN UINTN DataLen,
1098 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
1099 IN VOID *Context
1100 );
1101
1102 /**
1103 Free an allocated URB.
1104
1105 @param Xhc The XHCI device.
1106 @param Urb The URB to free.
1107
1108 **/
1109 VOID
1110 XhcPeiFreeUrb (
1111 IN PEI_XHC_DEV *Xhc,
1112 IN URB *Urb
1113 );
1114
1115 /**
1116 Create a transfer TRB.
1117
1118 @param Xhc The XHCI device
1119 @param Urb The urb used to construct the transfer TRB.
1120
1121 @return Created TRB or NULL
1122
1123 **/
1124 EFI_STATUS
1125 XhcPeiCreateTransferTrb (
1126 IN PEI_XHC_DEV *Xhc,
1127 IN URB *Urb
1128 );
1129
1130 /**
1131 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1132
1133 @param Xhc The XHCI device.
1134 @param TrsRing The transfer ring to sync.
1135
1136 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1137
1138 **/
1139 EFI_STATUS
1140 XhcPeiSyncTrsRing (
1141 IN PEI_XHC_DEV *Xhc,
1142 IN TRANSFER_RING *TrsRing
1143 );
1144
1145 /**
1146 Create XHCI transfer ring.
1147
1148 @param Xhc The XHCI Device.
1149 @param TrbNum The number of TRB in the ring.
1150 @param TransferRing The created transfer ring.
1151
1152 **/
1153 VOID
1154 XhcPeiCreateTransferRing (
1155 IN PEI_XHC_DEV *Xhc,
1156 IN UINTN TrbNum,
1157 OUT TRANSFER_RING *TransferRing
1158 );
1159
1160 /**
1161 Check if there is a new generated event.
1162
1163 @param Xhc The XHCI device.
1164 @param EvtRing The event ring to check.
1165 @param NewEvtTrb The new event TRB found.
1166
1167 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1168 @retval EFI_NOT_READY The event ring has no new event.
1169
1170 **/
1171 EFI_STATUS
1172 XhcPeiCheckNewEvent (
1173 IN PEI_XHC_DEV *Xhc,
1174 IN EVENT_RING *EvtRing,
1175 OUT TRB_TEMPLATE **NewEvtTrb
1176 );
1177
1178 /**
1179 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1180
1181 @param Xhc The XHCI device.
1182 @param EvtRing The event ring to sync.
1183
1184 @retval EFI_SUCCESS The event ring is synchronized successfully.
1185
1186 **/
1187 EFI_STATUS
1188 XhcPeiSyncEventRing (
1189 IN PEI_XHC_DEV *Xhc,
1190 IN EVENT_RING *EvtRing
1191 );
1192
1193 /**
1194 Create XHCI event ring.
1195
1196 @param Xhc The XHCI device.
1197 @param EventRing The created event ring.
1198
1199 **/
1200 VOID
1201 XhcPeiCreateEventRing (
1202 IN PEI_XHC_DEV *Xhc,
1203 OUT EVENT_RING *EventRing
1204 );
1205
1206 /**
1207 Initialize the XHCI host controller for schedule.
1208
1209 @param Xhc The XHCI device to be initialized.
1210
1211 **/
1212 VOID
1213 XhcPeiInitSched (
1214 IN PEI_XHC_DEV *Xhc
1215 );
1216
1217 /**
1218 Free the resouce allocated at initializing schedule.
1219
1220 @param Xhc The XHCI device.
1221
1222 **/
1223 VOID
1224 XhcPeiFreeSched (
1225 IN PEI_XHC_DEV *Xhc
1226 );
1227
1228 #endif
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