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[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhciSched.h
1 /** @file
2 Private Header file for Usb Host Controller PEIM
3
4 Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 #ifndef _EFI_PEI_XHCI_SCHED_H_
11 #define _EFI_PEI_XHCI_SCHED_H_
12
13 //
14 // Transfer types, used in URB to identify the transfer type
15 //
16 #define XHC_CTRL_TRANSFER 0x01
17 #define XHC_BULK_TRANSFER 0x02
18
19 //
20 // 6.4.6 TRB Types
21 //
22 #define TRB_TYPE_NORMAL 1
23 #define TRB_TYPE_SETUP_STAGE 2
24 #define TRB_TYPE_DATA_STAGE 3
25 #define TRB_TYPE_STATUS_STAGE 4
26 #define TRB_TYPE_ISOCH 5
27 #define TRB_TYPE_LINK 6
28 #define TRB_TYPE_EVENT_DATA 7
29 #define TRB_TYPE_NO_OP 8
30 #define TRB_TYPE_EN_SLOT 9
31 #define TRB_TYPE_DIS_SLOT 10
32 #define TRB_TYPE_ADDRESS_DEV 11
33 #define TRB_TYPE_CON_ENDPOINT 12
34 #define TRB_TYPE_EVALU_CONTXT 13
35 #define TRB_TYPE_RESET_ENDPOINT 14
36 #define TRB_TYPE_STOP_ENDPOINT 15
37 #define TRB_TYPE_SET_TR_DEQUE 16
38 #define TRB_TYPE_RESET_DEV 17
39 #define TRB_TYPE_GET_PORT_BANW 21
40 #define TRB_TYPE_FORCE_HEADER 22
41 #define TRB_TYPE_NO_OP_COMMAND 23
42 #define TRB_TYPE_TRANS_EVENT 32
43 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
44 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
45 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
46 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
47 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
48
49 //
50 // Endpoint Type (EP Type).
51 //
52 #define ED_NOT_VALID 0
53 #define ED_ISOCH_OUT 1
54 #define ED_BULK_OUT 2
55 #define ED_INTERRUPT_OUT 3
56 #define ED_CONTROL_BIDIR 4
57 #define ED_ISOCH_IN 5
58 #define ED_BULK_IN 6
59 #define ED_INTERRUPT_IN 7
60
61 //
62 // 6.4.5 TRB Completion Codes
63 //
64 #define TRB_COMPLETION_INVALID 0
65 #define TRB_COMPLETION_SUCCESS 1
66 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
67 #define TRB_COMPLETION_BABBLE_ERROR 3
68 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
69 #define TRB_COMPLETION_TRB_ERROR 5
70 #define TRB_COMPLETION_STALL_ERROR 6
71 #define TRB_COMPLETION_SHORT_PACKET 13
72
73 //
74 // The topology string used to present usb device location
75 //
76 typedef struct _USB_DEV_TOPOLOGY {
77 //
78 // The tier concatenation of down stream port.
79 //
80 UINT32 RouteString:20;
81 //
82 // The root port number of the chain.
83 //
84 UINT32 RootPortNum:8;
85 //
86 // The Tier the device reside.
87 //
88 UINT32 TierNum:4;
89 } USB_DEV_TOPOLOGY;
90
91 //
92 // USB Device's RouteChart
93 //
94 typedef union _USB_DEV_ROUTE {
95 UINT32 Dword;
96 USB_DEV_TOPOLOGY Route;
97 } USB_DEV_ROUTE;
98
99 //
100 // Endpoint address and its capabilities
101 //
102 typedef struct _USB_ENDPOINT {
103 //
104 // Store logical device address assigned by UsbBus
105 // It's because some XHCI host controllers may assign the same physcial device
106 // address for those devices inserted at different root port.
107 //
108 UINT8 BusAddr;
109 UINT8 DevAddr;
110 UINT8 EpAddr;
111 EFI_USB_DATA_DIRECTION Direction;
112 UINT8 DevSpeed;
113 UINTN MaxPacket;
114 UINTN Type;
115 } USB_ENDPOINT;
116
117 //
118 // TRB Template
119 //
120 typedef struct _TRB_TEMPLATE {
121 UINT32 Parameter1;
122
123 UINT32 Parameter2;
124
125 UINT32 Status;
126
127 UINT32 CycleBit:1;
128 UINT32 RsvdZ1:9;
129 UINT32 Type:6;
130 UINT32 Control:16;
131 } TRB_TEMPLATE;
132
133 typedef struct _TRANSFER_RING {
134 VOID *RingSeg0;
135 UINTN TrbNumber;
136 TRB_TEMPLATE *RingEnqueue;
137 TRB_TEMPLATE *RingDequeue;
138 UINT32 RingPCS;
139 } TRANSFER_RING;
140
141 typedef struct _EVENT_RING {
142 VOID *ERSTBase;
143 VOID *EventRingSeg0;
144 UINTN TrbNumber;
145 TRB_TEMPLATE *EventRingEnqueue;
146 TRB_TEMPLATE *EventRingDequeue;
147 UINT32 EventRingCCS;
148 } EVENT_RING;
149
150 #define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
151
152 //
153 // URB (Usb Request Block) contains information for all kinds of
154 // usb requests.
155 //
156 typedef struct _URB {
157 UINT32 Signature;
158 //
159 // Usb Device URB related information
160 //
161 USB_ENDPOINT Ep;
162 EFI_USB_DEVICE_REQUEST *Request;
163 VOID *Data;
164 UINTN DataLen;
165 VOID *DataPhy;
166 VOID *DataMap;
167 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
168 VOID *Context;
169 //
170 // Execute result
171 //
172 UINT32 Result;
173 //
174 // completed data length
175 //
176 UINTN Completed;
177 //
178 // Command/Tranfer Ring info
179 //
180 TRANSFER_RING *Ring;
181 TRB_TEMPLATE *TrbStart;
182 TRB_TEMPLATE *TrbEnd;
183 UINTN TrbNum;
184 BOOLEAN StartDone;
185 BOOLEAN EndDone;
186 BOOLEAN Finished;
187
188 TRB_TEMPLATE *EvtTrb;
189 } URB;
190
191 //
192 // 6.5 Event Ring Segment Table
193 // The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime
194 // expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the
195 // Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table
196 // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
197 //
198 typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
199 UINT32 PtrLo;
200 UINT32 PtrHi;
201 UINT32 RingTrbSize:16;
202 UINT32 RsvdZ1:16;
203 UINT32 RsvdZ2;
204 } EVENT_RING_SEG_TABLE_ENTRY;
205
206 //
207 // 6.4.1.1 Normal TRB
208 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
209 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
210 // Rings, and to define the Data stage information for Control Transfer Rings.
211 //
212 typedef struct _TRANSFER_TRB_NORMAL {
213 UINT32 TRBPtrLo;
214
215 UINT32 TRBPtrHi;
216
217 UINT32 Length:17;
218 UINT32 TDSize:5;
219 UINT32 IntTarget:10;
220
221 UINT32 CycleBit:1;
222 UINT32 ENT:1;
223 UINT32 ISP:1;
224 UINT32 NS:1;
225 UINT32 CH:1;
226 UINT32 IOC:1;
227 UINT32 IDT:1;
228 UINT32 RsvdZ1:2;
229 UINT32 BEI:1;
230 UINT32 Type:6;
231 UINT32 RsvdZ2:16;
232 } TRANSFER_TRB_NORMAL;
233
234 //
235 // 6.4.1.2.1 Setup Stage TRB
236 // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
237 //
238 typedef struct _TRANSFER_TRB_CONTROL_SETUP {
239 UINT32 bmRequestType:8;
240 UINT32 bRequest:8;
241 UINT32 wValue:16;
242
243 UINT32 wIndex:16;
244 UINT32 wLength:16;
245
246 UINT32 Length:17;
247 UINT32 RsvdZ1:5;
248 UINT32 IntTarget:10;
249
250 UINT32 CycleBit:1;
251 UINT32 RsvdZ2:4;
252 UINT32 IOC:1;
253 UINT32 IDT:1;
254 UINT32 RsvdZ3:3;
255 UINT32 Type:6;
256 UINT32 TRT:2;
257 UINT32 RsvdZ4:14;
258 } TRANSFER_TRB_CONTROL_SETUP;
259
260 //
261 // 6.4.1.2.2 Data Stage TRB
262 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
263 //
264 typedef struct _TRANSFER_TRB_CONTROL_DATA {
265 UINT32 TRBPtrLo;
266
267 UINT32 TRBPtrHi;
268
269 UINT32 Length:17;
270 UINT32 TDSize:5;
271 UINT32 IntTarget:10;
272
273 UINT32 CycleBit:1;
274 UINT32 ENT:1;
275 UINT32 ISP:1;
276 UINT32 NS:1;
277 UINT32 CH:1;
278 UINT32 IOC:1;
279 UINT32 IDT:1;
280 UINT32 RsvdZ1:3;
281 UINT32 Type:6;
282 UINT32 DIR:1;
283 UINT32 RsvdZ2:15;
284 } TRANSFER_TRB_CONTROL_DATA;
285
286 //
287 // 6.4.1.2.2 Data Stage TRB
288 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
289 //
290 typedef struct _TRANSFER_TRB_CONTROL_STATUS {
291 UINT32 RsvdZ1;
292 UINT32 RsvdZ2;
293
294 UINT32 RsvdZ3:22;
295 UINT32 IntTarget:10;
296
297 UINT32 CycleBit:1;
298 UINT32 ENT:1;
299 UINT32 RsvdZ4:2;
300 UINT32 CH:1;
301 UINT32 IOC:1;
302 UINT32 RsvdZ5:4;
303 UINT32 Type:6;
304 UINT32 DIR:1;
305 UINT32 RsvdZ6:15;
306 } TRANSFER_TRB_CONTROL_STATUS;
307
308 //
309 // 6.4.2.1 Transfer Event TRB
310 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
311 // for more information on the use and operation of Transfer Events.
312 //
313 typedef struct _EVT_TRB_TRANSFER {
314 UINT32 TRBPtrLo;
315
316 UINT32 TRBPtrHi;
317
318 UINT32 Length:24;
319 UINT32 Completecode:8;
320
321 UINT32 CycleBit:1;
322 UINT32 RsvdZ1:1;
323 UINT32 ED:1;
324 UINT32 RsvdZ2:7;
325 UINT32 Type:6;
326 UINT32 EndpointId:5;
327 UINT32 RsvdZ3:3;
328 UINT32 SlotId:8;
329 } EVT_TRB_TRANSFER;
330
331 //
332 // 6.4.2.2 Command Completion Event TRB
333 // A Command Completion Event TRB shall be generated by the xHC when a command completes on the
334 // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
335 //
336 typedef struct _EVT_TRB_COMMAND_COMPLETION {
337 UINT32 TRBPtrLo;
338
339 UINT32 TRBPtrHi;
340
341 UINT32 RsvdZ2:24;
342 UINT32 Completecode:8;
343
344 UINT32 CycleBit:1;
345 UINT32 RsvdZ3:9;
346 UINT32 Type:6;
347 UINT32 VFID:8;
348 UINT32 SlotId:8;
349 } EVT_TRB_COMMAND_COMPLETION;
350
351 typedef union _TRB {
352 TRB_TEMPLATE TrbTemplate;
353 TRANSFER_TRB_NORMAL TrbNormal;
354 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
355 TRANSFER_TRB_CONTROL_DATA TrbCtrData;
356 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
357 } TRB;
358
359 //
360 // 6.4.3.1 No Op Command TRB
361 // The No Op Command TRB provides a simple means for verifying the operation of the Command Ring
362 // mechanisms offered by the xHCI.
363 //
364 typedef struct _CMD_TRB_NO_OP {
365 UINT32 RsvdZ0;
366 UINT32 RsvdZ1;
367 UINT32 RsvdZ2;
368
369 UINT32 CycleBit:1;
370 UINT32 RsvdZ3:9;
371 UINT32 Type:6;
372 UINT32 RsvdZ4:16;
373 } CMD_TRB_NO_OP;
374
375 //
376 // 6.4.3.2 Enable Slot Command TRB
377 // The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the
378 // selected slot to the host in a Command Completion Event.
379 //
380 typedef struct _CMD_TRB_ENABLE_SLOT {
381 UINT32 RsvdZ0;
382 UINT32 RsvdZ1;
383 UINT32 RsvdZ2;
384
385 UINT32 CycleBit:1;
386 UINT32 RsvdZ3:9;
387 UINT32 Type:6;
388 UINT32 RsvdZ4:16;
389 } CMD_TRB_ENABLE_SLOT;
390
391 //
392 // 6.4.3.3 Disable Slot Command TRB
393 // The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any
394 // internal xHC resources assigned to the slot.
395 //
396 typedef struct _CMD_TRB_DISABLE_SLOT {
397 UINT32 RsvdZ0;
398 UINT32 RsvdZ1;
399 UINT32 RsvdZ2;
400
401 UINT32 CycleBit:1;
402 UINT32 RsvdZ3:9;
403 UINT32 Type:6;
404 UINT32 RsvdZ4:8;
405 UINT32 SlotId:8;
406 } CMD_TRB_DISABLE_SLOT;
407
408 //
409 // 6.4.3.4 Address Device Command TRB
410 // The Address Device Command TRB transitions the selected Device Context from the Default to the
411 // Addressed state and causes the xHC to select an address for the USB device in the Default State and
412 // issue a SET_ADDRESS request to the USB device.
413 //
414 typedef struct _CMD_TRB_ADDRESS_DEVICE {
415 UINT32 PtrLo;
416
417 UINT32 PtrHi;
418
419 UINT32 RsvdZ1;
420
421 UINT32 CycleBit:1;
422 UINT32 RsvdZ2:8;
423 UINT32 BSR:1;
424 UINT32 Type:6;
425 UINT32 RsvdZ3:8;
426 UINT32 SlotId:8;
427 } CMD_TRB_ADDRESS_DEVICE;
428
429 //
430 // 6.4.3.5 Configure Endpoint Command TRB
431 // The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the
432 // endpoints selected by the command.
433 //
434 typedef struct _CMD_TRB_CONFIG_ENDPOINT {
435 UINT32 PtrLo;
436
437 UINT32 PtrHi;
438
439 UINT32 RsvdZ1;
440
441 UINT32 CycleBit:1;
442 UINT32 RsvdZ2:8;
443 UINT32 DC:1;
444 UINT32 Type:6;
445 UINT32 RsvdZ3:8;
446 UINT32 SlotId:8;
447 } CMD_TRB_CONFIG_ENDPOINT;
448
449 //
450 // 6.4.3.6 Evaluate Context Command TRB
451 // The Evaluate Context Command TRB is used by system software to inform the xHC that the selected
452 // Context data structures in the Device Context have been modified by system software and that the xHC
453 // shall evaluate any changes
454 //
455 typedef struct _CMD_TRB_EVALUATE_CONTEXT {
456 UINT32 PtrLo;
457
458 UINT32 PtrHi;
459
460 UINT32 RsvdZ1;
461
462 UINT32 CycleBit:1;
463 UINT32 RsvdZ2:9;
464 UINT32 Type:6;
465 UINT32 RsvdZ3:8;
466 UINT32 SlotId:8;
467 } CMD_TRB_EVALUATE_CONTEXT;
468
469 //
470 // 6.4.3.7 Reset Endpoint Command TRB
471 // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
472 //
473 typedef struct _CMD_TRB_RESET_ENDPOINT {
474 UINT32 RsvdZ0;
475 UINT32 RsvdZ1;
476 UINT32 RsvdZ2;
477
478 UINT32 CycleBit:1;
479 UINT32 RsvdZ3:8;
480 UINT32 TSP:1;
481 UINT32 Type:6;
482 UINT32 EDID:5;
483 UINT32 RsvdZ4:3;
484 UINT32 SlotId:8;
485 } CMD_TRB_RESET_ENDPOINT;
486
487 //
488 // 6.4.3.8 Stop Endpoint Command TRB
489 // The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a
490 // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
491 //
492 typedef struct _CMD_TRB_STOP_ENDPOINT {
493 UINT32 RsvdZ0;
494 UINT32 RsvdZ1;
495 UINT32 RsvdZ2;
496
497 UINT32 CycleBit:1;
498 UINT32 RsvdZ3:9;
499 UINT32 Type:6;
500 UINT32 EDID:5;
501 UINT32 RsvdZ4:2;
502 UINT32 SP:1;
503 UINT32 SlotId:8;
504 } CMD_TRB_STOP_ENDPOINT;
505
506 //
507 // 6.4.3.9 Set TR Dequeue Pointer Command TRB
508 // The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue
509 // Pointer and DCS fields of an Endpoint or Stream Context.
510 //
511 typedef struct _CMD_SET_TR_DEQ_POINTER {
512 UINT32 PtrLo;
513
514 UINT32 PtrHi;
515
516 UINT32 RsvdZ1:16;
517 UINT32 StreamID:16;
518
519 UINT32 CycleBit:1;
520 UINT32 RsvdZ2:9;
521 UINT32 Type:6;
522 UINT32 Endpoint:5;
523 UINT32 RsvdZ3:3;
524 UINT32 SlotId:8;
525 } CMD_SET_TR_DEQ_POINTER;
526
527 //
528 // 6.4.4.1 Link TRB
529 // A Link TRB provides support for non-contiguous TRB Rings.
530 //
531 typedef struct _LINK_TRB {
532 UINT32 PtrLo;
533
534 UINT32 PtrHi;
535
536 UINT32 RsvdZ1:22;
537 UINT32 InterTarget:10;
538
539 UINT32 CycleBit:1;
540 UINT32 TC:1;
541 UINT32 RsvdZ2:2;
542 UINT32 CH:1;
543 UINT32 IOC:1;
544 UINT32 RsvdZ3:4;
545 UINT32 Type:6;
546 UINT32 RsvdZ4:16;
547 } LINK_TRB;
548
549 //
550 // 6.2.2 Slot Context
551 //
552 typedef struct _SLOT_CONTEXT {
553 UINT32 RouteString:20;
554 UINT32 Speed:4;
555 UINT32 RsvdZ1:1;
556 UINT32 MTT:1;
557 UINT32 Hub:1;
558 UINT32 ContextEntries:5;
559
560 UINT32 MaxExitLatency:16;
561 UINT32 RootHubPortNum:8;
562 UINT32 PortNum:8;
563
564 UINT32 TTHubSlotId:8;
565 UINT32 TTPortNum:8;
566 UINT32 TTT:2;
567 UINT32 RsvdZ2:4;
568 UINT32 InterTarget:10;
569
570 UINT32 DeviceAddress:8;
571 UINT32 RsvdZ3:19;
572 UINT32 SlotState:5;
573
574 UINT32 RsvdZ4;
575 UINT32 RsvdZ5;
576 UINT32 RsvdZ6;
577 UINT32 RsvdZ7;
578 } SLOT_CONTEXT;
579
580 typedef struct _SLOT_CONTEXT_64 {
581 UINT32 RouteString:20;
582 UINT32 Speed:4;
583 UINT32 RsvdZ1:1;
584 UINT32 MTT:1;
585 UINT32 Hub:1;
586 UINT32 ContextEntries:5;
587
588 UINT32 MaxExitLatency:16;
589 UINT32 RootHubPortNum:8;
590 UINT32 PortNum:8;
591
592 UINT32 TTHubSlotId:8;
593 UINT32 TTPortNum:8;
594 UINT32 TTT:2;
595 UINT32 RsvdZ2:4;
596 UINT32 InterTarget:10;
597
598 UINT32 DeviceAddress:8;
599 UINT32 RsvdZ3:19;
600 UINT32 SlotState:5;
601
602 UINT32 RsvdZ4;
603 UINT32 RsvdZ5;
604 UINT32 RsvdZ6;
605 UINT32 RsvdZ7;
606
607 UINT32 RsvdZ8;
608 UINT32 RsvdZ9;
609 UINT32 RsvdZ10;
610 UINT32 RsvdZ11;
611
612 UINT32 RsvdZ12;
613 UINT32 RsvdZ13;
614 UINT32 RsvdZ14;
615 UINT32 RsvdZ15;
616
617 } SLOT_CONTEXT_64;
618
619
620 //
621 // 6.2.3 Endpoint Context
622 //
623 typedef struct _ENDPOINT_CONTEXT {
624 UINT32 EPState:3;
625 UINT32 RsvdZ1:5;
626 UINT32 Mult:2;
627 UINT32 MaxPStreams:5;
628 UINT32 LSA:1;
629 UINT32 Interval:8;
630 UINT32 RsvdZ2:8;
631
632 UINT32 RsvdZ3:1;
633 UINT32 CErr:2;
634 UINT32 EPType:3;
635 UINT32 RsvdZ4:1;
636 UINT32 HID:1;
637 UINT32 MaxBurstSize:8;
638 UINT32 MaxPacketSize:16;
639
640 UINT32 PtrLo;
641
642 UINT32 PtrHi;
643
644 UINT32 AverageTRBLength:16;
645 UINT32 MaxESITPayload:16;
646
647 UINT32 RsvdZ5;
648 UINT32 RsvdZ6;
649 UINT32 RsvdZ7;
650 } ENDPOINT_CONTEXT;
651
652 typedef struct _ENDPOINT_CONTEXT_64 {
653 UINT32 EPState:3;
654 UINT32 RsvdZ1:5;
655 UINT32 Mult:2;
656 UINT32 MaxPStreams:5;
657 UINT32 LSA:1;
658 UINT32 Interval:8;
659 UINT32 RsvdZ2:8;
660
661 UINT32 RsvdZ3:1;
662 UINT32 CErr:2;
663 UINT32 EPType:3;
664 UINT32 RsvdZ4:1;
665 UINT32 HID:1;
666 UINT32 MaxBurstSize:8;
667 UINT32 MaxPacketSize:16;
668
669 UINT32 PtrLo;
670
671 UINT32 PtrHi;
672
673 UINT32 AverageTRBLength:16;
674 UINT32 MaxESITPayload:16;
675
676 UINT32 RsvdZ5;
677 UINT32 RsvdZ6;
678 UINT32 RsvdZ7;
679
680 UINT32 RsvdZ8;
681 UINT32 RsvdZ9;
682 UINT32 RsvdZ10;
683 UINT32 RsvdZ11;
684
685 UINT32 RsvdZ12;
686 UINT32 RsvdZ13;
687 UINT32 RsvdZ14;
688 UINT32 RsvdZ15;
689
690 } ENDPOINT_CONTEXT_64;
691
692
693 //
694 // 6.2.5.1 Input Control Context
695 //
696 typedef struct _INPUT_CONTRL_CONTEXT {
697 UINT32 Dword1;
698 UINT32 Dword2;
699 UINT32 RsvdZ1;
700 UINT32 RsvdZ2;
701 UINT32 RsvdZ3;
702 UINT32 RsvdZ4;
703 UINT32 RsvdZ5;
704 UINT32 RsvdZ6;
705 } INPUT_CONTRL_CONTEXT;
706
707 typedef struct _INPUT_CONTRL_CONTEXT_64 {
708 UINT32 Dword1;
709 UINT32 Dword2;
710 UINT32 RsvdZ1;
711 UINT32 RsvdZ2;
712 UINT32 RsvdZ3;
713 UINT32 RsvdZ4;
714 UINT32 RsvdZ5;
715 UINT32 RsvdZ6;
716 UINT32 RsvdZ7;
717 UINT32 RsvdZ8;
718 UINT32 RsvdZ9;
719 UINT32 RsvdZ10;
720 UINT32 RsvdZ11;
721 UINT32 RsvdZ12;
722 UINT32 RsvdZ13;
723 UINT32 RsvdZ14;
724 } INPUT_CONTRL_CONTEXT_64;
725
726 //
727 // 6.2.1 Device Context
728 //
729 typedef struct _DEVICE_CONTEXT {
730 SLOT_CONTEXT Slot;
731 ENDPOINT_CONTEXT EP[31];
732 } DEVICE_CONTEXT;
733
734 typedef struct _DEVICE_CONTEXT_64 {
735 SLOT_CONTEXT_64 Slot;
736 ENDPOINT_CONTEXT_64 EP[31];
737 } DEVICE_CONTEXT_64;
738
739 //
740 // 6.2.5 Input Context
741 //
742 typedef struct _INPUT_CONTEXT {
743 INPUT_CONTRL_CONTEXT InputControlContext;
744 SLOT_CONTEXT Slot;
745 ENDPOINT_CONTEXT EP[31];
746 } INPUT_CONTEXT;
747
748 typedef struct _INPUT_CONTEXT_64 {
749 INPUT_CONTRL_CONTEXT_64 InputControlContext;
750 SLOT_CONTEXT_64 Slot;
751 ENDPOINT_CONTEXT_64 EP[31];
752 } INPUT_CONTEXT_64;
753
754 /**
755 Execute the transfer by polling the URB. This is a synchronous operation.
756
757 @param Xhc The XHCI device.
758 @param CmdTransfer The executed URB is for cmd transfer or not.
759 @param Urb The URB to execute.
760 @param Timeout The time to wait before abort, in millisecond.
761
762 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
763 @return EFI_TIMEOUT The transfer failed due to time out.
764 @return EFI_SUCCESS The transfer finished OK.
765
766 **/
767 EFI_STATUS
768 XhcPeiExecTransfer (
769 IN PEI_XHC_DEV *Xhc,
770 IN BOOLEAN CmdTransfer,
771 IN URB *Urb,
772 IN UINTN Timeout
773 );
774
775 /**
776 Find out the actual device address according to the requested device address from UsbBus.
777
778 @param Xhc The XHCI device.
779 @param BusDevAddr The requested device address by UsbBus upper driver.
780
781 @return The actual device address assigned to the device.
782
783 **/
784 UINT8
785 XhcPeiBusDevAddrToSlotId (
786 IN PEI_XHC_DEV *Xhc,
787 IN UINT8 BusDevAddr
788 );
789
790 /**
791 Find out the slot id according to the device's route string.
792
793 @param Xhc The XHCI device.
794 @param RouteString The route string described the device location.
795
796 @return The slot id used by the device.
797
798 **/
799 UINT8
800 XhcPeiRouteStringToSlotId (
801 IN PEI_XHC_DEV *Xhc,
802 IN USB_DEV_ROUTE RouteString
803 );
804
805 /**
806 Calculate the device context index by endpoint address and direction.
807
808 @param EpAddr The target endpoint number.
809 @param Direction The direction of the target endpoint.
810
811 @return The device context index of endpoint.
812
813 **/
814 UINT8
815 XhcPeiEndpointToDci (
816 IN UINT8 EpAddr,
817 IN EFI_USB_DATA_DIRECTION Direction
818 );
819
820 /**
821 Ring the door bell to notify XHCI there is a transaction to be executed.
822
823 @param Xhc The XHCI device.
824 @param SlotId The slot id of the target device.
825 @param Dci The device context index of the target slot or endpoint.
826
827 **/
828 VOID
829 XhcPeiRingDoorBell (
830 IN PEI_XHC_DEV *Xhc,
831 IN UINT8 SlotId,
832 IN UINT8 Dci
833 );
834
835 /**
836 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
837
838 @param Xhc The XHCI device.
839 @param ParentRouteChart The route string pointed to the parent device if it exists.
840 @param Port The port to be polled.
841 @param PortState The port state.
842
843 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
844 @retval Others Should not appear.
845
846 **/
847 EFI_STATUS
848 XhcPeiPollPortStatusChange (
849 IN PEI_XHC_DEV *Xhc,
850 IN USB_DEV_ROUTE ParentRouteChart,
851 IN UINT8 Port,
852 IN EFI_USB_PORT_STATUS *PortState
853 );
854
855 /**
856 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
857
858 @param Xhc The XHCI device.
859 @param SlotId The slot id to be configured.
860 @param PortNum The total number of downstream port supported by the hub.
861 @param TTT The TT think time of the hub device.
862 @param MTT The multi-TT of the hub device.
863
864 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
865
866 **/
867 EFI_STATUS
868 XhcPeiConfigHubContext (
869 IN PEI_XHC_DEV *Xhc,
870 IN UINT8 SlotId,
871 IN UINT8 PortNum,
872 IN UINT8 TTT,
873 IN UINT8 MTT
874 );
875
876 /**
877 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
878
879 @param Xhc The XHCI device.
880 @param SlotId The slot id to be configured.
881 @param PortNum The total number of downstream port supported by the hub.
882 @param TTT The TT think time of the hub device.
883 @param MTT The multi-TT of the hub device.
884
885 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
886
887 **/
888 EFI_STATUS
889 XhcPeiConfigHubContext64 (
890 IN PEI_XHC_DEV *Xhc,
891 IN UINT8 SlotId,
892 IN UINT8 PortNum,
893 IN UINT8 TTT,
894 IN UINT8 MTT
895 );
896
897 /**
898 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
899
900 @param Xhc The XHCI device.
901 @param SlotId The slot id to be configured.
902 @param DeviceSpeed The device's speed.
903 @param ConfigDesc The pointer to the usb device configuration descriptor.
904
905 @retval EFI_SUCCESS Successfully configure all the device endpoints.
906
907 **/
908 EFI_STATUS
909 XhcPeiSetConfigCmd (
910 IN PEI_XHC_DEV *Xhc,
911 IN UINT8 SlotId,
912 IN UINT8 DeviceSpeed,
913 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
914 );
915
916 /**
917 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
918
919 @param Xhc The XHCI device.
920 @param SlotId The slot id to be configured.
921 @param DeviceSpeed The device's speed.
922 @param ConfigDesc The pointer to the usb device configuration descriptor.
923
924 @retval EFI_SUCCESS Successfully configure all the device endpoints.
925
926 **/
927 EFI_STATUS
928 XhcPeiSetConfigCmd64 (
929 IN PEI_XHC_DEV *Xhc,
930 IN UINT8 SlotId,
931 IN UINT8 DeviceSpeed,
932 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
933 );
934
935 /**
936 Stop endpoint through XHCI's Stop_Endpoint cmd.
937
938 @param Xhc The XHCI device.
939 @param SlotId The slot id of the target device.
940 @param Dci The device context index of the target slot or endpoint.
941
942 @retval EFI_SUCCESS Stop endpoint successfully.
943 @retval Others Failed to stop endpoint.
944
945 **/
946 EFI_STATUS
947 EFIAPI
948 XhcPeiStopEndpoint (
949 IN PEI_XHC_DEV *Xhc,
950 IN UINT8 SlotId,
951 IN UINT8 Dci
952 );
953
954 /**
955 Reset endpoint through XHCI's Reset_Endpoint cmd.
956
957 @param Xhc The XHCI device.
958 @param SlotId The slot id of the target device.
959 @param Dci The device context index of the target slot or endpoint.
960
961 @retval EFI_SUCCESS Reset endpoint successfully.
962 @retval Others Failed to reset endpoint.
963
964 **/
965 EFI_STATUS
966 EFIAPI
967 XhcPeiResetEndpoint (
968 IN PEI_XHC_DEV *Xhc,
969 IN UINT8 SlotId,
970 IN UINT8 Dci
971 );
972
973 /**
974 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.
975
976 @param Xhc The XHCI device.
977 @param SlotId The slot id of the target device.
978 @param Dci The device context index of the target slot or endpoint.
979 @param Urb The dequeue pointer of the transfer ring specified
980 by the urb to be updated.
981
982 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.
983 @retval Others Failed to set transfer ring dequeue pointer.
984
985 **/
986 EFI_STATUS
987 EFIAPI
988 XhcPeiSetTrDequeuePointer (
989 IN PEI_XHC_DEV *Xhc,
990 IN UINT8 SlotId,
991 IN UINT8 Dci,
992 IN URB *Urb
993 );
994
995 /**
996 Assign and initialize the device slot for a new device.
997
998 @param Xhc The XHCI device.
999 @param ParentRouteChart The route string pointed to the parent device.
1000 @param ParentPort The port at which the device is located.
1001 @param RouteChart The route string pointed to the device.
1002 @param DeviceSpeed The device speed.
1003
1004 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1005 @retval Others Fail to initialize device slot.
1006
1007 **/
1008 EFI_STATUS
1009 XhcPeiInitializeDeviceSlot (
1010 IN PEI_XHC_DEV *Xhc,
1011 IN USB_DEV_ROUTE ParentRouteChart,
1012 IN UINT16 ParentPort,
1013 IN USB_DEV_ROUTE RouteChart,
1014 IN UINT8 DeviceSpeed
1015 );
1016
1017 /**
1018 Assign and initialize the device slot for a new device.
1019
1020 @param Xhc The XHCI device.
1021 @param ParentRouteChart The route string pointed to the parent device.
1022 @param ParentPort The port at which the device is located.
1023 @param RouteChart The route string pointed to the device.
1024 @param DeviceSpeed The device speed.
1025
1026 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1027 @retval Others Fail to initialize device slot.
1028
1029 **/
1030 EFI_STATUS
1031 XhcPeiInitializeDeviceSlot64 (
1032 IN PEI_XHC_DEV *Xhc,
1033 IN USB_DEV_ROUTE ParentRouteChart,
1034 IN UINT16 ParentPort,
1035 IN USB_DEV_ROUTE RouteChart,
1036 IN UINT8 DeviceSpeed
1037 );
1038
1039 /**
1040 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1041
1042 @param Xhc The XHCI device.
1043 @param SlotId The slot id to be evaluated.
1044 @param MaxPacketSize The max packet size supported by the device control transfer.
1045
1046 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1047
1048 **/
1049 EFI_STATUS
1050 XhcPeiEvaluateContext (
1051 IN PEI_XHC_DEV *Xhc,
1052 IN UINT8 SlotId,
1053 IN UINT32 MaxPacketSize
1054 );
1055
1056 /**
1057 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1058
1059 @param Xhc The XHCI device.
1060 @param SlotId The slot id to be evaluated.
1061 @param MaxPacketSize The max packet size supported by the device control transfer.
1062
1063 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1064
1065 **/
1066 EFI_STATUS
1067 XhcPeiEvaluateContext64 (
1068 IN PEI_XHC_DEV *Xhc,
1069 IN UINT8 SlotId,
1070 IN UINT32 MaxPacketSize
1071 );
1072
1073 /**
1074 Disable the specified device slot.
1075
1076 @param Xhc The XHCI device.
1077 @param SlotId The slot id to be disabled.
1078
1079 @retval EFI_SUCCESS Successfully disable the device slot.
1080
1081 **/
1082 EFI_STATUS
1083 XhcPeiDisableSlotCmd (
1084 IN PEI_XHC_DEV *Xhc,
1085 IN UINT8 SlotId
1086 );
1087
1088 /**
1089 Disable the specified device slot.
1090
1091 @param Xhc The XHCI device.
1092 @param SlotId The slot id to be disabled.
1093
1094 @retval EFI_SUCCESS Successfully disable the device slot.
1095
1096 **/
1097 EFI_STATUS
1098 XhcPeiDisableSlotCmd64 (
1099 IN PEI_XHC_DEV *Xhc,
1100 IN UINT8 SlotId
1101 );
1102
1103 /**
1104 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
1105 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
1106 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
1107 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
1108 Stopped to the Running state.
1109
1110 @param Xhc The XHCI device.
1111 @param Urb The urb which makes the endpoint halted.
1112
1113 @retval EFI_SUCCESS The recovery is successful.
1114 @retval Others Failed to recovery halted endpoint.
1115
1116 **/
1117 EFI_STATUS
1118 XhcPeiRecoverHaltedEndpoint (
1119 IN PEI_XHC_DEV *Xhc,
1120 IN URB *Urb
1121 );
1122
1123 /**
1124 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer
1125 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to
1126 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running
1127 state.
1128
1129 @param Xhc The XHCI device.
1130 @param Urb The urb which doesn't get completed in a specified timeout range.
1131
1132 @retval EFI_SUCCESS The dequeuing of the TDs is successful.
1133 @retval Others Failed to stop the endpoint and dequeue the TDs.
1134
1135 **/
1136 EFI_STATUS
1137 XhcPeiDequeueTrbFromEndpoint (
1138 IN PEI_XHC_DEV *Xhc,
1139 IN URB *Urb
1140 );
1141
1142 /**
1143 Create a new URB for a new transaction.
1144
1145 @param Xhc The XHCI device
1146 @param DevAddr The device address
1147 @param EpAddr Endpoint addrress
1148 @param DevSpeed The device speed
1149 @param MaxPacket The max packet length of the endpoint
1150 @param Type The transaction type
1151 @param Request The standard USB request for control transfer
1152 @param Data The user data to transfer
1153 @param DataLen The length of data buffer
1154 @param Callback The function to call when data is transferred
1155 @param Context The context to the callback
1156
1157 @return Created URB or NULL
1158
1159 **/
1160 URB*
1161 XhcPeiCreateUrb (
1162 IN PEI_XHC_DEV *Xhc,
1163 IN UINT8 DevAddr,
1164 IN UINT8 EpAddr,
1165 IN UINT8 DevSpeed,
1166 IN UINTN MaxPacket,
1167 IN UINTN Type,
1168 IN EFI_USB_DEVICE_REQUEST *Request,
1169 IN VOID *Data,
1170 IN UINTN DataLen,
1171 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
1172 IN VOID *Context
1173 );
1174
1175 /**
1176 Free an allocated URB.
1177
1178 @param Xhc The XHCI device.
1179 @param Urb The URB to free.
1180
1181 **/
1182 VOID
1183 XhcPeiFreeUrb (
1184 IN PEI_XHC_DEV *Xhc,
1185 IN URB *Urb
1186 );
1187
1188 /**
1189 Create a transfer TRB.
1190
1191 @param Xhc The XHCI device
1192 @param Urb The urb used to construct the transfer TRB.
1193
1194 @return Created TRB or NULL
1195
1196 **/
1197 EFI_STATUS
1198 XhcPeiCreateTransferTrb (
1199 IN PEI_XHC_DEV *Xhc,
1200 IN URB *Urb
1201 );
1202
1203 /**
1204 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1205
1206 @param Xhc The XHCI device.
1207 @param TrsRing The transfer ring to sync.
1208
1209 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1210
1211 **/
1212 EFI_STATUS
1213 XhcPeiSyncTrsRing (
1214 IN PEI_XHC_DEV *Xhc,
1215 IN TRANSFER_RING *TrsRing
1216 );
1217
1218 /**
1219 Create XHCI transfer ring.
1220
1221 @param Xhc The XHCI Device.
1222 @param TrbNum The number of TRB in the ring.
1223 @param TransferRing The created transfer ring.
1224
1225 **/
1226 VOID
1227 XhcPeiCreateTransferRing (
1228 IN PEI_XHC_DEV *Xhc,
1229 IN UINTN TrbNum,
1230 OUT TRANSFER_RING *TransferRing
1231 );
1232
1233 /**
1234 Check if there is a new generated event.
1235
1236 @param Xhc The XHCI device.
1237 @param EvtRing The event ring to check.
1238 @param NewEvtTrb The new event TRB found.
1239
1240 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1241 @retval EFI_NOT_READY The event ring has no new event.
1242
1243 **/
1244 EFI_STATUS
1245 XhcPeiCheckNewEvent (
1246 IN PEI_XHC_DEV *Xhc,
1247 IN EVENT_RING *EvtRing,
1248 OUT TRB_TEMPLATE **NewEvtTrb
1249 );
1250
1251 /**
1252 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1253
1254 @param Xhc The XHCI device.
1255 @param EvtRing The event ring to sync.
1256
1257 @retval EFI_SUCCESS The event ring is synchronized successfully.
1258
1259 **/
1260 EFI_STATUS
1261 XhcPeiSyncEventRing (
1262 IN PEI_XHC_DEV *Xhc,
1263 IN EVENT_RING *EvtRing
1264 );
1265
1266 /**
1267 Create XHCI event ring.
1268
1269 @param Xhc The XHCI device.
1270 @param EventRing The created event ring.
1271
1272 **/
1273 VOID
1274 XhcPeiCreateEventRing (
1275 IN PEI_XHC_DEV *Xhc,
1276 OUT EVENT_RING *EventRing
1277 );
1278
1279 /**
1280 Initialize the XHCI host controller for schedule.
1281
1282 @param Xhc The XHCI device to be initialized.
1283
1284 **/
1285 VOID
1286 XhcPeiInitSched (
1287 IN PEI_XHC_DEV *Xhc
1288 );
1289
1290 /**
1291 Free the resouce allocated at initializing schedule.
1292
1293 @param Xhc The XHCI device.
1294
1295 **/
1296 VOID
1297 XhcPeiFreeSched (
1298 IN PEI_XHC_DEV *Xhc
1299 );
1300
1301 #endif
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