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1 /** @file
2 Private Header file for Usb Host Controller PEIM
3
4 Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
5
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions
8 of the BSD License which accompanies this distribution. The
9 full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _EFI_PEI_XHCI_SCHED_H_
18 #define _EFI_PEI_XHCI_SCHED_H_
19
20 //
21 // Transfer types, used in URB to identify the transfer type
22 //
23 #define XHC_CTRL_TRANSFER 0x01
24 #define XHC_BULK_TRANSFER 0x02
25
26 //
27 // 6.4.6 TRB Types
28 //
29 #define TRB_TYPE_NORMAL 1
30 #define TRB_TYPE_SETUP_STAGE 2
31 #define TRB_TYPE_DATA_STAGE 3
32 #define TRB_TYPE_STATUS_STAGE 4
33 #define TRB_TYPE_ISOCH 5
34 #define TRB_TYPE_LINK 6
35 #define TRB_TYPE_EVENT_DATA 7
36 #define TRB_TYPE_NO_OP 8
37 #define TRB_TYPE_EN_SLOT 9
38 #define TRB_TYPE_DIS_SLOT 10
39 #define TRB_TYPE_ADDRESS_DEV 11
40 #define TRB_TYPE_CON_ENDPOINT 12
41 #define TRB_TYPE_EVALU_CONTXT 13
42 #define TRB_TYPE_RESET_ENDPOINT 14
43 #define TRB_TYPE_STOP_ENDPOINT 15
44 #define TRB_TYPE_SET_TR_DEQUE 16
45 #define TRB_TYPE_RESET_DEV 17
46 #define TRB_TYPE_GET_PORT_BANW 21
47 #define TRB_TYPE_FORCE_HEADER 22
48 #define TRB_TYPE_NO_OP_COMMAND 23
49 #define TRB_TYPE_TRANS_EVENT 32
50 #define TRB_TYPE_COMMAND_COMPLT_EVENT 33
51 #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34
52 #define TRB_TYPE_HOST_CONTROLLER_EVENT 37
53 #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38
54 #define TRB_TYPE_MFINDEX_WRAP_EVENT 39
55
56 //
57 // Endpoint Type (EP Type).
58 //
59 #define ED_NOT_VALID 0
60 #define ED_ISOCH_OUT 1
61 #define ED_BULK_OUT 2
62 #define ED_INTERRUPT_OUT 3
63 #define ED_CONTROL_BIDIR 4
64 #define ED_ISOCH_IN 5
65 #define ED_BULK_IN 6
66 #define ED_INTERRUPT_IN 7
67
68 //
69 // 6.4.5 TRB Completion Codes
70 //
71 #define TRB_COMPLETION_INVALID 0
72 #define TRB_COMPLETION_SUCCESS 1
73 #define TRB_COMPLETION_DATA_BUFFER_ERROR 2
74 #define TRB_COMPLETION_BABBLE_ERROR 3
75 #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4
76 #define TRB_COMPLETION_TRB_ERROR 5
77 #define TRB_COMPLETION_STALL_ERROR 6
78 #define TRB_COMPLETION_SHORT_PACKET 13
79
80 //
81 // The topology string used to present usb device location
82 //
83 typedef struct _USB_DEV_TOPOLOGY {
84 //
85 // The tier concatenation of down stream port.
86 //
87 UINT32 RouteString:20;
88 //
89 // The root port number of the chain.
90 //
91 UINT32 RootPortNum:8;
92 //
93 // The Tier the device reside.
94 //
95 UINT32 TierNum:4;
96 } USB_DEV_TOPOLOGY;
97
98 //
99 // USB Device's RouteChart
100 //
101 typedef union _USB_DEV_ROUTE {
102 UINT32 Dword;
103 USB_DEV_TOPOLOGY Route;
104 } USB_DEV_ROUTE;
105
106 //
107 // Endpoint address and its capabilities
108 //
109 typedef struct _USB_ENDPOINT {
110 //
111 // Store logical device address assigned by UsbBus
112 // It's because some XHCI host controllers may assign the same physcial device
113 // address for those devices inserted at different root port.
114 //
115 UINT8 BusAddr;
116 UINT8 DevAddr;
117 UINT8 EpAddr;
118 EFI_USB_DATA_DIRECTION Direction;
119 UINT8 DevSpeed;
120 UINTN MaxPacket;
121 UINTN Type;
122 } USB_ENDPOINT;
123
124 //
125 // TRB Template
126 //
127 typedef struct _TRB_TEMPLATE {
128 UINT32 Parameter1;
129
130 UINT32 Parameter2;
131
132 UINT32 Status;
133
134 UINT32 CycleBit:1;
135 UINT32 RsvdZ1:9;
136 UINT32 Type:6;
137 UINT32 Control:16;
138 } TRB_TEMPLATE;
139
140 typedef struct _TRANSFER_RING {
141 VOID *RingSeg0;
142 UINTN TrbNumber;
143 TRB_TEMPLATE *RingEnqueue;
144 TRB_TEMPLATE *RingDequeue;
145 UINT32 RingPCS;
146 } TRANSFER_RING;
147
148 typedef struct _EVENT_RING {
149 VOID *ERSTBase;
150 VOID *EventRingSeg0;
151 UINTN TrbNumber;
152 TRB_TEMPLATE *EventRingEnqueue;
153 TRB_TEMPLATE *EventRingDequeue;
154 UINT32 EventRingCCS;
155 } EVENT_RING;
156
157 #define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')
158
159 //
160 // URB (Usb Request Block) contains information for all kinds of
161 // usb requests.
162 //
163 typedef struct _URB {
164 UINT32 Signature;
165 //
166 // Usb Device URB related information
167 //
168 USB_ENDPOINT Ep;
169 EFI_USB_DEVICE_REQUEST *Request;
170 VOID *Data;
171 UINTN DataLen;
172 VOID *DataPhy;
173 VOID *DataMap;
174 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;
175 VOID *Context;
176 //
177 // Execute result
178 //
179 UINT32 Result;
180 //
181 // completed data length
182 //
183 UINTN Completed;
184 //
185 // Command/Tranfer Ring info
186 //
187 TRANSFER_RING *Ring;
188 TRB_TEMPLATE *TrbStart;
189 TRB_TEMPLATE *TrbEnd;
190 UINTN TrbNum;
191 BOOLEAN StartDone;
192 BOOLEAN EndDone;
193 BOOLEAN Finished;
194
195 TRB_TEMPLATE *EvtTrb;
196 } URB;
197
198 //
199 // 6.5 Event Ring Segment Table
200 // The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime
201 // expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the
202 // Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table
203 // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).
204 //
205 typedef struct _EVENT_RING_SEG_TABLE_ENTRY {
206 UINT32 PtrLo;
207 UINT32 PtrHi;
208 UINT32 RingTrbSize:16;
209 UINT32 RsvdZ1:16;
210 UINT32 RsvdZ2;
211 } EVENT_RING_SEG_TABLE_ENTRY;
212
213 //
214 // 6.4.1.1 Normal TRB
215 // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and
216 // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer
217 // Rings, and to define the Data stage information for Control Transfer Rings.
218 //
219 typedef struct _TRANSFER_TRB_NORMAL {
220 UINT32 TRBPtrLo;
221
222 UINT32 TRBPtrHi;
223
224 UINT32 Length:17;
225 UINT32 TDSize:5;
226 UINT32 IntTarget:10;
227
228 UINT32 CycleBit:1;
229 UINT32 ENT:1;
230 UINT32 ISP:1;
231 UINT32 NS:1;
232 UINT32 CH:1;
233 UINT32 IOC:1;
234 UINT32 IDT:1;
235 UINT32 RsvdZ1:2;
236 UINT32 BEI:1;
237 UINT32 Type:6;
238 UINT32 RsvdZ2:16;
239 } TRANSFER_TRB_NORMAL;
240
241 //
242 // 6.4.1.2.1 Setup Stage TRB
243 // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.
244 //
245 typedef struct _TRANSFER_TRB_CONTROL_SETUP {
246 UINT32 bmRequestType:8;
247 UINT32 bRequest:8;
248 UINT32 wValue:16;
249
250 UINT32 wIndex:16;
251 UINT32 wLength:16;
252
253 UINT32 Length:17;
254 UINT32 RsvdZ1:5;
255 UINT32 IntTarget:10;
256
257 UINT32 CycleBit:1;
258 UINT32 RsvdZ2:4;
259 UINT32 IOC:1;
260 UINT32 IDT:1;
261 UINT32 RsvdZ3:3;
262 UINT32 Type:6;
263 UINT32 TRT:2;
264 UINT32 RsvdZ4:14;
265 } TRANSFER_TRB_CONTROL_SETUP;
266
267 //
268 // 6.4.1.2.2 Data Stage TRB
269 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
270 //
271 typedef struct _TRANSFER_TRB_CONTROL_DATA {
272 UINT32 TRBPtrLo;
273
274 UINT32 TRBPtrHi;
275
276 UINT32 Length:17;
277 UINT32 TDSize:5;
278 UINT32 IntTarget:10;
279
280 UINT32 CycleBit:1;
281 UINT32 ENT:1;
282 UINT32 ISP:1;
283 UINT32 NS:1;
284 UINT32 CH:1;
285 UINT32 IOC:1;
286 UINT32 IDT:1;
287 UINT32 RsvdZ1:3;
288 UINT32 Type:6;
289 UINT32 DIR:1;
290 UINT32 RsvdZ2:15;
291 } TRANSFER_TRB_CONTROL_DATA;
292
293 //
294 // 6.4.1.2.2 Data Stage TRB
295 // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.
296 //
297 typedef struct _TRANSFER_TRB_CONTROL_STATUS {
298 UINT32 RsvdZ1;
299 UINT32 RsvdZ2;
300
301 UINT32 RsvdZ3:22;
302 UINT32 IntTarget:10;
303
304 UINT32 CycleBit:1;
305 UINT32 ENT:1;
306 UINT32 RsvdZ4:2;
307 UINT32 CH:1;
308 UINT32 IOC:1;
309 UINT32 RsvdZ5:4;
310 UINT32 Type:6;
311 UINT32 DIR:1;
312 UINT32 RsvdZ6:15;
313 } TRANSFER_TRB_CONTROL_STATUS;
314
315 //
316 // 6.4.2.1 Transfer Event TRB
317 // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1
318 // for more information on the use and operation of Transfer Events.
319 //
320 typedef struct _EVT_TRB_TRANSFER {
321 UINT32 TRBPtrLo;
322
323 UINT32 TRBPtrHi;
324
325 UINT32 Length:24;
326 UINT32 Completecode:8;
327
328 UINT32 CycleBit:1;
329 UINT32 RsvdZ1:1;
330 UINT32 ED:1;
331 UINT32 RsvdZ2:7;
332 UINT32 Type:6;
333 UINT32 EndpointId:5;
334 UINT32 RsvdZ3:3;
335 UINT32 SlotId:8;
336 } EVT_TRB_TRANSFER;
337
338 //
339 // 6.4.2.2 Command Completion Event TRB
340 // A Command Completion Event TRB shall be generated by the xHC when a command completes on the
341 // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.
342 //
343 typedef struct _EVT_TRB_COMMAND_COMPLETION {
344 UINT32 TRBPtrLo;
345
346 UINT32 TRBPtrHi;
347
348 UINT32 RsvdZ2:24;
349 UINT32 Completecode:8;
350
351 UINT32 CycleBit:1;
352 UINT32 RsvdZ3:9;
353 UINT32 Type:6;
354 UINT32 VFID:8;
355 UINT32 SlotId:8;
356 } EVT_TRB_COMMAND_COMPLETION;
357
358 typedef union _TRB {
359 TRB_TEMPLATE TrbTemplate;
360 TRANSFER_TRB_NORMAL TrbNormal;
361 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;
362 TRANSFER_TRB_CONTROL_DATA TrbCtrData;
363 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;
364 } TRB;
365
366 //
367 // 6.4.3.1 No Op Command TRB
368 // The No Op Command TRB provides a simple means for verifying the operation of the Command Ring
369 // mechanisms offered by the xHCI.
370 //
371 typedef struct _CMD_TRB_NO_OP {
372 UINT32 RsvdZ0;
373 UINT32 RsvdZ1;
374 UINT32 RsvdZ2;
375
376 UINT32 CycleBit:1;
377 UINT32 RsvdZ3:9;
378 UINT32 Type:6;
379 UINT32 RsvdZ4:16;
380 } CMD_TRB_NO_OP;
381
382 //
383 // 6.4.3.2 Enable Slot Command TRB
384 // The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the
385 // selected slot to the host in a Command Completion Event.
386 //
387 typedef struct _CMD_TRB_ENABLE_SLOT {
388 UINT32 RsvdZ0;
389 UINT32 RsvdZ1;
390 UINT32 RsvdZ2;
391
392 UINT32 CycleBit:1;
393 UINT32 RsvdZ3:9;
394 UINT32 Type:6;
395 UINT32 RsvdZ4:16;
396 } CMD_TRB_ENABLE_SLOT;
397
398 //
399 // 6.4.3.3 Disable Slot Command TRB
400 // The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any
401 // internal xHC resources assigned to the slot.
402 //
403 typedef struct _CMD_TRB_DISABLE_SLOT {
404 UINT32 RsvdZ0;
405 UINT32 RsvdZ1;
406 UINT32 RsvdZ2;
407
408 UINT32 CycleBit:1;
409 UINT32 RsvdZ3:9;
410 UINT32 Type:6;
411 UINT32 RsvdZ4:8;
412 UINT32 SlotId:8;
413 } CMD_TRB_DISABLE_SLOT;
414
415 //
416 // 6.4.3.4 Address Device Command TRB
417 // The Address Device Command TRB transitions the selected Device Context from the Default to the
418 // Addressed state and causes the xHC to select an address for the USB device in the Default State and
419 // issue a SET_ADDRESS request to the USB device.
420 //
421 typedef struct _CMD_TRB_ADDRESS_DEVICE {
422 UINT32 PtrLo;
423
424 UINT32 PtrHi;
425
426 UINT32 RsvdZ1;
427
428 UINT32 CycleBit:1;
429 UINT32 RsvdZ2:8;
430 UINT32 BSR:1;
431 UINT32 Type:6;
432 UINT32 RsvdZ3:8;
433 UINT32 SlotId:8;
434 } CMD_TRB_ADDRESS_DEVICE;
435
436 //
437 // 6.4.3.5 Configure Endpoint Command TRB
438 // The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the
439 // endpoints selected by the command.
440 //
441 typedef struct _CMD_TRB_CONFIG_ENDPOINT {
442 UINT32 PtrLo;
443
444 UINT32 PtrHi;
445
446 UINT32 RsvdZ1;
447
448 UINT32 CycleBit:1;
449 UINT32 RsvdZ2:8;
450 UINT32 DC:1;
451 UINT32 Type:6;
452 UINT32 RsvdZ3:8;
453 UINT32 SlotId:8;
454 } CMD_TRB_CONFIG_ENDPOINT;
455
456 //
457 // 6.4.3.6 Evaluate Context Command TRB
458 // The Evaluate Context Command TRB is used by system software to inform the xHC that the selected
459 // Context data structures in the Device Context have been modified by system software and that the xHC
460 // shall evaluate any changes
461 //
462 typedef struct _CMD_TRB_EVALUATE_CONTEXT {
463 UINT32 PtrLo;
464
465 UINT32 PtrHi;
466
467 UINT32 RsvdZ1;
468
469 UINT32 CycleBit:1;
470 UINT32 RsvdZ2:9;
471 UINT32 Type:6;
472 UINT32 RsvdZ3:8;
473 UINT32 SlotId:8;
474 } CMD_TRB_EVALUATE_CONTEXT;
475
476 //
477 // 6.4.3.7 Reset Endpoint Command TRB
478 // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring
479 //
480 typedef struct _CMD_TRB_RESET_ENDPOINT {
481 UINT32 RsvdZ0;
482 UINT32 RsvdZ1;
483 UINT32 RsvdZ2;
484
485 UINT32 CycleBit:1;
486 UINT32 RsvdZ3:8;
487 UINT32 TSP:1;
488 UINT32 Type:6;
489 UINT32 EDID:5;
490 UINT32 RsvdZ4:3;
491 UINT32 SlotId:8;
492 } CMD_TRB_RESET_ENDPOINT;
493
494 //
495 // 6.4.3.8 Stop Endpoint Command TRB
496 // The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a
497 // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.
498 //
499 typedef struct _CMD_TRB_STOP_ENDPOINT {
500 UINT32 RsvdZ0;
501 UINT32 RsvdZ1;
502 UINT32 RsvdZ2;
503
504 UINT32 CycleBit:1;
505 UINT32 RsvdZ3:9;
506 UINT32 Type:6;
507 UINT32 EDID:5;
508 UINT32 RsvdZ4:2;
509 UINT32 SP:1;
510 UINT32 SlotId:8;
511 } CMD_TRB_STOP_ENDPOINT;
512
513 //
514 // 6.4.3.9 Set TR Dequeue Pointer Command TRB
515 // The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue
516 // Pointer and DCS fields of an Endpoint or Stream Context.
517 //
518 typedef struct _CMD_SET_TR_DEQ_POINTER {
519 UINT32 PtrLo;
520
521 UINT32 PtrHi;
522
523 UINT32 RsvdZ1:16;
524 UINT32 StreamID:16;
525
526 UINT32 CycleBit:1;
527 UINT32 RsvdZ2:9;
528 UINT32 Type:6;
529 UINT32 Endpoint:5;
530 UINT32 RsvdZ3:3;
531 UINT32 SlotId:8;
532 } CMD_SET_TR_DEQ_POINTER;
533
534 //
535 // 6.4.4.1 Link TRB
536 // A Link TRB provides support for non-contiguous TRB Rings.
537 //
538 typedef struct _LINK_TRB {
539 UINT32 PtrLo;
540
541 UINT32 PtrHi;
542
543 UINT32 RsvdZ1:22;
544 UINT32 InterTarget:10;
545
546 UINT32 CycleBit:1;
547 UINT32 TC:1;
548 UINT32 RsvdZ2:2;
549 UINT32 CH:1;
550 UINT32 IOC:1;
551 UINT32 RsvdZ3:4;
552 UINT32 Type:6;
553 UINT32 RsvdZ4:16;
554 } LINK_TRB;
555
556 //
557 // 6.2.2 Slot Context
558 //
559 typedef struct _SLOT_CONTEXT {
560 UINT32 RouteString:20;
561 UINT32 Speed:4;
562 UINT32 RsvdZ1:1;
563 UINT32 MTT:1;
564 UINT32 Hub:1;
565 UINT32 ContextEntries:5;
566
567 UINT32 MaxExitLatency:16;
568 UINT32 RootHubPortNum:8;
569 UINT32 PortNum:8;
570
571 UINT32 TTHubSlotId:8;
572 UINT32 TTPortNum:8;
573 UINT32 TTT:2;
574 UINT32 RsvdZ2:4;
575 UINT32 InterTarget:10;
576
577 UINT32 DeviceAddress:8;
578 UINT32 RsvdZ3:19;
579 UINT32 SlotState:5;
580
581 UINT32 RsvdZ4;
582 UINT32 RsvdZ5;
583 UINT32 RsvdZ6;
584 UINT32 RsvdZ7;
585 } SLOT_CONTEXT;
586
587 typedef struct _SLOT_CONTEXT_64 {
588 UINT32 RouteString:20;
589 UINT32 Speed:4;
590 UINT32 RsvdZ1:1;
591 UINT32 MTT:1;
592 UINT32 Hub:1;
593 UINT32 ContextEntries:5;
594
595 UINT32 MaxExitLatency:16;
596 UINT32 RootHubPortNum:8;
597 UINT32 PortNum:8;
598
599 UINT32 TTHubSlotId:8;
600 UINT32 TTPortNum:8;
601 UINT32 TTT:2;
602 UINT32 RsvdZ2:4;
603 UINT32 InterTarget:10;
604
605 UINT32 DeviceAddress:8;
606 UINT32 RsvdZ3:19;
607 UINT32 SlotState:5;
608
609 UINT32 RsvdZ4;
610 UINT32 RsvdZ5;
611 UINT32 RsvdZ6;
612 UINT32 RsvdZ7;
613
614 UINT32 RsvdZ8;
615 UINT32 RsvdZ9;
616 UINT32 RsvdZ10;
617 UINT32 RsvdZ11;
618
619 UINT32 RsvdZ12;
620 UINT32 RsvdZ13;
621 UINT32 RsvdZ14;
622 UINT32 RsvdZ15;
623
624 } SLOT_CONTEXT_64;
625
626
627 //
628 // 6.2.3 Endpoint Context
629 //
630 typedef struct _ENDPOINT_CONTEXT {
631 UINT32 EPState:3;
632 UINT32 RsvdZ1:5;
633 UINT32 Mult:2;
634 UINT32 MaxPStreams:5;
635 UINT32 LSA:1;
636 UINT32 Interval:8;
637 UINT32 RsvdZ2:8;
638
639 UINT32 RsvdZ3:1;
640 UINT32 CErr:2;
641 UINT32 EPType:3;
642 UINT32 RsvdZ4:1;
643 UINT32 HID:1;
644 UINT32 MaxBurstSize:8;
645 UINT32 MaxPacketSize:16;
646
647 UINT32 PtrLo;
648
649 UINT32 PtrHi;
650
651 UINT32 AverageTRBLength:16;
652 UINT32 MaxESITPayload:16;
653
654 UINT32 RsvdZ5;
655 UINT32 RsvdZ6;
656 UINT32 RsvdZ7;
657 } ENDPOINT_CONTEXT;
658
659 typedef struct _ENDPOINT_CONTEXT_64 {
660 UINT32 EPState:3;
661 UINT32 RsvdZ1:5;
662 UINT32 Mult:2;
663 UINT32 MaxPStreams:5;
664 UINT32 LSA:1;
665 UINT32 Interval:8;
666 UINT32 RsvdZ2:8;
667
668 UINT32 RsvdZ3:1;
669 UINT32 CErr:2;
670 UINT32 EPType:3;
671 UINT32 RsvdZ4:1;
672 UINT32 HID:1;
673 UINT32 MaxBurstSize:8;
674 UINT32 MaxPacketSize:16;
675
676 UINT32 PtrLo;
677
678 UINT32 PtrHi;
679
680 UINT32 AverageTRBLength:16;
681 UINT32 MaxESITPayload:16;
682
683 UINT32 RsvdZ5;
684 UINT32 RsvdZ6;
685 UINT32 RsvdZ7;
686
687 UINT32 RsvdZ8;
688 UINT32 RsvdZ9;
689 UINT32 RsvdZ10;
690 UINT32 RsvdZ11;
691
692 UINT32 RsvdZ12;
693 UINT32 RsvdZ13;
694 UINT32 RsvdZ14;
695 UINT32 RsvdZ15;
696
697 } ENDPOINT_CONTEXT_64;
698
699
700 //
701 // 6.2.5.1 Input Control Context
702 //
703 typedef struct _INPUT_CONTRL_CONTEXT {
704 UINT32 Dword1;
705 UINT32 Dword2;
706 UINT32 RsvdZ1;
707 UINT32 RsvdZ2;
708 UINT32 RsvdZ3;
709 UINT32 RsvdZ4;
710 UINT32 RsvdZ5;
711 UINT32 RsvdZ6;
712 } INPUT_CONTRL_CONTEXT;
713
714 typedef struct _INPUT_CONTRL_CONTEXT_64 {
715 UINT32 Dword1;
716 UINT32 Dword2;
717 UINT32 RsvdZ1;
718 UINT32 RsvdZ2;
719 UINT32 RsvdZ3;
720 UINT32 RsvdZ4;
721 UINT32 RsvdZ5;
722 UINT32 RsvdZ6;
723 UINT32 RsvdZ7;
724 UINT32 RsvdZ8;
725 UINT32 RsvdZ9;
726 UINT32 RsvdZ10;
727 UINT32 RsvdZ11;
728 UINT32 RsvdZ12;
729 UINT32 RsvdZ13;
730 UINT32 RsvdZ14;
731 } INPUT_CONTRL_CONTEXT_64;
732
733 //
734 // 6.2.1 Device Context
735 //
736 typedef struct _DEVICE_CONTEXT {
737 SLOT_CONTEXT Slot;
738 ENDPOINT_CONTEXT EP[31];
739 } DEVICE_CONTEXT;
740
741 typedef struct _DEVICE_CONTEXT_64 {
742 SLOT_CONTEXT_64 Slot;
743 ENDPOINT_CONTEXT_64 EP[31];
744 } DEVICE_CONTEXT_64;
745
746 //
747 // 6.2.5 Input Context
748 //
749 typedef struct _INPUT_CONTEXT {
750 INPUT_CONTRL_CONTEXT InputControlContext;
751 SLOT_CONTEXT Slot;
752 ENDPOINT_CONTEXT EP[31];
753 } INPUT_CONTEXT;
754
755 typedef struct _INPUT_CONTEXT_64 {
756 INPUT_CONTRL_CONTEXT_64 InputControlContext;
757 SLOT_CONTEXT_64 Slot;
758 ENDPOINT_CONTEXT_64 EP[31];
759 } INPUT_CONTEXT_64;
760
761 /**
762 Execute the transfer by polling the URB. This is a synchronous operation.
763
764 @param Xhc The XHCI device.
765 @param CmdTransfer The executed URB is for cmd transfer or not.
766 @param Urb The URB to execute.
767 @param Timeout The time to wait before abort, in millisecond.
768
769 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.
770 @return EFI_TIMEOUT The transfer failed due to time out.
771 @return EFI_SUCCESS The transfer finished OK.
772
773 **/
774 EFI_STATUS
775 XhcPeiExecTransfer (
776 IN PEI_XHC_DEV *Xhc,
777 IN BOOLEAN CmdTransfer,
778 IN URB *Urb,
779 IN UINTN Timeout
780 );
781
782 /**
783 Find out the actual device address according to the requested device address from UsbBus.
784
785 @param Xhc The XHCI device.
786 @param BusDevAddr The requested device address by UsbBus upper driver.
787
788 @return The actual device address assigned to the device.
789
790 **/
791 UINT8
792 XhcPeiBusDevAddrToSlotId (
793 IN PEI_XHC_DEV *Xhc,
794 IN UINT8 BusDevAddr
795 );
796
797 /**
798 Find out the slot id according to the device's route string.
799
800 @param Xhc The XHCI device.
801 @param RouteString The route string described the device location.
802
803 @return The slot id used by the device.
804
805 **/
806 UINT8
807 XhcPeiRouteStringToSlotId (
808 IN PEI_XHC_DEV *Xhc,
809 IN USB_DEV_ROUTE RouteString
810 );
811
812 /**
813 Calculate the device context index by endpoint address and direction.
814
815 @param EpAddr The target endpoint number.
816 @param Direction The direction of the target endpoint.
817
818 @return The device context index of endpoint.
819
820 **/
821 UINT8
822 XhcPeiEndpointToDci (
823 IN UINT8 EpAddr,
824 IN EFI_USB_DATA_DIRECTION Direction
825 );
826
827 /**
828 Ring the door bell to notify XHCI there is a transaction to be executed.
829
830 @param Xhc The XHCI device.
831 @param SlotId The slot id of the target device.
832 @param Dci The device context index of the target slot or endpoint.
833
834 **/
835 VOID
836 XhcPeiRingDoorBell (
837 IN PEI_XHC_DEV *Xhc,
838 IN UINT8 SlotId,
839 IN UINT8 Dci
840 );
841
842 /**
843 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.
844
845 @param Xhc The XHCI device.
846 @param ParentRouteChart The route string pointed to the parent device if it exists.
847 @param Port The port to be polled.
848 @param PortState The port state.
849
850 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.
851 @retval Others Should not appear.
852
853 **/
854 EFI_STATUS
855 XhcPeiPollPortStatusChange (
856 IN PEI_XHC_DEV *Xhc,
857 IN USB_DEV_ROUTE ParentRouteChart,
858 IN UINT8 Port,
859 IN EFI_USB_PORT_STATUS *PortState
860 );
861
862 /**
863 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
864
865 @param Xhc The XHCI device.
866 @param SlotId The slot id to be configured.
867 @param PortNum The total number of downstream port supported by the hub.
868 @param TTT The TT think time of the hub device.
869 @param MTT The multi-TT of the hub device.
870
871 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
872
873 **/
874 EFI_STATUS
875 XhcPeiConfigHubContext (
876 IN PEI_XHC_DEV *Xhc,
877 IN UINT8 SlotId,
878 IN UINT8 PortNum,
879 IN UINT8 TTT,
880 IN UINT8 MTT
881 );
882
883 /**
884 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.
885
886 @param Xhc The XHCI device.
887 @param SlotId The slot id to be configured.
888 @param PortNum The total number of downstream port supported by the hub.
889 @param TTT The TT think time of the hub device.
890 @param MTT The multi-TT of the hub device.
891
892 @retval EFI_SUCCESS Successfully configure the hub device's slot context.
893
894 **/
895 EFI_STATUS
896 XhcPeiConfigHubContext64 (
897 IN PEI_XHC_DEV *Xhc,
898 IN UINT8 SlotId,
899 IN UINT8 PortNum,
900 IN UINT8 TTT,
901 IN UINT8 MTT
902 );
903
904 /**
905 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
906
907 @param Xhc The XHCI device.
908 @param SlotId The slot id to be configured.
909 @param DeviceSpeed The device's speed.
910 @param ConfigDesc The pointer to the usb device configuration descriptor.
911
912 @retval EFI_SUCCESS Successfully configure all the device endpoints.
913
914 **/
915 EFI_STATUS
916 XhcPeiSetConfigCmd (
917 IN PEI_XHC_DEV *Xhc,
918 IN UINT8 SlotId,
919 IN UINT8 DeviceSpeed,
920 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
921 );
922
923 /**
924 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.
925
926 @param Xhc The XHCI device.
927 @param SlotId The slot id to be configured.
928 @param DeviceSpeed The device's speed.
929 @param ConfigDesc The pointer to the usb device configuration descriptor.
930
931 @retval EFI_SUCCESS Successfully configure all the device endpoints.
932
933 **/
934 EFI_STATUS
935 XhcPeiSetConfigCmd64 (
936 IN PEI_XHC_DEV *Xhc,
937 IN UINT8 SlotId,
938 IN UINT8 DeviceSpeed,
939 IN USB_CONFIG_DESCRIPTOR *ConfigDesc
940 );
941
942 /**
943 Stop endpoint through XHCI's Stop_Endpoint cmd.
944
945 @param Xhc The XHCI device.
946 @param SlotId The slot id of the target device.
947 @param Dci The device context index of the target slot or endpoint.
948
949 @retval EFI_SUCCESS Stop endpoint successfully.
950 @retval Others Failed to stop endpoint.
951
952 **/
953 EFI_STATUS
954 EFIAPI
955 XhcPeiStopEndpoint (
956 IN PEI_XHC_DEV *Xhc,
957 IN UINT8 SlotId,
958 IN UINT8 Dci
959 );
960
961 /**
962 Reset endpoint through XHCI's Reset_Endpoint cmd.
963
964 @param Xhc The XHCI device.
965 @param SlotId The slot id of the target device.
966 @param Dci The device context index of the target slot or endpoint.
967
968 @retval EFI_SUCCESS Reset endpoint successfully.
969 @retval Others Failed to reset endpoint.
970
971 **/
972 EFI_STATUS
973 EFIAPI
974 XhcPeiResetEndpoint (
975 IN PEI_XHC_DEV *Xhc,
976 IN UINT8 SlotId,
977 IN UINT8 Dci
978 );
979
980 /**
981 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.
982
983 @param Xhc The XHCI device.
984 @param SlotId The slot id of the target device.
985 @param Dci The device context index of the target slot or endpoint.
986 @param Urb The dequeue pointer of the transfer ring specified
987 by the urb to be updated.
988
989 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.
990 @retval Others Failed to set transfer ring dequeue pointer.
991
992 **/
993 EFI_STATUS
994 EFIAPI
995 XhcPeiSetTrDequeuePointer (
996 IN PEI_XHC_DEV *Xhc,
997 IN UINT8 SlotId,
998 IN UINT8 Dci,
999 IN URB *Urb
1000 );
1001
1002 /**
1003 Assign and initialize the device slot for a new device.
1004
1005 @param Xhc The XHCI device.
1006 @param ParentRouteChart The route string pointed to the parent device.
1007 @param ParentPort The port at which the device is located.
1008 @param RouteChart The route string pointed to the device.
1009 @param DeviceSpeed The device speed.
1010
1011 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1012 @retval Others Fail to initialize device slot.
1013
1014 **/
1015 EFI_STATUS
1016 XhcPeiInitializeDeviceSlot (
1017 IN PEI_XHC_DEV *Xhc,
1018 IN USB_DEV_ROUTE ParentRouteChart,
1019 IN UINT16 ParentPort,
1020 IN USB_DEV_ROUTE RouteChart,
1021 IN UINT8 DeviceSpeed
1022 );
1023
1024 /**
1025 Assign and initialize the device slot for a new device.
1026
1027 @param Xhc The XHCI device.
1028 @param ParentRouteChart The route string pointed to the parent device.
1029 @param ParentPort The port at which the device is located.
1030 @param RouteChart The route string pointed to the device.
1031 @param DeviceSpeed The device speed.
1032
1033 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.
1034 @retval Others Fail to initialize device slot.
1035
1036 **/
1037 EFI_STATUS
1038 XhcPeiInitializeDeviceSlot64 (
1039 IN PEI_XHC_DEV *Xhc,
1040 IN USB_DEV_ROUTE ParentRouteChart,
1041 IN UINT16 ParentPort,
1042 IN USB_DEV_ROUTE RouteChart,
1043 IN UINT8 DeviceSpeed
1044 );
1045
1046 /**
1047 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1048
1049 @param Xhc The XHCI device.
1050 @param SlotId The slot id to be evaluated.
1051 @param MaxPacketSize The max packet size supported by the device control transfer.
1052
1053 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1054
1055 **/
1056 EFI_STATUS
1057 XhcPeiEvaluateContext (
1058 IN PEI_XHC_DEV *Xhc,
1059 IN UINT8 SlotId,
1060 IN UINT32 MaxPacketSize
1061 );
1062
1063 /**
1064 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.
1065
1066 @param Xhc The XHCI device.
1067 @param SlotId The slot id to be evaluated.
1068 @param MaxPacketSize The max packet size supported by the device control transfer.
1069
1070 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.
1071
1072 **/
1073 EFI_STATUS
1074 XhcPeiEvaluateContext64 (
1075 IN PEI_XHC_DEV *Xhc,
1076 IN UINT8 SlotId,
1077 IN UINT32 MaxPacketSize
1078 );
1079
1080 /**
1081 Disable the specified device slot.
1082
1083 @param Xhc The XHCI device.
1084 @param SlotId The slot id to be disabled.
1085
1086 @retval EFI_SUCCESS Successfully disable the device slot.
1087
1088 **/
1089 EFI_STATUS
1090 XhcPeiDisableSlotCmd (
1091 IN PEI_XHC_DEV *Xhc,
1092 IN UINT8 SlotId
1093 );
1094
1095 /**
1096 Disable the specified device slot.
1097
1098 @param Xhc The XHCI device.
1099 @param SlotId The slot id to be disabled.
1100
1101 @retval EFI_SUCCESS Successfully disable the device slot.
1102
1103 **/
1104 EFI_STATUS
1105 XhcPeiDisableSlotCmd64 (
1106 IN PEI_XHC_DEV *Xhc,
1107 IN UINT8 SlotId
1108 );
1109
1110 /**
1111 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted
1112 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint
1113 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is
1114 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the
1115 Stopped to the Running state.
1116
1117 @param Xhc The XHCI device.
1118 @param Urb The urb which makes the endpoint halted.
1119
1120 @retval EFI_SUCCESS The recovery is successful.
1121 @retval Others Failed to recovery halted endpoint.
1122
1123 **/
1124 EFI_STATUS
1125 XhcPeiRecoverHaltedEndpoint (
1126 IN PEI_XHC_DEV *Xhc,
1127 IN URB *Urb
1128 );
1129
1130 /**
1131 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer
1132 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to
1133 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running
1134 state.
1135
1136 @param Xhc The XHCI device.
1137 @param Urb The urb which doesn't get completed in a specified timeout range.
1138
1139 @retval EFI_SUCCESS The dequeuing of the TDs is successful.
1140 @retval Others Failed to stop the endpoint and dequeue the TDs.
1141
1142 **/
1143 EFI_STATUS
1144 XhcPeiDequeueTrbFromEndpoint (
1145 IN PEI_XHC_DEV *Xhc,
1146 IN URB *Urb
1147 );
1148
1149 /**
1150 Create a new URB for a new transaction.
1151
1152 @param Xhc The XHCI device
1153 @param DevAddr The device address
1154 @param EpAddr Endpoint addrress
1155 @param DevSpeed The device speed
1156 @param MaxPacket The max packet length of the endpoint
1157 @param Type The transaction type
1158 @param Request The standard USB request for control transfer
1159 @param Data The user data to transfer
1160 @param DataLen The length of data buffer
1161 @param Callback The function to call when data is transferred
1162 @param Context The context to the callback
1163
1164 @return Created URB or NULL
1165
1166 **/
1167 URB*
1168 XhcPeiCreateUrb (
1169 IN PEI_XHC_DEV *Xhc,
1170 IN UINT8 DevAddr,
1171 IN UINT8 EpAddr,
1172 IN UINT8 DevSpeed,
1173 IN UINTN MaxPacket,
1174 IN UINTN Type,
1175 IN EFI_USB_DEVICE_REQUEST *Request,
1176 IN VOID *Data,
1177 IN UINTN DataLen,
1178 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,
1179 IN VOID *Context
1180 );
1181
1182 /**
1183 Free an allocated URB.
1184
1185 @param Xhc The XHCI device.
1186 @param Urb The URB to free.
1187
1188 **/
1189 VOID
1190 XhcPeiFreeUrb (
1191 IN PEI_XHC_DEV *Xhc,
1192 IN URB *Urb
1193 );
1194
1195 /**
1196 Create a transfer TRB.
1197
1198 @param Xhc The XHCI device
1199 @param Urb The urb used to construct the transfer TRB.
1200
1201 @return Created TRB or NULL
1202
1203 **/
1204 EFI_STATUS
1205 XhcPeiCreateTransferTrb (
1206 IN PEI_XHC_DEV *Xhc,
1207 IN URB *Urb
1208 );
1209
1210 /**
1211 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.
1212
1213 @param Xhc The XHCI device.
1214 @param TrsRing The transfer ring to sync.
1215
1216 @retval EFI_SUCCESS The transfer ring is synchronized successfully.
1217
1218 **/
1219 EFI_STATUS
1220 XhcPeiSyncTrsRing (
1221 IN PEI_XHC_DEV *Xhc,
1222 IN TRANSFER_RING *TrsRing
1223 );
1224
1225 /**
1226 Create XHCI transfer ring.
1227
1228 @param Xhc The XHCI Device.
1229 @param TrbNum The number of TRB in the ring.
1230 @param TransferRing The created transfer ring.
1231
1232 **/
1233 VOID
1234 XhcPeiCreateTransferRing (
1235 IN PEI_XHC_DEV *Xhc,
1236 IN UINTN TrbNum,
1237 OUT TRANSFER_RING *TransferRing
1238 );
1239
1240 /**
1241 Check if there is a new generated event.
1242
1243 @param Xhc The XHCI device.
1244 @param EvtRing The event ring to check.
1245 @param NewEvtTrb The new event TRB found.
1246
1247 @retval EFI_SUCCESS Found a new event TRB at the event ring.
1248 @retval EFI_NOT_READY The event ring has no new event.
1249
1250 **/
1251 EFI_STATUS
1252 XhcPeiCheckNewEvent (
1253 IN PEI_XHC_DEV *Xhc,
1254 IN EVENT_RING *EvtRing,
1255 OUT TRB_TEMPLATE **NewEvtTrb
1256 );
1257
1258 /**
1259 Synchronize the specified event ring to update the enqueue and dequeue pointer.
1260
1261 @param Xhc The XHCI device.
1262 @param EvtRing The event ring to sync.
1263
1264 @retval EFI_SUCCESS The event ring is synchronized successfully.
1265
1266 **/
1267 EFI_STATUS
1268 XhcPeiSyncEventRing (
1269 IN PEI_XHC_DEV *Xhc,
1270 IN EVENT_RING *EvtRing
1271 );
1272
1273 /**
1274 Create XHCI event ring.
1275
1276 @param Xhc The XHCI device.
1277 @param EventRing The created event ring.
1278
1279 **/
1280 VOID
1281 XhcPeiCreateEventRing (
1282 IN PEI_XHC_DEV *Xhc,
1283 OUT EVENT_RING *EventRing
1284 );
1285
1286 /**
1287 Initialize the XHCI host controller for schedule.
1288
1289 @param Xhc The XHCI device to be initialized.
1290
1291 **/
1292 VOID
1293 XhcPeiInitSched (
1294 IN PEI_XHC_DEV *Xhc
1295 );
1296
1297 /**
1298 Free the resouce allocated at initializing schedule.
1299
1300 @param Xhc The XHCI device.
1301
1302 **/
1303 VOID
1304 XhcPeiFreeSched (
1305 IN PEI_XHC_DEV *Xhc
1306 );
1307
1308 #endif
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