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MdeModulePkg/SdMmcPciHcDxe: Use BaseClk if the target clock is larger
[mirror_edk2.git] / MdeModulePkg / Bus / Sd / SdBlockIoPei / SdHci.c
1 /** @file
2
3 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
4 This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php.
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 **/
13
14 #include "SdBlockIoPei.h"
15
16 /**
17 Read/Write specified SD host controller mmio register.
18
19 @param[in] Address The address of the mmio register to be read/written.
20 @param[in] Read A boolean to indicate it's read or write operation.
21 @param[in] Count The width of the mmio register in bytes.
22 Must be 1, 2 , 4 or 8 bytes.
23 @param[in, out] Data For read operations, the destination buffer to store
24 the results. For write operations, the source buffer
25 to write data from. The caller is responsible for
26 having ownership of the data buffer and ensuring its
27 size not less than Count bytes.
28
29 @retval EFI_INVALID_PARAMETER The Address or the Data or the Count is not valid.
30 @retval EFI_SUCCESS The read/write operation succeeds.
31 @retval Others The read/write operation fails.
32
33 **/
34 EFI_STATUS
35 EFIAPI
36 SdPeimHcRwMmio (
37 IN UINTN Address,
38 IN BOOLEAN Read,
39 IN UINT8 Count,
40 IN OUT VOID *Data
41 )
42 {
43 if ((Address == 0) || (Data == NULL)) {
44 return EFI_INVALID_PARAMETER;
45 }
46
47 if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
48 return EFI_INVALID_PARAMETER;
49 }
50
51 switch (Count) {
52 case 1:
53 if (Read) {
54 *(UINT8*)Data = MmioRead8 (Address);
55 } else {
56 MmioWrite8 (Address, *(UINT8*)Data);
57 }
58 break;
59 case 2:
60 if (Read) {
61 *(UINT16*)Data = MmioRead16 (Address);
62 } else {
63 MmioWrite16 (Address, *(UINT16*)Data);
64 }
65 break;
66 case 4:
67 if (Read) {
68 *(UINT32*)Data = MmioRead32 (Address);
69 } else {
70 MmioWrite32 (Address, *(UINT32*)Data);
71 }
72 break;
73 case 8:
74 if (Read) {
75 *(UINT64*)Data = MmioRead64 (Address);
76 } else {
77 MmioWrite64 (Address, *(UINT64*)Data);
78 }
79 break;
80 default:
81 ASSERT (FALSE);
82 return EFI_INVALID_PARAMETER;
83 }
84
85 return EFI_SUCCESS;
86 }
87
88 /**
89 Do OR operation with the value of the specified SD host controller mmio register.
90
91 @param[in] Address The address of the mmio register to be read/written.
92 @param[in] Count The width of the mmio register in bytes.
93 Must be 1, 2 , 4 or 8 bytes.
94 @param[in] OrData The pointer to the data used to do OR operation.
95 The caller is responsible for having ownership of
96 the data buffer and ensuring its size not less than
97 Count bytes.
98
99 @retval EFI_INVALID_PARAMETER The Address or the OrData or the Count is not valid.
100 @retval EFI_SUCCESS The OR operation succeeds.
101 @retval Others The OR operation fails.
102
103 **/
104 EFI_STATUS
105 EFIAPI
106 SdPeimHcOrMmio (
107 IN UINTN Address,
108 IN UINT8 Count,
109 IN VOID *OrData
110 )
111 {
112 EFI_STATUS Status;
113 UINT64 Data;
114 UINT64 Or;
115
116 Status = SdPeimHcRwMmio (Address, TRUE, Count, &Data);
117 if (EFI_ERROR (Status)) {
118 return Status;
119 }
120
121 if (Count == 1) {
122 Or = *(UINT8*) OrData;
123 } else if (Count == 2) {
124 Or = *(UINT16*) OrData;
125 } else if (Count == 4) {
126 Or = *(UINT32*) OrData;
127 } else if (Count == 8) {
128 Or = *(UINT64*) OrData;
129 } else {
130 return EFI_INVALID_PARAMETER;
131 }
132
133 Data |= Or;
134 Status = SdPeimHcRwMmio (Address, FALSE, Count, &Data);
135
136 return Status;
137 }
138
139 /**
140 Do AND operation with the value of the specified SD host controller mmio register.
141
142 @param[in] Address The address of the mmio register to be read/written.
143 @param[in] Count The width of the mmio register in bytes.
144 Must be 1, 2 , 4 or 8 bytes.
145 @param[in] AndData The pointer to the data used to do AND operation.
146 The caller is responsible for having ownership of
147 the data buffer and ensuring its size not less than
148 Count bytes.
149
150 @retval EFI_INVALID_PARAMETER The Address or the AndData or the Count is not valid.
151 @retval EFI_SUCCESS The AND operation succeeds.
152 @retval Others The AND operation fails.
153
154 **/
155 EFI_STATUS
156 EFIAPI
157 SdPeimHcAndMmio (
158 IN UINTN Address,
159 IN UINT8 Count,
160 IN VOID *AndData
161 )
162 {
163 EFI_STATUS Status;
164 UINT64 Data;
165 UINT64 And;
166
167 Status = SdPeimHcRwMmio (Address, TRUE, Count, &Data);
168 if (EFI_ERROR (Status)) {
169 return Status;
170 }
171
172 if (Count == 1) {
173 And = *(UINT8*) AndData;
174 } else if (Count == 2) {
175 And = *(UINT16*) AndData;
176 } else if (Count == 4) {
177 And = *(UINT32*) AndData;
178 } else if (Count == 8) {
179 And = *(UINT64*) AndData;
180 } else {
181 return EFI_INVALID_PARAMETER;
182 }
183
184 Data &= And;
185 Status = SdPeimHcRwMmio (Address, FALSE, Count, &Data);
186
187 return Status;
188 }
189
190 /**
191 Wait for the value of the specified MMIO register set to the test value.
192
193 @param[in] Address The address of the mmio register to be checked.
194 @param[in] Count The width of the mmio register in bytes.
195 Must be 1, 2, 4 or 8 bytes.
196 @param[in] MaskValue The mask value of memory.
197 @param[in] TestValue The test value of memory.
198
199 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
200 @retval EFI_SUCCESS The MMIO register has expected value.
201 @retval Others The MMIO operation fails.
202
203 **/
204 EFI_STATUS
205 EFIAPI
206 SdPeimHcCheckMmioSet (
207 IN UINTN Address,
208 IN UINT8 Count,
209 IN UINT64 MaskValue,
210 IN UINT64 TestValue
211 )
212 {
213 EFI_STATUS Status;
214 UINT64 Value;
215
216 //
217 // Access PCI MMIO space to see if the value is the tested one.
218 //
219 Value = 0;
220 Status = SdPeimHcRwMmio (Address, TRUE, Count, &Value);
221 if (EFI_ERROR (Status)) {
222 return Status;
223 }
224
225 Value &= MaskValue;
226
227 if (Value == TestValue) {
228 return EFI_SUCCESS;
229 }
230
231 return EFI_NOT_READY;
232 }
233
234 /**
235 Wait for the value of the specified MMIO register set to the test value.
236
237 @param[in] Address The address of the mmio register to wait.
238 @param[in] Count The width of the mmio register in bytes.
239 Must be 1, 2, 4 or 8 bytes.
240 @param[in] MaskValue The mask value of memory.
241 @param[in] TestValue The test value of memory.
242 @param[in] Timeout The time out value for wait memory set, uses 1
243 microsecond as a unit.
244
245 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
246 range.
247 @retval EFI_SUCCESS The MMIO register has expected value.
248 @retval Others The MMIO operation fails.
249
250 **/
251 EFI_STATUS
252 EFIAPI
253 SdPeimHcWaitMmioSet (
254 IN UINTN Address,
255 IN UINT8 Count,
256 IN UINT64 MaskValue,
257 IN UINT64 TestValue,
258 IN UINT64 Timeout
259 )
260 {
261 EFI_STATUS Status;
262 BOOLEAN InfiniteWait;
263
264 if (Timeout == 0) {
265 InfiniteWait = TRUE;
266 } else {
267 InfiniteWait = FALSE;
268 }
269
270 while (InfiniteWait || (Timeout > 0)) {
271 Status = SdPeimHcCheckMmioSet (
272 Address,
273 Count,
274 MaskValue,
275 TestValue
276 );
277 if (Status != EFI_NOT_READY) {
278 return Status;
279 }
280
281 //
282 // Stall for 1 microsecond.
283 //
284 MicroSecondDelay (1);
285
286 Timeout--;
287 }
288
289 return EFI_TIMEOUT;
290 }
291
292 /**
293 Software reset the specified SD host controller and enable all interrupts.
294
295 @param[in] Bar The mmio base address of the slot to be accessed.
296
297 @retval EFI_SUCCESS The software reset executes successfully.
298 @retval Others The software reset fails.
299
300 **/
301 EFI_STATUS
302 SdPeimHcReset (
303 IN UINTN Bar
304 )
305 {
306 EFI_STATUS Status;
307 UINT8 SwReset;
308
309 SwReset = 0xFF;
310 Status = SdPeimHcRwMmio (Bar + SD_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);
311
312 if (EFI_ERROR (Status)) {
313 DEBUG ((EFI_D_ERROR, "SdPeimHcReset: write full 1 fails: %r\n", Status));
314 return Status;
315 }
316
317 Status = SdPeimHcWaitMmioSet (
318 Bar + SD_HC_SW_RST,
319 sizeof (SwReset),
320 0xFF,
321 0x00,
322 SD_TIMEOUT
323 );
324 if (EFI_ERROR (Status)) {
325 DEBUG ((EFI_D_INFO, "SdPeimHcReset: reset done with %r\n", Status));
326 return Status;
327 }
328 //
329 // Enable all interrupt after reset all.
330 //
331 Status = SdPeimHcEnableInterrupt (Bar);
332
333 return Status;
334 }
335
336 /**
337 Set all interrupt status bits in Normal and Error Interrupt Status Enable
338 register.
339
340 @param[in] Bar The mmio base address of the slot to be accessed.
341
342 @retval EFI_SUCCESS The operation executes successfully.
343 @retval Others The operation fails.
344
345 **/
346 EFI_STATUS
347 SdPeimHcEnableInterrupt (
348 IN UINTN Bar
349 )
350 {
351 EFI_STATUS Status;
352 UINT16 IntStatus;
353
354 //
355 // Enable all bits in Error Interrupt Status Enable Register
356 //
357 IntStatus = 0xFFFF;
358 Status = SdPeimHcRwMmio (Bar + SD_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
359 if (EFI_ERROR (Status)) {
360 return Status;
361 }
362 //
363 // Enable all bits in Normal Interrupt Status Enable Register
364 //
365 IntStatus = 0xFFFF;
366 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
367
368 return Status;
369 }
370
371 /**
372 Get the capability data from the specified slot.
373
374 @param[in] Bar The mmio base address of the slot to be accessed.
375 @param[out] Capability The buffer to store the capability data.
376
377 @retval EFI_SUCCESS The operation executes successfully.
378 @retval Others The operation fails.
379
380 **/
381 EFI_STATUS
382 SdPeimHcGetCapability (
383 IN UINTN Bar,
384 OUT SD_HC_SLOT_CAP *Capability
385 )
386 {
387 EFI_STATUS Status;
388 UINT64 Cap;
389
390 Status = SdPeimHcRwMmio (Bar + SD_HC_CAP, TRUE, sizeof (Cap), &Cap);
391 if (EFI_ERROR (Status)) {
392 return Status;
393 }
394
395 CopyMem (Capability, &Cap, sizeof (Cap));
396
397 return EFI_SUCCESS;
398 }
399
400 /**
401 Detect whether there is a SD card attached at the specified SD host controller
402 slot.
403
404 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
405
406 @param[in] Bar The mmio base address of the slot to be accessed.
407
408 @retval EFI_SUCCESS There is a SD card attached.
409 @retval EFI_NO_MEDIA There is not a SD card attached.
410 @retval Others The detection fails.
411
412 **/
413 EFI_STATUS
414 SdPeimHcCardDetect (
415 IN UINTN Bar
416 )
417 {
418 EFI_STATUS Status;
419 UINT16 Data;
420 UINT32 PresentState;
421
422 //
423 // Check Normal Interrupt Status Register
424 //
425 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
426 if (EFI_ERROR (Status)) {
427 return Status;
428 }
429
430 if ((Data & (BIT6 | BIT7)) != 0) {
431 //
432 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
433 //
434 Data &= BIT6 | BIT7;
435 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
436 if (EFI_ERROR (Status)) {
437 return Status;
438 }
439 }
440
441 //
442 // Check Present State Register to see if there is a card presented.
443 //
444 Status = SdPeimHcRwMmio (Bar + SD_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
445 if (EFI_ERROR (Status)) {
446 return Status;
447 }
448
449 if ((PresentState & BIT16) != 0) {
450 return EFI_SUCCESS;
451 } else {
452 return EFI_NO_MEDIA;
453 }
454 }
455
456 /**
457 Stop SD card clock.
458
459 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
460
461 @param[in] Bar The mmio base address of the slot to be accessed.
462
463 @retval EFI_SUCCESS Succeed to stop SD clock.
464 @retval Others Fail to stop SD clock.
465
466 **/
467 EFI_STATUS
468 SdPeimHcStopClock (
469 IN UINTN Bar
470 )
471 {
472 EFI_STATUS Status;
473 UINT32 PresentState;
474 UINT16 ClockCtrl;
475
476 //
477 // Ensure no SD transactions are occurring on the SD Bus by
478 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
479 // in the Present State register to be 0.
480 //
481 Status = SdPeimHcWaitMmioSet (
482 Bar + SD_HC_PRESENT_STATE,
483 sizeof (PresentState),
484 BIT0 | BIT1,
485 0,
486 SD_TIMEOUT
487 );
488 if (EFI_ERROR (Status)) {
489 return Status;
490 }
491
492 //
493 // Set SD Clock Enable in the Clock Control register to 0
494 //
495 ClockCtrl = (UINT16)~BIT2;
496 Status = SdPeimHcAndMmio (Bar + SD_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
497
498 return Status;
499 }
500
501 /**
502 SD card clock supply.
503
504 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
505
506 @param[in] Bar The mmio base address of the slot to be accessed.
507 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
508
509 @retval EFI_SUCCESS The clock is supplied successfully.
510 @retval Others The clock isn't supplied successfully.
511
512 **/
513 EFI_STATUS
514 SdPeimHcClockSupply (
515 IN UINTN Bar,
516 IN UINT64 ClockFreq
517 )
518 {
519 EFI_STATUS Status;
520 SD_HC_SLOT_CAP Capability;
521 UINT32 BaseClkFreq;
522 UINT32 SettingFreq;
523 UINT32 Divisor;
524 UINT32 Remainder;
525 UINT16 ControllerVer;
526 UINT16 ClockCtrl;
527
528 //
529 // Calculate a divisor for SD clock frequency
530 //
531 Status = SdPeimHcGetCapability (Bar, &Capability);
532 if (EFI_ERROR (Status)) {
533 return Status;
534 }
535 ASSERT (Capability.BaseClkFreq != 0);
536
537 BaseClkFreq = Capability.BaseClkFreq;
538
539 if (ClockFreq == 0) {
540 return EFI_INVALID_PARAMETER;
541 }
542
543 if (ClockFreq > (BaseClkFreq * 1000)) {
544 ClockFreq = BaseClkFreq * 1000;
545 }
546
547 //
548 // Calculate the divisor of base frequency.
549 //
550 Divisor = 0;
551 SettingFreq = BaseClkFreq * 1000;
552 while (ClockFreq < SettingFreq) {
553 Divisor++;
554
555 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
556 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
557 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
558 break;
559 }
560 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
561 SettingFreq ++;
562 }
563 }
564
565 DEBUG ((EFI_D_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
566
567 Status = SdPeimHcRwMmio (Bar + SD_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
568 if (EFI_ERROR (Status)) {
569 return Status;
570 }
571 //
572 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
573 //
574 if ((ControllerVer & 0xFF) == 2) {
575 ASSERT (Divisor <= 0x3FF);
576 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
577 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
578 //
579 // Only the most significant bit can be used as divisor.
580 //
581 if (((Divisor - 1) & Divisor) != 0) {
582 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
583 }
584 ASSERT (Divisor <= 0x80);
585 ClockCtrl = (Divisor & 0xFF) << 8;
586 } else {
587 DEBUG ((EFI_D_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
588 return EFI_UNSUPPORTED;
589 }
590
591 //
592 // Stop bus clock at first
593 //
594 Status = SdPeimHcStopClock (Bar);
595 if (EFI_ERROR (Status)) {
596 return Status;
597 }
598
599 //
600 // Supply clock frequency with specified divisor
601 //
602 ClockCtrl |= BIT0;
603 Status = SdPeimHcRwMmio (Bar + SD_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
604 if (EFI_ERROR (Status)) {
605 DEBUG ((EFI_D_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
606 return Status;
607 }
608
609 //
610 // Wait Internal Clock Stable in the Clock Control register to be 1
611 //
612 Status = SdPeimHcWaitMmioSet (
613 Bar + SD_HC_CLOCK_CTRL,
614 sizeof (ClockCtrl),
615 BIT1,
616 BIT1,
617 SD_TIMEOUT
618 );
619 if (EFI_ERROR (Status)) {
620 return Status;
621 }
622
623 //
624 // Set SD Clock Enable in the Clock Control register to 1
625 //
626 ClockCtrl = BIT2;
627 Status = SdPeimHcOrMmio (Bar + SD_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
628
629 return Status;
630 }
631
632 /**
633 SD bus power control.
634
635 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
636
637 @param[in] Bar The mmio base address of the slot to be accessed.
638 @param[in] PowerCtrl The value setting to the power control register.
639
640 @retval TRUE There is a SD card attached.
641 @retval FALSE There is no a SD card attached.
642
643 **/
644 EFI_STATUS
645 SdPeimHcPowerControl (
646 IN UINTN Bar,
647 IN UINT8 PowerCtrl
648 )
649 {
650 EFI_STATUS Status;
651
652 //
653 // Clr SD Bus Power
654 //
655 PowerCtrl &= (UINT8)~BIT0;
656 Status = SdPeimHcRwMmio (Bar + SD_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
657 if (EFI_ERROR (Status)) {
658 return Status;
659 }
660
661 //
662 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
663 //
664 PowerCtrl |= BIT0;
665 Status = SdPeimHcRwMmio (Bar + SD_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
666
667 return Status;
668 }
669
670 /**
671 Set the SD bus width.
672
673 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
674
675 @param[in] Bar The mmio base address of the slot to be accessed.
676 @param[in] BusWidth The bus width used by the SD device, it must be 1, 4 or 8.
677
678 @retval EFI_SUCCESS The bus width is set successfully.
679 @retval Others The bus width isn't set successfully.
680
681 **/
682 EFI_STATUS
683 SdPeimHcSetBusWidth (
684 IN UINTN Bar,
685 IN UINT16 BusWidth
686 )
687 {
688 EFI_STATUS Status;
689 UINT8 HostCtrl1;
690
691 if (BusWidth == 1) {
692 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
693 Status = SdPeimHcAndMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
694 } else if (BusWidth == 4) {
695 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
696 if (EFI_ERROR (Status)) {
697 return Status;
698 }
699 HostCtrl1 |= BIT1;
700 HostCtrl1 &= (UINT8)~BIT5;
701 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
702 } else if (BusWidth == 8) {
703 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
704 if (EFI_ERROR (Status)) {
705 return Status;
706 }
707 HostCtrl1 &= (UINT8)~BIT1;
708 HostCtrl1 |= BIT5;
709 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
710 } else {
711 ASSERT (FALSE);
712 return EFI_INVALID_PARAMETER;
713 }
714
715 return Status;
716 }
717
718 /**
719 Supply SD card with lowest clock frequency at initialization.
720
721 @param[in] Bar The mmio base address of the slot to be accessed.
722
723 @retval EFI_SUCCESS The clock is supplied successfully.
724 @retval Others The clock isn't supplied successfully.
725
726 **/
727 EFI_STATUS
728 SdPeimHcInitClockFreq (
729 IN UINTN Bar
730 )
731 {
732 EFI_STATUS Status;
733 SD_HC_SLOT_CAP Capability;
734 UINT32 InitFreq;
735
736 //
737 // Calculate a divisor for SD clock frequency
738 //
739 Status = SdPeimHcGetCapability (Bar, &Capability);
740 if (EFI_ERROR (Status)) {
741 return Status;
742 }
743
744 if (Capability.BaseClkFreq == 0) {
745 //
746 // Don't support get Base Clock Frequency information via another method
747 //
748 return EFI_UNSUPPORTED;
749 }
750 //
751 // Supply 400KHz clock frequency at initialization phase.
752 //
753 InitFreq = 400;
754 Status = SdPeimHcClockSupply (Bar, InitFreq);
755 return Status;
756 }
757
758 /**
759 Supply SD card with maximum voltage at initialization.
760
761 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
762
763 @param[in] Bar The mmio base address of the slot to be accessed.
764
765 @retval EFI_SUCCESS The voltage is supplied successfully.
766 @retval Others The voltage isn't supplied successfully.
767
768 **/
769 EFI_STATUS
770 SdPeimHcInitPowerVoltage (
771 IN UINTN Bar
772 )
773 {
774 EFI_STATUS Status;
775 SD_HC_SLOT_CAP Capability;
776 UINT8 MaxVoltage;
777 UINT8 HostCtrl2;
778
779 //
780 // Get the support voltage of the Host Controller
781 //
782 Status = SdPeimHcGetCapability (Bar, &Capability);
783 if (EFI_ERROR (Status)) {
784 return Status;
785 }
786 //
787 // Calculate supported maximum voltage according to SD Bus Voltage Select
788 //
789 if (Capability.Voltage33 != 0) {
790 //
791 // Support 3.3V
792 //
793 MaxVoltage = 0x0E;
794 } else if (Capability.Voltage30 != 0) {
795 //
796 // Support 3.0V
797 //
798 MaxVoltage = 0x0C;
799 } else if (Capability.Voltage18 != 0) {
800 //
801 // Support 1.8V
802 //
803 MaxVoltage = 0x0A;
804 HostCtrl2 = BIT3;
805 Status = SdPeimHcOrMmio (Bar + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
806 if (EFI_ERROR (Status)) {
807 return Status;
808 }
809 MicroSecondDelay (5000);
810 } else {
811 ASSERT (FALSE);
812 return EFI_DEVICE_ERROR;
813 }
814
815 //
816 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
817 //
818 Status = SdPeimHcPowerControl (Bar, MaxVoltage);
819
820 return Status;
821 }
822
823 /**
824 Initialize the Timeout Control register with most conservative value at initialization.
825
826 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
827
828 @param[in] Bar The mmio base address of the slot to be accessed.
829
830 @retval EFI_SUCCESS The timeout control register is configured successfully.
831 @retval Others The timeout control register isn't configured successfully.
832
833 **/
834 EFI_STATUS
835 SdPeimHcInitTimeoutCtrl (
836 IN UINTN Bar
837 )
838 {
839 EFI_STATUS Status;
840 UINT8 Timeout;
841
842 Timeout = 0x0E;
843 Status = SdPeimHcRwMmio (Bar + SD_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
844
845 return Status;
846 }
847
848 /**
849 Initial SD host controller with lowest clock frequency, max power and max timeout value
850 at initialization.
851
852 @param[in] Bar The mmio base address of the slot to be accessed.
853
854 @retval EFI_SUCCESS The host controller is initialized successfully.
855 @retval Others The host controller isn't initialized successfully.
856
857 **/
858 EFI_STATUS
859 SdPeimHcInitHost (
860 IN UINTN Bar
861 )
862 {
863 EFI_STATUS Status;
864
865 Status = SdPeimHcInitClockFreq (Bar);
866 if (EFI_ERROR (Status)) {
867 return Status;
868 }
869
870 Status = SdPeimHcInitPowerVoltage (Bar);
871 if (EFI_ERROR (Status)) {
872 return Status;
873 }
874
875 Status = SdPeimHcInitTimeoutCtrl (Bar);
876 return Status;
877 }
878
879 /**
880 Turn on/off LED.
881
882 @param[in] Bar The mmio base address of the slot to be accessed.
883 @param[in] On The boolean to turn on/off LED.
884
885 @retval EFI_SUCCESS The LED is turned on/off successfully.
886 @retval Others The LED isn't turned on/off successfully.
887
888 **/
889 EFI_STATUS
890 SdPeimHcLedOnOff (
891 IN UINTN Bar,
892 IN BOOLEAN On
893 )
894 {
895 EFI_STATUS Status;
896 UINT8 HostCtrl1;
897
898 if (On) {
899 HostCtrl1 = BIT0;
900 Status = SdPeimHcOrMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
901 } else {
902 HostCtrl1 = (UINT8)~BIT0;
903 Status = SdPeimHcAndMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
904 }
905
906 return Status;
907 }
908
909 /**
910 Build ADMA descriptor table for transfer.
911
912 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
913
914 @param[in] Trb The pointer to the SD_TRB instance.
915
916 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
917 @retval Others The ADMA descriptor table isn't created successfully.
918
919 **/
920 EFI_STATUS
921 BuildAdmaDescTable (
922 IN SD_TRB *Trb
923 )
924 {
925 EFI_PHYSICAL_ADDRESS Data;
926 UINT64 DataLen;
927 UINT64 Entries;
928 UINT32 Index;
929 UINT64 Remaining;
930 UINT32 Address;
931
932 Data = (EFI_PHYSICAL_ADDRESS)(UINTN)Trb->Data;
933 DataLen = Trb->DataLen;
934 //
935 // Only support 32bit ADMA Descriptor Table
936 //
937 if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {
938 return EFI_INVALID_PARAMETER;
939 }
940 //
941 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
942 // for 32-bit address descriptor table.
943 //
944 if ((Data & (BIT0 | BIT1)) != 0) {
945 DEBUG ((EFI_D_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
946 }
947
948 Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);
949
950 Trb->AdmaDescSize = (UINTN)MultU64x32 (Entries, sizeof (SD_HC_ADMA_DESC_LINE));
951 Trb->AdmaDesc = SdPeimAllocateMem (Trb->Slot->Private->Pool, Trb->AdmaDescSize);
952 if (Trb->AdmaDesc == NULL) {
953 return EFI_OUT_OF_RESOURCES;
954 }
955
956 Remaining = DataLen;
957 Address = (UINT32)Data;
958 for (Index = 0; Index < Entries; Index++) {
959 if (Remaining <= ADMA_MAX_DATA_PER_LINE) {
960 Trb->AdmaDesc[Index].Valid = 1;
961 Trb->AdmaDesc[Index].Act = 2;
962 Trb->AdmaDesc[Index].Length = (UINT16)Remaining;
963 Trb->AdmaDesc[Index].Address = Address;
964 break;
965 } else {
966 Trb->AdmaDesc[Index].Valid = 1;
967 Trb->AdmaDesc[Index].Act = 2;
968 Trb->AdmaDesc[Index].Length = 0;
969 Trb->AdmaDesc[Index].Address = Address;
970 }
971
972 Remaining -= ADMA_MAX_DATA_PER_LINE;
973 Address += ADMA_MAX_DATA_PER_LINE;
974 }
975
976 //
977 // Set the last descriptor line as end of descriptor table
978 //
979 Trb->AdmaDesc[Index].End = 1;
980 return EFI_SUCCESS;
981 }
982
983 /**
984 Create a new TRB for the SD cmd request.
985
986 @param[in] Slot The slot number of the SD card to send the command to.
987 @param[in] Packet A pointer to the SD command data structure.
988
989 @return Created Trb or NULL.
990
991 **/
992 SD_TRB *
993 SdPeimCreateTrb (
994 IN SD_PEIM_HC_SLOT *Slot,
995 IN SD_COMMAND_PACKET *Packet
996 )
997 {
998 SD_TRB *Trb;
999 EFI_STATUS Status;
1000 SD_HC_SLOT_CAP Capability;
1001
1002 //
1003 // Calculate a divisor for SD clock frequency
1004 //
1005 Status = SdPeimHcGetCapability (Slot->SdHcBase, &Capability);
1006 if (EFI_ERROR (Status)) {
1007 return NULL;
1008 }
1009
1010 Trb = SdPeimAllocateMem (Slot->Private->Pool, sizeof (SD_TRB));
1011 if (Trb == NULL) {
1012 return NULL;
1013 }
1014
1015 Trb->Slot = Slot;
1016 Trb->BlockSize = 0x200;
1017 Trb->Packet = Packet;
1018 Trb->Timeout = Packet->Timeout;
1019
1020 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1021 Trb->Data = Packet->InDataBuffer;
1022 Trb->DataLen = Packet->InTransferLength;
1023 Trb->Read = TRUE;
1024 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1025 Trb->Data = Packet->OutDataBuffer;
1026 Trb->DataLen = Packet->OutTransferLength;
1027 Trb->Read = FALSE;
1028 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1029 Trb->Data = NULL;
1030 Trb->DataLen = 0;
1031 } else {
1032 goto Error;
1033 }
1034
1035 if ((Trb->DataLen % Trb->BlockSize) != 0) {
1036 if (Trb->DataLen < Trb->BlockSize) {
1037 Trb->BlockSize = (UINT16)Trb->DataLen;
1038 }
1039 }
1040
1041 if (Trb->DataLen == 0) {
1042 Trb->Mode = SdNoData;
1043 } else if (Capability.Adma2 != 0) {
1044 Trb->Mode = SdAdmaMode;
1045 Status = BuildAdmaDescTable (Trb);
1046 if (EFI_ERROR (Status)) {
1047 goto Error;
1048 }
1049 } else if (Capability.Sdma != 0) {
1050 Trb->Mode = SdSdmaMode;
1051 } else {
1052 Trb->Mode = SdPioMode;
1053 }
1054
1055 return Trb;
1056
1057 Error:
1058 SdPeimFreeTrb (Trb);
1059 return NULL;
1060 }
1061
1062 /**
1063 Free the resource used by the TRB.
1064
1065 @param[in] Trb The pointer to the SD_TRB instance.
1066
1067 **/
1068 VOID
1069 SdPeimFreeTrb (
1070 IN SD_TRB *Trb
1071 )
1072 {
1073 if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) {
1074 SdPeimFreeMem (Trb->Slot->Private->Pool, Trb->AdmaDesc, Trb->AdmaDescSize);
1075 }
1076
1077 if (Trb != NULL) {
1078 SdPeimFreeMem (Trb->Slot->Private->Pool, Trb, sizeof (SD_TRB));
1079 }
1080 return;
1081 }
1082
1083 /**
1084 Check if the env is ready for execute specified TRB.
1085
1086 @param[in] Bar The mmio base address of the slot to be accessed.
1087 @param[in] Trb The pointer to the SD_TRB instance.
1088
1089 @retval EFI_SUCCESS The env is ready for TRB execution.
1090 @retval EFI_NOT_READY The env is not ready for TRB execution.
1091 @retval Others Some erros happen.
1092
1093 **/
1094 EFI_STATUS
1095 SdPeimCheckTrbEnv (
1096 IN UINTN Bar,
1097 IN SD_TRB *Trb
1098 )
1099 {
1100 EFI_STATUS Status;
1101 SD_COMMAND_PACKET *Packet;
1102 UINT32 PresentState;
1103
1104 Packet = Trb->Packet;
1105
1106 if ((Packet->SdCmdBlk->CommandType == SdCommandTypeAdtc) ||
1107 (Packet->SdCmdBlk->ResponseType == SdResponseTypeR1b) ||
1108 (Packet->SdCmdBlk->ResponseType == SdResponseTypeR5b)) {
1109 //
1110 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1111 // the Present State register to be 0
1112 //
1113 PresentState = BIT0 | BIT1;
1114 if (Packet->SdCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK) {
1115 PresentState = BIT0;
1116 }
1117 } else {
1118 //
1119 // Wait Command Inhibit (CMD) in the Present State register
1120 // to be 0
1121 //
1122 PresentState = BIT0;
1123 }
1124
1125 Status = SdPeimHcCheckMmioSet (
1126 Bar + SD_HC_PRESENT_STATE,
1127 sizeof (PresentState),
1128 PresentState,
1129 0
1130 );
1131
1132 return Status;
1133 }
1134
1135 /**
1136 Wait for the env to be ready for execute specified TRB.
1137
1138 @param[in] Bar The mmio base address of the slot to be accessed.
1139 @param[in] Trb The pointer to the SD_TRB instance.
1140
1141 @retval EFI_SUCCESS The env is ready for TRB execution.
1142 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1143 @retval Others Some erros happen.
1144
1145 **/
1146 EFI_STATUS
1147 SdPeimWaitTrbEnv (
1148 IN UINTN Bar,
1149 IN SD_TRB *Trb
1150 )
1151 {
1152 EFI_STATUS Status;
1153 SD_COMMAND_PACKET *Packet;
1154 UINT64 Timeout;
1155 BOOLEAN InfiniteWait;
1156
1157 //
1158 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1159 //
1160 Packet = Trb->Packet;
1161 Timeout = Packet->Timeout;
1162 if (Timeout == 0) {
1163 InfiniteWait = TRUE;
1164 } else {
1165 InfiniteWait = FALSE;
1166 }
1167
1168 while (InfiniteWait || (Timeout > 0)) {
1169 //
1170 // Check Trb execution result by reading Normal Interrupt Status register.
1171 //
1172 Status = SdPeimCheckTrbEnv (Bar, Trb);
1173 if (Status != EFI_NOT_READY) {
1174 return Status;
1175 }
1176 //
1177 // Stall for 1 microsecond.
1178 //
1179 MicroSecondDelay (1);
1180
1181 Timeout--;
1182 }
1183
1184 return EFI_TIMEOUT;
1185 }
1186
1187 /**
1188 Execute the specified TRB.
1189
1190 @param[in] Bar The mmio base address of the slot to be accessed.
1191 @param[in] Trb The pointer to the SD_TRB instance.
1192
1193 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1194 @retval Others Some erros happen when sending this request to the host controller.
1195
1196 **/
1197 EFI_STATUS
1198 SdPeimExecTrb (
1199 IN UINTN Bar,
1200 IN SD_TRB *Trb
1201 )
1202 {
1203 EFI_STATUS Status;
1204 SD_COMMAND_PACKET *Packet;
1205 UINT16 Cmd;
1206 UINT16 IntStatus;
1207 UINT32 Argument;
1208 UINT16 BlkCount;
1209 UINT16 BlkSize;
1210 UINT16 TransMode;
1211 UINT8 HostCtrl1;
1212 UINT32 SdmaAddr;
1213 UINT64 AdmaAddr;
1214
1215 Packet = Trb->Packet;
1216 //
1217 // Clear all bits in Error Interrupt Status Register
1218 //
1219 IntStatus = 0xFFFF;
1220 Status = SdPeimHcRwMmio (Bar + SD_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1221 if (EFI_ERROR (Status)) {
1222 return Status;
1223 }
1224 //
1225 // Clear all bits in Normal Interrupt Status Register
1226 //
1227 IntStatus = 0xFFFF;
1228 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1229 if (EFI_ERROR (Status)) {
1230 return Status;
1231 }
1232 //
1233 // Set Host Control 1 register DMA Select field
1234 //
1235 if (Trb->Mode == SdAdmaMode) {
1236 HostCtrl1 = BIT4;
1237 Status = SdPeimHcOrMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1238 if (EFI_ERROR (Status)) {
1239 return Status;
1240 }
1241 }
1242
1243 SdPeimHcLedOnOff (Bar, TRUE);
1244
1245 if (Trb->Mode == SdSdmaMode) {
1246 if ((UINT64)(UINTN)Trb->Data >= 0x100000000ul) {
1247 return EFI_INVALID_PARAMETER;
1248 }
1249
1250 SdmaAddr = (UINT32)(UINTN)Trb->Data;
1251 Status = SdPeimHcRwMmio (Bar + SD_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);
1252 if (EFI_ERROR (Status)) {
1253 return Status;
1254 }
1255 } else if (Trb->Mode == SdAdmaMode) {
1256 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDesc;
1257 Status = SdPeimHcRwMmio (Bar + SD_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
1258 if (EFI_ERROR (Status)) {
1259 return Status;
1260 }
1261 }
1262
1263 BlkSize = Trb->BlockSize;
1264 if (Trb->Mode == SdSdmaMode) {
1265 //
1266 // Set SDMA boundary to be 512K bytes.
1267 //
1268 BlkSize |= 0x7000;
1269 }
1270
1271 Status = SdPeimHcRwMmio (Bar + SD_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
1272 if (EFI_ERROR (Status)) {
1273 return Status;
1274 }
1275
1276 BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);
1277 Status = SdPeimHcRwMmio (Bar + SD_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);
1278 if (EFI_ERROR (Status)) {
1279 return Status;
1280 }
1281
1282 Argument = Packet->SdCmdBlk->CommandArgument;
1283 Status = SdPeimHcRwMmio (Bar + SD_HC_ARG1, FALSE, sizeof (Argument), &Argument);
1284 if (EFI_ERROR (Status)) {
1285 return Status;
1286 }
1287
1288 TransMode = 0;
1289 if (Trb->Mode != SdNoData) {
1290 if (Trb->Mode != SdPioMode) {
1291 TransMode |= BIT0;
1292 }
1293 if (Trb->Read) {
1294 TransMode |= BIT4;
1295 }
1296 if (BlkCount != 0) {
1297 TransMode |= BIT5 | BIT1;
1298 }
1299 if (BlkCount > 1) {
1300 TransMode |= BIT2;
1301 }
1302 }
1303
1304 Status = SdPeimHcRwMmio (Bar + SD_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
1305 if (EFI_ERROR (Status)) {
1306 return Status;
1307 }
1308
1309 Cmd = (UINT16)LShiftU64(Packet->SdCmdBlk->CommandIndex, 8);
1310 if (Packet->SdCmdBlk->CommandType == SdCommandTypeAdtc) {
1311 Cmd |= BIT5;
1312 }
1313 //
1314 // Convert ResponseType to value
1315 //
1316 if (Packet->SdCmdBlk->CommandType != SdCommandTypeBc) {
1317 switch (Packet->SdCmdBlk->ResponseType) {
1318 case SdResponseTypeR1:
1319 case SdResponseTypeR5:
1320 case SdResponseTypeR6:
1321 case SdResponseTypeR7:
1322 Cmd |= (BIT1 | BIT3 | BIT4);
1323 break;
1324 case SdResponseTypeR2:
1325 Cmd |= (BIT0 | BIT3);
1326 break;
1327 case SdResponseTypeR3:
1328 case SdResponseTypeR4:
1329 Cmd |= BIT1;
1330 break;
1331 case SdResponseTypeR1b:
1332 case SdResponseTypeR5b:
1333 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
1334 break;
1335 default:
1336 ASSERT (FALSE);
1337 break;
1338 }
1339 }
1340 //
1341 // Execute cmd
1342 //
1343 Status = SdPeimHcRwMmio (Bar + SD_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
1344 return Status;
1345 }
1346
1347 /**
1348 Check the TRB execution result.
1349
1350 @param[in] Bar The mmio base address of the slot to be accessed.
1351 @param[in] Trb The pointer to the SD_TRB instance.
1352
1353 @retval EFI_SUCCESS The TRB is executed successfully.
1354 @retval EFI_NOT_READY The TRB is not completed for execution.
1355 @retval Others Some erros happen when executing this request.
1356
1357 **/
1358 EFI_STATUS
1359 SdPeimCheckTrbResult (
1360 IN UINTN Bar,
1361 IN SD_TRB *Trb
1362 )
1363 {
1364 EFI_STATUS Status;
1365 SD_COMMAND_PACKET *Packet;
1366 UINT16 IntStatus;
1367 UINT32 Response[4];
1368 UINT32 SdmaAddr;
1369 UINT8 Index;
1370 UINT8 SwReset;
1371
1372 SwReset = 0;
1373 Packet = Trb->Packet;
1374 //
1375 // Check Trb execution result by reading Normal Interrupt Status register.
1376 //
1377 Status = SdPeimHcRwMmio (
1378 Bar + SD_HC_NOR_INT_STS,
1379 TRUE,
1380 sizeof (IntStatus),
1381 &IntStatus
1382 );
1383 if (EFI_ERROR (Status)) {
1384 goto Done;
1385 }
1386 //
1387 // Check Transfer Complete bit is set or not.
1388 //
1389 if ((IntStatus & BIT1) == BIT1) {
1390 if ((IntStatus & BIT15) == BIT15) {
1391 //
1392 // Read Error Interrupt Status register to check if the error is
1393 // Data Timeout Error.
1394 // If yes, treat it as success as Transfer Complete has higher
1395 // priority than Data Timeout Error.
1396 //
1397 Status = SdPeimHcRwMmio (
1398 Bar + SD_HC_ERR_INT_STS,
1399 TRUE,
1400 sizeof (IntStatus),
1401 &IntStatus
1402 );
1403 if (!EFI_ERROR (Status)) {
1404 if ((IntStatus & BIT4) == BIT4) {
1405 Status = EFI_SUCCESS;
1406 } else {
1407 Status = EFI_DEVICE_ERROR;
1408 }
1409 }
1410 }
1411
1412 goto Done;
1413 }
1414 //
1415 // Check if there is a error happened during cmd execution.
1416 // If yes, then do error recovery procedure to follow SD Host Controller
1417 // Simplified Spec 3.0 section 3.10.1.
1418 //
1419 if ((IntStatus & BIT15) == BIT15) {
1420 Status = SdPeimHcRwMmio (
1421 Bar + SD_HC_ERR_INT_STS,
1422 TRUE,
1423 sizeof (IntStatus),
1424 &IntStatus
1425 );
1426 if (EFI_ERROR (Status)) {
1427 goto Done;
1428 }
1429
1430 if ((IntStatus & 0x0F) != 0) {
1431 SwReset |= BIT1;
1432 }
1433 if ((IntStatus & 0xF0) != 0) {
1434 SwReset |= BIT2;
1435 }
1436
1437 Status = SdPeimHcRwMmio (
1438 Bar + SD_HC_SW_RST,
1439 FALSE,
1440 sizeof (SwReset),
1441 &SwReset
1442 );
1443 if (EFI_ERROR (Status)) {
1444 goto Done;
1445 }
1446 Status = SdPeimHcWaitMmioSet (
1447 Bar + SD_HC_SW_RST,
1448 sizeof (SwReset),
1449 0xFF,
1450 0,
1451 SD_TIMEOUT
1452 );
1453 if (EFI_ERROR (Status)) {
1454 goto Done;
1455 }
1456
1457 Status = EFI_DEVICE_ERROR;
1458 goto Done;
1459 }
1460 //
1461 // Check if DMA interrupt is signalled for the SDMA transfer.
1462 //
1463 if ((Trb->Mode == SdSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
1464 //
1465 // Clear DMA interrupt bit.
1466 //
1467 IntStatus = BIT3;
1468 Status = SdPeimHcRwMmio (
1469 Bar + SD_HC_NOR_INT_STS,
1470 FALSE,
1471 sizeof (IntStatus),
1472 &IntStatus
1473 );
1474 if (EFI_ERROR (Status)) {
1475 goto Done;
1476 }
1477 //
1478 // Update SDMA Address register.
1479 //
1480 SdmaAddr = SD_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->Data, SD_SDMA_BOUNDARY);
1481 Status = SdPeimHcRwMmio (
1482 Bar + SD_HC_SDMA_ADDR,
1483 FALSE,
1484 sizeof (UINT32),
1485 &SdmaAddr
1486 );
1487 if (EFI_ERROR (Status)) {
1488 goto Done;
1489 }
1490 Trb->Data = (VOID*)(UINTN)SdmaAddr;
1491 }
1492
1493 if ((Packet->SdCmdBlk->CommandType != SdCommandTypeAdtc) &&
1494 (Packet->SdCmdBlk->ResponseType != SdResponseTypeR1b) &&
1495 (Packet->SdCmdBlk->ResponseType != SdResponseTypeR5b)) {
1496 if ((IntStatus & BIT0) == BIT0) {
1497 Status = EFI_SUCCESS;
1498 goto Done;
1499 }
1500 }
1501
1502 if (Packet->SdCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK) {
1503 Status = EFI_SUCCESS;
1504 goto Done;
1505 }
1506
1507 Status = EFI_NOT_READY;
1508 Done:
1509 //
1510 // Get response data when the cmd is executed successfully.
1511 //
1512 if (!EFI_ERROR (Status)) {
1513 if (Packet->SdCmdBlk->CommandType != SdCommandTypeBc) {
1514 for (Index = 0; Index < 4; Index++) {
1515 Status = SdPeimHcRwMmio (
1516 Bar + SD_HC_RESPONSE + Index * 4,
1517 TRUE,
1518 sizeof (UINT32),
1519 &Response[Index]
1520 );
1521 if (EFI_ERROR (Status)) {
1522 SdPeimHcLedOnOff (Bar, FALSE);
1523 return Status;
1524 }
1525 }
1526 CopyMem (Packet->SdStatusBlk, Response, sizeof (Response));
1527 }
1528 }
1529
1530 if (Status != EFI_NOT_READY) {
1531 SdPeimHcLedOnOff (Bar, FALSE);
1532 }
1533
1534 return Status;
1535 }
1536
1537 /**
1538 Wait for the TRB execution result.
1539
1540 @param[in] Bar The mmio base address of the slot to be accessed.
1541 @param[in] Trb The pointer to the SD_TRB instance.
1542
1543 @retval EFI_SUCCESS The TRB is executed successfully.
1544 @retval Others Some erros happen when executing this request.
1545
1546 **/
1547 EFI_STATUS
1548 SdPeimWaitTrbResult (
1549 IN UINTN Bar,
1550 IN SD_TRB *Trb
1551 )
1552 {
1553 EFI_STATUS Status;
1554 SD_COMMAND_PACKET *Packet;
1555 UINT64 Timeout;
1556 BOOLEAN InfiniteWait;
1557
1558 Packet = Trb->Packet;
1559 //
1560 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1561 //
1562 Timeout = Packet->Timeout;
1563 if (Timeout == 0) {
1564 InfiniteWait = TRUE;
1565 } else {
1566 InfiniteWait = FALSE;
1567 }
1568
1569 while (InfiniteWait || (Timeout > 0)) {
1570 //
1571 // Check Trb execution result by reading Normal Interrupt Status register.
1572 //
1573 Status = SdPeimCheckTrbResult (Bar, Trb);
1574 if (Status != EFI_NOT_READY) {
1575 return Status;
1576 }
1577 //
1578 // Stall for 1 microsecond.
1579 //
1580 MicroSecondDelay (1);
1581
1582 Timeout--;
1583 }
1584
1585 return EFI_TIMEOUT;
1586 }
1587
1588 /**
1589 Sends SD command to an SD card that is attached to the SD controller.
1590
1591 If Packet is successfully sent to the SD card, then EFI_SUCCESS is returned.
1592
1593 If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned.
1594
1595 If Slot is not in a valid range for the SD controller, then EFI_INVALID_PARAMETER
1596 is returned.
1597
1598 If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL,
1599 EFI_INVALID_PARAMETER is returned.
1600
1601 @param[in] Slot The slot number of the Sd card to send the command to.
1602 @param[in,out] Packet A pointer to the SD command data structure.
1603
1604 @retval EFI_SUCCESS The SD Command Packet was sent by the host.
1605 @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the SD
1606 command Packet.
1607 @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid.
1608 @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and
1609 OutDataBuffer are NULL.
1610 @retval EFI_NO_MEDIA SD Device not present in the Slot.
1611 @retval EFI_UNSUPPORTED The command described by the SD Command Packet is not
1612 supported by the host controller.
1613 @retval EFI_BAD_BUFFER_SIZE The InTransferLength or OutTransferLength exceeds the
1614 limit supported by SD card ( i.e. if the number of bytes
1615 exceed the Last LBA).
1616
1617 **/
1618 EFI_STATUS
1619 EFIAPI
1620 SdPeimExecCmd (
1621 IN SD_PEIM_HC_SLOT *Slot,
1622 IN OUT SD_COMMAND_PACKET *Packet
1623 )
1624 {
1625 EFI_STATUS Status;
1626 SD_TRB *Trb;
1627
1628 if (Packet == NULL) {
1629 return EFI_INVALID_PARAMETER;
1630 }
1631
1632 if ((Packet->SdCmdBlk == NULL) || (Packet->SdStatusBlk == NULL)) {
1633 return EFI_INVALID_PARAMETER;
1634 }
1635
1636 if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {
1637 return EFI_INVALID_PARAMETER;
1638 }
1639
1640 if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {
1641 return EFI_INVALID_PARAMETER;
1642 }
1643
1644 Trb = SdPeimCreateTrb (Slot, Packet);
1645 if (Trb == NULL) {
1646 return EFI_OUT_OF_RESOURCES;
1647 }
1648
1649 Status = SdPeimWaitTrbEnv (Slot->SdHcBase, Trb);
1650 if (EFI_ERROR (Status)) {
1651 goto Done;
1652 }
1653
1654 Status = SdPeimExecTrb (Slot->SdHcBase, Trb);
1655 if (EFI_ERROR (Status)) {
1656 goto Done;
1657 }
1658
1659 Status = SdPeimWaitTrbResult (Slot->SdHcBase, Trb);
1660 if (EFI_ERROR (Status)) {
1661 goto Done;
1662 }
1663
1664 Done:
1665 SdPeimFreeTrb (Trb);
1666
1667 return Status;
1668 }
1669
1670 /**
1671 Send command GO_IDLE_STATE to the device to make it go to Idle State.
1672
1673 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1674
1675 @param[in] Slot The slot number of the SD card to send the command to.
1676
1677 @retval EFI_SUCCESS The SD device is reset correctly.
1678 @retval Others The device reset fails.
1679
1680 **/
1681 EFI_STATUS
1682 SdPeimReset (
1683 IN SD_PEIM_HC_SLOT *Slot
1684 )
1685 {
1686 SD_COMMAND_BLOCK SdCmdBlk;
1687 SD_STATUS_BLOCK SdStatusBlk;
1688 SD_COMMAND_PACKET Packet;
1689 EFI_STATUS Status;
1690
1691 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1692 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1693 ZeroMem (&Packet, sizeof (Packet));
1694
1695 Packet.SdCmdBlk = &SdCmdBlk;
1696 Packet.SdStatusBlk = &SdStatusBlk;
1697 Packet.Timeout = SD_TIMEOUT;
1698
1699 SdCmdBlk.CommandIndex = SD_GO_IDLE_STATE;
1700 SdCmdBlk.CommandType = SdCommandTypeBc;
1701 SdCmdBlk.ResponseType = 0;
1702 SdCmdBlk.CommandArgument = 0;
1703
1704 Status = SdPeimExecCmd (Slot, &Packet);
1705
1706 return Status;
1707 }
1708
1709 /**
1710 Send command SEND_IF_COND to the device to inquiry the SD Memory Card interface
1711 condition.
1712
1713 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1714
1715 @param[in] Slot The slot number of the SD card to send the command to.
1716 @param[in] SupplyVoltage The supplied voltage by the host.
1717 @param[in] CheckPattern The check pattern to be sent to the device.
1718
1719 @retval EFI_SUCCESS The operation is done correctly.
1720 @retval Others The operation fails.
1721
1722 **/
1723 EFI_STATUS
1724 SdPeimVoltageCheck (
1725 IN SD_PEIM_HC_SLOT *Slot,
1726 IN UINT8 SupplyVoltage,
1727 IN UINT8 CheckPattern
1728 )
1729 {
1730 SD_COMMAND_BLOCK SdCmdBlk;
1731 SD_STATUS_BLOCK SdStatusBlk;
1732 SD_COMMAND_PACKET Packet;
1733 EFI_STATUS Status;
1734
1735 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1736 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1737 ZeroMem (&Packet, sizeof (Packet));
1738
1739 Packet.SdCmdBlk = &SdCmdBlk;
1740 Packet.SdStatusBlk = &SdStatusBlk;
1741 Packet.Timeout = SD_TIMEOUT;
1742
1743 SdCmdBlk.CommandIndex = SD_SEND_IF_COND;
1744 SdCmdBlk.CommandType = SdCommandTypeBcr;
1745 SdCmdBlk.ResponseType = SdResponseTypeR7;
1746 SdCmdBlk.CommandArgument = (SupplyVoltage << 8) | CheckPattern;
1747
1748 Status = SdPeimExecCmd (Slot, &Packet);
1749 if (!EFI_ERROR (Status)) {
1750 if (SdStatusBlk.Resp0 != SdCmdBlk.CommandArgument) {
1751 return EFI_DEVICE_ERROR;
1752 }
1753 }
1754
1755 return Status;
1756 }
1757
1758 /**
1759 Send command SDIO_SEND_OP_COND to the device to see whether it is SDIO device.
1760
1761 Refer to SDIO Simplified Spec 3 Section 3.2 for details.
1762
1763 @param[in] Slot The slot number of the SD card to send the command to.
1764 @param[in] VoltageWindow The supply voltage window.
1765 @param[in] S18r The boolean to show if it should switch to 1.8v.
1766
1767 @retval EFI_SUCCESS The operation is done correctly.
1768 @retval Others The operation fails.
1769
1770 **/
1771 EFI_STATUS
1772 SdioSendOpCond (
1773 IN SD_PEIM_HC_SLOT *Slot,
1774 IN UINT32 VoltageWindow,
1775 IN BOOLEAN S18r
1776 )
1777 {
1778 SD_COMMAND_BLOCK SdCmdBlk;
1779 SD_STATUS_BLOCK SdStatusBlk;
1780 SD_COMMAND_PACKET Packet;
1781 EFI_STATUS Status;
1782 UINT32 Switch;
1783
1784 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1785 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1786 ZeroMem (&Packet, sizeof (Packet));
1787
1788 Packet.SdCmdBlk = &SdCmdBlk;
1789 Packet.SdStatusBlk = &SdStatusBlk;
1790 Packet.Timeout = SD_TIMEOUT;
1791
1792 SdCmdBlk.CommandIndex = SDIO_SEND_OP_COND;
1793 SdCmdBlk.CommandType = SdCommandTypeBcr;
1794 SdCmdBlk.ResponseType = SdResponseTypeR4;
1795
1796 Switch = S18r ? BIT24 : 0;
1797
1798 SdCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch;
1799
1800 Status = SdPeimExecCmd (Slot, &Packet);
1801
1802 return Status;
1803 }
1804
1805 /**
1806 Send command SD_SEND_OP_COND to the device to see whether it is SDIO device.
1807
1808 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1809
1810 @param[in] Slot The slot number of the SD card to send the command to.
1811 @param[in] Rca The relative device address of addressed device.
1812 @param[in] VoltageWindow The supply voltage window.
1813 @param[in] S18r The boolean to show if it should switch to 1.8v.
1814 @param[in] Xpc The boolean to show if it should provide 0.36w power control.
1815 @param[in] Hcs The boolean to show if it support host capacity info.
1816 @param[out] Ocr The buffer to store returned OCR register value.
1817
1818
1819 @retval EFI_SUCCESS The operation is done correctly.
1820 @retval Others The operation fails.
1821
1822 **/
1823 EFI_STATUS
1824 SdPeimSendOpCond (
1825 IN SD_PEIM_HC_SLOT *Slot,
1826 IN UINT16 Rca,
1827 IN UINT32 VoltageWindow,
1828 IN BOOLEAN S18r,
1829 IN BOOLEAN Xpc,
1830 IN BOOLEAN Hcs,
1831 OUT UINT32 *Ocr
1832 )
1833 {
1834 SD_COMMAND_BLOCK SdCmdBlk;
1835 SD_STATUS_BLOCK SdStatusBlk;
1836 SD_COMMAND_PACKET Packet;
1837 EFI_STATUS Status;
1838 UINT32 Switch;
1839 UINT32 MaxPower;
1840 UINT32 HostCapacity;
1841
1842 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1843 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1844 ZeroMem (&Packet, sizeof (Packet));
1845
1846 Packet.SdCmdBlk = &SdCmdBlk;
1847 Packet.SdStatusBlk = &SdStatusBlk;
1848 Packet.Timeout = SD_TIMEOUT;
1849
1850 SdCmdBlk.CommandIndex = SD_APP_CMD;
1851 SdCmdBlk.CommandType = SdCommandTypeAc;
1852 SdCmdBlk.ResponseType = SdResponseTypeR1;
1853 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
1854
1855 Status = SdPeimExecCmd (Slot, &Packet);
1856 if (EFI_ERROR (Status)) {
1857 return Status;
1858 }
1859
1860 SdCmdBlk.CommandIndex = SD_SEND_OP_COND;
1861 SdCmdBlk.CommandType = SdCommandTypeBcr;
1862 SdCmdBlk.ResponseType = SdResponseTypeR3;
1863
1864 Switch = S18r ? BIT24 : 0;
1865 MaxPower = Xpc ? BIT28 : 0;
1866 HostCapacity = Hcs ? BIT30 : 0;
1867 SdCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch | MaxPower | HostCapacity;
1868
1869 Status = SdPeimExecCmd (Slot, &Packet);
1870 if (!EFI_ERROR (Status)) {
1871 //
1872 // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
1873 //
1874 *Ocr = SdStatusBlk.Resp0;
1875 }
1876
1877 return Status;
1878 }
1879
1880 /**
1881 Broadcast command ALL_SEND_CID to the bus to ask all the SD devices to send the
1882 data of their CID registers.
1883
1884 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1885
1886 @param[in] Slot The slot number of the SD card to send the command to.
1887
1888 @retval EFI_SUCCESS The operation is done correctly.
1889 @retval Others The operation fails.
1890
1891 **/
1892 EFI_STATUS
1893 SdPeimAllSendCid (
1894 IN SD_PEIM_HC_SLOT *Slot
1895 )
1896 {
1897 SD_COMMAND_BLOCK SdCmdBlk;
1898 SD_STATUS_BLOCK SdStatusBlk;
1899 SD_COMMAND_PACKET Packet;
1900 EFI_STATUS Status;
1901
1902 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1903 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1904 ZeroMem (&Packet, sizeof (Packet));
1905
1906 Packet.SdCmdBlk = &SdCmdBlk;
1907 Packet.SdStatusBlk = &SdStatusBlk;
1908 Packet.Timeout = SD_TIMEOUT;
1909
1910 SdCmdBlk.CommandIndex = SD_ALL_SEND_CID;
1911 SdCmdBlk.CommandType = SdCommandTypeBcr;
1912 SdCmdBlk.ResponseType = SdResponseTypeR2;
1913 SdCmdBlk.CommandArgument = 0;
1914
1915 Status = SdPeimExecCmd (Slot, &Packet);
1916
1917 return Status;
1918 }
1919
1920 /**
1921 Send command SET_RELATIVE_ADDR to the SD device to assign a Relative device
1922 Address (RCA).
1923
1924 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1925
1926 @param[in] Slot The slot number of the SD card to send the command to.
1927 @param[out] Rca The relative device address to be assigned.
1928
1929 @retval EFI_SUCCESS The operation is done correctly.
1930 @retval Others The operation fails.
1931
1932 **/
1933 EFI_STATUS
1934 SdPeimSetRca (
1935 IN SD_PEIM_HC_SLOT *Slot,
1936 OUT UINT16 *Rca
1937 )
1938 {
1939 SD_COMMAND_BLOCK SdCmdBlk;
1940 SD_STATUS_BLOCK SdStatusBlk;
1941 SD_COMMAND_PACKET Packet;
1942 EFI_STATUS Status;
1943
1944 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1945 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1946 ZeroMem (&Packet, sizeof (Packet));
1947
1948 Packet.SdCmdBlk = &SdCmdBlk;
1949 Packet.SdStatusBlk = &SdStatusBlk;
1950 Packet.Timeout = SD_TIMEOUT;
1951
1952 SdCmdBlk.CommandIndex = SD_SET_RELATIVE_ADDR;
1953 SdCmdBlk.CommandType = SdCommandTypeBcr;
1954 SdCmdBlk.ResponseType = SdResponseTypeR6;
1955
1956 Status = SdPeimExecCmd (Slot, &Packet);
1957 if (!EFI_ERROR (Status)) {
1958 *Rca = (UINT16)(SdStatusBlk.Resp0 >> 16);
1959 }
1960
1961 return Status;
1962 }
1963
1964 /**
1965 Send command SEND_CSD to the SD device to get the data of the CSD register.
1966
1967 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1968
1969 @param[in] Slot The slot number of the SD card to send the command to.
1970 @param[in] Rca The relative device address of selected device.
1971 @param[out] Csd The buffer to store the content of the CSD register.
1972 Note the caller should ignore the lowest byte of this
1973 buffer as the content of this byte is meaningless even
1974 if the operation succeeds.
1975
1976 @retval EFI_SUCCESS The operation is done correctly.
1977 @retval Others The operation fails.
1978
1979 **/
1980 EFI_STATUS
1981 SdPeimGetCsd (
1982 IN SD_PEIM_HC_SLOT *Slot,
1983 IN UINT16 Rca,
1984 OUT SD_CSD *Csd
1985 )
1986 {
1987 SD_COMMAND_BLOCK SdCmdBlk;
1988 SD_STATUS_BLOCK SdStatusBlk;
1989 SD_COMMAND_PACKET Packet;
1990 EFI_STATUS Status;
1991
1992 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1993 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1994 ZeroMem (&Packet, sizeof (Packet));
1995
1996 Packet.SdCmdBlk = &SdCmdBlk;
1997 Packet.SdStatusBlk = &SdStatusBlk;
1998 Packet.Timeout = SD_TIMEOUT;
1999
2000 SdCmdBlk.CommandIndex = SD_SEND_CSD;
2001 SdCmdBlk.CommandType = SdCommandTypeAc;
2002 SdCmdBlk.ResponseType = SdResponseTypeR2;
2003 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
2004
2005 Status = SdPeimExecCmd (Slot, &Packet);
2006 if (!EFI_ERROR (Status)) {
2007 //
2008 // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
2009 //
2010 CopyMem (((UINT8*)Csd) + 1, &SdStatusBlk.Resp0, sizeof (SD_CSD) - 1);
2011 }
2012
2013 return Status;
2014 }
2015
2016 /**
2017 Send command SELECT_DESELECT_CARD to the SD device to select/deselect it.
2018
2019 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2020
2021 @param[in] Slot The slot number of the SD card to send the command to.
2022 @param[in] Rca The relative device address of selected device.
2023
2024 @retval EFI_SUCCESS The operation is done correctly.
2025 @retval Others The operation fails.
2026
2027 **/
2028 EFI_STATUS
2029 SdPeimSelect (
2030 IN SD_PEIM_HC_SLOT *Slot,
2031 IN UINT16 Rca
2032 )
2033 {
2034 SD_COMMAND_BLOCK SdCmdBlk;
2035 SD_STATUS_BLOCK SdStatusBlk;
2036 SD_COMMAND_PACKET Packet;
2037 EFI_STATUS Status;
2038
2039 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2040 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2041 ZeroMem (&Packet, sizeof (Packet));
2042
2043 Packet.SdCmdBlk = &SdCmdBlk;
2044 Packet.SdStatusBlk = &SdStatusBlk;
2045 Packet.Timeout = SD_TIMEOUT;
2046
2047 SdCmdBlk.CommandIndex = SD_SELECT_DESELECT_CARD;
2048 SdCmdBlk.CommandType = SdCommandTypeAc;
2049 SdCmdBlk.ResponseType = SdResponseTypeR1b;
2050 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
2051
2052 Status = SdPeimExecCmd (Slot, &Packet);
2053
2054 return Status;
2055 }
2056
2057 /**
2058 Send command VOLTAGE_SWITCH to the SD device to switch the voltage of the device.
2059
2060 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2061
2062 @param[in] Slot The slot number of the SD card to send the command to.
2063
2064 @retval EFI_SUCCESS The operation is done correctly.
2065 @retval Others The operation fails.
2066
2067 **/
2068 EFI_STATUS
2069 SdPeimVoltageSwitch (
2070 IN SD_PEIM_HC_SLOT *Slot
2071 )
2072 {
2073 SD_COMMAND_BLOCK SdCmdBlk;
2074 SD_STATUS_BLOCK SdStatusBlk;
2075 SD_COMMAND_PACKET Packet;
2076 EFI_STATUS Status;
2077
2078 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2079 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2080 ZeroMem (&Packet, sizeof (Packet));
2081
2082 Packet.SdCmdBlk = &SdCmdBlk;
2083 Packet.SdStatusBlk = &SdStatusBlk;
2084 Packet.Timeout = SD_TIMEOUT;
2085
2086 SdCmdBlk.CommandIndex = SD_VOLTAGE_SWITCH;
2087 SdCmdBlk.CommandType = SdCommandTypeAc;
2088 SdCmdBlk.ResponseType = SdResponseTypeR1;
2089 SdCmdBlk.CommandArgument = 0;
2090
2091 Status = SdPeimExecCmd (Slot, &Packet);
2092
2093 return Status;
2094 }
2095
2096 /**
2097 Send command SET_BUS_WIDTH to the SD device to set the bus width.
2098
2099 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2100
2101 @param[in] Slot The slot number of the SD card to send the command to.
2102 @param[in] Rca The relative device address of addressed device.
2103 @param[in] BusWidth The bus width to be set, it could be 1 or 4.
2104
2105 @retval EFI_SUCCESS The operation is done correctly.
2106 @retval Others The operation fails.
2107
2108 **/
2109 EFI_STATUS
2110 SdPeimSetBusWidth (
2111 IN SD_PEIM_HC_SLOT *Slot,
2112 IN UINT16 Rca,
2113 IN UINT8 BusWidth
2114 )
2115 {
2116 SD_COMMAND_BLOCK SdCmdBlk;
2117 SD_STATUS_BLOCK SdStatusBlk;
2118 SD_COMMAND_PACKET Packet;
2119 EFI_STATUS Status;
2120 UINT8 Value;
2121
2122 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2123 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2124 ZeroMem (&Packet, sizeof (Packet));
2125
2126 Packet.SdCmdBlk = &SdCmdBlk;
2127 Packet.SdStatusBlk = &SdStatusBlk;
2128 Packet.Timeout = SD_TIMEOUT;
2129
2130 SdCmdBlk.CommandIndex = SD_APP_CMD;
2131 SdCmdBlk.CommandType = SdCommandTypeAc;
2132 SdCmdBlk.ResponseType = SdResponseTypeR1;
2133 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
2134
2135 Status = SdPeimExecCmd (Slot, &Packet);
2136 if (EFI_ERROR (Status)) {
2137 return Status;
2138 }
2139
2140 SdCmdBlk.CommandIndex = SD_SET_BUS_WIDTH;
2141 SdCmdBlk.CommandType = SdCommandTypeAc;
2142 SdCmdBlk.ResponseType = SdResponseTypeR1;
2143
2144 if (BusWidth == 1) {
2145 Value = 0;
2146 } else if (BusWidth == 4) {
2147 Value = 2;
2148 } else {
2149 return EFI_INVALID_PARAMETER;
2150 }
2151 SdCmdBlk.CommandArgument = Value & 0x3;
2152
2153 Status = SdPeimExecCmd (Slot, &Packet);
2154
2155 return Status;
2156 }
2157
2158 /**
2159 Send command SWITCH_FUNC to the SD device to check switchable function or switch card function.
2160
2161 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2162
2163 @param[in] Slot The slot number of the SD card to send the command to.
2164 @param[in] AccessMode The value for access mode group.
2165 @param[in] CommandSystem The value for command set group.
2166 @param[in] DriveStrength The value for drive length group.
2167 @param[in] PowerLimit The value for power limit group.
2168 @param[in] Mode Switch or check function.
2169
2170 @retval EFI_SUCCESS The operation is done correctly.
2171 @retval Others The operation fails.
2172
2173 **/
2174 EFI_STATUS
2175 SdPeimSwitch (
2176 IN SD_PEIM_HC_SLOT *Slot,
2177 IN UINT8 AccessMode,
2178 IN UINT8 CommandSystem,
2179 IN UINT8 DriveStrength,
2180 IN UINT8 PowerLimit,
2181 IN BOOLEAN Mode
2182 )
2183 {
2184 SD_COMMAND_BLOCK SdCmdBlk;
2185 SD_STATUS_BLOCK SdStatusBlk;
2186 SD_COMMAND_PACKET Packet;
2187 EFI_STATUS Status;
2188 UINT32 ModeValue;
2189 UINT8 Data[64];
2190
2191 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2192 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2193 ZeroMem (&Packet, sizeof (Packet));
2194
2195 Packet.SdCmdBlk = &SdCmdBlk;
2196 Packet.SdStatusBlk = &SdStatusBlk;
2197 Packet.Timeout = SD_TIMEOUT;
2198
2199 SdCmdBlk.CommandIndex = SD_SWITCH_FUNC;
2200 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2201 SdCmdBlk.ResponseType = SdResponseTypeR1;
2202
2203 ModeValue = Mode ? BIT31 : 0;
2204 SdCmdBlk.CommandArgument = (AccessMode & 0xF) | ((PowerLimit & 0xF) << 4) | \
2205 ((DriveStrength & 0xF) << 8) | ((DriveStrength & 0xF) << 12) | \
2206 ModeValue;
2207 Packet.InDataBuffer = Data;
2208 Packet.InTransferLength = sizeof (Data);
2209
2210 Status = SdPeimExecCmd (Slot, &Packet);
2211
2212 return Status;
2213 }
2214
2215 /**
2216 Send command SEND_STATUS to the addressed SD device to get its status register.
2217
2218 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2219
2220 @param[in] Slot The slot number of the SD card to send the command to.
2221 @param[in] Rca The relative device address of addressed device.
2222 @param[out] DevStatus The returned device status.
2223
2224 @retval EFI_SUCCESS The operation is done correctly.
2225 @retval Others The operation fails.
2226
2227 **/
2228 EFI_STATUS
2229 SdPeimSendStatus (
2230 IN SD_PEIM_HC_SLOT *Slot,
2231 IN UINT16 Rca,
2232 OUT UINT32 *DevStatus
2233 )
2234 {
2235 SD_COMMAND_BLOCK SdCmdBlk;
2236 SD_STATUS_BLOCK SdStatusBlk;
2237 SD_COMMAND_PACKET Packet;
2238 EFI_STATUS Status;
2239
2240 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2241 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2242 ZeroMem (&Packet, sizeof (Packet));
2243
2244 Packet.SdCmdBlk = &SdCmdBlk;
2245 Packet.SdStatusBlk = &SdStatusBlk;
2246 Packet.Timeout = SD_TIMEOUT;
2247
2248 SdCmdBlk.CommandIndex = SD_SEND_STATUS;
2249 SdCmdBlk.CommandType = SdCommandTypeAc;
2250 SdCmdBlk.ResponseType = SdResponseTypeR1;
2251 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
2252
2253 Status = SdPeimExecCmd (Slot, &Packet);
2254 if (!EFI_ERROR (Status)) {
2255 *DevStatus = SdStatusBlk.Resp0;
2256 }
2257
2258 return Status;
2259 }
2260
2261 /**
2262 Send command READ_SINGLE_BLOCK/WRITE_SINGLE_BLOCK to the addressed SD device
2263 to read/write the specified number of blocks.
2264
2265 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2266
2267 @param[in] Slot The slot number of the SD card to send the command to.
2268 @param[in] Lba The logical block address of starting access.
2269 @param[in] BlockSize The block size of specified SD device partition.
2270 @param[in] Buffer The pointer to the transfer buffer.
2271 @param[in] BufferSize The size of transfer buffer.
2272 @param[in] IsRead Boolean to show the operation direction.
2273
2274 @retval EFI_SUCCESS The operation is done correctly.
2275 @retval Others The operation fails.
2276
2277 **/
2278 EFI_STATUS
2279 SdPeimRwSingleBlock (
2280 IN SD_PEIM_HC_SLOT *Slot,
2281 IN EFI_LBA Lba,
2282 IN UINT32 BlockSize,
2283 IN VOID *Buffer,
2284 IN UINTN BufferSize,
2285 IN BOOLEAN IsRead
2286 )
2287 {
2288 SD_COMMAND_BLOCK SdCmdBlk;
2289 SD_STATUS_BLOCK SdStatusBlk;
2290 SD_COMMAND_PACKET Packet;
2291 EFI_STATUS Status;
2292
2293 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2294 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2295 ZeroMem (&Packet, sizeof (Packet));
2296
2297 Packet.SdCmdBlk = &SdCmdBlk;
2298 Packet.SdStatusBlk = &SdStatusBlk;
2299 //
2300 // Calculate timeout value through the below formula.
2301 // Timeout = (transfer size) / (2MB/s).
2302 // Taking 2MB/s as divisor is because it's the lowest
2303 // transfer speed of class 2.
2304 //
2305 Packet.Timeout = (BufferSize / (2 * 1024 * 1024) + 1) * 1000 * 1000;;
2306
2307 if (IsRead) {
2308 Packet.InDataBuffer = Buffer;
2309 Packet.InTransferLength = (UINT32)BufferSize;
2310
2311 SdCmdBlk.CommandIndex = SD_READ_SINGLE_BLOCK;
2312 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2313 SdCmdBlk.ResponseType = SdResponseTypeR1;
2314 } else {
2315 Packet.OutDataBuffer = Buffer;
2316 Packet.OutTransferLength = (UINT32)BufferSize;
2317
2318 SdCmdBlk.CommandIndex = SD_WRITE_SINGLE_BLOCK;
2319 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2320 SdCmdBlk.ResponseType = SdResponseTypeR1;
2321 }
2322
2323 if (Slot->SectorAddressing) {
2324 SdCmdBlk.CommandArgument = (UINT32)Lba;
2325 } else {
2326 SdCmdBlk.CommandArgument = (UINT32)MultU64x32 (Lba, BlockSize);
2327 }
2328
2329 Status = SdPeimExecCmd (Slot, &Packet);
2330
2331 return Status;
2332 }
2333
2334 /**
2335 Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed SD device
2336 to read/write the specified number of blocks.
2337
2338 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2339
2340 @param[in] Slot The slot number of the SD card to send the command to.
2341 @param[in] Lba The logical block address of starting access.
2342 @param[in] BlockSize The block size of specified SD device partition.
2343 @param[in] Buffer The pointer to the transfer buffer.
2344 @param[in] BufferSize The size of transfer buffer.
2345 @param[in] IsRead Boolean to show the operation direction.
2346
2347 @retval EFI_SUCCESS The operation is done correctly.
2348 @retval Others The operation fails.
2349
2350 **/
2351 EFI_STATUS
2352 SdPeimRwMultiBlocks (
2353 IN SD_PEIM_HC_SLOT *Slot,
2354 IN EFI_LBA Lba,
2355 IN UINT32 BlockSize,
2356 IN VOID *Buffer,
2357 IN UINTN BufferSize,
2358 IN BOOLEAN IsRead
2359 )
2360 {
2361 SD_COMMAND_BLOCK SdCmdBlk;
2362 SD_STATUS_BLOCK SdStatusBlk;
2363 SD_COMMAND_PACKET Packet;
2364 EFI_STATUS Status;
2365
2366 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2367 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2368 ZeroMem (&Packet, sizeof (Packet));
2369
2370 Packet.SdCmdBlk = &SdCmdBlk;
2371 Packet.SdStatusBlk = &SdStatusBlk;
2372 //
2373 // Calculate timeout value through the below formula.
2374 // Timeout = (transfer size) / (2MB/s).
2375 // Taking 2MB/s as divisor is because it's the lowest
2376 // transfer speed of class 2.
2377 //
2378 Packet.Timeout = (BufferSize / (2 * 1024 * 1024) + 1) * 1000 * 1000;;
2379
2380 if (IsRead) {
2381 Packet.InDataBuffer = Buffer;
2382 Packet.InTransferLength = (UINT32)BufferSize;
2383
2384 SdCmdBlk.CommandIndex = SD_READ_MULTIPLE_BLOCK;
2385 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2386 SdCmdBlk.ResponseType = SdResponseTypeR1;
2387 } else {
2388 Packet.OutDataBuffer = Buffer;
2389 Packet.OutTransferLength = (UINT32)BufferSize;
2390
2391 SdCmdBlk.CommandIndex = SD_WRITE_MULTIPLE_BLOCK;
2392 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2393 SdCmdBlk.ResponseType = SdResponseTypeR1;
2394 }
2395
2396 if (Slot->SectorAddressing) {
2397 SdCmdBlk.CommandArgument = (UINT32)Lba;
2398 } else {
2399 SdCmdBlk.CommandArgument = (UINT32)MultU64x32 (Lba, BlockSize);
2400 }
2401
2402 Status = SdPeimExecCmd (Slot, &Packet);
2403
2404 return Status;
2405 }
2406
2407 /**
2408 Send command SEND_TUNING_BLOCK to the SD device for SDR104/SDR50 optimal sampling point
2409 detection.
2410
2411 It may be sent up to 40 times until the host finishes the tuning procedure.
2412
2413 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2414
2415 @param[in] Slot The slot number of the SD card to send the command to.
2416
2417 @retval EFI_SUCCESS The operation is done correctly.
2418 @retval Others The operation fails.
2419
2420 **/
2421 EFI_STATUS
2422 SdPeimSendTuningBlk (
2423 IN SD_PEIM_HC_SLOT *Slot
2424 )
2425 {
2426 SD_COMMAND_BLOCK SdCmdBlk;
2427 SD_STATUS_BLOCK SdStatusBlk;
2428 SD_COMMAND_PACKET Packet;
2429 EFI_STATUS Status;
2430 UINT8 TuningBlock[64];
2431
2432 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2433 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2434 ZeroMem (&Packet, sizeof (Packet));
2435
2436 Packet.SdCmdBlk = &SdCmdBlk;
2437 Packet.SdStatusBlk = &SdStatusBlk;
2438 Packet.Timeout = SD_TIMEOUT;
2439
2440 SdCmdBlk.CommandIndex = SD_SEND_TUNING_BLOCK;
2441 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2442 SdCmdBlk.ResponseType = SdResponseTypeR1;
2443 SdCmdBlk.CommandArgument = 0;
2444
2445 Packet.InDataBuffer = TuningBlock;
2446 Packet.InTransferLength = sizeof (TuningBlock);
2447
2448 Status = SdPeimExecCmd (Slot, &Packet);
2449
2450 return Status;
2451 }
2452
2453 /**
2454 Tunning the sampling point of SDR104 or SDR50 bus speed mode.
2455
2456 Command SD_SEND_TUNING_BLOCK may be sent up to 40 times until the host finishes the
2457 tuning procedure.
2458
2459 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and SD Host Controller
2460 Simplified Spec 3.0 Figure 2-29 for details.
2461
2462 @param[in] Slot The slot number of the SD card to send the command to.
2463
2464 @retval EFI_SUCCESS The operation is done correctly.
2465 @retval Others The operation fails.
2466
2467 **/
2468 EFI_STATUS
2469 SdPeimTuningClock (
2470 IN SD_PEIM_HC_SLOT *Slot
2471 )
2472 {
2473 EFI_STATUS Status;
2474 UINT8 HostCtrl2;
2475 UINT8 Retry;
2476
2477 //
2478 // Notify the host that the sampling clock tuning procedure starts.
2479 //
2480 HostCtrl2 = BIT6;
2481 Status = SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2482 if (EFI_ERROR (Status)) {
2483 return Status;
2484 }
2485 //
2486 // Ask the device to send a sequence of tuning blocks till the tuning procedure is done.
2487 //
2488 Retry = 0;
2489 do {
2490 Status = SdPeimSendTuningBlk (Slot);
2491 if (EFI_ERROR (Status)) {
2492 return Status;
2493 }
2494
2495 Status = SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);
2496 if (EFI_ERROR (Status)) {
2497 return Status;
2498 }
2499
2500 if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {
2501 break;
2502 }
2503 } while (++Retry < 40);
2504
2505 if (Retry == 40) {
2506 Status = EFI_TIMEOUT;
2507 }
2508 return Status;
2509 }
2510
2511 /**
2512 Switch the bus width to specified width.
2513
2514 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and
2515 SD Host Controller Simplified Spec 3.0 section Figure 3-7 for details.
2516
2517 @param[in] Slot The slot number of the SD card to send the command to.
2518 @param[in] Rca The relative device address to be assigned.
2519 @param[in] BusWidth The bus width to be set, it could be 4 or 8.
2520
2521 @retval EFI_SUCCESS The operation is done correctly.
2522 @retval Others The operation fails.
2523
2524 **/
2525 EFI_STATUS
2526 SdPeimSwitchBusWidth (
2527 IN SD_PEIM_HC_SLOT *Slot,
2528 IN UINT16 Rca,
2529 IN UINT8 BusWidth
2530 )
2531 {
2532 EFI_STATUS Status;
2533 UINT32 DevStatus;
2534
2535 Status = SdPeimSetBusWidth (Slot, Rca, BusWidth);
2536 if (EFI_ERROR (Status)) {
2537 return Status;
2538 }
2539
2540 Status = SdPeimSendStatus (Slot, Rca, &DevStatus);
2541 if (EFI_ERROR (Status)) {
2542 return Status;
2543 }
2544 //
2545 // Check the switch operation is really successful or not.
2546 //
2547 if ((DevStatus >> 16) != 0) {
2548 return EFI_DEVICE_ERROR;
2549 }
2550
2551 Status = SdPeimHcSetBusWidth (Slot->SdHcBase, BusWidth);
2552
2553 return Status;
2554 }
2555
2556 /**
2557 Switch the high speed timing according to request.
2558
2559 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and
2560 SD Host Controller Simplified Spec 3.0 section Figure 2-29 for details.
2561
2562 @param[in] Slot The slot number of the SD card to send the command to.
2563 @param[in] Rca The relative device address to be assigned.
2564 @param[in] S18a The boolean to show if it's a UHS-I SD card.
2565
2566 @retval EFI_SUCCESS The operation is done correctly.
2567 @retval Others The operation fails.
2568
2569 **/
2570 EFI_STATUS
2571 SdPeimSetBusMode (
2572 IN SD_PEIM_HC_SLOT *Slot,
2573 IN UINT16 Rca,
2574 IN BOOLEAN S18a
2575 )
2576 {
2577 EFI_STATUS Status;
2578 SD_HC_SLOT_CAP Capability;
2579 UINT32 ClockFreq;
2580 UINT8 BusWidth;
2581 UINT8 AccessMode;
2582 UINT8 HostCtrl1;
2583 UINT8 HostCtrl2;
2584
2585 Status = SdPeimGetCsd (Slot, Rca, &Slot->Csd);
2586 if (EFI_ERROR (Status)) {
2587 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimGetCsd fails with %r\n", Status));
2588 return Status;
2589 }
2590
2591 Status = SdPeimHcGetCapability (Slot->SdHcBase, &Capability);
2592 if (EFI_ERROR (Status)) {
2593 return Status;
2594 }
2595
2596 Status = SdPeimSelect (Slot, Rca);
2597 if (EFI_ERROR (Status)) {
2598 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSelect fails with %r\n", Status));
2599 return Status;
2600 }
2601
2602 BusWidth = 4;
2603 Status = SdPeimSwitchBusWidth (Slot, Rca, BusWidth);
2604 if (EFI_ERROR (Status)) {
2605 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSwitchBusWidth fails with %r\n", Status));
2606 return Status;
2607 }
2608
2609 //
2610 // Calculate supported bus speed/bus width/clock frequency.
2611 //
2612 ClockFreq = 0;
2613 if (S18a && (Capability.Sdr104 != 0)) {
2614 ClockFreq = 208;
2615 AccessMode = 3;
2616 } else if (S18a && (Capability.Sdr50 != 0)) {
2617 ClockFreq = 100;
2618 AccessMode = 2;
2619 } else if (S18a && (Capability.Ddr50 != 0)) {
2620 ClockFreq = 50;
2621 AccessMode = 4;
2622 } else {
2623 ClockFreq = 50;
2624 AccessMode = 1;
2625 }
2626
2627 DEBUG ((EFI_D_INFO, "AccessMode %d ClockFreq %d BusWidth %d\n", AccessMode, ClockFreq, BusWidth));
2628
2629 Status = SdPeimSwitch (Slot, AccessMode, 0, 0, 0, TRUE);
2630 if (EFI_ERROR (Status)) {
2631 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSwitch fails with %r\n", Status));
2632 return Status;
2633 }
2634
2635 //
2636 // Set to Hight Speed timing
2637 //
2638 if (AccessMode == 1) {
2639 HostCtrl1 = BIT2;
2640 Status = SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
2641 if (EFI_ERROR (Status)) {
2642 return Status;
2643 }
2644 }
2645
2646 HostCtrl2 = (UINT8)~0x7;
2647 Status = SdPeimHcAndMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2648 if (EFI_ERROR (Status)) {
2649 return Status;
2650 }
2651 HostCtrl2 = AccessMode;
2652 Status = SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2653 if (EFI_ERROR (Status)) {
2654 return Status;
2655 }
2656
2657 Status = SdPeimHcClockSupply (Slot->SdHcBase, ClockFreq * 1000);
2658 if (EFI_ERROR (Status)) {
2659 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimHcClockSupply %r\n", Status));
2660 return Status;
2661 }
2662
2663 if ((AccessMode == 3) || ((AccessMode == 2) && (Capability.TuningSDR50 != 0))) {
2664 Status = SdPeimTuningClock (Slot);
2665 if (EFI_ERROR (Status)) {
2666 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimTuningClock fails with %r\n", Status));
2667 return Status;
2668 }
2669 }
2670
2671 DEBUG ((EFI_D_INFO, "SdPeimSetBusMode: SdPeimSetBusMode %r\n", Status));
2672
2673 return Status;
2674 }
2675
2676 /**
2677 Execute SD device identification procedure.
2678
2679 Refer to SD Physical Layer Simplified Spec 4.1 Section 3.6 for details.
2680
2681 @param[in] Slot The slot number of the SD card to send the command to.
2682
2683 @retval EFI_SUCCESS There is a SD card.
2684 @retval Others There is not a SD card.
2685
2686 **/
2687 EFI_STATUS
2688 SdPeimIdentification (
2689 IN SD_PEIM_HC_SLOT *Slot
2690 )
2691 {
2692 EFI_STATUS Status;
2693 UINT32 Ocr;
2694 UINT16 Rca;
2695 BOOLEAN Xpc;
2696 BOOLEAN S18r;
2697 UINT64 MaxCurrent;
2698 UINT64 Current;
2699 UINT16 ControllerVer;
2700 UINT8 PowerCtrl;
2701 UINT32 PresentState;
2702 UINT8 HostCtrl2;
2703 SD_HC_SLOT_CAP Capability;
2704
2705 //
2706 // 1. Send Cmd0 to the device
2707 //
2708 Status = SdPeimReset (Slot);
2709 if (EFI_ERROR (Status)) {
2710 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing Cmd0 fails with %r\n", Status));
2711 return Status;
2712 }
2713 //
2714 // 2. Send Cmd8 to the device
2715 //
2716 Status = SdPeimVoltageCheck (Slot, 0x1, 0xFF);
2717 if (EFI_ERROR (Status)) {
2718 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing Cmd8 fails with %r\n", Status));
2719 return Status;
2720 }
2721 //
2722 // 3. Send SDIO Cmd5 to the device to the SDIO device OCR register.
2723 //
2724 Status = SdioSendOpCond (Slot, 0, FALSE);
2725 if (!EFI_ERROR (Status)) {
2726 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Found SDIO device, ignore it as we don't support\n"));
2727 return EFI_DEVICE_ERROR;
2728 }
2729 //
2730 // 4. Send Acmd41 with voltage window 0 to the device
2731 //
2732 Status = SdPeimSendOpCond (Slot, 0, 0, FALSE, FALSE, FALSE, &Ocr);
2733 if (EFI_ERROR (Status)) {
2734 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimSendOpCond fails with %r\n", Status));
2735 return EFI_DEVICE_ERROR;
2736 }
2737
2738 Status = SdPeimHcGetCapability (Slot->SdHcBase, &Capability);
2739 if (EFI_ERROR (Status)) {
2740 return Status;
2741 }
2742
2743 Status = SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_MAX_CURRENT_CAP, TRUE, sizeof (Current), &Current);
2744 if (EFI_ERROR (Status)) {
2745 return Status;
2746 }
2747
2748 if (Capability.Voltage33 != 0) {
2749 //
2750 // Support 3.3V
2751 //
2752 MaxCurrent = ((UINT32)Current & 0xFF) * 4;
2753 } else if (Capability.Voltage30 != 0) {
2754 //
2755 // Support 3.0V
2756 //
2757 MaxCurrent = (((UINT32)Current >> 8) & 0xFF) * 4;
2758 } else if (Capability.Voltage18 != 0) {
2759 //
2760 // Support 1.8V
2761 //
2762 MaxCurrent = (((UINT32)Current >> 16) & 0xFF) * 4;
2763 } else {
2764 ASSERT (FALSE);
2765 return EFI_DEVICE_ERROR;
2766 }
2767
2768 if (MaxCurrent >= 150) {
2769 Xpc = TRUE;
2770 } else {
2771 Xpc = FALSE;
2772 }
2773
2774 Status = SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
2775 if (EFI_ERROR (Status)) {
2776 return Status;
2777 }
2778
2779 if ((ControllerVer & 0xFF) == 2) {
2780 S18r = TRUE;
2781 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
2782 S18r = FALSE;
2783 } else {
2784 ASSERT (FALSE);
2785 return EFI_UNSUPPORTED;
2786 }
2787 //
2788 // 5. Repeatly send Acmd41 with supply voltage window to the device.
2789 // Note here we only support the cards complied with SD physical
2790 // layer simplified spec version 2.0 and version 3.0 and above.
2791 //
2792 do {
2793 Status = SdPeimSendOpCond (Slot, 0, Ocr, S18r, Xpc, TRUE, &Ocr);
2794 if (EFI_ERROR (Status)) {
2795 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SdPeimSendOpCond fails with %r Ocr %x, S18r %x, Xpc %x\n", Status, Ocr, S18r, Xpc));
2796 return EFI_DEVICE_ERROR;
2797 }
2798 } while ((Ocr & BIT31) == 0);
2799
2800 //
2801 // 6. If the S18a bit is set and the Host Controller supports 1.8V signaling
2802 // (One of support bits is set to 1: SDR50, SDR104 or DDR50 in the
2803 // Capabilities register), switch its voltage to 1.8V.
2804 //
2805 if ((Capability.Sdr50 != 0 ||
2806 Capability.Sdr104 != 0 ||
2807 Capability.Ddr50 != 0) &&
2808 ((Ocr & BIT24) != 0)) {
2809 Status = SdPeimVoltageSwitch (Slot);
2810 if (EFI_ERROR (Status)) {
2811 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimVoltageSwitch fails with %r\n", Status));
2812 Status = EFI_DEVICE_ERROR;
2813 goto Error;
2814 } else {
2815 Status = SdPeimHcStopClock (Slot->SdHcBase);
2816 if (EFI_ERROR (Status)) {
2817 Status = EFI_DEVICE_ERROR;
2818 goto Error;
2819 }
2820
2821 SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
2822 if (((PresentState >> 20) & 0xF) != 0) {
2823 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SwitchVoltage fails with PresentState = 0x%x\n", PresentState));
2824 Status = EFI_DEVICE_ERROR;
2825 goto Error;
2826 }
2827 HostCtrl2 = BIT3;
2828 SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2829
2830 MicroSecondDelay (5000);
2831
2832 SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);
2833 if ((HostCtrl2 & BIT3) == 0) {
2834 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SwitchVoltage fails with HostCtrl2 = 0x%x\n", HostCtrl2));
2835 Status = EFI_DEVICE_ERROR;
2836 goto Error;
2837 }
2838
2839 SdPeimHcInitClockFreq (Slot->SdHcBase);
2840
2841 MicroSecondDelay (1000);
2842
2843 SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
2844 if (((PresentState >> 20) & 0xF) != 0xF) {
2845 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SwitchVoltage fails with PresentState = 0x%x, It should be 0xF\n", PresentState));
2846 Status = EFI_DEVICE_ERROR;
2847 goto Error;
2848 }
2849 }
2850 DEBUG ((EFI_D_INFO, "SdPeimIdentification: Switch to 1.8v signal voltage success\n"));
2851 }
2852
2853 Status = SdPeimAllSendCid (Slot);
2854 if (EFI_ERROR (Status)) {
2855 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimAllSendCid fails with %r\n", Status));
2856 return Status;
2857 }
2858
2859 Status = SdPeimSetRca (Slot, &Rca);
2860 if (EFI_ERROR (Status)) {
2861 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimSetRca fails with %r\n", Status));
2862 return Status;
2863 }
2864 //
2865 // Enter Data Tranfer Mode.
2866 //
2867 DEBUG ((EFI_D_INFO, "Found a SD device at slot [%d]\n", Slot));
2868
2869 Status = SdPeimSetBusMode (Slot, Rca, ((Ocr & BIT24) != 0));
2870
2871 return Status;
2872
2873 Error:
2874 //
2875 // Set SD Bus Power = 0
2876 //
2877 PowerCtrl = (UINT8)~BIT0;
2878 Status = SdPeimHcAndMmio (Slot->SdHcBase + SD_HC_POWER_CTRL, sizeof (PowerCtrl), &PowerCtrl);
2879 return EFI_DEVICE_ERROR;
2880 }
EFI Development Kit II mirror for PVE