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UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm
[mirror_edk2.git] / MdeModulePkg / Bus / Sd / SdBlockIoPei / SdHci.c
1 /** @file
2
3 Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
4 SPDX-License-Identifier: BSD-2-Clause-Patent
5
6 **/
7
8 #include "SdBlockIoPei.h"
9
10 /**
11 Read/Write specified SD host controller mmio register.
12
13 @param[in] Address The address of the mmio register to be read/written.
14 @param[in] Read A boolean to indicate it's read or write operation.
15 @param[in] Count The width of the mmio register in bytes.
16 Must be 1, 2 , 4 or 8 bytes.
17 @param[in, out] Data For read operations, the destination buffer to store
18 the results. For write operations, the source buffer
19 to write data from. The caller is responsible for
20 having ownership of the data buffer and ensuring its
21 size not less than Count bytes.
22
23 @retval EFI_INVALID_PARAMETER The Address or the Data or the Count is not valid.
24 @retval EFI_SUCCESS The read/write operation succeeds.
25 @retval Others The read/write operation fails.
26
27 **/
28 EFI_STATUS
29 EFIAPI
30 SdPeimHcRwMmio (
31 IN UINTN Address,
32 IN BOOLEAN Read,
33 IN UINT8 Count,
34 IN OUT VOID *Data
35 )
36 {
37 if ((Address == 0) || (Data == NULL)) {
38 return EFI_INVALID_PARAMETER;
39 }
40
41 if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
42 return EFI_INVALID_PARAMETER;
43 }
44
45 switch (Count) {
46 case 1:
47 if (Read) {
48 *(UINT8*)Data = MmioRead8 (Address);
49 } else {
50 MmioWrite8 (Address, *(UINT8*)Data);
51 }
52 break;
53 case 2:
54 if (Read) {
55 *(UINT16*)Data = MmioRead16 (Address);
56 } else {
57 MmioWrite16 (Address, *(UINT16*)Data);
58 }
59 break;
60 case 4:
61 if (Read) {
62 *(UINT32*)Data = MmioRead32 (Address);
63 } else {
64 MmioWrite32 (Address, *(UINT32*)Data);
65 }
66 break;
67 case 8:
68 if (Read) {
69 *(UINT64*)Data = MmioRead64 (Address);
70 } else {
71 MmioWrite64 (Address, *(UINT64*)Data);
72 }
73 break;
74 default:
75 ASSERT (FALSE);
76 return EFI_INVALID_PARAMETER;
77 }
78
79 return EFI_SUCCESS;
80 }
81
82 /**
83 Do OR operation with the value of the specified SD host controller mmio register.
84
85 @param[in] Address The address of the mmio register to be read/written.
86 @param[in] Count The width of the mmio register in bytes.
87 Must be 1, 2 , 4 or 8 bytes.
88 @param[in] OrData The pointer to the data used to do OR operation.
89 The caller is responsible for having ownership of
90 the data buffer and ensuring its size not less than
91 Count bytes.
92
93 @retval EFI_INVALID_PARAMETER The Address or the OrData or the Count is not valid.
94 @retval EFI_SUCCESS The OR operation succeeds.
95 @retval Others The OR operation fails.
96
97 **/
98 EFI_STATUS
99 EFIAPI
100 SdPeimHcOrMmio (
101 IN UINTN Address,
102 IN UINT8 Count,
103 IN VOID *OrData
104 )
105 {
106 EFI_STATUS Status;
107 UINT64 Data;
108 UINT64 Or;
109
110 Status = SdPeimHcRwMmio (Address, TRUE, Count, &Data);
111 if (EFI_ERROR (Status)) {
112 return Status;
113 }
114
115 if (Count == 1) {
116 Or = *(UINT8*) OrData;
117 } else if (Count == 2) {
118 Or = *(UINT16*) OrData;
119 } else if (Count == 4) {
120 Or = *(UINT32*) OrData;
121 } else if (Count == 8) {
122 Or = *(UINT64*) OrData;
123 } else {
124 return EFI_INVALID_PARAMETER;
125 }
126
127 Data |= Or;
128 Status = SdPeimHcRwMmio (Address, FALSE, Count, &Data);
129
130 return Status;
131 }
132
133 /**
134 Do AND operation with the value of the specified SD host controller mmio register.
135
136 @param[in] Address The address of the mmio register to be read/written.
137 @param[in] Count The width of the mmio register in bytes.
138 Must be 1, 2 , 4 or 8 bytes.
139 @param[in] AndData The pointer to the data used to do AND operation.
140 The caller is responsible for having ownership of
141 the data buffer and ensuring its size not less than
142 Count bytes.
143
144 @retval EFI_INVALID_PARAMETER The Address or the AndData or the Count is not valid.
145 @retval EFI_SUCCESS The AND operation succeeds.
146 @retval Others The AND operation fails.
147
148 **/
149 EFI_STATUS
150 EFIAPI
151 SdPeimHcAndMmio (
152 IN UINTN Address,
153 IN UINT8 Count,
154 IN VOID *AndData
155 )
156 {
157 EFI_STATUS Status;
158 UINT64 Data;
159 UINT64 And;
160
161 Status = SdPeimHcRwMmio (Address, TRUE, Count, &Data);
162 if (EFI_ERROR (Status)) {
163 return Status;
164 }
165
166 if (Count == 1) {
167 And = *(UINT8*) AndData;
168 } else if (Count == 2) {
169 And = *(UINT16*) AndData;
170 } else if (Count == 4) {
171 And = *(UINT32*) AndData;
172 } else if (Count == 8) {
173 And = *(UINT64*) AndData;
174 } else {
175 return EFI_INVALID_PARAMETER;
176 }
177
178 Data &= And;
179 Status = SdPeimHcRwMmio (Address, FALSE, Count, &Data);
180
181 return Status;
182 }
183
184 /**
185 Wait for the value of the specified MMIO register set to the test value.
186
187 @param[in] Address The address of the mmio register to be checked.
188 @param[in] Count The width of the mmio register in bytes.
189 Must be 1, 2, 4 or 8 bytes.
190 @param[in] MaskValue The mask value of memory.
191 @param[in] TestValue The test value of memory.
192
193 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.
194 @retval EFI_SUCCESS The MMIO register has expected value.
195 @retval Others The MMIO operation fails.
196
197 **/
198 EFI_STATUS
199 EFIAPI
200 SdPeimHcCheckMmioSet (
201 IN UINTN Address,
202 IN UINT8 Count,
203 IN UINT64 MaskValue,
204 IN UINT64 TestValue
205 )
206 {
207 EFI_STATUS Status;
208 UINT64 Value;
209
210 //
211 // Access PCI MMIO space to see if the value is the tested one.
212 //
213 Value = 0;
214 Status = SdPeimHcRwMmio (Address, TRUE, Count, &Value);
215 if (EFI_ERROR (Status)) {
216 return Status;
217 }
218
219 Value &= MaskValue;
220
221 if (Value == TestValue) {
222 return EFI_SUCCESS;
223 }
224
225 return EFI_NOT_READY;
226 }
227
228 /**
229 Wait for the value of the specified MMIO register set to the test value.
230
231 @param[in] Address The address of the mmio register to wait.
232 @param[in] Count The width of the mmio register in bytes.
233 Must be 1, 2, 4 or 8 bytes.
234 @param[in] MaskValue The mask value of memory.
235 @param[in] TestValue The test value of memory.
236 @param[in] Timeout The time out value for wait memory set, uses 1
237 microsecond as a unit.
238
239 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout
240 range.
241 @retval EFI_SUCCESS The MMIO register has expected value.
242 @retval Others The MMIO operation fails.
243
244 **/
245 EFI_STATUS
246 EFIAPI
247 SdPeimHcWaitMmioSet (
248 IN UINTN Address,
249 IN UINT8 Count,
250 IN UINT64 MaskValue,
251 IN UINT64 TestValue,
252 IN UINT64 Timeout
253 )
254 {
255 EFI_STATUS Status;
256 BOOLEAN InfiniteWait;
257
258 if (Timeout == 0) {
259 InfiniteWait = TRUE;
260 } else {
261 InfiniteWait = FALSE;
262 }
263
264 while (InfiniteWait || (Timeout > 0)) {
265 Status = SdPeimHcCheckMmioSet (
266 Address,
267 Count,
268 MaskValue,
269 TestValue
270 );
271 if (Status != EFI_NOT_READY) {
272 return Status;
273 }
274
275 //
276 // Stall for 1 microsecond.
277 //
278 MicroSecondDelay (1);
279
280 Timeout--;
281 }
282
283 return EFI_TIMEOUT;
284 }
285
286 /**
287 Software reset the specified SD host controller and enable all interrupts.
288
289 @param[in] Bar The mmio base address of the slot to be accessed.
290
291 @retval EFI_SUCCESS The software reset executes successfully.
292 @retval Others The software reset fails.
293
294 **/
295 EFI_STATUS
296 SdPeimHcReset (
297 IN UINTN Bar
298 )
299 {
300 EFI_STATUS Status;
301 UINT8 SwReset;
302
303 SwReset = 0xFF;
304 Status = SdPeimHcRwMmio (Bar + SD_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);
305
306 if (EFI_ERROR (Status)) {
307 DEBUG ((EFI_D_ERROR, "SdPeimHcReset: write full 1 fails: %r\n", Status));
308 return Status;
309 }
310
311 Status = SdPeimHcWaitMmioSet (
312 Bar + SD_HC_SW_RST,
313 sizeof (SwReset),
314 0xFF,
315 0x00,
316 SD_TIMEOUT
317 );
318 if (EFI_ERROR (Status)) {
319 DEBUG ((EFI_D_INFO, "SdPeimHcReset: reset done with %r\n", Status));
320 return Status;
321 }
322 //
323 // Enable all interrupt after reset all.
324 //
325 Status = SdPeimHcEnableInterrupt (Bar);
326
327 return Status;
328 }
329
330 /**
331 Set all interrupt status bits in Normal and Error Interrupt Status Enable
332 register.
333
334 @param[in] Bar The mmio base address of the slot to be accessed.
335
336 @retval EFI_SUCCESS The operation executes successfully.
337 @retval Others The operation fails.
338
339 **/
340 EFI_STATUS
341 SdPeimHcEnableInterrupt (
342 IN UINTN Bar
343 )
344 {
345 EFI_STATUS Status;
346 UINT16 IntStatus;
347
348 //
349 // Enable all bits in Error Interrupt Status Enable Register
350 //
351 IntStatus = 0xFFFF;
352 Status = SdPeimHcRwMmio (Bar + SD_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
353 if (EFI_ERROR (Status)) {
354 return Status;
355 }
356 //
357 // Enable all bits in Normal Interrupt Status Enable Register
358 //
359 IntStatus = 0xFFFF;
360 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);
361
362 return Status;
363 }
364
365 /**
366 Get the capability data from the specified slot.
367
368 @param[in] Bar The mmio base address of the slot to be accessed.
369 @param[out] Capability The buffer to store the capability data.
370
371 @retval EFI_SUCCESS The operation executes successfully.
372 @retval Others The operation fails.
373
374 **/
375 EFI_STATUS
376 SdPeimHcGetCapability (
377 IN UINTN Bar,
378 OUT SD_HC_SLOT_CAP *Capability
379 )
380 {
381 EFI_STATUS Status;
382 UINT64 Cap;
383
384 Status = SdPeimHcRwMmio (Bar + SD_HC_CAP, TRUE, sizeof (Cap), &Cap);
385 if (EFI_ERROR (Status)) {
386 return Status;
387 }
388
389 CopyMem (Capability, &Cap, sizeof (Cap));
390
391 return EFI_SUCCESS;
392 }
393
394 /**
395 Detect whether there is a SD card attached at the specified SD host controller
396 slot.
397
398 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.
399
400 @param[in] Bar The mmio base address of the slot to be accessed.
401
402 @retval EFI_SUCCESS There is a SD card attached.
403 @retval EFI_NO_MEDIA There is not a SD card attached.
404 @retval Others The detection fails.
405
406 **/
407 EFI_STATUS
408 SdPeimHcCardDetect (
409 IN UINTN Bar
410 )
411 {
412 EFI_STATUS Status;
413 UINT16 Data;
414 UINT32 PresentState;
415
416 //
417 // Check Normal Interrupt Status Register
418 //
419 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);
420 if (EFI_ERROR (Status)) {
421 return Status;
422 }
423
424 if ((Data & (BIT6 | BIT7)) != 0) {
425 //
426 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.
427 //
428 Data &= BIT6 | BIT7;
429 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);
430 if (EFI_ERROR (Status)) {
431 return Status;
432 }
433 }
434
435 //
436 // Check Present State Register to see if there is a card presented.
437 //
438 Status = SdPeimHcRwMmio (Bar + SD_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
439 if (EFI_ERROR (Status)) {
440 return Status;
441 }
442
443 if ((PresentState & BIT16) != 0) {
444 return EFI_SUCCESS;
445 } else {
446 return EFI_NO_MEDIA;
447 }
448 }
449
450 /**
451 Stop SD card clock.
452
453 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.
454
455 @param[in] Bar The mmio base address of the slot to be accessed.
456
457 @retval EFI_SUCCESS Succeed to stop SD clock.
458 @retval Others Fail to stop SD clock.
459
460 **/
461 EFI_STATUS
462 SdPeimHcStopClock (
463 IN UINTN Bar
464 )
465 {
466 EFI_STATUS Status;
467 UINT32 PresentState;
468 UINT16 ClockCtrl;
469
470 //
471 // Ensure no SD transactions are occurring on the SD Bus by
472 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)
473 // in the Present State register to be 0.
474 //
475 Status = SdPeimHcWaitMmioSet (
476 Bar + SD_HC_PRESENT_STATE,
477 sizeof (PresentState),
478 BIT0 | BIT1,
479 0,
480 SD_TIMEOUT
481 );
482 if (EFI_ERROR (Status)) {
483 return Status;
484 }
485
486 //
487 // Set SD Clock Enable in the Clock Control register to 0
488 //
489 ClockCtrl = (UINT16)~BIT2;
490 Status = SdPeimHcAndMmio (Bar + SD_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
491
492 return Status;
493 }
494
495 /**
496 SD card clock supply.
497
498 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
499
500 @param[in] Bar The mmio base address of the slot to be accessed.
501 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
502
503 @retval EFI_SUCCESS The clock is supplied successfully.
504 @retval Others The clock isn't supplied successfully.
505
506 **/
507 EFI_STATUS
508 SdPeimHcClockSupply (
509 IN UINTN Bar,
510 IN UINT64 ClockFreq
511 )
512 {
513 EFI_STATUS Status;
514 SD_HC_SLOT_CAP Capability;
515 UINT32 BaseClkFreq;
516 UINT32 SettingFreq;
517 UINT32 Divisor;
518 UINT32 Remainder;
519 UINT16 ControllerVer;
520 UINT16 ClockCtrl;
521
522 //
523 // Calculate a divisor for SD clock frequency
524 //
525 Status = SdPeimHcGetCapability (Bar, &Capability);
526 if (EFI_ERROR (Status)) {
527 return Status;
528 }
529 ASSERT (Capability.BaseClkFreq != 0);
530
531 BaseClkFreq = Capability.BaseClkFreq;
532
533 if (ClockFreq == 0) {
534 return EFI_INVALID_PARAMETER;
535 }
536
537 if (ClockFreq > (BaseClkFreq * 1000)) {
538 ClockFreq = BaseClkFreq * 1000;
539 }
540
541 //
542 // Calculate the divisor of base frequency.
543 //
544 Divisor = 0;
545 SettingFreq = BaseClkFreq * 1000;
546 while (ClockFreq < SettingFreq) {
547 Divisor++;
548
549 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);
550 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);
551 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {
552 break;
553 }
554 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {
555 SettingFreq ++;
556 }
557 }
558
559 DEBUG ((EFI_D_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));
560
561 Status = SdPeimHcRwMmio (Bar + SD_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
562 if (EFI_ERROR (Status)) {
563 return Status;
564 }
565 //
566 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.
567 //
568 if ((ControllerVer & 0xFF) == 2) {
569 ASSERT (Divisor <= 0x3FF);
570 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);
571 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
572 //
573 // Only the most significant bit can be used as divisor.
574 //
575 if (((Divisor - 1) & Divisor) != 0) {
576 Divisor = 1 << (HighBitSet32 (Divisor) + 1);
577 }
578 ASSERT (Divisor <= 0x80);
579 ClockCtrl = (Divisor & 0xFF) << 8;
580 } else {
581 DEBUG ((EFI_D_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));
582 return EFI_UNSUPPORTED;
583 }
584
585 //
586 // Stop bus clock at first
587 //
588 Status = SdPeimHcStopClock (Bar);
589 if (EFI_ERROR (Status)) {
590 return Status;
591 }
592
593 //
594 // Supply clock frequency with specified divisor
595 //
596 ClockCtrl |= BIT0;
597 Status = SdPeimHcRwMmio (Bar + SD_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);
598 if (EFI_ERROR (Status)) {
599 DEBUG ((EFI_D_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));
600 return Status;
601 }
602
603 //
604 // Wait Internal Clock Stable in the Clock Control register to be 1
605 //
606 Status = SdPeimHcWaitMmioSet (
607 Bar + SD_HC_CLOCK_CTRL,
608 sizeof (ClockCtrl),
609 BIT1,
610 BIT1,
611 SD_TIMEOUT
612 );
613 if (EFI_ERROR (Status)) {
614 return Status;
615 }
616
617 //
618 // Set SD Clock Enable in the Clock Control register to 1
619 //
620 ClockCtrl = BIT2;
621 Status = SdPeimHcOrMmio (Bar + SD_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);
622
623 return Status;
624 }
625
626 /**
627 SD bus power control.
628
629 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
630
631 @param[in] Bar The mmio base address of the slot to be accessed.
632 @param[in] PowerCtrl The value setting to the power control register.
633
634 @retval TRUE There is a SD card attached.
635 @retval FALSE There is no a SD card attached.
636
637 **/
638 EFI_STATUS
639 SdPeimHcPowerControl (
640 IN UINTN Bar,
641 IN UINT8 PowerCtrl
642 )
643 {
644 EFI_STATUS Status;
645
646 //
647 // Clr SD Bus Power
648 //
649 PowerCtrl &= (UINT8)~BIT0;
650 Status = SdPeimHcRwMmio (Bar + SD_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
651 if (EFI_ERROR (Status)) {
652 return Status;
653 }
654
655 //
656 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
657 //
658 PowerCtrl |= BIT0;
659 Status = SdPeimHcRwMmio (Bar + SD_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);
660
661 return Status;
662 }
663
664 /**
665 Set the SD bus width.
666
667 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.
668
669 @param[in] Bar The mmio base address of the slot to be accessed.
670 @param[in] BusWidth The bus width used by the SD device, it must be 1, 4 or 8.
671
672 @retval EFI_SUCCESS The bus width is set successfully.
673 @retval Others The bus width isn't set successfully.
674
675 **/
676 EFI_STATUS
677 SdPeimHcSetBusWidth (
678 IN UINTN Bar,
679 IN UINT16 BusWidth
680 )
681 {
682 EFI_STATUS Status;
683 UINT8 HostCtrl1;
684
685 if (BusWidth == 1) {
686 HostCtrl1 = (UINT8)~(BIT5 | BIT1);
687 Status = SdPeimHcAndMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
688 } else if (BusWidth == 4) {
689 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
690 if (EFI_ERROR (Status)) {
691 return Status;
692 }
693 HostCtrl1 |= BIT1;
694 HostCtrl1 &= (UINT8)~BIT5;
695 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
696 } else if (BusWidth == 8) {
697 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);
698 if (EFI_ERROR (Status)) {
699 return Status;
700 }
701 HostCtrl1 &= (UINT8)~BIT1;
702 HostCtrl1 |= BIT5;
703 Status = SdPeimHcRwMmio (Bar + SD_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);
704 } else {
705 ASSERT (FALSE);
706 return EFI_INVALID_PARAMETER;
707 }
708
709 return Status;
710 }
711
712 /**
713 Supply SD card with lowest clock frequency at initialization.
714
715 @param[in] Bar The mmio base address of the slot to be accessed.
716
717 @retval EFI_SUCCESS The clock is supplied successfully.
718 @retval Others The clock isn't supplied successfully.
719
720 **/
721 EFI_STATUS
722 SdPeimHcInitClockFreq (
723 IN UINTN Bar
724 )
725 {
726 EFI_STATUS Status;
727 SD_HC_SLOT_CAP Capability;
728 UINT32 InitFreq;
729
730 //
731 // Calculate a divisor for SD clock frequency
732 //
733 Status = SdPeimHcGetCapability (Bar, &Capability);
734 if (EFI_ERROR (Status)) {
735 return Status;
736 }
737
738 if (Capability.BaseClkFreq == 0) {
739 //
740 // Don't support get Base Clock Frequency information via another method
741 //
742 return EFI_UNSUPPORTED;
743 }
744 //
745 // Supply 400KHz clock frequency at initialization phase.
746 //
747 InitFreq = 400;
748 Status = SdPeimHcClockSupply (Bar, InitFreq);
749 return Status;
750 }
751
752 /**
753 Supply SD card with maximum voltage at initialization.
754
755 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.
756
757 @param[in] Bar The mmio base address of the slot to be accessed.
758
759 @retval EFI_SUCCESS The voltage is supplied successfully.
760 @retval Others The voltage isn't supplied successfully.
761
762 **/
763 EFI_STATUS
764 SdPeimHcInitPowerVoltage (
765 IN UINTN Bar
766 )
767 {
768 EFI_STATUS Status;
769 SD_HC_SLOT_CAP Capability;
770 UINT8 MaxVoltage;
771 UINT8 HostCtrl2;
772
773 //
774 // Get the support voltage of the Host Controller
775 //
776 Status = SdPeimHcGetCapability (Bar, &Capability);
777 if (EFI_ERROR (Status)) {
778 return Status;
779 }
780 //
781 // Calculate supported maximum voltage according to SD Bus Voltage Select
782 //
783 if (Capability.Voltage33 != 0) {
784 //
785 // Support 3.3V
786 //
787 MaxVoltage = 0x0E;
788 } else if (Capability.Voltage30 != 0) {
789 //
790 // Support 3.0V
791 //
792 MaxVoltage = 0x0C;
793 } else if (Capability.Voltage18 != 0) {
794 //
795 // Support 1.8V
796 //
797 MaxVoltage = 0x0A;
798 HostCtrl2 = BIT3;
799 Status = SdPeimHcOrMmio (Bar + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
800 if (EFI_ERROR (Status)) {
801 return Status;
802 }
803 MicroSecondDelay (5000);
804 } else {
805 ASSERT (FALSE);
806 return EFI_DEVICE_ERROR;
807 }
808
809 //
810 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register
811 //
812 Status = SdPeimHcPowerControl (Bar, MaxVoltage);
813
814 return Status;
815 }
816
817 /**
818 Initialize the Timeout Control register with most conservative value at initialization.
819
820 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.
821
822 @param[in] Bar The mmio base address of the slot to be accessed.
823
824 @retval EFI_SUCCESS The timeout control register is configured successfully.
825 @retval Others The timeout control register isn't configured successfully.
826
827 **/
828 EFI_STATUS
829 SdPeimHcInitTimeoutCtrl (
830 IN UINTN Bar
831 )
832 {
833 EFI_STATUS Status;
834 UINT8 Timeout;
835
836 Timeout = 0x0E;
837 Status = SdPeimHcRwMmio (Bar + SD_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);
838
839 return Status;
840 }
841
842 /**
843 Initial SD host controller with lowest clock frequency, max power and max timeout value
844 at initialization.
845
846 @param[in] Bar The mmio base address of the slot to be accessed.
847
848 @retval EFI_SUCCESS The host controller is initialized successfully.
849 @retval Others The host controller isn't initialized successfully.
850
851 **/
852 EFI_STATUS
853 SdPeimHcInitHost (
854 IN UINTN Bar
855 )
856 {
857 EFI_STATUS Status;
858
859 Status = SdPeimHcInitClockFreq (Bar);
860 if (EFI_ERROR (Status)) {
861 return Status;
862 }
863
864 Status = SdPeimHcInitPowerVoltage (Bar);
865 if (EFI_ERROR (Status)) {
866 return Status;
867 }
868
869 Status = SdPeimHcInitTimeoutCtrl (Bar);
870 return Status;
871 }
872
873 /**
874 Turn on/off LED.
875
876 @param[in] Bar The mmio base address of the slot to be accessed.
877 @param[in] On The boolean to turn on/off LED.
878
879 @retval EFI_SUCCESS The LED is turned on/off successfully.
880 @retval Others The LED isn't turned on/off successfully.
881
882 **/
883 EFI_STATUS
884 SdPeimHcLedOnOff (
885 IN UINTN Bar,
886 IN BOOLEAN On
887 )
888 {
889 EFI_STATUS Status;
890 UINT8 HostCtrl1;
891
892 if (On) {
893 HostCtrl1 = BIT0;
894 Status = SdPeimHcOrMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
895 } else {
896 HostCtrl1 = (UINT8)~BIT0;
897 Status = SdPeimHcAndMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
898 }
899
900 return Status;
901 }
902
903 /**
904 Build ADMA descriptor table for transfer.
905
906 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.
907
908 @param[in] Trb The pointer to the SD_TRB instance.
909
910 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.
911 @retval Others The ADMA descriptor table isn't created successfully.
912
913 **/
914 EFI_STATUS
915 BuildAdmaDescTable (
916 IN SD_TRB *Trb
917 )
918 {
919 EFI_PHYSICAL_ADDRESS Data;
920 UINT64 DataLen;
921 UINT64 Entries;
922 UINT32 Index;
923 UINT64 Remaining;
924 UINT32 Address;
925
926 Data = Trb->DataPhy;
927 DataLen = Trb->DataLen;
928 //
929 // Only support 32bit ADMA Descriptor Table
930 //
931 if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {
932 return EFI_INVALID_PARAMETER;
933 }
934 //
935 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)
936 // for 32-bit address descriptor table.
937 //
938 if ((Data & (BIT0 | BIT1)) != 0) {
939 DEBUG ((EFI_D_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));
940 }
941
942 Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);
943
944 Trb->AdmaDescSize = (UINTN)MultU64x32 (Entries, sizeof (SD_HC_ADMA_DESC_LINE));
945 Trb->AdmaDesc = SdPeimAllocateMem (Trb->Slot->Private->Pool, Trb->AdmaDescSize);
946 if (Trb->AdmaDesc == NULL) {
947 return EFI_OUT_OF_RESOURCES;
948 }
949
950 Remaining = DataLen;
951 Address = (UINT32)Data;
952 for (Index = 0; Index < Entries; Index++) {
953 if (Remaining <= ADMA_MAX_DATA_PER_LINE) {
954 Trb->AdmaDesc[Index].Valid = 1;
955 Trb->AdmaDesc[Index].Act = 2;
956 Trb->AdmaDesc[Index].Length = (UINT16)Remaining;
957 Trb->AdmaDesc[Index].Address = Address;
958 break;
959 } else {
960 Trb->AdmaDesc[Index].Valid = 1;
961 Trb->AdmaDesc[Index].Act = 2;
962 Trb->AdmaDesc[Index].Length = 0;
963 Trb->AdmaDesc[Index].Address = Address;
964 }
965
966 Remaining -= ADMA_MAX_DATA_PER_LINE;
967 Address += ADMA_MAX_DATA_PER_LINE;
968 }
969
970 //
971 // Set the last descriptor line as end of descriptor table
972 //
973 Trb->AdmaDesc[Index].End = 1;
974 return EFI_SUCCESS;
975 }
976
977 /**
978 Create a new TRB for the SD cmd request.
979
980 @param[in] Slot The slot number of the SD card to send the command to.
981 @param[in] Packet A pointer to the SD command data structure.
982
983 @return Created Trb or NULL.
984
985 **/
986 SD_TRB *
987 SdPeimCreateTrb (
988 IN SD_PEIM_HC_SLOT *Slot,
989 IN SD_COMMAND_PACKET *Packet
990 )
991 {
992 SD_TRB *Trb;
993 EFI_STATUS Status;
994 SD_HC_SLOT_CAP Capability;
995 EDKII_IOMMU_OPERATION MapOp;
996 UINTN MapLength;
997
998 //
999 // Calculate a divisor for SD clock frequency
1000 //
1001 Status = SdPeimHcGetCapability (Slot->SdHcBase, &Capability);
1002 if (EFI_ERROR (Status)) {
1003 return NULL;
1004 }
1005
1006 Trb = AllocateZeroPool (sizeof (SD_TRB));
1007 if (Trb == NULL) {
1008 return NULL;
1009 }
1010
1011 Trb->Slot = Slot;
1012 Trb->BlockSize = 0x200;
1013 Trb->Packet = Packet;
1014 Trb->Timeout = Packet->Timeout;
1015
1016 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
1017 Trb->Data = Packet->InDataBuffer;
1018 Trb->DataLen = Packet->InTransferLength;
1019 Trb->Read = TRUE;
1020 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {
1021 Trb->Data = Packet->OutDataBuffer;
1022 Trb->DataLen = Packet->OutTransferLength;
1023 Trb->Read = FALSE;
1024 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {
1025 Trb->Data = NULL;
1026 Trb->DataLen = 0;
1027 } else {
1028 goto Error;
1029 }
1030
1031 if ((Trb->DataLen != 0) && (Trb->DataLen < Trb->BlockSize)) {
1032 Trb->BlockSize = (UINT16)Trb->DataLen;
1033 }
1034
1035 if (Packet->SdCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK) {
1036 Trb->Mode = SdPioMode;
1037 } else {
1038 if (Trb->Read) {
1039 MapOp = EdkiiIoMmuOperationBusMasterWrite;
1040 } else {
1041 MapOp = EdkiiIoMmuOperationBusMasterRead;
1042 }
1043
1044 if (Trb->DataLen != 0) {
1045 MapLength = Trb->DataLen;
1046 Status = IoMmuMap (MapOp, Trb->Data, &MapLength, &Trb->DataPhy, &Trb->DataMap);
1047
1048 if (EFI_ERROR (Status) || (MapLength != Trb->DataLen)) {
1049 DEBUG ((DEBUG_ERROR, "SdPeimCreateTrb: Fail to map data buffer.\n"));
1050 goto Error;
1051 }
1052 }
1053
1054 if (Trb->DataLen == 0) {
1055 Trb->Mode = SdNoData;
1056 } else if (Capability.Adma2 != 0) {
1057 Trb->Mode = SdAdmaMode;
1058 Status = BuildAdmaDescTable (Trb);
1059 if (EFI_ERROR (Status)) {
1060 goto Error;
1061 }
1062 } else if (Capability.Sdma != 0) {
1063 Trb->Mode = SdSdmaMode;
1064 } else {
1065 Trb->Mode = SdPioMode;
1066 }
1067 }
1068 return Trb;
1069
1070 Error:
1071 SdPeimFreeTrb (Trb);
1072 return NULL;
1073 }
1074
1075 /**
1076 Free the resource used by the TRB.
1077
1078 @param[in] Trb The pointer to the SD_TRB instance.
1079
1080 **/
1081 VOID
1082 SdPeimFreeTrb (
1083 IN SD_TRB *Trb
1084 )
1085 {
1086 if ((Trb != NULL) && (Trb->DataMap != NULL)) {
1087 IoMmuUnmap (Trb->DataMap);
1088 }
1089
1090 if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) {
1091 SdPeimFreeMem (Trb->Slot->Private->Pool, Trb->AdmaDesc, Trb->AdmaDescSize);
1092 }
1093
1094 if (Trb != NULL) {
1095 FreePool (Trb);
1096 }
1097 return;
1098 }
1099
1100 /**
1101 Check if the env is ready for execute specified TRB.
1102
1103 @param[in] Bar The mmio base address of the slot to be accessed.
1104 @param[in] Trb The pointer to the SD_TRB instance.
1105
1106 @retval EFI_SUCCESS The env is ready for TRB execution.
1107 @retval EFI_NOT_READY The env is not ready for TRB execution.
1108 @retval Others Some erros happen.
1109
1110 **/
1111 EFI_STATUS
1112 SdPeimCheckTrbEnv (
1113 IN UINTN Bar,
1114 IN SD_TRB *Trb
1115 )
1116 {
1117 EFI_STATUS Status;
1118 SD_COMMAND_PACKET *Packet;
1119 UINT32 PresentState;
1120
1121 Packet = Trb->Packet;
1122
1123 if ((Packet->SdCmdBlk->CommandType == SdCommandTypeAdtc) ||
1124 (Packet->SdCmdBlk->ResponseType == SdResponseTypeR1b) ||
1125 (Packet->SdCmdBlk->ResponseType == SdResponseTypeR5b)) {
1126 //
1127 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in
1128 // the Present State register to be 0
1129 //
1130 PresentState = BIT0 | BIT1;
1131 } else {
1132 //
1133 // Wait Command Inhibit (CMD) in the Present State register
1134 // to be 0
1135 //
1136 PresentState = BIT0;
1137 }
1138
1139 Status = SdPeimHcCheckMmioSet (
1140 Bar + SD_HC_PRESENT_STATE,
1141 sizeof (PresentState),
1142 PresentState,
1143 0
1144 );
1145
1146 return Status;
1147 }
1148
1149 /**
1150 Wait for the env to be ready for execute specified TRB.
1151
1152 @param[in] Bar The mmio base address of the slot to be accessed.
1153 @param[in] Trb The pointer to the SD_TRB instance.
1154
1155 @retval EFI_SUCCESS The env is ready for TRB execution.
1156 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.
1157 @retval Others Some erros happen.
1158
1159 **/
1160 EFI_STATUS
1161 SdPeimWaitTrbEnv (
1162 IN UINTN Bar,
1163 IN SD_TRB *Trb
1164 )
1165 {
1166 EFI_STATUS Status;
1167 SD_COMMAND_PACKET *Packet;
1168 UINT64 Timeout;
1169 BOOLEAN InfiniteWait;
1170
1171 //
1172 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1173 //
1174 Packet = Trb->Packet;
1175 Timeout = Packet->Timeout;
1176 if (Timeout == 0) {
1177 InfiniteWait = TRUE;
1178 } else {
1179 InfiniteWait = FALSE;
1180 }
1181
1182 while (InfiniteWait || (Timeout > 0)) {
1183 //
1184 // Check Trb execution result by reading Normal Interrupt Status register.
1185 //
1186 Status = SdPeimCheckTrbEnv (Bar, Trb);
1187 if (Status != EFI_NOT_READY) {
1188 return Status;
1189 }
1190 //
1191 // Stall for 1 microsecond.
1192 //
1193 MicroSecondDelay (1);
1194
1195 Timeout--;
1196 }
1197
1198 return EFI_TIMEOUT;
1199 }
1200
1201 /**
1202 Execute the specified TRB.
1203
1204 @param[in] Bar The mmio base address of the slot to be accessed.
1205 @param[in] Trb The pointer to the SD_TRB instance.
1206
1207 @retval EFI_SUCCESS The TRB is sent to host controller successfully.
1208 @retval Others Some erros happen when sending this request to the host controller.
1209
1210 **/
1211 EFI_STATUS
1212 SdPeimExecTrb (
1213 IN UINTN Bar,
1214 IN SD_TRB *Trb
1215 )
1216 {
1217 EFI_STATUS Status;
1218 SD_COMMAND_PACKET *Packet;
1219 UINT16 Cmd;
1220 UINT16 IntStatus;
1221 UINT32 Argument;
1222 UINT16 BlkCount;
1223 UINT16 BlkSize;
1224 UINT16 TransMode;
1225 UINT8 HostCtrl1;
1226 UINT32 SdmaAddr;
1227 UINT64 AdmaAddr;
1228
1229 Packet = Trb->Packet;
1230 //
1231 // Clear all bits in Error Interrupt Status Register
1232 //
1233 IntStatus = 0xFFFF;
1234 Status = SdPeimHcRwMmio (Bar + SD_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1235 if (EFI_ERROR (Status)) {
1236 return Status;
1237 }
1238 //
1239 // Clear all bits in Normal Interrupt Status Register
1240 //
1241 IntStatus = 0xFFFF;
1242 Status = SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1243 if (EFI_ERROR (Status)) {
1244 return Status;
1245 }
1246 //
1247 // Set Host Control 1 register DMA Select field
1248 //
1249 if (Trb->Mode == SdAdmaMode) {
1250 HostCtrl1 = BIT4;
1251 Status = SdPeimHcOrMmio (Bar + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
1252 if (EFI_ERROR (Status)) {
1253 return Status;
1254 }
1255 }
1256
1257 SdPeimHcLedOnOff (Bar, TRUE);
1258
1259 if (Trb->Mode == SdSdmaMode) {
1260 if ((UINT64)(UINTN)Trb->DataPhy >= 0x100000000ul) {
1261 return EFI_INVALID_PARAMETER;
1262 }
1263
1264 SdmaAddr = (UINT32)(UINTN)Trb->DataPhy;
1265 Status = SdPeimHcRwMmio (Bar + SD_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);
1266 if (EFI_ERROR (Status)) {
1267 return Status;
1268 }
1269 } else if (Trb->Mode == SdAdmaMode) {
1270 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDesc;
1271 Status = SdPeimHcRwMmio (Bar + SD_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);
1272 if (EFI_ERROR (Status)) {
1273 return Status;
1274 }
1275 }
1276
1277 BlkSize = Trb->BlockSize;
1278 if (Trb->Mode == SdSdmaMode) {
1279 //
1280 // Set SDMA boundary to be 512K bytes.
1281 //
1282 BlkSize |= 0x7000;
1283 }
1284
1285 Status = SdPeimHcRwMmio (Bar + SD_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);
1286 if (EFI_ERROR (Status)) {
1287 return Status;
1288 }
1289
1290 BlkCount = 0;
1291 if (Trb->Mode != SdNoData) {
1292 //
1293 // Calculate Block Count.
1294 //
1295 BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);
1296 }
1297 Status = SdPeimHcRwMmio (Bar + SD_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);
1298 if (EFI_ERROR (Status)) {
1299 return Status;
1300 }
1301
1302 Argument = Packet->SdCmdBlk->CommandArgument;
1303 Status = SdPeimHcRwMmio (Bar + SD_HC_ARG1, FALSE, sizeof (Argument), &Argument);
1304 if (EFI_ERROR (Status)) {
1305 return Status;
1306 }
1307
1308 TransMode = 0;
1309 if (Trb->Mode != SdNoData) {
1310 if (Trb->Mode != SdPioMode) {
1311 TransMode |= BIT0;
1312 }
1313 if (Trb->Read) {
1314 TransMode |= BIT4;
1315 }
1316 if (BlkCount > 1) {
1317 TransMode |= BIT5 | BIT1;
1318 }
1319 //
1320 // SD memory card needs to use AUTO CMD12 feature.
1321 //
1322 if (BlkCount > 1) {
1323 TransMode |= BIT2;
1324 }
1325 }
1326
1327 Status = SdPeimHcRwMmio (Bar + SD_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);
1328 if (EFI_ERROR (Status)) {
1329 return Status;
1330 }
1331
1332 Cmd = (UINT16)LShiftU64(Packet->SdCmdBlk->CommandIndex, 8);
1333 if (Packet->SdCmdBlk->CommandType == SdCommandTypeAdtc) {
1334 Cmd |= BIT5;
1335 }
1336 //
1337 // Convert ResponseType to value
1338 //
1339 if (Packet->SdCmdBlk->CommandType != SdCommandTypeBc) {
1340 switch (Packet->SdCmdBlk->ResponseType) {
1341 case SdResponseTypeR1:
1342 case SdResponseTypeR5:
1343 case SdResponseTypeR6:
1344 case SdResponseTypeR7:
1345 Cmd |= (BIT1 | BIT3 | BIT4);
1346 break;
1347 case SdResponseTypeR2:
1348 Cmd |= (BIT0 | BIT3);
1349 break;
1350 case SdResponseTypeR3:
1351 case SdResponseTypeR4:
1352 Cmd |= BIT1;
1353 break;
1354 case SdResponseTypeR1b:
1355 case SdResponseTypeR5b:
1356 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);
1357 break;
1358 default:
1359 ASSERT (FALSE);
1360 break;
1361 }
1362 }
1363 //
1364 // Execute cmd
1365 //
1366 Status = SdPeimHcRwMmio (Bar + SD_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);
1367 return Status;
1368 }
1369
1370 /**
1371 Check the TRB execution result.
1372
1373 @param[in] Bar The mmio base address of the slot to be accessed.
1374 @param[in] Trb The pointer to the SD_TRB instance.
1375
1376 @retval EFI_SUCCESS The TRB is executed successfully.
1377 @retval EFI_NOT_READY The TRB is not completed for execution.
1378 @retval Others Some erros happen when executing this request.
1379
1380 **/
1381 EFI_STATUS
1382 SdPeimCheckTrbResult (
1383 IN UINTN Bar,
1384 IN SD_TRB *Trb
1385 )
1386 {
1387 EFI_STATUS Status;
1388 SD_COMMAND_PACKET *Packet;
1389 UINT16 IntStatus;
1390 UINT32 Response[4];
1391 UINT32 SdmaAddr;
1392 UINT8 Index;
1393 UINT8 SwReset;
1394 UINT32 PioLength;
1395
1396 SwReset = 0;
1397 Packet = Trb->Packet;
1398 //
1399 // Check Trb execution result by reading Normal Interrupt Status register.
1400 //
1401 Status = SdPeimHcRwMmio (
1402 Bar + SD_HC_NOR_INT_STS,
1403 TRUE,
1404 sizeof (IntStatus),
1405 &IntStatus
1406 );
1407 if (EFI_ERROR (Status)) {
1408 goto Done;
1409 }
1410 //
1411 // Check Transfer Complete bit is set or not.
1412 //
1413 if ((IntStatus & BIT1) == BIT1) {
1414 if ((IntStatus & BIT15) == BIT15) {
1415 //
1416 // Read Error Interrupt Status register to check if the error is
1417 // Data Timeout Error.
1418 // If yes, treat it as success as Transfer Complete has higher
1419 // priority than Data Timeout Error.
1420 //
1421 Status = SdPeimHcRwMmio (
1422 Bar + SD_HC_ERR_INT_STS,
1423 TRUE,
1424 sizeof (IntStatus),
1425 &IntStatus
1426 );
1427 if (!EFI_ERROR (Status)) {
1428 if ((IntStatus & BIT4) == BIT4) {
1429 Status = EFI_SUCCESS;
1430 } else {
1431 Status = EFI_DEVICE_ERROR;
1432 }
1433 }
1434 }
1435
1436 goto Done;
1437 }
1438 //
1439 // Check if there is a error happened during cmd execution.
1440 // If yes, then do error recovery procedure to follow SD Host Controller
1441 // Simplified Spec 3.0 section 3.10.1.
1442 //
1443 if ((IntStatus & BIT15) == BIT15) {
1444 Status = SdPeimHcRwMmio (
1445 Bar + SD_HC_ERR_INT_STS,
1446 TRUE,
1447 sizeof (IntStatus),
1448 &IntStatus
1449 );
1450 if (EFI_ERROR (Status)) {
1451 goto Done;
1452 }
1453
1454 if ((IntStatus & 0x0F) != 0) {
1455 SwReset |= BIT1;
1456 }
1457 if ((IntStatus & 0xF0) != 0) {
1458 SwReset |= BIT2;
1459 }
1460
1461 Status = SdPeimHcRwMmio (
1462 Bar + SD_HC_SW_RST,
1463 FALSE,
1464 sizeof (SwReset),
1465 &SwReset
1466 );
1467 if (EFI_ERROR (Status)) {
1468 goto Done;
1469 }
1470 Status = SdPeimHcWaitMmioSet (
1471 Bar + SD_HC_SW_RST,
1472 sizeof (SwReset),
1473 0xFF,
1474 0,
1475 SD_TIMEOUT
1476 );
1477 if (EFI_ERROR (Status)) {
1478 goto Done;
1479 }
1480
1481 Status = EFI_DEVICE_ERROR;
1482 goto Done;
1483 }
1484 //
1485 // Check if DMA interrupt is signalled for the SDMA transfer.
1486 //
1487 if ((Trb->Mode == SdSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
1488 //
1489 // Clear DMA interrupt bit.
1490 //
1491 IntStatus = BIT3;
1492 Status = SdPeimHcRwMmio (
1493 Bar + SD_HC_NOR_INT_STS,
1494 FALSE,
1495 sizeof (IntStatus),
1496 &IntStatus
1497 );
1498 if (EFI_ERROR (Status)) {
1499 goto Done;
1500 }
1501 //
1502 // Update SDMA Address register.
1503 //
1504 SdmaAddr = SD_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->DataPhy, SD_SDMA_BOUNDARY);
1505 Status = SdPeimHcRwMmio (
1506 Bar + SD_HC_SDMA_ADDR,
1507 FALSE,
1508 sizeof (UINT32),
1509 &SdmaAddr
1510 );
1511 if (EFI_ERROR (Status)) {
1512 goto Done;
1513 }
1514 Trb->DataPhy = (UINT32)(UINTN)SdmaAddr;
1515 }
1516
1517 if ((Packet->SdCmdBlk->CommandType != SdCommandTypeAdtc) &&
1518 (Packet->SdCmdBlk->ResponseType != SdResponseTypeR1b) &&
1519 (Packet->SdCmdBlk->ResponseType != SdResponseTypeR5b)) {
1520 if ((IntStatus & BIT0) == BIT0) {
1521 Status = EFI_SUCCESS;
1522 goto Done;
1523 }
1524 }
1525
1526 if (Packet->SdCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK) {
1527 //
1528 // When performing tuning procedure (Execute Tuning is set to 1) through PIO mode,
1529 // wait Buffer Read Ready bit of Normal Interrupt Status Register to be 1.
1530 // Refer to SD Host Controller Simplified Specification 3.0 figure 2-29 for details.
1531 //
1532 if ((IntStatus & BIT5) == BIT5) {
1533 //
1534 // Clear Buffer Read Ready interrupt at first.
1535 //
1536 IntStatus = BIT5;
1537 SdPeimHcRwMmio (Bar + SD_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);
1538 //
1539 // Read data out from Buffer Port register
1540 //
1541 for (PioLength = 0; PioLength < Trb->DataLen; PioLength += 4) {
1542 SdPeimHcRwMmio (Bar + SD_HC_BUF_DAT_PORT, TRUE, 4, (UINT8*)Trb->Data + PioLength);
1543 }
1544 Status = EFI_SUCCESS;
1545 goto Done;
1546 }
1547 }
1548
1549 Status = EFI_NOT_READY;
1550 Done:
1551 //
1552 // Get response data when the cmd is executed successfully.
1553 //
1554 if (!EFI_ERROR (Status)) {
1555 if (Packet->SdCmdBlk->CommandType != SdCommandTypeBc) {
1556 for (Index = 0; Index < 4; Index++) {
1557 Status = SdPeimHcRwMmio (
1558 Bar + SD_HC_RESPONSE + Index * 4,
1559 TRUE,
1560 sizeof (UINT32),
1561 &Response[Index]
1562 );
1563 if (EFI_ERROR (Status)) {
1564 SdPeimHcLedOnOff (Bar, FALSE);
1565 return Status;
1566 }
1567 }
1568 CopyMem (Packet->SdStatusBlk, Response, sizeof (Response));
1569 }
1570 }
1571
1572 if (Status != EFI_NOT_READY) {
1573 SdPeimHcLedOnOff (Bar, FALSE);
1574 }
1575
1576 return Status;
1577 }
1578
1579 /**
1580 Wait for the TRB execution result.
1581
1582 @param[in] Bar The mmio base address of the slot to be accessed.
1583 @param[in] Trb The pointer to the SD_TRB instance.
1584
1585 @retval EFI_SUCCESS The TRB is executed successfully.
1586 @retval Others Some erros happen when executing this request.
1587
1588 **/
1589 EFI_STATUS
1590 SdPeimWaitTrbResult (
1591 IN UINTN Bar,
1592 IN SD_TRB *Trb
1593 )
1594 {
1595 EFI_STATUS Status;
1596 SD_COMMAND_PACKET *Packet;
1597 UINT64 Timeout;
1598 BOOLEAN InfiniteWait;
1599
1600 Packet = Trb->Packet;
1601 //
1602 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register
1603 //
1604 Timeout = Packet->Timeout;
1605 if (Timeout == 0) {
1606 InfiniteWait = TRUE;
1607 } else {
1608 InfiniteWait = FALSE;
1609 }
1610
1611 while (InfiniteWait || (Timeout > 0)) {
1612 //
1613 // Check Trb execution result by reading Normal Interrupt Status register.
1614 //
1615 Status = SdPeimCheckTrbResult (Bar, Trb);
1616 if (Status != EFI_NOT_READY) {
1617 return Status;
1618 }
1619 //
1620 // Stall for 1 microsecond.
1621 //
1622 MicroSecondDelay (1);
1623
1624 Timeout--;
1625 }
1626
1627 return EFI_TIMEOUT;
1628 }
1629
1630 /**
1631 Sends SD command to an SD card that is attached to the SD controller.
1632
1633 If Packet is successfully sent to the SD card, then EFI_SUCCESS is returned.
1634
1635 If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned.
1636
1637 If Slot is not in a valid range for the SD controller, then EFI_INVALID_PARAMETER
1638 is returned.
1639
1640 If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL,
1641 EFI_INVALID_PARAMETER is returned.
1642
1643 @param[in] Slot The slot number of the Sd card to send the command to.
1644 @param[in,out] Packet A pointer to the SD command data structure.
1645
1646 @retval EFI_SUCCESS The SD Command Packet was sent by the host.
1647 @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the SD
1648 command Packet.
1649 @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid.
1650 @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and
1651 OutDataBuffer are NULL.
1652 @retval EFI_NO_MEDIA SD Device not present in the Slot.
1653 @retval EFI_UNSUPPORTED The command described by the SD Command Packet is not
1654 supported by the host controller.
1655 @retval EFI_BAD_BUFFER_SIZE The InTransferLength or OutTransferLength exceeds the
1656 limit supported by SD card ( i.e. if the number of bytes
1657 exceed the Last LBA).
1658
1659 **/
1660 EFI_STATUS
1661 EFIAPI
1662 SdPeimExecCmd (
1663 IN SD_PEIM_HC_SLOT *Slot,
1664 IN OUT SD_COMMAND_PACKET *Packet
1665 )
1666 {
1667 EFI_STATUS Status;
1668 SD_TRB *Trb;
1669
1670 if (Packet == NULL) {
1671 return EFI_INVALID_PARAMETER;
1672 }
1673
1674 if ((Packet->SdCmdBlk == NULL) || (Packet->SdStatusBlk == NULL)) {
1675 return EFI_INVALID_PARAMETER;
1676 }
1677
1678 if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {
1679 return EFI_INVALID_PARAMETER;
1680 }
1681
1682 if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {
1683 return EFI_INVALID_PARAMETER;
1684 }
1685
1686 Trb = SdPeimCreateTrb (Slot, Packet);
1687 if (Trb == NULL) {
1688 return EFI_OUT_OF_RESOURCES;
1689 }
1690
1691 Status = SdPeimWaitTrbEnv (Slot->SdHcBase, Trb);
1692 if (EFI_ERROR (Status)) {
1693 goto Done;
1694 }
1695
1696 Status = SdPeimExecTrb (Slot->SdHcBase, Trb);
1697 if (EFI_ERROR (Status)) {
1698 goto Done;
1699 }
1700
1701 Status = SdPeimWaitTrbResult (Slot->SdHcBase, Trb);
1702 if (EFI_ERROR (Status)) {
1703 goto Done;
1704 }
1705
1706 Done:
1707 SdPeimFreeTrb (Trb);
1708
1709 return Status;
1710 }
1711
1712 /**
1713 Send command GO_IDLE_STATE to the device to make it go to Idle State.
1714
1715 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1716
1717 @param[in] Slot The slot number of the SD card to send the command to.
1718
1719 @retval EFI_SUCCESS The SD device is reset correctly.
1720 @retval Others The device reset fails.
1721
1722 **/
1723 EFI_STATUS
1724 SdPeimReset (
1725 IN SD_PEIM_HC_SLOT *Slot
1726 )
1727 {
1728 SD_COMMAND_BLOCK SdCmdBlk;
1729 SD_STATUS_BLOCK SdStatusBlk;
1730 SD_COMMAND_PACKET Packet;
1731 EFI_STATUS Status;
1732
1733 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1734 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1735 ZeroMem (&Packet, sizeof (Packet));
1736
1737 Packet.SdCmdBlk = &SdCmdBlk;
1738 Packet.SdStatusBlk = &SdStatusBlk;
1739 Packet.Timeout = SD_TIMEOUT;
1740
1741 SdCmdBlk.CommandIndex = SD_GO_IDLE_STATE;
1742 SdCmdBlk.CommandType = SdCommandTypeBc;
1743 SdCmdBlk.ResponseType = 0;
1744 SdCmdBlk.CommandArgument = 0;
1745
1746 Status = SdPeimExecCmd (Slot, &Packet);
1747
1748 return Status;
1749 }
1750
1751 /**
1752 Send command SEND_IF_COND to the device to inquiry the SD Memory Card interface
1753 condition.
1754
1755 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1756
1757 @param[in] Slot The slot number of the SD card to send the command to.
1758 @param[in] SupplyVoltage The supplied voltage by the host.
1759 @param[in] CheckPattern The check pattern to be sent to the device.
1760
1761 @retval EFI_SUCCESS The operation is done correctly.
1762 @retval Others The operation fails.
1763
1764 **/
1765 EFI_STATUS
1766 SdPeimVoltageCheck (
1767 IN SD_PEIM_HC_SLOT *Slot,
1768 IN UINT8 SupplyVoltage,
1769 IN UINT8 CheckPattern
1770 )
1771 {
1772 SD_COMMAND_BLOCK SdCmdBlk;
1773 SD_STATUS_BLOCK SdStatusBlk;
1774 SD_COMMAND_PACKET Packet;
1775 EFI_STATUS Status;
1776
1777 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1778 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1779 ZeroMem (&Packet, sizeof (Packet));
1780
1781 Packet.SdCmdBlk = &SdCmdBlk;
1782 Packet.SdStatusBlk = &SdStatusBlk;
1783 Packet.Timeout = SD_TIMEOUT;
1784
1785 SdCmdBlk.CommandIndex = SD_SEND_IF_COND;
1786 SdCmdBlk.CommandType = SdCommandTypeBcr;
1787 SdCmdBlk.ResponseType = SdResponseTypeR7;
1788 SdCmdBlk.CommandArgument = (SupplyVoltage << 8) | CheckPattern;
1789
1790 Status = SdPeimExecCmd (Slot, &Packet);
1791 if (!EFI_ERROR (Status)) {
1792 if (SdStatusBlk.Resp0 != SdCmdBlk.CommandArgument) {
1793 return EFI_DEVICE_ERROR;
1794 }
1795 }
1796
1797 return Status;
1798 }
1799
1800 /**
1801 Send command SDIO_SEND_OP_COND to the device to see whether it is SDIO device.
1802
1803 Refer to SDIO Simplified Spec 3 Section 3.2 for details.
1804
1805 @param[in] Slot The slot number of the SD card to send the command to.
1806 @param[in] VoltageWindow The supply voltage window.
1807 @param[in] S18r The boolean to show if it should switch to 1.8v.
1808
1809 @retval EFI_SUCCESS The operation is done correctly.
1810 @retval Others The operation fails.
1811
1812 **/
1813 EFI_STATUS
1814 SdioSendOpCond (
1815 IN SD_PEIM_HC_SLOT *Slot,
1816 IN UINT32 VoltageWindow,
1817 IN BOOLEAN S18r
1818 )
1819 {
1820 SD_COMMAND_BLOCK SdCmdBlk;
1821 SD_STATUS_BLOCK SdStatusBlk;
1822 SD_COMMAND_PACKET Packet;
1823 EFI_STATUS Status;
1824 UINT32 Switch;
1825
1826 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1827 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1828 ZeroMem (&Packet, sizeof (Packet));
1829
1830 Packet.SdCmdBlk = &SdCmdBlk;
1831 Packet.SdStatusBlk = &SdStatusBlk;
1832 Packet.Timeout = SD_TIMEOUT;
1833
1834 SdCmdBlk.CommandIndex = SDIO_SEND_OP_COND;
1835 SdCmdBlk.CommandType = SdCommandTypeBcr;
1836 SdCmdBlk.ResponseType = SdResponseTypeR4;
1837
1838 Switch = S18r ? BIT24 : 0;
1839
1840 SdCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch;
1841
1842 Status = SdPeimExecCmd (Slot, &Packet);
1843
1844 return Status;
1845 }
1846
1847 /**
1848 Send command SD_SEND_OP_COND to the device to see whether it is SDIO device.
1849
1850 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1851
1852 @param[in] Slot The slot number of the SD card to send the command to.
1853 @param[in] Rca The relative device address of addressed device.
1854 @param[in] VoltageWindow The supply voltage window.
1855 @param[in] S18r The boolean to show if it should switch to 1.8v.
1856 @param[in] Xpc The boolean to show if it should provide 0.36w power control.
1857 @param[in] Hcs The boolean to show if it support host capacity info.
1858 @param[out] Ocr The buffer to store returned OCR register value.
1859
1860
1861 @retval EFI_SUCCESS The operation is done correctly.
1862 @retval Others The operation fails.
1863
1864 **/
1865 EFI_STATUS
1866 SdPeimSendOpCond (
1867 IN SD_PEIM_HC_SLOT *Slot,
1868 IN UINT16 Rca,
1869 IN UINT32 VoltageWindow,
1870 IN BOOLEAN S18r,
1871 IN BOOLEAN Xpc,
1872 IN BOOLEAN Hcs,
1873 OUT UINT32 *Ocr
1874 )
1875 {
1876 SD_COMMAND_BLOCK SdCmdBlk;
1877 SD_STATUS_BLOCK SdStatusBlk;
1878 SD_COMMAND_PACKET Packet;
1879 EFI_STATUS Status;
1880 UINT32 Switch;
1881 UINT32 MaxPower;
1882 UINT32 HostCapacity;
1883
1884 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1885 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1886 ZeroMem (&Packet, sizeof (Packet));
1887
1888 Packet.SdCmdBlk = &SdCmdBlk;
1889 Packet.SdStatusBlk = &SdStatusBlk;
1890 Packet.Timeout = SD_TIMEOUT;
1891
1892 SdCmdBlk.CommandIndex = SD_APP_CMD;
1893 SdCmdBlk.CommandType = SdCommandTypeAc;
1894 SdCmdBlk.ResponseType = SdResponseTypeR1;
1895 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
1896
1897 Status = SdPeimExecCmd (Slot, &Packet);
1898 if (EFI_ERROR (Status)) {
1899 return Status;
1900 }
1901
1902 SdCmdBlk.CommandIndex = SD_SEND_OP_COND;
1903 SdCmdBlk.CommandType = SdCommandTypeBcr;
1904 SdCmdBlk.ResponseType = SdResponseTypeR3;
1905
1906 Switch = S18r ? BIT24 : 0;
1907 MaxPower = Xpc ? BIT28 : 0;
1908 HostCapacity = Hcs ? BIT30 : 0;
1909 SdCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch | MaxPower | HostCapacity;
1910
1911 Status = SdPeimExecCmd (Slot, &Packet);
1912 if (!EFI_ERROR (Status)) {
1913 //
1914 // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
1915 //
1916 *Ocr = SdStatusBlk.Resp0;
1917 }
1918
1919 return Status;
1920 }
1921
1922 /**
1923 Broadcast command ALL_SEND_CID to the bus to ask all the SD devices to send the
1924 data of their CID registers.
1925
1926 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1927
1928 @param[in] Slot The slot number of the SD card to send the command to.
1929
1930 @retval EFI_SUCCESS The operation is done correctly.
1931 @retval Others The operation fails.
1932
1933 **/
1934 EFI_STATUS
1935 SdPeimAllSendCid (
1936 IN SD_PEIM_HC_SLOT *Slot
1937 )
1938 {
1939 SD_COMMAND_BLOCK SdCmdBlk;
1940 SD_STATUS_BLOCK SdStatusBlk;
1941 SD_COMMAND_PACKET Packet;
1942 EFI_STATUS Status;
1943
1944 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1945 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1946 ZeroMem (&Packet, sizeof (Packet));
1947
1948 Packet.SdCmdBlk = &SdCmdBlk;
1949 Packet.SdStatusBlk = &SdStatusBlk;
1950 Packet.Timeout = SD_TIMEOUT;
1951
1952 SdCmdBlk.CommandIndex = SD_ALL_SEND_CID;
1953 SdCmdBlk.CommandType = SdCommandTypeBcr;
1954 SdCmdBlk.ResponseType = SdResponseTypeR2;
1955 SdCmdBlk.CommandArgument = 0;
1956
1957 Status = SdPeimExecCmd (Slot, &Packet);
1958
1959 return Status;
1960 }
1961
1962 /**
1963 Send command SET_RELATIVE_ADDR to the SD device to assign a Relative device
1964 Address (RCA).
1965
1966 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
1967
1968 @param[in] Slot The slot number of the SD card to send the command to.
1969 @param[out] Rca The relative device address to be assigned.
1970
1971 @retval EFI_SUCCESS The operation is done correctly.
1972 @retval Others The operation fails.
1973
1974 **/
1975 EFI_STATUS
1976 SdPeimSetRca (
1977 IN SD_PEIM_HC_SLOT *Slot,
1978 OUT UINT16 *Rca
1979 )
1980 {
1981 SD_COMMAND_BLOCK SdCmdBlk;
1982 SD_STATUS_BLOCK SdStatusBlk;
1983 SD_COMMAND_PACKET Packet;
1984 EFI_STATUS Status;
1985
1986 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
1987 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
1988 ZeroMem (&Packet, sizeof (Packet));
1989
1990 Packet.SdCmdBlk = &SdCmdBlk;
1991 Packet.SdStatusBlk = &SdStatusBlk;
1992 Packet.Timeout = SD_TIMEOUT;
1993
1994 SdCmdBlk.CommandIndex = SD_SET_RELATIVE_ADDR;
1995 SdCmdBlk.CommandType = SdCommandTypeBcr;
1996 SdCmdBlk.ResponseType = SdResponseTypeR6;
1997
1998 Status = SdPeimExecCmd (Slot, &Packet);
1999 if (!EFI_ERROR (Status)) {
2000 *Rca = (UINT16)(SdStatusBlk.Resp0 >> 16);
2001 }
2002
2003 return Status;
2004 }
2005
2006 /**
2007 Send command SEND_CSD to the SD device to get the data of the CSD register.
2008
2009 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2010
2011 @param[in] Slot The slot number of the SD card to send the command to.
2012 @param[in] Rca The relative device address of selected device.
2013 @param[out] Csd The buffer to store the content of the CSD register.
2014 Note the caller should ignore the lowest byte of this
2015 buffer as the content of this byte is meaningless even
2016 if the operation succeeds.
2017
2018 @retval EFI_SUCCESS The operation is done correctly.
2019 @retval Others The operation fails.
2020
2021 **/
2022 EFI_STATUS
2023 SdPeimGetCsd (
2024 IN SD_PEIM_HC_SLOT *Slot,
2025 IN UINT16 Rca,
2026 OUT SD_CSD *Csd
2027 )
2028 {
2029 SD_COMMAND_BLOCK SdCmdBlk;
2030 SD_STATUS_BLOCK SdStatusBlk;
2031 SD_COMMAND_PACKET Packet;
2032 EFI_STATUS Status;
2033
2034 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2035 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2036 ZeroMem (&Packet, sizeof (Packet));
2037
2038 Packet.SdCmdBlk = &SdCmdBlk;
2039 Packet.SdStatusBlk = &SdStatusBlk;
2040 Packet.Timeout = SD_TIMEOUT;
2041
2042 SdCmdBlk.CommandIndex = SD_SEND_CSD;
2043 SdCmdBlk.CommandType = SdCommandTypeAc;
2044 SdCmdBlk.ResponseType = SdResponseTypeR2;
2045 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
2046
2047 Status = SdPeimExecCmd (Slot, &Packet);
2048 if (!EFI_ERROR (Status)) {
2049 //
2050 // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
2051 //
2052 CopyMem (((UINT8*)Csd) + 1, &SdStatusBlk.Resp0, sizeof (SD_CSD) - 1);
2053 }
2054
2055 return Status;
2056 }
2057
2058 /**
2059 Send command SELECT_DESELECT_CARD to the SD device to select/deselect it.
2060
2061 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2062
2063 @param[in] Slot The slot number of the SD card to send the command to.
2064 @param[in] Rca The relative device address of selected device.
2065
2066 @retval EFI_SUCCESS The operation is done correctly.
2067 @retval Others The operation fails.
2068
2069 **/
2070 EFI_STATUS
2071 SdPeimSelect (
2072 IN SD_PEIM_HC_SLOT *Slot,
2073 IN UINT16 Rca
2074 )
2075 {
2076 SD_COMMAND_BLOCK SdCmdBlk;
2077 SD_STATUS_BLOCK SdStatusBlk;
2078 SD_COMMAND_PACKET Packet;
2079 EFI_STATUS Status;
2080
2081 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2082 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2083 ZeroMem (&Packet, sizeof (Packet));
2084
2085 Packet.SdCmdBlk = &SdCmdBlk;
2086 Packet.SdStatusBlk = &SdStatusBlk;
2087 Packet.Timeout = SD_TIMEOUT;
2088
2089 SdCmdBlk.CommandIndex = SD_SELECT_DESELECT_CARD;
2090 SdCmdBlk.CommandType = SdCommandTypeAc;
2091 SdCmdBlk.ResponseType = SdResponseTypeR1b;
2092 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
2093
2094 Status = SdPeimExecCmd (Slot, &Packet);
2095
2096 return Status;
2097 }
2098
2099 /**
2100 Send command VOLTAGE_SWITCH to the SD device to switch the voltage of the device.
2101
2102 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2103
2104 @param[in] Slot The slot number of the SD card to send the command to.
2105
2106 @retval EFI_SUCCESS The operation is done correctly.
2107 @retval Others The operation fails.
2108
2109 **/
2110 EFI_STATUS
2111 SdPeimVoltageSwitch (
2112 IN SD_PEIM_HC_SLOT *Slot
2113 )
2114 {
2115 SD_COMMAND_BLOCK SdCmdBlk;
2116 SD_STATUS_BLOCK SdStatusBlk;
2117 SD_COMMAND_PACKET Packet;
2118 EFI_STATUS Status;
2119
2120 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2121 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2122 ZeroMem (&Packet, sizeof (Packet));
2123
2124 Packet.SdCmdBlk = &SdCmdBlk;
2125 Packet.SdStatusBlk = &SdStatusBlk;
2126 Packet.Timeout = SD_TIMEOUT;
2127
2128 SdCmdBlk.CommandIndex = SD_VOLTAGE_SWITCH;
2129 SdCmdBlk.CommandType = SdCommandTypeAc;
2130 SdCmdBlk.ResponseType = SdResponseTypeR1;
2131 SdCmdBlk.CommandArgument = 0;
2132
2133 Status = SdPeimExecCmd (Slot, &Packet);
2134
2135 return Status;
2136 }
2137
2138 /**
2139 Send command SET_BUS_WIDTH to the SD device to set the bus width.
2140
2141 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2142
2143 @param[in] Slot The slot number of the SD card to send the command to.
2144 @param[in] Rca The relative device address of addressed device.
2145 @param[in] BusWidth The bus width to be set, it could be 1 or 4.
2146
2147 @retval EFI_SUCCESS The operation is done correctly.
2148 @retval Others The operation fails.
2149
2150 **/
2151 EFI_STATUS
2152 SdPeimSetBusWidth (
2153 IN SD_PEIM_HC_SLOT *Slot,
2154 IN UINT16 Rca,
2155 IN UINT8 BusWidth
2156 )
2157 {
2158 SD_COMMAND_BLOCK SdCmdBlk;
2159 SD_STATUS_BLOCK SdStatusBlk;
2160 SD_COMMAND_PACKET Packet;
2161 EFI_STATUS Status;
2162 UINT8 Value;
2163
2164 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2165 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2166 ZeroMem (&Packet, sizeof (Packet));
2167
2168 Packet.SdCmdBlk = &SdCmdBlk;
2169 Packet.SdStatusBlk = &SdStatusBlk;
2170 Packet.Timeout = SD_TIMEOUT;
2171
2172 SdCmdBlk.CommandIndex = SD_APP_CMD;
2173 SdCmdBlk.CommandType = SdCommandTypeAc;
2174 SdCmdBlk.ResponseType = SdResponseTypeR1;
2175 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
2176
2177 Status = SdPeimExecCmd (Slot, &Packet);
2178 if (EFI_ERROR (Status)) {
2179 return Status;
2180 }
2181
2182 SdCmdBlk.CommandIndex = SD_SET_BUS_WIDTH;
2183 SdCmdBlk.CommandType = SdCommandTypeAc;
2184 SdCmdBlk.ResponseType = SdResponseTypeR1;
2185
2186 if (BusWidth == 1) {
2187 Value = 0;
2188 } else if (BusWidth == 4) {
2189 Value = 2;
2190 } else {
2191 return EFI_INVALID_PARAMETER;
2192 }
2193 SdCmdBlk.CommandArgument = Value & 0x3;
2194
2195 Status = SdPeimExecCmd (Slot, &Packet);
2196
2197 return Status;
2198 }
2199
2200 /**
2201 Send command SWITCH_FUNC to the SD device to check switchable function or switch card function.
2202
2203 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2204
2205 @param[in] Slot The slot number of the SD card to send the command to.
2206 @param[in] AccessMode The value for access mode group.
2207 @param[in] CommandSystem The value for command set group.
2208 @param[in] DriveStrength The value for drive length group.
2209 @param[in] PowerLimit The value for power limit group.
2210 @param[in] Mode Switch or check function.
2211 @param[out] SwitchResp The return switch function status.
2212
2213 @retval EFI_SUCCESS The operation is done correctly.
2214 @retval Others The operation fails.
2215
2216 **/
2217 EFI_STATUS
2218 SdPeimSwitch (
2219 IN SD_PEIM_HC_SLOT *Slot,
2220 IN UINT8 AccessMode,
2221 IN UINT8 CommandSystem,
2222 IN UINT8 DriveStrength,
2223 IN UINT8 PowerLimit,
2224 IN BOOLEAN Mode,
2225 OUT UINT8 *SwitchResp
2226 )
2227 {
2228 SD_COMMAND_BLOCK SdCmdBlk;
2229 SD_STATUS_BLOCK SdStatusBlk;
2230 SD_COMMAND_PACKET Packet;
2231 EFI_STATUS Status;
2232 UINT32 ModeValue;
2233
2234 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2235 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2236 ZeroMem (&Packet, sizeof (Packet));
2237
2238 Packet.SdCmdBlk = &SdCmdBlk;
2239 Packet.SdStatusBlk = &SdStatusBlk;
2240 Packet.Timeout = SD_TIMEOUT;
2241
2242 SdCmdBlk.CommandIndex = SD_SWITCH_FUNC;
2243 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2244 SdCmdBlk.ResponseType = SdResponseTypeR1;
2245
2246 ModeValue = Mode ? BIT31 : 0;
2247 SdCmdBlk.CommandArgument = (AccessMode & 0xF) | ((PowerLimit & 0xF) << 4) | \
2248 ((DriveStrength & 0xF) << 8) | ((DriveStrength & 0xF) << 12) | \
2249 ModeValue;
2250 Packet.InDataBuffer = SwitchResp;
2251 Packet.InTransferLength = 64;
2252
2253 Status = SdPeimExecCmd (Slot, &Packet);
2254
2255 return Status;
2256 }
2257
2258 /**
2259 Send command SEND_STATUS to the addressed SD device to get its status register.
2260
2261 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2262
2263 @param[in] Slot The slot number of the SD card to send the command to.
2264 @param[in] Rca The relative device address of addressed device.
2265 @param[out] DevStatus The returned device status.
2266
2267 @retval EFI_SUCCESS The operation is done correctly.
2268 @retval Others The operation fails.
2269
2270 **/
2271 EFI_STATUS
2272 SdPeimSendStatus (
2273 IN SD_PEIM_HC_SLOT *Slot,
2274 IN UINT16 Rca,
2275 OUT UINT32 *DevStatus
2276 )
2277 {
2278 SD_COMMAND_BLOCK SdCmdBlk;
2279 SD_STATUS_BLOCK SdStatusBlk;
2280 SD_COMMAND_PACKET Packet;
2281 EFI_STATUS Status;
2282
2283 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2284 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2285 ZeroMem (&Packet, sizeof (Packet));
2286
2287 Packet.SdCmdBlk = &SdCmdBlk;
2288 Packet.SdStatusBlk = &SdStatusBlk;
2289 Packet.Timeout = SD_TIMEOUT;
2290
2291 SdCmdBlk.CommandIndex = SD_SEND_STATUS;
2292 SdCmdBlk.CommandType = SdCommandTypeAc;
2293 SdCmdBlk.ResponseType = SdResponseTypeR1;
2294 SdCmdBlk.CommandArgument = (UINT32)Rca << 16;
2295
2296 Status = SdPeimExecCmd (Slot, &Packet);
2297 if (!EFI_ERROR (Status)) {
2298 *DevStatus = SdStatusBlk.Resp0;
2299 }
2300
2301 return Status;
2302 }
2303
2304 /**
2305 Send command READ_SINGLE_BLOCK/WRITE_SINGLE_BLOCK to the addressed SD device
2306 to read/write the specified number of blocks.
2307
2308 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2309
2310 @param[in] Slot The slot number of the SD card to send the command to.
2311 @param[in] Lba The logical block address of starting access.
2312 @param[in] BlockSize The block size of specified SD device partition.
2313 @param[in] Buffer The pointer to the transfer buffer.
2314 @param[in] BufferSize The size of transfer buffer.
2315 @param[in] IsRead Boolean to show the operation direction.
2316
2317 @retval EFI_SUCCESS The operation is done correctly.
2318 @retval Others The operation fails.
2319
2320 **/
2321 EFI_STATUS
2322 SdPeimRwSingleBlock (
2323 IN SD_PEIM_HC_SLOT *Slot,
2324 IN EFI_LBA Lba,
2325 IN UINT32 BlockSize,
2326 IN VOID *Buffer,
2327 IN UINTN BufferSize,
2328 IN BOOLEAN IsRead
2329 )
2330 {
2331 SD_COMMAND_BLOCK SdCmdBlk;
2332 SD_STATUS_BLOCK SdStatusBlk;
2333 SD_COMMAND_PACKET Packet;
2334 EFI_STATUS Status;
2335
2336 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2337 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2338 ZeroMem (&Packet, sizeof (Packet));
2339
2340 Packet.SdCmdBlk = &SdCmdBlk;
2341 Packet.SdStatusBlk = &SdStatusBlk;
2342 //
2343 // Calculate timeout value through the below formula.
2344 // Timeout = (transfer size) / (2MB/s).
2345 // Taking 2MB/s as divisor is because it's the lowest
2346 // transfer speed of class 2.
2347 //
2348 Packet.Timeout = (BufferSize / (2 * 1024 * 1024) + 1) * 1000 * 1000;;
2349
2350 if (IsRead) {
2351 Packet.InDataBuffer = Buffer;
2352 Packet.InTransferLength = (UINT32)BufferSize;
2353
2354 SdCmdBlk.CommandIndex = SD_READ_SINGLE_BLOCK;
2355 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2356 SdCmdBlk.ResponseType = SdResponseTypeR1;
2357 } else {
2358 Packet.OutDataBuffer = Buffer;
2359 Packet.OutTransferLength = (UINT32)BufferSize;
2360
2361 SdCmdBlk.CommandIndex = SD_WRITE_SINGLE_BLOCK;
2362 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2363 SdCmdBlk.ResponseType = SdResponseTypeR1;
2364 }
2365
2366 if (Slot->SectorAddressing) {
2367 SdCmdBlk.CommandArgument = (UINT32)Lba;
2368 } else {
2369 SdCmdBlk.CommandArgument = (UINT32)MultU64x32 (Lba, BlockSize);
2370 }
2371
2372 Status = SdPeimExecCmd (Slot, &Packet);
2373
2374 return Status;
2375 }
2376
2377 /**
2378 Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed SD device
2379 to read/write the specified number of blocks.
2380
2381 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2382
2383 @param[in] Slot The slot number of the SD card to send the command to.
2384 @param[in] Lba The logical block address of starting access.
2385 @param[in] BlockSize The block size of specified SD device partition.
2386 @param[in] Buffer The pointer to the transfer buffer.
2387 @param[in] BufferSize The size of transfer buffer.
2388 @param[in] IsRead Boolean to show the operation direction.
2389
2390 @retval EFI_SUCCESS The operation is done correctly.
2391 @retval Others The operation fails.
2392
2393 **/
2394 EFI_STATUS
2395 SdPeimRwMultiBlocks (
2396 IN SD_PEIM_HC_SLOT *Slot,
2397 IN EFI_LBA Lba,
2398 IN UINT32 BlockSize,
2399 IN VOID *Buffer,
2400 IN UINTN BufferSize,
2401 IN BOOLEAN IsRead
2402 )
2403 {
2404 SD_COMMAND_BLOCK SdCmdBlk;
2405 SD_STATUS_BLOCK SdStatusBlk;
2406 SD_COMMAND_PACKET Packet;
2407 EFI_STATUS Status;
2408
2409 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2410 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2411 ZeroMem (&Packet, sizeof (Packet));
2412
2413 Packet.SdCmdBlk = &SdCmdBlk;
2414 Packet.SdStatusBlk = &SdStatusBlk;
2415 //
2416 // Calculate timeout value through the below formula.
2417 // Timeout = (transfer size) / (2MB/s).
2418 // Taking 2MB/s as divisor is because it's the lowest
2419 // transfer speed of class 2.
2420 //
2421 Packet.Timeout = (BufferSize / (2 * 1024 * 1024) + 1) * 1000 * 1000;;
2422
2423 if (IsRead) {
2424 Packet.InDataBuffer = Buffer;
2425 Packet.InTransferLength = (UINT32)BufferSize;
2426
2427 SdCmdBlk.CommandIndex = SD_READ_MULTIPLE_BLOCK;
2428 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2429 SdCmdBlk.ResponseType = SdResponseTypeR1;
2430 } else {
2431 Packet.OutDataBuffer = Buffer;
2432 Packet.OutTransferLength = (UINT32)BufferSize;
2433
2434 SdCmdBlk.CommandIndex = SD_WRITE_MULTIPLE_BLOCK;
2435 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2436 SdCmdBlk.ResponseType = SdResponseTypeR1;
2437 }
2438
2439 if (Slot->SectorAddressing) {
2440 SdCmdBlk.CommandArgument = (UINT32)Lba;
2441 } else {
2442 SdCmdBlk.CommandArgument = (UINT32)MultU64x32 (Lba, BlockSize);
2443 }
2444
2445 Status = SdPeimExecCmd (Slot, &Packet);
2446
2447 return Status;
2448 }
2449
2450 /**
2451 Send command SEND_TUNING_BLOCK to the SD device for SDR104/SDR50 optimal sampling point
2452 detection.
2453
2454 It may be sent up to 40 times until the host finishes the tuning procedure.
2455
2456 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
2457
2458 @param[in] Slot The slot number of the SD card to send the command to.
2459
2460 @retval EFI_SUCCESS The operation is done correctly.
2461 @retval Others The operation fails.
2462
2463 **/
2464 EFI_STATUS
2465 SdPeimSendTuningBlk (
2466 IN SD_PEIM_HC_SLOT *Slot
2467 )
2468 {
2469 SD_COMMAND_BLOCK SdCmdBlk;
2470 SD_STATUS_BLOCK SdStatusBlk;
2471 SD_COMMAND_PACKET Packet;
2472 EFI_STATUS Status;
2473 UINT8 TuningBlock[64];
2474
2475 ZeroMem (&SdCmdBlk, sizeof (SdCmdBlk));
2476 ZeroMem (&SdStatusBlk, sizeof (SdStatusBlk));
2477 ZeroMem (&Packet, sizeof (Packet));
2478
2479 Packet.SdCmdBlk = &SdCmdBlk;
2480 Packet.SdStatusBlk = &SdStatusBlk;
2481 Packet.Timeout = SD_TIMEOUT;
2482
2483 SdCmdBlk.CommandIndex = SD_SEND_TUNING_BLOCK;
2484 SdCmdBlk.CommandType = SdCommandTypeAdtc;
2485 SdCmdBlk.ResponseType = SdResponseTypeR1;
2486 SdCmdBlk.CommandArgument = 0;
2487
2488 Packet.InDataBuffer = TuningBlock;
2489 Packet.InTransferLength = sizeof (TuningBlock);
2490
2491 Status = SdPeimExecCmd (Slot, &Packet);
2492
2493 return Status;
2494 }
2495
2496 /**
2497 Tuning the sampling point of SDR104 or SDR50 bus speed mode.
2498
2499 Command SD_SEND_TUNING_BLOCK may be sent up to 40 times until the host finishes the
2500 tuning procedure.
2501
2502 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and SD Host Controller
2503 Simplified Spec 3.0 Figure 2-29 for details.
2504
2505 @param[in] Slot The slot number of the SD card to send the command to.
2506
2507 @retval EFI_SUCCESS The operation is done correctly.
2508 @retval Others The operation fails.
2509
2510 **/
2511 EFI_STATUS
2512 SdPeimTuningClock (
2513 IN SD_PEIM_HC_SLOT *Slot
2514 )
2515 {
2516 EFI_STATUS Status;
2517 UINT8 HostCtrl2;
2518 UINT8 Retry;
2519
2520 //
2521 // Notify the host that the sampling clock tuning procedure starts.
2522 //
2523 HostCtrl2 = BIT6;
2524 Status = SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2525 if (EFI_ERROR (Status)) {
2526 return Status;
2527 }
2528 //
2529 // Ask the device to send a sequence of tuning blocks till the tuning procedure is done.
2530 //
2531 Retry = 0;
2532 do {
2533 Status = SdPeimSendTuningBlk (Slot);
2534 if (EFI_ERROR (Status)) {
2535 return Status;
2536 }
2537
2538 Status = SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);
2539 if (EFI_ERROR (Status)) {
2540 return Status;
2541 }
2542
2543 if ((HostCtrl2 & (BIT6 | BIT7)) == 0) {
2544 break;
2545 }
2546
2547 if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {
2548 return EFI_SUCCESS;
2549 }
2550 } while (++Retry < 40);
2551
2552 DEBUG ((EFI_D_ERROR, "SdPeimTuningClock: Send tuning block fails at %d times with HostCtrl2 %02x\n", Retry, HostCtrl2));
2553 //
2554 // Abort the tuning procedure and reset the tuning circuit.
2555 //
2556 HostCtrl2 = (UINT8)~(BIT6 | BIT7);
2557 Status = SdPeimHcAndMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2558 if (EFI_ERROR (Status)) {
2559 return Status;
2560 }
2561 return EFI_DEVICE_ERROR;
2562 }
2563
2564 /**
2565 Switch the bus width to specified width.
2566
2567 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and
2568 SD Host Controller Simplified Spec 3.0 section Figure 3-7 for details.
2569
2570 @param[in] Slot The slot number of the SD card to send the command to.
2571 @param[in] Rca The relative device address to be assigned.
2572 @param[in] BusWidth The bus width to be set, it could be 4 or 8.
2573
2574 @retval EFI_SUCCESS The operation is done correctly.
2575 @retval Others The operation fails.
2576
2577 **/
2578 EFI_STATUS
2579 SdPeimSwitchBusWidth (
2580 IN SD_PEIM_HC_SLOT *Slot,
2581 IN UINT16 Rca,
2582 IN UINT8 BusWidth
2583 )
2584 {
2585 EFI_STATUS Status;
2586 UINT32 DevStatus;
2587
2588 Status = SdPeimSetBusWidth (Slot, Rca, BusWidth);
2589 if (EFI_ERROR (Status)) {
2590 return Status;
2591 }
2592
2593 Status = SdPeimSendStatus (Slot, Rca, &DevStatus);
2594 if (EFI_ERROR (Status)) {
2595 return Status;
2596 }
2597 //
2598 // Check the switch operation is really successful or not.
2599 //
2600 if ((DevStatus >> 16) != 0) {
2601 return EFI_DEVICE_ERROR;
2602 }
2603
2604 Status = SdPeimHcSetBusWidth (Slot->SdHcBase, BusWidth);
2605
2606 return Status;
2607 }
2608
2609 /**
2610 Switch the high speed timing according to request.
2611
2612 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and
2613 SD Host Controller Simplified Spec 3.0 section Figure 2-29 for details.
2614
2615 @param[in] Slot The slot number of the SD card to send the command to.
2616 @param[in] Rca The relative device address to be assigned.
2617 @param[in] S18a The boolean to show if it's a UHS-I SD card.
2618
2619 @retval EFI_SUCCESS The operation is done correctly.
2620 @retval Others The operation fails.
2621
2622 **/
2623 EFI_STATUS
2624 SdPeimSetBusMode (
2625 IN SD_PEIM_HC_SLOT *Slot,
2626 IN UINT16 Rca,
2627 IN BOOLEAN S18a
2628 )
2629 {
2630 EFI_STATUS Status;
2631 SD_HC_SLOT_CAP Capability;
2632 UINT32 ClockFreq;
2633 UINT8 BusWidth;
2634 UINT8 AccessMode;
2635 UINT8 HostCtrl1;
2636 UINT8 HostCtrl2;
2637 UINT8 SwitchResp[64];
2638
2639 Status = SdPeimGetCsd (Slot, Rca, &Slot->Csd);
2640 if (EFI_ERROR (Status)) {
2641 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimGetCsd fails with %r\n", Status));
2642 return Status;
2643 }
2644
2645 Status = SdPeimHcGetCapability (Slot->SdHcBase, &Capability);
2646 if (EFI_ERROR (Status)) {
2647 return Status;
2648 }
2649
2650 Status = SdPeimSelect (Slot, Rca);
2651 if (EFI_ERROR (Status)) {
2652 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSelect fails with %r\n", Status));
2653 return Status;
2654 }
2655
2656 BusWidth = 4;
2657 Status = SdPeimSwitchBusWidth (Slot, Rca, BusWidth);
2658 if (EFI_ERROR (Status)) {
2659 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSwitchBusWidth fails with %r\n", Status));
2660 return Status;
2661 }
2662
2663 //
2664 // Get the supported bus speed from SWITCH cmd return data group #1.
2665 //
2666 ZeroMem (SwitchResp, sizeof (SwitchResp));
2667 Status = SdPeimSwitch (Slot, 0xF, 0xF, 0xF, 0xF, FALSE, SwitchResp);
2668 if (EFI_ERROR (Status)) {
2669 return Status;
2670 }
2671 //
2672 // Calculate supported bus speed/bus width/clock frequency by host and device capability.
2673 //
2674 ClockFreq = 0;
2675 if (S18a && (Capability.Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
2676 ClockFreq = 208;
2677 AccessMode = 3;
2678 } else if (S18a && (Capability.Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
2679 ClockFreq = 100;
2680 AccessMode = 2;
2681 } else if (S18a && (Capability.Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
2682 ClockFreq = 50;
2683 AccessMode = 4;
2684 } else if ((SwitchResp[13] & BIT1) != 0) {
2685 ClockFreq = 50;
2686 AccessMode = 1;
2687 } else {
2688 ClockFreq = 25;
2689 AccessMode = 0;
2690 }
2691
2692 DEBUG ((EFI_D_INFO, "SdPeimSetBusMode: AccessMode %d ClockFreq %d BusWidth %d\n", AccessMode, ClockFreq, BusWidth));
2693
2694 Status = SdPeimSwitch (Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
2695 if (EFI_ERROR (Status)) {
2696 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSwitch fails with %r\n", Status));
2697 return Status;
2698 }
2699
2700 if ((SwitchResp[16] & 0xF) != AccessMode) {
2701 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimSwitch to AccessMode %d ClockFreq %d BusWidth %d fails! The Switch response is 0x%1x\n", AccessMode, ClockFreq, BusWidth, SwitchResp[16] & 0xF));
2702 return EFI_DEVICE_ERROR;
2703 }
2704 //
2705 // Set to High Speed timing
2706 //
2707 if (AccessMode == 1) {
2708 HostCtrl1 = BIT2;
2709 Status = SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);
2710 if (EFI_ERROR (Status)) {
2711 return Status;
2712 }
2713 }
2714
2715 HostCtrl2 = (UINT8)~0x7;
2716 Status = SdPeimHcAndMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2717 if (EFI_ERROR (Status)) {
2718 return Status;
2719 }
2720 HostCtrl2 = AccessMode;
2721 Status = SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2722 if (EFI_ERROR (Status)) {
2723 return Status;
2724 }
2725
2726 Status = SdPeimHcClockSupply (Slot->SdHcBase, ClockFreq * 1000);
2727 if (EFI_ERROR (Status)) {
2728 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimHcClockSupply %r\n", Status));
2729 return Status;
2730 }
2731
2732 if ((AccessMode == 3) || ((AccessMode == 2) && (Capability.TuningSDR50 != 0))) {
2733 Status = SdPeimTuningClock (Slot);
2734 if (EFI_ERROR (Status)) {
2735 DEBUG ((EFI_D_ERROR, "SdPeimSetBusMode: SdPeimTuningClock fails with %r\n", Status));
2736 return Status;
2737 }
2738 }
2739
2740 DEBUG ((EFI_D_INFO, "SdPeimSetBusMode: SdPeimSetBusMode %r\n", Status));
2741
2742 return Status;
2743 }
2744
2745 /**
2746 Execute SD device identification procedure.
2747
2748 Refer to SD Physical Layer Simplified Spec 4.1 Section 3.6 for details.
2749
2750 @param[in] Slot The slot number of the SD card to send the command to.
2751
2752 @retval EFI_SUCCESS There is a SD card.
2753 @retval Others There is not a SD card.
2754
2755 **/
2756 EFI_STATUS
2757 SdPeimIdentification (
2758 IN SD_PEIM_HC_SLOT *Slot
2759 )
2760 {
2761 EFI_STATUS Status;
2762 UINT32 Ocr;
2763 UINT16 Rca;
2764 BOOLEAN Xpc;
2765 BOOLEAN S18r;
2766 UINT64 MaxCurrent;
2767 UINT64 Current;
2768 UINT16 ControllerVer;
2769 UINT8 PowerCtrl;
2770 UINT32 PresentState;
2771 UINT8 HostCtrl2;
2772 SD_HC_SLOT_CAP Capability;
2773 UINTN Retry;
2774 //
2775 // 1. Send Cmd0 to the device
2776 //
2777 Status = SdPeimReset (Slot);
2778 if (EFI_ERROR (Status)) {
2779 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing Cmd0 fails with %r\n", Status));
2780 return Status;
2781 }
2782 //
2783 // 2. Send Cmd8 to the device
2784 //
2785 Status = SdPeimVoltageCheck (Slot, 0x1, 0xFF);
2786 if (EFI_ERROR (Status)) {
2787 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing Cmd8 fails with %r\n", Status));
2788 return Status;
2789 }
2790 //
2791 // 3. Send SDIO Cmd5 to the device to the SDIO device OCR register.
2792 //
2793 Status = SdioSendOpCond (Slot, 0, FALSE);
2794 if (!EFI_ERROR (Status)) {
2795 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Found SDIO device, ignore it as we don't support\n"));
2796 return EFI_DEVICE_ERROR;
2797 }
2798 //
2799 // 4. Send Acmd41 with voltage window 0 to the device
2800 //
2801 Status = SdPeimSendOpCond (Slot, 0, 0, FALSE, FALSE, FALSE, &Ocr);
2802 if (EFI_ERROR (Status)) {
2803 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimSendOpCond fails with %r\n", Status));
2804 return EFI_DEVICE_ERROR;
2805 }
2806
2807 Status = SdPeimHcGetCapability (Slot->SdHcBase, &Capability);
2808 if (EFI_ERROR (Status)) {
2809 return Status;
2810 }
2811
2812 Status = SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_MAX_CURRENT_CAP, TRUE, sizeof (Current), &Current);
2813 if (EFI_ERROR (Status)) {
2814 return Status;
2815 }
2816
2817 if (Capability.Voltage33 != 0) {
2818 //
2819 // Support 3.3V
2820 //
2821 MaxCurrent = ((UINT32)Current & 0xFF) * 4;
2822 } else if (Capability.Voltage30 != 0) {
2823 //
2824 // Support 3.0V
2825 //
2826 MaxCurrent = (((UINT32)Current >> 8) & 0xFF) * 4;
2827 } else if (Capability.Voltage18 != 0) {
2828 //
2829 // Support 1.8V
2830 //
2831 MaxCurrent = (((UINT32)Current >> 16) & 0xFF) * 4;
2832 } else {
2833 ASSERT (FALSE);
2834 return EFI_DEVICE_ERROR;
2835 }
2836
2837 if (MaxCurrent >= 150) {
2838 Xpc = TRUE;
2839 } else {
2840 Xpc = FALSE;
2841 }
2842
2843 Status = SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);
2844 if (EFI_ERROR (Status)) {
2845 return Status;
2846 }
2847
2848 if ((ControllerVer & 0xFF) == 2) {
2849 S18r = TRUE;
2850 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
2851 S18r = FALSE;
2852 } else {
2853 ASSERT (FALSE);
2854 return EFI_UNSUPPORTED;
2855 }
2856 //
2857 // 5. Repeatly send Acmd41 with supply voltage window to the device.
2858 // Note here we only support the cards complied with SD physical
2859 // layer simplified spec version 2.0 and version 3.0 and above.
2860 //
2861 Ocr = 0;
2862 Retry = 0;
2863 do {
2864 Status = SdPeimSendOpCond (Slot, 0, Ocr, S18r, Xpc, TRUE, &Ocr);
2865 if (EFI_ERROR (Status)) {
2866 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SdPeimSendOpCond fails with %r Ocr %x, S18r %x, Xpc %x\n", Status, Ocr, S18r, Xpc));
2867 return EFI_DEVICE_ERROR;
2868 }
2869
2870 if (Retry++ == 100) {
2871 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SdPeimSendOpCond fails too many times\n"));
2872 return EFI_DEVICE_ERROR;
2873 }
2874 MicroSecondDelay (10 * 1000);
2875 } while ((Ocr & BIT31) == 0);
2876
2877 //
2878 // 6. If the S18a bit is set and the Host Controller supports 1.8V signaling
2879 // (One of support bits is set to 1: SDR50, SDR104 or DDR50 in the
2880 // Capabilities register), switch its voltage to 1.8V.
2881 //
2882 if ((Capability.Sdr50 != 0 ||
2883 Capability.Sdr104 != 0 ||
2884 Capability.Ddr50 != 0) &&
2885 ((Ocr & BIT24) != 0)) {
2886 Status = SdPeimVoltageSwitch (Slot);
2887 if (EFI_ERROR (Status)) {
2888 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimVoltageSwitch fails with %r\n", Status));
2889 Status = EFI_DEVICE_ERROR;
2890 goto Error;
2891 } else {
2892 Status = SdPeimHcStopClock (Slot->SdHcBase);
2893 if (EFI_ERROR (Status)) {
2894 Status = EFI_DEVICE_ERROR;
2895 goto Error;
2896 }
2897
2898 SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
2899 if (((PresentState >> 20) & 0xF) != 0) {
2900 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SwitchVoltage fails with PresentState = 0x%x\n", PresentState));
2901 Status = EFI_DEVICE_ERROR;
2902 goto Error;
2903 }
2904 HostCtrl2 = BIT3;
2905 SdPeimHcOrMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
2906
2907 MicroSecondDelay (5000);
2908
2909 SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);
2910 if ((HostCtrl2 & BIT3) == 0) {
2911 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SwitchVoltage fails with HostCtrl2 = 0x%x\n", HostCtrl2));
2912 Status = EFI_DEVICE_ERROR;
2913 goto Error;
2914 }
2915
2916 SdPeimHcInitClockFreq (Slot->SdHcBase);
2917
2918 MicroSecondDelay (1000);
2919
2920 SdPeimHcRwMmio (Slot->SdHcBase + SD_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);
2921 if (((PresentState >> 20) & 0xF) != 0xF) {
2922 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: SwitchVoltage fails with PresentState = 0x%x, It should be 0xF\n", PresentState));
2923 Status = EFI_DEVICE_ERROR;
2924 goto Error;
2925 }
2926 }
2927 DEBUG ((EFI_D_INFO, "SdPeimIdentification: Switch to 1.8v signal voltage success\n"));
2928 }
2929
2930 Status = SdPeimAllSendCid (Slot);
2931 if (EFI_ERROR (Status)) {
2932 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimAllSendCid fails with %r\n", Status));
2933 return Status;
2934 }
2935
2936 Status = SdPeimSetRca (Slot, &Rca);
2937 if (EFI_ERROR (Status)) {
2938 DEBUG ((EFI_D_ERROR, "SdPeimIdentification: Executing SdPeimSetRca fails with %r\n", Status));
2939 return Status;
2940 }
2941 //
2942 // Enter Data Tranfer Mode.
2943 //
2944 DEBUG ((EFI_D_INFO, "Found a SD device at slot [%d]\n", Slot));
2945
2946 Status = SdPeimSetBusMode (Slot, Rca, ((Ocr & BIT24) != 0));
2947
2948 return Status;
2949
2950 Error:
2951 //
2952 // Set SD Bus Power = 0
2953 //
2954 PowerCtrl = (UINT8)~BIT0;
2955 Status = SdPeimHcAndMmio (Slot->SdHcBase + SD_HC_POWER_CTRL, sizeof (PowerCtrl), &PowerCtrl);
2956 return EFI_DEVICE_ERROR;
2957 }
EFI Development Kit II mirror for PVE