MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.h

   1 /** @file
   2   UfsPassThruDxe driver is used to produce EFI_EXT_SCSI_PASS_THRU protocol interface
   3   for upper layer application to execute UFS-supported SCSI cmds.
   4
   5   Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php.
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _UFS_PASS_THRU_HCI_H_
  17 #define _UFS_PASS_THRU_HCI_H_
  18
  19 //
  20 // Host Capabilities Register Offsets
  21 //
  22 #define UFS_HC_CAP_OFFSET          0x0000  // Controller Capabilities
  23 #define UFS_HC_VER_OFFSET          0x0008  // Version
  24 #define UFS_HC_DDID_OFFSET         0x0010  // Device ID and Device Class
  25 #define UFS_HC_PMID_OFFSET         0x0014  // Product ID and Manufacturer ID
  26 #define UFS_HC_AHIT_OFFSET         0x0018  // Auto-Hibernate Idle Timer
  27 //
  28 // Operation and Runtime Register Offsets
  29 //
  30 #define UFS_HC_IS_OFFSET           0x0020  // Interrupt Status
  31 #define UFS_HC_IE_OFFSET           0x0024  // Interrupt Enable
  32 #define UFS_HC_STATUS_OFFSET       0x0030  // Host Controller Status
  33 #define UFS_HC_ENABLE_OFFSET       0x0034  // Host Controller Enable
  34 #define UFS_HC_UECPA_OFFSET        0x0038  // Host UIC Error Code PHY Adapter Layer
  35 #define UFS_HC_UECDL_OFFSET        0x003c  // Host UIC Error Code Data Link Layer
  36 #define UFS_HC_UECN_OFFSET         0x0040  // Host UIC Error Code Network Layer
  37 #define UFS_HC_UECT_OFFSET         0x0044  // Host UIC Error Code Transport Layer
  38 #define UFS_HC_UECDME_OFFSET       0x0048  // Host UIC Error Code DME
  39 #define UFS_HC_UTRIACR_OFFSET      0x004c  // UTP Transfer Request Interrupt Aggregation Control Register
  40 //
  41 // UTP Transfer Register Offsets
  42 //
  43 #define UFS_HC_UTRLBA_OFFSET       0x0050  // UTP Transfer Request List Base Address
  44 #define UFS_HC_UTRLBAU_OFFSET      0x0054  // UTP Transfer Request List Base Address Upper 32-Bits
  45 #define UFS_HC_UTRLDBR_OFFSET      0x0058  // UTP Transfer Request List Door Bell Register
  46 #define UFS_HC_UTRLCLR_OFFSET      0x005c  // UTP Transfer Request List CLear Register
  47 #define UFS_HC_UTRLRSR_OFFSET      0x0060  // UTP Transfer Request Run-Stop Register
  48 //
  49 // UTP Task Management Register Offsets
  50 //
  51 #define UFS_HC_UTMRLBA_OFFSET      0x0070  // UTP Task Management Request List Base Address
  52 #define UFS_HC_UTMRLBAU_OFFSET     0x0074  // UTP Task Management Request List Base Address Upper 32-Bits
  53 #define UFS_HC_UTMRLDBR_OFFSET     0x0078  // UTP Task Management Request List Door Bell Register
  54 #define UFS_HC_UTMRLCLR_OFFSET     0x007c  // UTP Task Management Request List CLear Register
  55 #define UFS_HC_UTMRLRSR_OFFSET     0x0080  // UTP Task Management Run-Stop Register
  56 //
  57 // UIC Command Register Offsets
  58 //
  59 #define UFS_HC_UIC_CMD_OFFSET      0x0090  // UIC Command Register
  60 #define UFS_HC_UCMD_ARG1_OFFSET    0x0094  // UIC Command Argument 1
  61 #define UFS_HC_UCMD_ARG2_OFFSET    0x0098  // UIC Command Argument 2
  62 #define UFS_HC_UCMD_ARG3_OFFSET    0x009c  // UIC Command Argument 3
  63 //
  64 // UMA Register Offsets
  65 //
  66 #define UFS_HC_UMA_OFFSET          0x00b0  // Reserved for Unified Memory Extension
  67
  68 #define UFS_HC_HCE_EN              BIT0
  69 #define UFS_HC_HCS_DP              BIT0
  70 #define UFS_HC_HCS_UCRDY           BIT3
  71 #define UFS_HC_IS_ULSS             BIT8
  72 #define UFS_HC_IS_UCCS             BIT10
  73 #define UFS_HC_CAP_64ADDR          BIT24
  74 #define UFS_HC_CAP_NUTMRS          (BIT16 | BIT17 | BIT18)
  75 #define UFS_HC_CAP_NUTRS           (BIT0 | BIT1 | BIT2 | BIT3 | BIT4)
  76 #define UFS_HC_UTMRLRSR            BIT0
  77 #define UFS_HC_UTRLRSR             BIT0
  78
  79 //
  80 // The initial value of the OCS field of UTP TRD or TMRD descriptor
  81 // defined in JEDEC JESD223 specification
  82 //
  83 #define UFS_HC_TRD_OCS_INIT_VALUE  0x0F
  84
  85 //
  86 // A maximum of length of 256KB is supported by PRDT entry
  87 //
  88 #define UFS_MAX_DATA_LEN_PER_PRD   0x40000
  89
  90 #define UFS_STORAGE_COMMAND_TYPE   0x01
  91
  92 #define UFS_REGULAR_COMMAND        0x00
  93 #define UFS_INTERRUPT_COMMAND      0x01
  94
  95 #define UFS_LUN_0                  0x00
  96 #define UFS_LUN_1                  0x01
  97 #define UFS_LUN_2                  0x02
  98 #define UFS_LUN_3                  0x03
  99 #define UFS_LUN_4                  0x04
 100 #define UFS_LUN_5                  0x05
 101 #define UFS_LUN_6                  0x06
 102 #define UFS_LUN_7                  0x07
 103 #define UFS_WLUN_REPORT_LUNS       0x81
 104 #define UFS_WLUN_UFS_DEV           0xD0
 105 #define UFS_WLUN_BOOT              0xB0
 106 #define UFS_WLUN_RPMB              0xC4
 107
 108 #pragma pack(1)
 109
 110 //
 111 // UFSHCI 2.0 Spec Section 5.2.1 Offset 00h: CAP - Controller Capabilities
 112 //
 113 typedef struct {
 114   UINT8  Nutrs:4;      // Number of UTP Transfer Request Slots
 115   UINT8  Rsvd1:4;
 116
 117   UINT8  NoRtt;        // Number of outstanding READY TO TRANSFER (RTT) requests supported
 118
 119   UINT8  Nutmrs:3;     // Number of UTP Task Management Request Slots
 120   UINT8  Rsvd2:4;
 121   UINT8  AutoHs:1;     // Auto-Hibernation Support
 122
 123   UINT8  As64:1;       // 64-bit addressing supported
 124   UINT8  Oodds:1;      // Out of order data delivery supported
 125   UINT8  UicDmetms:1;  // UIC DME_TEST_MODE command supported
 126   UINT8  Ume:1;        // Reserved for Unified Memory Extension
 127   UINT8  Rsvd4:4;
 128 } UFS_HC_CAP;
 129
 130 //
 131 // UFSHCI 2.0 Spec Section 5.2.2 Offset 08h: VER - UFS Version
 132 //
 133 typedef struct {
 134   UINT8  Vs:4;         // Version Suffix
 135   UINT8  Mnr:4;        // Minor version number
 136
 137   UINT8  Mjr;          // Major version number
 138
 139   UINT16 Rsvd1;
 140 } UFS_HC_VER;
 141
 142 //
 143 // UFSHCI 2.0 Spec Section 5.2.3 Offset 10h: HCPID - Host Controller Product ID
 144 //
 145 #define UFS_HC_PID     UINT32
 146
 147 //
 148 // UFSHCI 2.0 Spec Section 5.2.4 Offset 14h: HCMID - Host Controller Manufacturer ID
 149 //
 150 #define UFS_HC_MID     UINT32
 151
 152 //
 153 // UFSHCI 2.0 Spec Section 5.2.5 Offset 18h: AHIT - Auto-Hibernate Idle Timer
 154 //
 155 typedef struct {
 156   UINT32 Ahitv:10;     // Auto-Hibernate Idle Timer Value
 157   UINT32 Ts:3;         // Timer scale
 158   UINT32 Rsvd1:19;
 159 } UFS_HC_AHIT;
 160
 161 //
 162 // UFSHCI 2.0 Spec Section 5.3.1 Offset 20h: IS - Interrupt Status
 163 //
 164 typedef struct {
 165   UINT16 Utrcs:1;      // UTP Transfer Request Completion Status
 166   UINT16 Udepri:1;     // UIC DME_ENDPOINT_RESET Indication
 167   UINT16 Ue:1;         // UIC Error
 168   UINT16 Utms:1;       // UIC Test Mode Status
 169
 170   UINT16 Upms:1;       // UIC Power Mode Status
 171   UINT16 Uhxs:1;       // UIC Hibernate Exit Status
 172   UINT16 Uhes:1;       // UIC Hibernate Enter Status
 173   UINT16 Ulls:1;       // UIC Link Lost Status
 174
 175   UINT16 Ulss:1;       // UIC Link Startup Status
 176   UINT16 Utmrcs:1;     // UTP Task  Management Request Completion Status
 177   UINT16 Uccs:1;       // UIC Command Completion Status
 178   UINT16 Dfes:1;       // Device Fatal Error Status
 179
 180   UINT16 Utpes:1;      // UTP Error Status
 181   UINT16 Rsvd1:3;
 182
 183   UINT16 Hcfes:1;      // Host Controller Fatal Error Status
 184   UINT16 Sbfes:1;      // System Bus Fatal Error Status
 185   UINT16 Rsvd2:14;
 186 } UFS_HC_IS;
 187
 188 //
 189 // UFSHCI 2.0 Spec Section 5.3.2 Offset 24h: IE - Interrupt Enable
 190 //
 191 typedef struct {
 192   UINT16 Utrce:1;      // UTP Transfer Request Completion Enable
 193   UINT16 Udeprie:1;    // UIC DME_ENDPOINT_RESET Enable
 194   UINT16 Uee:1;        // UIC Error Enable
 195   UINT16 Utmse:1;      // UIC Test Mode Status Enable
 196
 197   UINT16 Upmse:1;      // UIC Power Mode Status Enable
 198   UINT16 Uhxse:1;      // UIC Hibernate Exit Status Enable
 199   UINT16 Uhese:1;      // UIC Hibernate Enter Status Enable
 200   UINT16 Ullse:1;      // UIC Link Lost Status Enable
 201
 202   UINT16 Ulsse:1;      // UIC Link Startup Status Enable
 203   UINT16 Utmrce:1;     // UTP Task  Management Request Completion Enable
 204   UINT16 Ucce:1;       // UIC Command Completion Enable
 205   UINT16 Dfee:1;       // Device Fatal Error Enable
 206
 207   UINT16 Utpee:1;      // UTP Error Enable
 208   UINT16 Rsvd1:3;
 209
 210   UINT16 Hcfee:1;      // Host Controller Fatal Error Enable
 211   UINT16 Sbfee:1;      // System Bus Fatal Error Enable
 212   UINT16 Rsvd2:14;
 213 } UFS_HC_IE;
 214
 215 //
 216 // UFSHCI 2.0 Spec Section 5.3.3 Offset 30h: HCS - Host Controller Status
 217 //
 218 typedef struct {
 219   UINT8  Dp:1;         // Device Present
 220   UINT8  UtrlRdy:1;    // UTP Transfer Request List Ready
 221   UINT8  UtmrlRdy:1;   // UTP Task Management Request List Ready
 222   UINT8  UcRdy:1;      // UIC COMMAND Ready
 223   UINT8  Rsvd1:4;
 224
 225   UINT8  Upmcrs:3;     // UIC Power Mode Change Request Status
 226   UINT8  Rsvd2:1;      // UIC Hibernate Exit Status Enable
 227   UINT8  Utpec:4;      // UTP Error Code
 228
 229   UINT8  TtagUtpE;     // Task Tag of UTP error
 230   UINT8  TlunUtpE;     // Target LUN of UTP error
 231 } UFS_HC_STATUS;
 232
 233 //
 234 // UFSHCI 2.0 Spec Section 5.3.4 Offset 34h: HCE - Host Controller Enable
 235 //
 236 typedef struct {
 237   UINT32 Hce:1;        // Host Controller Enable
 238   UINT32 Rsvd1:31;
 239 } UFS_HC_ENABLE;
 240
 241 //
 242 // UFSHCI 2.0 Spec Section 5.3.5 Offset 38h: UECPA - Host UIC Error Code PHY Adapter Layer
 243 //
 244 typedef struct {
 245   UINT32 Ec:5;         // UIC PHY Adapter Layer Error Code
 246   UINT32 Rsvd1:26;
 247   UINT32 Err:1;        // UIC PHY Adapter Layer Error
 248 } UFS_HC_UECPA;
 249
 250 //
 251 // UFSHCI 2.0 Spec Section 5.3.6 Offset 3ch: UECDL - Host UIC Error Code Data Link Layer
 252 //
 253 typedef struct {
 254   UINT32 Ec:15;        // UIC Data Link Layer Error Code
 255   UINT32 Rsvd1:16;
 256   UINT32 Err:1;        // UIC Data Link Layer Error
 257 } UFS_HC_UECDL;
 258
 259 //
 260 // UFSHCI 2.0 Spec Section 5.3.7 Offset 40h: UECN - Host UIC Error Code Network Layer
 261 //
 262 typedef struct {
 263   UINT32 Ec:3;         // UIC Network Layer Error Code
 264   UINT32 Rsvd1:28;
 265   UINT32 Err:1;        // UIC Network Layer Error
 266 } UFS_HC_UECN;
 267
 268 //
 269 // UFSHCI 2.0 Spec Section 5.3.8 Offset 44h: UECT - Host UIC Error Code Transport Layer
 270 //
 271 typedef struct {
 272   UINT32 Ec:7;         // UIC Transport Layer Error Code
 273   UINT32 Rsvd1:24;
 274   UINT32 Err:1;        // UIC Transport Layer Error
 275 } UFS_HC_UECT;
 276
 277 //
 278 // UFSHCI 2.0 Spec Section 5.3.9 Offset 48h: UECDME - Host UIC Error Code
 279 //
 280 typedef struct {
 281   UINT32 Ec:1;         // UIC DME Error Code
 282   UINT32 Rsvd1:30;
 283   UINT32 Err:1;        // UIC DME Error
 284 } UFS_HC_UECDME;
 285
 286 //
 287 // UFSHCI 2.0 Spec Section 5.3.10 Offset 4Ch: UTRIACR - UTP Transfer Request Interrupt Aggregation Control Register
 288 //
 289 typedef struct {
 290   UINT8  IaToVal;      // Interrupt aggregation timeout value
 291
 292   UINT8  IacTh:5;      // Interrupt aggregation counter threshold
 293   UINT8  Rsvd1:3;
 294
 295   UINT8  Ctr:1;        // Counter and Timer Reset
 296   UINT8  Rsvd2:3;
 297   UINT8  Iasb:1;       // Interrupt aggregation status bit
 298   UINT8  Rsvd3:3;
 299
 300   UINT8  IapwEn:1;     // Interrupt aggregation parameter write enable
 301   UINT8  Rsvd4:6;
 302   UINT8  IaEn:1;       // Interrupt Aggregation Enable/Disable
 303 } UFS_HC_UTRIACR;
 304
 305 //
 306 // UFSHCI 2.0 Spec Section 5.4.1 Offset 50h: UTRLBA - UTP Transfer Request List Base Address
 307 //
 308 typedef struct {
 309   UINT32 Rsvd1:10;
 310   UINT32 UtrlBa:22;    // UTP Transfer Request List Base Address
 311 } UFS_HC_UTRLBA;
 312
 313 //
 314 // UFSHCI 2.0 Spec Section 5.4.2 Offset 54h: UTRLBAU - UTP Transfer Request List Base Address Upper 32-bits
 315 //
 316 #define UFS_HC_UTRLBAU UINT32
 317
 318 //
 319 // UFSHCI 2.0 Spec Section 5.4.3 Offset 58h: UTRLDBR - UTP Transfer Request List Door Bell Register
 320 //
 321 #define UFS_HC_UTRLDBR UINT32
 322
 323 //
 324 // UFSHCI 2.0 Spec Section 5.4.4 Offset 5Ch: UTRLCLR - UTP Transfer Request List CLear Register
 325 //
 326 #define UFS_HC_UTRLCLR UINT32
 327
 328 #if 0
 329 //
 330 // UFSHCI 2.0 Spec Section 5.4.5 Offset 60h: UTRLRSR - UTP Transfer Request List Run Stop Register
 331 //
 332 typedef struct {
 333   UINT32 UtrlRsr:1;    // UTP Transfer Request List Run-Stop Register
 334   UINT32 Rsvd1:31;
 335 } UFS_HC_UTRLRSR;
 336 #endif
 337
 338 //
 339 // UFSHCI 2.0 Spec Section 5.5.1 Offset 70h: UTMRLBA - UTP Task Management Request List Base Address
 340 //
 341 typedef struct {
 342   UINT32 Rsvd1:10;
 343   UINT32 UtmrlBa:22;   // UTP Task Management Request List Base Address
 344 } UFS_HC_UTMRLBA;
 345
 346 //
 347 // UFSHCI 2.0 Spec Section 5.5.2 Offset 74h: UTMRLBAU - UTP Task Management Request List Base Address Upper 32-bits
 348 //
 349 #define UFS_HC_UTMRLBAU UINT32
 350
 351 //
 352 // UFSHCI 2.0 Spec Section 5.5.3 Offset 78h: UTMRLDBR - UTP Task Management Request List Door Bell Register
 353 //
 354 typedef struct {
 355   UINT32 UtmrlDbr:8;   // UTP Task Management Request List Door bell Register
 356   UINT32 Rsvd1:24;
 357 } UFS_HC_UTMRLDBR;
 358
 359 //
 360 // UFSHCI 2.0 Spec Section 5.5.4 Offset 7Ch: UTMRLCLR - UTP Task Management Request List CLear Register
 361 //
 362 typedef struct {
 363   UINT32 UtmrlClr:8;   // UTP Task Management List Clear Register
 364   UINT32 Rsvd1:24;
 365 } UFS_HC_UTMRLCLR;
 366
 367 #if 0
 368 //
 369 // UFSHCI 2.0 Spec Section 5.5.5 Offset 80h: UTMRLRSR - UTP Task Management Request List Run Stop Register
 370 //
 371 typedef struct {
 372   UINT32 UtmrlRsr:1;   // UTP Task Management Request List Run-Stop Register
 373   UINT32 Rsvd1:31;
 374 } UFS_HC_UTMRLRSR;
 375 #endif
 376
 377 //
 378 // UFSHCI 2.0 Spec Section 5.6.1 Offset 90h: UICCMD - UIC Command
 379 //
 380 typedef struct {
 381   UINT32 CmdOp:8;      // Command Opcode
 382   UINT32 Rsvd1:24;
 383 } UFS_HC_UICCMD;
 384
 385 //
 386 // UFSHCI 2.0 Spec Section 5.6.2 Offset 94h: UICCMDARG1 - UIC Command Argument 1
 387 //
 388 #define UFS_HC_UICCMD_ARG1 UINT32
 389
 390 //
 391 // UFSHCI 2.0 Spec Section 5.6.2 Offset 98h: UICCMDARG2 - UIC Command Argument 2
 392 //
 393 #define UFS_HC_UICCMD_ARG2 UINT32
 394
 395 //
 396 // UFSHCI 2.0 Spec Section 5.6.2 Offset 9ch: UICCMDARG3 - UIC Command Argument 3
 397 //
 398 #define UFS_HC_UICCMD_ARG3 UINT32
 399
 400 //
 401 // UIC command opcodes
 402 //
 403 typedef enum {
 404   UfsUicDmeGet            = 0x01,
 405   UfsUicDmeSet            = 0x02,
 406   UfsUicDmePeerGet        = 0x03,
 407   UfsUicDmePeerSet        = 0x04,
 408   UfsUicDmePwrOn          = 0x10,
 409   UfsUicDmePwrOff         = 0x11,
 410   UfsUicDmeEnable         = 0x12,
 411   UfsUicDmeReset          = 0x14,
 412   UfsUicDmeEndpointReset  = 0x15,
 413   UfsUicDmeLinkStartup    = 0x16,
 414   UfsUicDmeHibernateEnter = 0x17,
 415   UfsUicDmeHibernateExit  = 0x18,
 416   UfsUicDmeTestMode       = 0x1A
 417 } UFS_UIC_OPCODE;
 418
 419 //
 420 // UTP Transfer Request Descriptor
 421 //
 422 typedef struct {
 423   //
 424   // DW0
 425   //
 426   UINT32 Rsvd1:24;
 427   UINT32 Int:1;               /* Interrupt */
 428   UINT32 Dd:2;                /* Data Direction */
 429   UINT32 Rsvd2:1;
 430   UINT32 Ct:4;                /* Command Type */
 431
 432   //
 433   // DW1
 434   //
 435   UINT32 Rsvd3;
 436
 437   //
 438   // DW2
 439   //
 440   UINT32 Ocs:8;               /* Overall Command Status */
 441   UINT32 Rsvd4:24;
 442
 443   //
 444   // DW3
 445   //
 446   UINT32 Rsvd5;
 447
 448   //
 449   // DW4
 450   //
 451   UINT32 Rsvd6:7;
 452   UINT32 UcdBa:25;            /* UTP Command Descriptor Base Address */
 453
 454   //
 455   // DW5
 456   //
 457   UINT32 UcdBaU;              /* UTP Command Descriptor Base Address Upper 32-bits */
 458
 459   //
 460   // DW6
 461   //
 462   UINT16 RuL;                 /* Response UPIU Length */
 463   UINT16 RuO;                 /* Response UPIU Offset */
 464
 465   //
 466   // DW7
 467   //
 468   UINT16 PrdtL;               /* PRDT Length */
 469   UINT16 PrdtO;               /* PRDT Offset */
 470 } UTP_TRD;
 471
 472 typedef struct {
 473   //
 474   // DW0
 475   //
 476   UINT32 Rsvd1:2;
 477   UINT32 DbAddr:30;           /* Data Base Address */
 478
 479   //
 480   // DW1
 481   //
 482   UINT32 DbAddrU;             /* Data Base Address Upper 32-bits */
 483
 484   //
 485   // DW2
 486   //
 487   UINT32 Rsvd2;
 488
 489   //
 490   // DW3
 491   //
 492   UINT32 DbCount:18;          /* Data Byte Count */
 493   UINT32 Rsvd3:14;
 494 } UTP_TR_PRD;
 495
 496 //
 497 // UFS 2.0 Spec Section 10.5.3 - UTP Command UPIU
 498 //
 499 typedef struct {
 500   //
 501   // DW0
 502   //
 503   UINT8  TransCode:6;         /* Transaction Type - 0x01*/
 504   UINT8  Dd:1;
 505   UINT8  Hd:1;
 506   UINT8  Flags;
 507   UINT8  Lun;
 508   UINT8  TaskTag;             /* Task Tag */
 509
 510   //
 511   // DW1
 512   //
 513   UINT8  CmdSet:4;            /* Command Set Type */
 514   UINT8  Rsvd1:4;
 515   UINT8  Rsvd2;
 516   UINT8  Rsvd3;
 517   UINT8  Rsvd4;
 518
 519   //
 520   // DW2
 521   //
 522   UINT8  EhsLen;              /* Total EHS Length - 0x00 */
 523   UINT8  Rsvd5;
 524   UINT16 DataSegLen;          /* Data Segment Length - Big Endian - 0x0000 */
 525
 526   //
 527   // DW3
 528   //
 529   UINT32 ExpDataTranLen;      /* Expected Data Transfer Length - Big Endian */
 530
 531   //
 532   // DW4 - DW7
 533   //
 534   UINT8  Cdb[16];
 535 } UTP_COMMAND_UPIU;
 536
 537 //
 538 // UFS 2.0 Spec Section 10.5.4 - UTP Response UPIU
 539 //
 540 typedef struct {
 541   //
 542   // DW0
 543   //
 544   UINT8  TransCode:6;         /* Transaction Type - 0x21*/
 545   UINT8  Dd:1;
 546   UINT8  Hd:1;
 547   UINT8  Flags;
 548   UINT8  Lun;
 549   UINT8  TaskTag;             /* Task Tag */
 550
 551   //
 552   // DW1
 553   //
 554   UINT8  CmdSet:4;            /* Command Set Type */
 555   UINT8  Rsvd1:4;
 556   UINT8  Rsvd2;
 557   UINT8  Response;            /* Response */
 558   UINT8  Status;              /* Status */
 559
 560   //
 561   // DW2
 562   //
 563   UINT8  EhsLen;              /* Total EHS Length - 0x00 */
 564   UINT8  DevInfo;             /* Device Information */
 565   UINT16 DataSegLen;          /* Data Segment Length - Big Endian */
 566
 567   //
 568   // DW3
 569   //
 570   UINT32 ResTranCount;        /* Residual Transfer Count - Big Endian */
 571
 572   //
 573   // DW4 - DW7
 574   //
 575   UINT8  Rsvd3[16];
 576
 577   //
 578   // Data Segment - Sense Data
 579   //
 580   UINT16 SenseDataLen;        /* Sense Data Length - Big Endian */
 581   UINT8  SenseData[18];       /* Sense Data */
 582 } UTP_RESPONSE_UPIU;
 583
 584 //
 585 // UFS 2.0 Spec Section 10.5.5 - UTP Data-Out UPIU
 586 //
 587 typedef struct {
 588   //
 589   // DW0
 590   //
 591   UINT8  TransCode:6;         /* Transaction Type - 0x02*/
 592   UINT8  Dd:1;
 593   UINT8  Hd:1;
 594   UINT8  Flags;
 595   UINT8  Lun;
 596   UINT8  TaskTag;             /* Task Tag */
 597
 598   //
 599   // DW1
 600   //
 601   UINT8  Rsvd1[4];
 602
 603   //
 604   // DW2
 605   //
 606   UINT8  EhsLen;              /* Total EHS Length - 0x00 */
 607   UINT8  Rsvd2;
 608   UINT16 DataSegLen;          /* Data Segment Length - Big Endian */
 609
 610   //
 611   // DW3
 612   //
 613   UINT32 DataBufOffset;       /* Data Buffer Offset - Big Endian */
 614
 615   //
 616   // DW4
 617   //
 618   UINT32 DataTranCount;       /* Data Transfer Count - Big Endian */
 619
 620   //
 621   // DW5 - DW7
 622   //
 623   UINT8  Rsvd3[12];
 624
 625   //
 626   // Data Segment - Data to be sent out
 627   //
 628   //UINT8  Data[];            /* Data to be sent out, maximum is 65535 bytes */
 629 } UTP_DATA_OUT_UPIU;
 630
 631 //
 632 // UFS 2.0 Spec Section 10.5.6 - UTP Data-In UPIU
 633 //
 634 typedef struct {
 635   //
 636   // DW0
 637   //
 638   UINT8  TransCode:6;         /* Transaction Type - 0x22*/
 639   UINT8  Dd:1;
 640   UINT8  Hd:1;
 641   UINT8  Flags;
 642   UINT8  Lun;
 643   UINT8  TaskTag;             /* Task Tag */
 644
 645   //
 646   // DW1
 647   //
 648   UINT8  Rsvd1[4];
 649
 650   //
 651   // DW2
 652   //
 653   UINT8  EhsLen;              /* Total EHS Length - 0x00 */
 654   UINT8  Rsvd2;
 655   UINT16 DataSegLen;          /* Data Segment Length - Big Endian */
 656
 657   //
 658   // DW3
 659   //
 660   UINT32 DataBufOffset;       /* Data Buffer Offset - Big Endian */
 661
 662   //
 663   // DW4
 664   //
 665   UINT32 DataTranCount;       /* Data Transfer Count - Big Endian */
 666
 667   //
 668   // DW5 - DW7
 669   //
 670   UINT8  Rsvd3[12];
 671
 672   //
 673   // Data Segment - Data to be read
 674   //
 675   //UINT8  Data[];            /* Data to be read, maximum is 65535 bytes */
 676 } UTP_DATA_IN_UPIU;
 677
 678 //
 679 // UFS 2.0 Spec Section 10.5.7 - UTP Ready-To-Transfer UPIU
 680 //
 681 typedef struct {
 682   //
 683   // DW0
 684   //
 685   UINT8  TransCode:6;         /* Transaction Type - 0x31*/
 686   UINT8  Dd:1;
 687   UINT8  Hd:1;
 688   UINT8  Flags;
 689   UINT8  Lun;
 690   UINT8  TaskTag;             /* Task Tag */
 691
 692   //
 693   // DW1
 694   //
 695   UINT8  Rsvd1[4];
 696
 697   //
 698   // DW2
 699   //
 700   UINT8  EhsLen;              /* Total EHS Length - 0x00 */
 701   UINT8  Rsvd2;
 702   UINT16 DataSegLen;          /* Data Segment Length - Big Endian - 0x0000 */
 703
 704   //
 705   // DW3
 706   //
 707   UINT32 DataBufOffset;       /* Data Buffer Offset - Big Endian */
 708
 709   //
 710   // DW4
 711   //
 712   UINT32 DataTranCount;       /* Data Transfer Count - Big Endian */
 713
 714   //
 715   // DW5 - DW7
 716   //
 717   UINT8  Rsvd3[12];
 718
 719   //
 720   // Data Segment - Data to be read
 721   //
 722   //UINT8  Data[];            /* Data to be read, maximum is 65535 bytes */
 723 } UTP_RDY_TO_TRAN_UPIU;
 724
 725 //
 726 // UFS 2.0 Spec Section 10.5.8 - UTP Task Management Request UPIU
 727 //
 728 typedef struct {
 729   //
 730   // DW0
 731   //
 732   UINT8  TransCode:6;         /* Transaction Type - 0x04*/
 733   UINT8  Dd:1;
 734   UINT8  Hd:1;
 735   UINT8  Flags;
 736   UINT8  Lun;
 737   UINT8  TaskTag;             /* Task Tag */
 738
 739   //
 740   // DW1
 741   //
 742   UINT8  Rsvd1;
 743   UINT8  TskManFunc;          /* Task Management Function */
 744   UINT8  Rsvd2[2];
 745
 746   //
 747   // DW2
 748   //
 749   UINT8  EhsLen;              /* Total EHS Length - 0x00 */
 750   UINT8  Rsvd3;
 751   UINT16 DataSegLen;          /* Data Segment Length - Big Endian - 0x0000 */
 752
 753   //
 754   // DW3
 755   //
 756   UINT32 InputParam1;         /* Input Parameter 1 - Big Endian */
 757
 758   //
 759   // DW4
 760   //
 761   UINT32 InputParam2;         /* Input Parameter 2 - Big Endian */
 762
 763   //
 764   // DW5
 765   //
 766   UINT32 InputParam3;         /* Input Parameter 3 - Big Endian */
 767
 768   //
 769   // DW6 - DW7
 770   //
 771   UINT8  Rsvd4[8];
 772 } UTP_TM_REQ_UPIU;
 773
 774 //
 775 // UFS 2.0 Spec Section 10.5.9 - UTP Task Management Response UPIU
 776 //
 777 typedef struct {
 778   //
 779   // DW0
 780   //
 781   UINT8  TransCode:6;         /* Transaction Type - 0x24*/
 782   UINT8  Dd:1;
 783   UINT8  Hd:1;
 784   UINT8  Flags;
 785   UINT8  Lun;
 786   UINT8  TaskTag;             /* Task Tag */
 787
 788   //
 789   // DW1
 790   //
 791   UINT8  Rsvd1[2];
 792   UINT8  Resp;                /* Response */
 793   UINT8  Rsvd2;
 794
 795   //
 796   // DW2
 797   //
 798   UINT8  EhsLen;              /* Total EHS Length - 0x00 */
 799   UINT8  Rsvd3;
 800   UINT16 DataSegLen;          /* Data Segment Length - Big Endian - 0x0000 */
 801
 802   //
 803   // DW3
 804   //
 805   UINT32 OutputParam1;        /* Output Parameter 1 - Big Endian */
 806
 807   //
 808   // DW4
 809   //
 810   UINT32 OutputParam2;        /* Output Parameter 2 - Big Endian */
 811
 812   //
 813   // DW5 - DW7
 814   //
 815   UINT8  Rsvd4[12];
 816 } UTP_TM_RESP_UPIU;
 817
 818 //
 819 // UTP Task Management Request Descriptor
 820 //
 821 typedef struct {
 822   //
 823   // DW0
 824   //
 825   UINT32 Rsvd1:24;
 826   UINT32 Int:1;               /* Interrupt */
 827   UINT32 Rsvd2:7;
 828
 829   //
 830   // DW1
 831   //
 832   UINT32 Rsvd3;
 833
 834   //
 835   // DW2
 836   //
 837   UINT32 Ocs:8;               /* Overall Command Status */
 838   UINT32 Rsvd4:24;
 839
 840   //
 841   // DW3
 842   //
 843   UINT32 Rsvd5;
 844
 845   //
 846   // DW4 - DW11
 847   //
 848   UTP_TM_REQ_UPIU TmReq;      /* Task Management Request UPIU */
 849
 850   //
 851   // DW12 - DW19
 852   //
 853   UTP_TM_RESP_UPIU TmResp;    /* Task Management Response UPIU */
 854 } UTP_TMRD;
 855
 856
 857 typedef struct {
 858   UINT8  Opcode;
 859   UINT8  DescId;
 860   UINT8  Index;
 861   UINT8  Selector;
 862   UINT16 Rsvd1;
 863   UINT16 Length;
 864   UINT32 Value;
 865   UINT32 Rsvd2;
 866 } UTP_UPIU_TSF;
 867
 868 //
 869 // UFS 2.0 Spec Section 10.5.10 - UTP Query Request UPIU
 870 //
 871 typedef struct {
 872   //
 873   // DW0
 874   //
 875   UINT8        TransCode:6;   /* Transaction Type - 0x16*/
 876   UINT8        Dd:1;
 877   UINT8        Hd:1;
 878   UINT8        Flags;
 879   UINT8        Rsvd1;
 880   UINT8        TaskTag;       /* Task Tag */
 881
 882   //
 883   // DW1
 884   //
 885   UINT8        Rsvd2;
 886   UINT8        QueryFunc;     /* Query Function */
 887   UINT8        Rsvd3[2];
 888
 889   //
 890   // DW2
 891   //
 892   UINT8        EhsLen;        /* Total EHS Length - 0x00 */
 893   UINT8        Rsvd4;
 894   UINT16       DataSegLen;    /* Data Segment Length - Big Endian */
 895
 896   //
 897   // DW3 - 6
 898   //
 899   UTP_UPIU_TSF Tsf;           /* Transaction Specific Fields */
 900
 901   //
 902   // DW7
 903   //
 904   UINT8        Rsvd5[4];
 905
 906   //
 907   // Data Segment - Data to be transferred
 908   //
 909   //UINT8  Data[];            /* Data to be transferred, maximum is 65535 bytes */
 910 } UTP_QUERY_REQ_UPIU;
 911
 912 #define QUERY_FUNC_STD_READ_REQ     0x01
 913 #define QUERY_FUNC_STD_WRITE_REQ    0x81
 914
 915 typedef enum {
 916   UtpQueryFuncOpcodeNop      = 0x00,
 917   UtpQueryFuncOpcodeRdDesc   = 0x01,
 918   UtpQueryFuncOpcodeWrDesc   = 0x02,
 919   UtpQueryFuncOpcodeRdAttr   = 0x03,
 920   UtpQueryFuncOpcodeWrAttr   = 0x04,
 921   UtpQueryFuncOpcodeRdFlag   = 0x05,
 922   UtpQueryFuncOpcodeSetFlag  = 0x06,
 923   UtpQueryFuncOpcodeClrFlag  = 0x07,
 924   UtpQueryFuncOpcodeTogFlag  = 0x08
 925 } UTP_QUERY_FUNC_OPCODE;
 926
 927 //
 928 // UFS 2.0 Spec Section 10.5.11 - UTP Query Response UPIU
 929 //
 930 typedef struct {
 931   //
 932   // DW0
 933   //
 934   UINT8        TransCode:6;   /* Transaction Type - 0x36*/
 935   UINT8        Dd:1;
 936   UINT8        Hd:1;
 937   UINT8        Flags;
 938   UINT8        Rsvd1;
 939   UINT8        TaskTag;       /* Task Tag */
 940
 941   //
 942   // DW1
 943   //
 944   UINT8        Rsvd2;
 945   UINT8        QueryFunc;     /* Query Function */
 946   UINT8        QueryResp;     /* Query Response */
 947   UINT8        Rsvd3;
 948
 949   //
 950   // DW2
 951   //
 952   UINT8        EhsLen;        /* Total EHS Length - 0x00 */
 953   UINT8        DevInfo;       /* Device Information */
 954   UINT16       DataSegLen;    /* Data Segment Length - Big Endian */
 955
 956   //
 957   // DW3 - 6
 958   //
 959   UTP_UPIU_TSF Tsf;           /* Transaction Specific Fields */
 960
 961   //
 962   // DW7
 963   //
 964   UINT8        Rsvd4[4];
 965
 966   //
 967   // Data Segment - Data to be transferred
 968   //
 969   //UINT8      Data[];        /* Data to be transferred, maximum is 65535 bytes */
 970 } UTP_QUERY_RESP_UPIU;
 971
 972 typedef enum {
 973   UfsUtpQueryResponseSuccess             = 0x00,
 974   UfsUtpQueryResponseParamNotReadable    = 0xF6,
 975   UfsUtpQueryResponseParamNotWriteable   = 0xF7,
 976   UfsUtpQueryResponseParamAlreadyWritten = 0xF8,
 977   UfsUtpQueryResponseInvalidLen          = 0xF9,
 978   UfsUtpQueryResponseInvalidVal          = 0xFA,
 979   UfsUtpQueryResponseInvalidSelector     = 0xFB,
 980   UfsUtpQueryResponseInvalidIndex        = 0xFC,
 981   UfsUtpQueryResponseInvalidIdn          = 0xFD,
 982   UfsUtpQueryResponseInvalidOpc          = 0xFE,
 983   UfsUtpQueryResponseGeneralFailure      = 0xFF
 984 } UTP_QUERY_RESP_CODE;
 985
 986 //
 987 // UFS 2.0 Spec Section 10.5.12 - UTP Reject UPIU
 988 //
 989 typedef struct {
 990   //
 991   // DW0
 992   //
 993   UINT8  TransCode:6;         /* Transaction Type - 0x3F*/
 994   UINT8  Dd:1;
 995   UINT8  Hd:1;
 996   UINT8  Flags;
 997   UINT8  Lun;
 998   UINT8  TaskTag;             /* Task Tag */
 999
1000   //
1001   // DW1
1002   //
1003   UINT8  Rsvd1[2];
1004   UINT8  Response;            /* Response - 0x01 */
1005   UINT8  Rsvd2;
1006
1007   //
1008   // DW2
1009   //
1010   UINT8  EhsLen;              /* Total EHS Length - 0x00 */
1011   UINT8  DevInfo;             /* Device Information - 0x00 */
1012   UINT16 DataSegLen;          /* Data Segment Length - Big Endian - 0x0000 */
1013
1014   //
1015   // DW3
1016   //
1017   UINT8  HdrSts;              /* Basic Header Status */
1018   UINT8  Rsvd3;
1019   UINT8  E2ESts;              /* End-to-End Status */
1020   UINT8  Rsvd4;
1021
1022   //
1023   // DW4 - DW7
1024   //
1025   UINT8  Rsvd5[16];
1026 } UTP_REJ_UPIU;
1027
1028 //
1029 // UFS 2.0 Spec Section 10.5.13 - UTP NOP OUT UPIU
1030 //
1031 typedef struct {
1032   //
1033   // DW0
1034   //
1035   UINT8  TransCode:6;         /* Transaction Type - 0x00*/
1036   UINT8  Dd:1;
1037   UINT8  Hd:1;
1038   UINT8  Flags;
1039   UINT8  Rsvd1;
1040   UINT8  TaskTag;             /* Task Tag */
1041
1042   //
1043   // DW1
1044   //
1045   UINT8  Rsvd2[4];
1046
1047   //
1048   // DW2
1049   //
1050   UINT8  EhsLen;              /* Total EHS Length - 0x00 */
1051   UINT8  Rsvd3;
1052   UINT16 DataSegLen;          /* Data Segment Length - Big Endian - 0x0000 */
1053
1054   //
1055   // DW3 - DW7
1056   //
1057   UINT8  Rsvd4[20];
1058 } UTP_NOP_OUT_UPIU;
1059
1060 //
1061 // UFS 2.0 Spec Section 10.5.14 - UTP NOP IN UPIU
1062 //
1063 typedef struct {
1064   //
1065   // DW0
1066   //
1067   UINT8  TransCode:6;         /* Transaction Type - 0x20*/
1068   UINT8  Dd:1;
1069   UINT8  Hd:1;
1070   UINT8  Flags;
1071   UINT8  Rsvd1;
1072   UINT8  TaskTag;             /* Task Tag */
1073
1074   //
1075   // DW1
1076   //
1077   UINT8  Rsvd2[2];
1078   UINT8  Resp;                /* Response - 0x00 */
1079   UINT8  Rsvd3;
1080
1081   //
1082   // DW2
1083   //
1084   UINT8  EhsLen;              /* Total EHS Length - 0x00 */
1085   UINT8  DevInfo;             /* Device Information - 0x00 */
1086   UINT16 DataSegLen;          /* Data Segment Length - Big Endian - 0x0000 */
1087
1088   //
1089   // DW3 - DW7
1090   //
1091   UINT8  Rsvd4[20];
1092 } UTP_NOP_IN_UPIU;
1093
1094 //
1095 // UFS Descriptors
1096 //
1097 typedef enum {
1098   UfsDeviceDesc     = 0x00,
1099   UfsConfigDesc     = 0x01,
1100   UfsUnitDesc       = 0x02,
1101   UfsInterConnDesc  = 0x04,
1102   UfsStringDesc     = 0x05,
1103   UfsGeometryDesc   = 0x07,
1104   UfsPowerDesc      = 0x08
1105 } UFS_DESC_IDN;
1106
1107 //
1108 // UFS 2.0 Spec Section 14.1.6.2 - Device Descriptor
1109 //
1110 typedef struct {
1111   UINT8  Length;
1112   UINT8  DescType;
1113   UINT8  Device;
1114   UINT8  DevClass;
1115   UINT8  DevSubClass;
1116   UINT8  Protocol;
1117   UINT8  NumLun;
1118   UINT8  NumWLun;
1119   UINT8  BootEn;
1120   UINT8  DescAccessEn;
1121   UINT8  InitPowerMode;
1122   UINT8  HighPriorityLun;
1123   UINT8  SecureRemovalType;
1124   UINT8  SecurityLun;
1125   UINT8  BgOpsTermLat;
1126   UINT8  InitActiveIccLevel;
1127   UINT16 SpecVersion;
1128   UINT16 ManufactureDate;
1129   UINT8  ManufacturerName;
1130   UINT8  ProductName;
1131   UINT8  SerialName;
1132   UINT8  OemId;
1133   UINT16 ManufacturerId;
1134   UINT8  Ud0BaseOffset;
1135   UINT8  Ud0ConfParamLen;
1136   UINT8  DevRttCap;
1137   UINT16 PeriodicRtcUpdate;
1138   UINT8  Rsvd1[17];
1139   UINT8  Rsvd2[16];
1140 } UFS_DEV_DESC;
1141
1142 typedef struct {
1143   UINT8  Length;
1144   UINT8  DescType;
1145   UINT8  Rsvd1;
1146   UINT8  BootEn;
1147   UINT8  DescAccessEn;
1148   UINT8  InitPowerMode;
1149   UINT8  HighPriorityLun;
1150   UINT8  SecureRemovalType;
1151   UINT8  InitActiveIccLevel;
1152   UINT16 PeriodicRtcUpdate;
1153   UINT8  Rsvd2[5];
1154 } UFS_CONFIG_DESC_GEN_HEADER;
1155
1156 typedef struct {
1157   UINT8  LunEn;
1158   UINT8  BootLunId;
1159   UINT8  LunWriteProt;
1160   UINT8  MemType;
1161   UINT32 NumAllocUnits;
1162   UINT8  DataReliability;
1163   UINT8  LogicBlkSize;
1164   UINT8  ProvisionType;
1165   UINT16 CtxCap;
1166   UINT8  Rsvd1[3];
1167 } UFS_UNIT_DESC_CONFIG_PARAMS;
1168
1169 //
1170 // UFS 2.0 Spec Section 14.1.6.3 - Configuration Descriptor
1171 //
1172 typedef struct {
1173   UFS_CONFIG_DESC_GEN_HEADER  Header;
1174   UFS_UNIT_DESC_CONFIG_PARAMS UnitDescConfParams[8];
1175 } UFS_CONFIG_DESC;
1176
1177 //
1178 // UFS 2.0 Spec Section 14.1.6.4 - Geometry Descriptor
1179 //
1180 typedef struct {
1181   UINT8  Length;
1182   UINT8  DescType;
1183   UINT8  MediaTech;
1184   UINT8  Rsvd1;
1185   UINT64 TotalRawDevCapacity;
1186   UINT8  Rsvd2;
1187   UINT32 SegSize;
1188   UINT8  AllocUnitSize;
1189   UINT8  MinAddrBlkSize;
1190   UINT8  OptReadBlkSize;
1191   UINT8  OptWriteBlkSize;
1192   UINT8  MaxInBufSize;
1193   UINT8  MaxOutBufSize;
1194   UINT8  RpmbRwSize;
1195   UINT8  Rsvd3;
1196   UINT8  DataOrder;
1197   UINT8  MaxCtxIdNum;
1198   UINT8  SysDataTagUnitSize;
1199   UINT8  SysDataResUnitSize;
1200   UINT8  SupSecRemovalTypes;
1201   UINT16 SupMemTypes;
1202   UINT32 SysCodeMaxNumAllocUnits;
1203   UINT16 SupCodeCapAdjFac;
1204   UINT32 NonPersMaxNumAllocUnits;
1205   UINT16 NonPersCapAdjFac;
1206   UINT32 Enhance1MaxNumAllocUnits;
1207   UINT16 Enhance1CapAdjFac;
1208   UINT32 Enhance2MaxNumAllocUnits;
1209   UINT16 Enhance2CapAdjFac;
1210   UINT32 Enhance3MaxNumAllocUnits;
1211   UINT16 Enhance3CapAdjFac;
1212   UINT32 Enhance4MaxNumAllocUnits;
1213   UINT16 Enhance4CapAdjFac;
1214 } UFS_GEOMETRY_DESC;
1215
1216 //
1217 // UFS 2.0 Spec Section 14.1.6.5 - Unit Descriptor
1218 //
1219 typedef struct {
1220   UINT8  Length;
1221   UINT8  DescType;
1222   UINT8  UnitIdx;
1223   UINT8  LunEn;
1224   UINT8  BootLunId;
1225   UINT8  LunWriteProt;
1226   UINT8  LunQueueDep;
1227   UINT8  Rsvd1;
1228   UINT8  MemType;
1229   UINT8  DataReliability;
1230   UINT8  LogicBlkSize;
1231   UINT64 LogicBlkCount;
1232   UINT32 EraseBlkSize;
1233   UINT8  ProvisionType;
1234   UINT64 PhyMemResCount;
1235   UINT16 CtxCap;
1236   UINT8  LargeUnitGranularity;
1237 } UFS_UNIT_DESC;
1238
1239 //
1240 // UFS 2.0 Spec Section 14.1.6.6 - RPMB Unit Descriptor
1241 //
1242 typedef struct {
1243   UINT8  Length;
1244   UINT8  DescType;
1245   UINT8  UnitIdx;
1246   UINT8  LunEn;
1247   UINT8  BootLunId;
1248   UINT8  LunWriteProt;
1249   UINT8  LunQueueDep;
1250   UINT8  Rsvd1;
1251   UINT8  MemType;
1252   UINT8  Rsvd2;
1253   UINT8  LogicBlkSize;
1254   UINT64 LogicBlkCount;
1255   UINT32 EraseBlkSize;
1256   UINT8  ProvisionType;
1257   UINT64 PhyMemResCount;
1258   UINT8  Rsvd3[3];
1259 } UFS_RPMB_UNIT_DESC;
1260
1261 typedef struct {
1262   UINT16 Value:10;
1263   UINT16 Rsvd1:4;
1264   UINT16 Unit:2;
1265 } UFS_POWER_PARAM_ELEMENT;
1266
1267 //
1268 // UFS 2.0 Spec Section 14.1.6.7 - Power Parameter Descriptor
1269 //
1270 typedef struct {
1271   UINT8                    Length;
1272   UINT8                    DescType;
1273   UFS_POWER_PARAM_ELEMENT  ActiveIccLevelVcc[16];
1274   UFS_POWER_PARAM_ELEMENT  ActiveIccLevelVccQ[16];
1275   UFS_POWER_PARAM_ELEMENT  ActiveIccLevelVccQ2[16];
1276 } UFS_POWER_DESC;
1277
1278 //
1279 // UFS 2.0 Spec Section 14.1.6.8 - InterConnect Descriptor
1280 //
1281 typedef struct {
1282   UINT8  Length;
1283   UINT8  DescType;
1284   UINT16 UniProVer;
1285   UINT16 MphyVer;
1286 } UFS_INTER_CONNECT_DESC;
1287
1288 //
1289 // UFS 2.0 Spec Section 14.1.6.9 - 14.1.6.12 - String Descriptor
1290 //
1291 typedef struct {
1292   UINT8  Length;
1293   UINT8  DescType;
1294   CHAR16 Unicode[126];
1295 } UFS_STRING_DESC;
1296
1297 //
1298 // UFS 2.0 Spec Section 14.2 - Flags
1299 //
1300 typedef enum {
1301   UfsFlagDevInit         = 0x01,
1302   UfsFlagPermWpEn        = 0x02,
1303   UfsFlagPowerOnWpEn     = 0x03,
1304   UfsFlagBgOpsEn         = 0x04,
1305   UfsFlagPurgeEn         = 0x06,
1306   UfsFlagPhyResRemoval   = 0x08,
1307   UfsFlagBusyRtc         = 0x09,
1308   UfsFlagPermDisFwUpdate = 0x0B
1309 } UFS_FLAGS_IDN;
1310
1311 //
1312 // UFS 2.0 Spec Section 14.2 - Attributes
1313 //
1314 typedef enum {
1315   UfsAttrBootLunEn         = 0x00,
1316   UfsAttrCurPowerMode      = 0x02,
1317   UfsAttrActiveIccLevel    = 0x03,
1318   UfsAttrOutOfOrderDataEn  = 0x04,
1319   UfsAttrBgOpStatus        = 0x05,
1320   UfsAttrPurgeStatus       = 0x06,
1321   UfsAttrMaxDataInSize     = 0x07,
1322   UfsAttrMaxDataOutSize    = 0x08,
1323   UfsAttrDynCapNeeded      = 0x09,
1324   UfsAttrRefClkFreq        = 0x0a,
1325   UfsAttrConfigDescLock    = 0x0b,
1326   UfsAttrMaxNumOfRtt       = 0x0c,
1327   UfsAttrExceptionEvtCtrl  = 0x0d,
1328   UfsAttrExceptionEvtSts   = 0x0e,
1329   UfsAttrSecondsPassed     = 0x0f,
1330   UfsAttrContextConf       = 0x10,
1331   UfsAttrCorrPrgBlkNum     = 0x11
1332 } UFS_ATTR_IDN;
1333
1334 typedef enum {
1335   UfsNoData                = 0,
1336   UfsDataOut               = 1,
1337   UfsDataIn                = 2,
1338   UfsDdReserved
1339 } UFS_DATA_DIRECTION;
1340
1341
1342 #pragma pack()
1343
1344 #endif
1345