2 Ia32-specific functionality for DxeLoad.
4 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include "VirtualMemory.h"
20 #define IDT_ENTRY_COUNT 32
22 typedef struct _X64_IDT_TABLE
{
24 // Reserved 4 bytes preceding PeiService and IdtTable,
25 // since IDT base address should be 8-byte alignment.
28 CONST EFI_PEI_SERVICES
**PeiService
;
29 X64_IDT_GATE_DESCRIPTOR IdtTable
[IDT_ENTRY_COUNT
];
33 // Global Descriptor Table (GDT)
35 GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT gGdtEntries
[] = {
36 /* selector { Global Segment Descriptor } */
37 /* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //null descriptor
38 /* 0x08 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //linear data segment descriptor
39 /* 0x10 */ {{0xffff, 0, 0, 0xf, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //linear code segment descriptor
40 /* 0x18 */ {{0xffff, 0, 0, 0x3, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system data segment descriptor
41 /* 0x20 */ {{0xffff, 0, 0, 0xa, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system code segment descriptor
42 /* 0x28 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //spare segment descriptor
43 /* 0x30 */ {{0xffff, 0, 0, 0x2, 1, 0, 1, 0xf, 0, 0, 1, 1, 0}}, //system data segment descriptor
44 /* 0x38 */ {{0xffff, 0, 0, 0xa, 1, 0, 1, 0xf, 0, 1, 0, 1, 0}}, //system code segment descriptor
45 /* 0x40 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, //spare segment descriptor
51 GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR gGdt
= {
52 sizeof (gGdtEntries
) - 1,
56 GLOBAL_REMOVE_IF_UNREFERENCED IA32_DESCRIPTOR gLidtDescriptor
= {
57 sizeof (X64_IDT_GATE_DESCRIPTOR
) * IDT_ENTRY_COUNT
- 1,
62 Allocates and fills in the Page Directory and Page Table Entries to
63 establish a 4G page table.
65 @param[in] StackBase Stack base address.
66 @param[in] StackSize Stack size.
68 @return The address of page table.
72 Create4GPageTablesIa32Pae (
73 IN EFI_PHYSICAL_ADDRESS StackBase
,
77 UINT8 PhysicalAddressBits
;
78 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
79 UINTN IndexOfPdpEntries
;
80 UINTN IndexOfPageDirectoryEntries
;
81 UINT32 NumberOfPdpEntriesNeeded
;
82 PAGE_MAP_AND_DIRECTORY_POINTER
*PageMap
;
83 PAGE_MAP_AND_DIRECTORY_POINTER
*PageDirectoryPointerEntry
;
84 PAGE_TABLE_ENTRY
*PageDirectoryEntry
;
87 UINT64 AddressEncMask
;
90 // Make sure AddressEncMask is contained to smallest supported address field
92 AddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
94 PhysicalAddressBits
= 32;
97 // Calculate the table entries needed.
99 NumberOfPdpEntriesNeeded
= (UINT32
) LShiftU64 (1, (PhysicalAddressBits
- 30));
101 TotalPagesNum
= NumberOfPdpEntriesNeeded
+ 1;
102 PageAddress
= (UINTN
) AllocatePages (TotalPagesNum
);
103 ASSERT (PageAddress
!= 0);
105 PageMap
= (VOID
*) PageAddress
;
106 PageAddress
+= SIZE_4KB
;
108 PageDirectoryPointerEntry
= PageMap
;
111 for (IndexOfPdpEntries
= 0; IndexOfPdpEntries
< NumberOfPdpEntriesNeeded
; IndexOfPdpEntries
++, PageDirectoryPointerEntry
++) {
113 // Each Directory Pointer entries points to a page of Page Directory entires.
114 // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
116 PageDirectoryEntry
= (VOID
*) PageAddress
;
117 PageAddress
+= SIZE_4KB
;
120 // Fill in a Page Directory Pointer Entries
122 PageDirectoryPointerEntry
->Uint64
= (UINT64
) (UINTN
) PageDirectoryEntry
| AddressEncMask
;
123 PageDirectoryPointerEntry
->Bits
.Present
= 1;
125 for (IndexOfPageDirectoryEntries
= 0; IndexOfPageDirectoryEntries
< 512; IndexOfPageDirectoryEntries
++, PageDirectoryEntry
++, PhysicalAddress
+= SIZE_2MB
) {
126 if ((PhysicalAddress
< StackBase
+ StackSize
) && ((PhysicalAddress
+ SIZE_2MB
) > StackBase
)) {
128 // Need to split this 2M page that covers stack range.
130 Split2MPageTo4K (PhysicalAddress
, (UINT64
*) PageDirectoryEntry
, StackBase
, StackSize
);
133 // Fill in the Page Directory entries
135 PageDirectoryEntry
->Uint64
= (UINT64
) PhysicalAddress
| AddressEncMask
;
136 PageDirectoryEntry
->Bits
.ReadWrite
= 1;
137 PageDirectoryEntry
->Bits
.Present
= 1;
138 PageDirectoryEntry
->Bits
.MustBe1
= 1;
143 for (; IndexOfPdpEntries
< 512; IndexOfPdpEntries
++, PageDirectoryPointerEntry
++) {
145 PageDirectoryPointerEntry
,
146 sizeof (PAGE_MAP_AND_DIRECTORY_POINTER
)
150 return (UINTN
) PageMap
;
154 The function will check if IA32 PAE is supported.
156 @retval TRUE IA32 PAE is supported.
157 @retval FALSE IA32 PAE is not supported.
167 BOOLEAN Ia32PaeSupport
;
169 Ia32PaeSupport
= FALSE
;
170 AsmCpuid (0x0, &RegEax
, NULL
, NULL
, NULL
);
172 AsmCpuid (0x1, NULL
, NULL
, NULL
, &RegEdx
);
173 if ((RegEdx
& BIT6
) != 0) {
174 Ia32PaeSupport
= TRUE
;
178 return Ia32PaeSupport
;
182 The function will check if Execute Disable Bit is available.
184 @retval TRUE Execute Disable Bit is available.
185 @retval FALSE Execute Disable Bit is not available.
189 IsExecuteDisableBitAvailable (
198 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
199 if (RegEax
>= 0x80000001) {
200 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
201 if ((RegEdx
& BIT20
) != 0) {
203 // Bit 20: Execute Disable Bit available.
213 Transfers control to DxeCore.
215 This function performs a CPU architecture specific operations to execute
216 the entry point of DxeCore with the parameters of HobList.
217 It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
219 @param DxeCoreEntryPoint The entry point of DxeCore.
220 @param HobList The start of HobList passed to DxeCore.
225 IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint
,
226 IN EFI_PEI_HOB_POINTERS HobList
230 EFI_PHYSICAL_ADDRESS BaseOfStack
;
231 EFI_PHYSICAL_ADDRESS TopOfStack
;
233 X64_IDT_GATE_DESCRIPTOR
*IdtTable
;
234 UINTN SizeOfTemplate
;
236 EFI_PHYSICAL_ADDRESS VectorAddress
;
238 X64_IDT_TABLE
*IdtTableForX64
;
239 EFI_VECTOR_HANDOFF_INFO
*VectorInfo
;
240 EFI_PEI_VECTOR_HANDOFF_INFO_PPI
*VectorHandoffInfoPpi
;
241 BOOLEAN BuildPageTablesIa32Pae
;
243 Status
= PeiServicesAllocatePages (EfiBootServicesData
, EFI_SIZE_TO_PAGES (STACK_SIZE
), &BaseOfStack
);
244 ASSERT_EFI_ERROR (Status
);
246 if (FeaturePcdGet(PcdDxeIplSwitchToLongMode
)) {
248 // Compute the top of the stack we were allocated, which is used to load X64 dxe core.
249 // Pre-allocate a 32 bytes which confroms to x64 calling convention.
251 // The first four parameters to a function are passed in rcx, rdx, r8 and r9.
252 // Any further parameters are pushed on the stack. Furthermore, space (4 * 8bytes) for the
253 // register parameters is reserved on the stack, in case the called function
254 // wants to spill them; this is important if the function is variadic.
256 TopOfStack
= BaseOfStack
+ EFI_SIZE_TO_PAGES (STACK_SIZE
) * EFI_PAGE_SIZE
- 32;
259 // x64 Calling Conventions requires that the stack must be aligned to 16 bytes
261 TopOfStack
= (EFI_PHYSICAL_ADDRESS
) (UINTN
) ALIGN_POINTER (TopOfStack
, 16);
264 // Load the GDT of Go64. Since the GDT of 32-bit Tiano locates in the BS_DATA
265 // memory, it may be corrupted when copying FV to high-end memory
267 AsmWriteGdtr (&gGdt
);
269 // Create page table and save PageMapLevel4 to CR3
271 PageTables
= CreateIdentityMappingPageTables (BaseOfStack
, STACK_SIZE
);
274 // End of PEI phase signal
276 Status
= PeiServicesInstallPpi (&gEndOfPeiSignalPpi
);
277 ASSERT_EFI_ERROR (Status
);
279 AsmWriteCr3 (PageTables
);
282 // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
284 UpdateStackHob (BaseOfStack
, STACK_SIZE
);
286 SizeOfTemplate
= AsmGetVectorTemplatInfo (&TemplateBase
);
288 Status
= PeiServicesAllocatePages (
290 EFI_SIZE_TO_PAGES(sizeof (X64_IDT_TABLE
) + SizeOfTemplate
* IDT_ENTRY_COUNT
),
293 ASSERT_EFI_ERROR (Status
);
296 // Store EFI_PEI_SERVICES** in the 4 bytes immediately preceding IDT to avoid that
297 // it may not be gotten correctly after IDT register is re-written.
299 IdtTableForX64
= (X64_IDT_TABLE
*) (UINTN
) VectorAddress
;
300 IdtTableForX64
->PeiService
= GetPeiServicesTablePointer ();
302 VectorAddress
= (EFI_PHYSICAL_ADDRESS
) (UINTN
) (IdtTableForX64
+ 1);
303 IdtTable
= IdtTableForX64
->IdtTable
;
304 for (Index
= 0; Index
< IDT_ENTRY_COUNT
; Index
++) {
305 IdtTable
[Index
].Ia32IdtEntry
.Bits
.GateType
= 0x8e;
306 IdtTable
[Index
].Ia32IdtEntry
.Bits
.Reserved_0
= 0;
307 IdtTable
[Index
].Ia32IdtEntry
.Bits
.Selector
= SYS_CODE64_SEL
;
309 IdtTable
[Index
].Ia32IdtEntry
.Bits
.OffsetLow
= (UINT16
) VectorAddress
;
310 IdtTable
[Index
].Ia32IdtEntry
.Bits
.OffsetHigh
= (UINT16
) (RShiftU64 (VectorAddress
, 16));
311 IdtTable
[Index
].Offset32To63
= (UINT32
) (RShiftU64 (VectorAddress
, 32));
312 IdtTable
[Index
].Reserved
= 0;
314 CopyMem ((VOID
*) (UINTN
) VectorAddress
, TemplateBase
, SizeOfTemplate
);
315 AsmVectorFixup ((VOID
*) (UINTN
) VectorAddress
, (UINT8
) Index
);
317 VectorAddress
+= SizeOfTemplate
;
320 gLidtDescriptor
.Base
= (UINTN
) IdtTable
;
323 // Disable interrupt of Debug timer, since new IDT table cannot handle it.
325 SaveAndSetDebugTimerInterrupt (FALSE
);
327 AsmWriteIdtr (&gLidtDescriptor
);
331 "%a() Stack Base: 0x%lx, Stack Size: 0x%x\n",
338 // Go to Long Mode and transfer control to DxeCore.
339 // Interrupts will not get turned on until the CPU AP is loaded.
340 // Call x64 drivers passing in single argument, a pointer to the HOBs.
345 (EFI_PHYSICAL_ADDRESS
)(UINTN
)(HobList
.Raw
),
351 // Get Vector Hand-off Info PPI and build Guided HOB
353 Status
= PeiServicesLocatePpi (
354 &gEfiVectorHandoffInfoPpiGuid
,
357 (VOID
**)&VectorHandoffInfoPpi
359 if (Status
== EFI_SUCCESS
) {
360 DEBUG ((EFI_D_INFO
, "Vector Hand-off Info PPI is gotten, GUIDed HOB is created!\n"));
361 VectorInfo
= VectorHandoffInfoPpi
->Info
;
363 while (VectorInfo
->Attribute
!= EFI_VECTOR_HANDOFF_LAST_ENTRY
) {
368 &gEfiVectorHandoffInfoPpiGuid
,
369 VectorHandoffInfoPpi
->Info
,
370 sizeof (EFI_VECTOR_HANDOFF_INFO
) * Index
375 // Compute the top of the stack we were allocated. Pre-allocate a UINTN
378 TopOfStack
= BaseOfStack
+ EFI_SIZE_TO_PAGES (STACK_SIZE
) * EFI_PAGE_SIZE
- CPU_STACK_ALIGNMENT
;
379 TopOfStack
= (EFI_PHYSICAL_ADDRESS
) (UINTN
) ALIGN_POINTER (TopOfStack
, CPU_STACK_ALIGNMENT
);
382 BuildPageTablesIa32Pae
= (BOOLEAN
) (PcdGetBool (PcdSetNxForStack
) && IsIa32PaeSupport () && IsExecuteDisableBitAvailable ());
383 if (BuildPageTablesIa32Pae
) {
384 PageTables
= Create4GPageTablesIa32Pae (BaseOfStack
, STACK_SIZE
);
385 EnableExecuteDisableBit ();
389 // End of PEI phase signal
391 Status
= PeiServicesInstallPpi (&gEndOfPeiSignalPpi
);
392 ASSERT_EFI_ERROR (Status
);
394 if (BuildPageTablesIa32Pae
) {
395 AsmWriteCr3 (PageTables
);
397 // Set Physical Address Extension (bit 5 of CR4).
399 AsmWriteCr4 (AsmReadCr4 () | BIT5
);
403 // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
405 UpdateStackHob (BaseOfStack
, STACK_SIZE
);
409 "%a() Stack Base: 0x%lx, Stack Size: 0x%x\n",
416 // Transfer the control to the entry point of DxeCore.
418 if (BuildPageTablesIa32Pae
) {
420 (SWITCH_STACK_ENTRY_POINT
)(UINTN
)DxeCoreEntryPoint
,
423 (VOID
*) (UINTN
) TopOfStack
427 (SWITCH_STACK_ENTRY_POINT
)(UINTN
)DxeCoreEntryPoint
,
430 (VOID
*) (UINTN
) TopOfStack