MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h

   1 /** @file
   2   x64 Long Mode Virtual Memory Management Definitions
   3
   4   References:
   5     1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
   6     2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
   7     3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
   8     4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
   9
  10 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
  11 This program and the accompanying materials
  12 are licensed and made available under the terms and conditions of the BSD License
  13 which accompanies this distribution.  The full text of the license may be found at
  14 http://opensource.org/licenses/bsd-license.php
  15
  16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  18
  19 **/
  20 #ifndef _VIRTUAL_MEMORY_H_
  21 #define _VIRTUAL_MEMORY_H_
  22
  23
  24 #define SYS_CODE64_SEL 0x38
  25
  26 #pragma pack(1)
  27
  28 typedef union {
  29   struct {
  30     UINT32  LimitLow    : 16;
  31     UINT32  BaseLow     : 16;
  32     UINT32  BaseMid     : 8;
  33     UINT32  Type        : 4;
  34     UINT32  System      : 1;
  35     UINT32  Dpl         : 2;
  36     UINT32  Present     : 1;
  37     UINT32  LimitHigh   : 4;
  38     UINT32  Software    : 1;
  39     UINT32  Reserved    : 1;
  40     UINT32  DefaultSize : 1;
  41     UINT32  Granularity : 1;
  42     UINT32  BaseHigh    : 8;
  43   } Bits;
  44   UINT64  Uint64;
  45 } IA32_GDT;
  46
  47 typedef struct {
  48   IA32_IDT_GATE_DESCRIPTOR  Ia32IdtEntry;
  49   UINT32                    Offset32To63;
  50   UINT32                    Reserved;
  51 } X64_IDT_GATE_DESCRIPTOR;
  52
  53 //
  54 // Page-Map Level-4 Offset (PML4) and
  55 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  56 //
  57
  58 typedef union {
  59   struct {
  60     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  61     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  62     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  63     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  64     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  65     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  66     UINT64  Reserved:1;               // Reserved
  67     UINT64  MustBeZero:2;             // Must Be Zero
  68     UINT64  Available:3;              // Available for use by system software
  69     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  70     UINT64  AvabilableHigh:11;        // Available for use by system software
  71     UINT64  Nx:1;                     // No Execute bit
  72   } Bits;
  73   UINT64    Uint64;
  74 } PAGE_MAP_AND_DIRECTORY_POINTER;
  75
  76 //
  77 // Page Table Entry 4KB
  78 //
  79 typedef union {
  80   struct {
  81     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  82     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  83     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  84     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  85     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  86     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  87     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
  88     UINT64  PAT:1;                    //
  89     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  90     UINT64  Available:3;              // Available for use by system software
  91     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  92     UINT64  AvabilableHigh:11;        // Available for use by system software
  93     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
  94   } Bits;
  95   UINT64    Uint64;
  96 } PAGE_TABLE_4K_ENTRY;
  97
  98 //
  99 // Page Table Entry 2MB
 100 //
 101 typedef union {
 102   struct {
 103     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
 104     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
 105     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
 106     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
 107     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 108     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
 109     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
 110     UINT64  MustBe1:1;                // Must be 1
 111     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 112     UINT64  Available:3;              // Available for use by system software
 113     UINT64  PAT:1;                    //
 114     UINT64  MustBeZero:8;             // Must be zero;
 115     UINT64  PageTableBaseAddress:31;  // Page Table Base Address
 116     UINT64  AvabilableHigh:11;        // Available for use by system software
 117     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
 118   } Bits;
 119   UINT64    Uint64;
 120 } PAGE_TABLE_ENTRY;
 121
 122 //
 123 // Page Table Entry 1GB
 124 //
 125 typedef union {
 126   struct {
 127     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
 128     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
 129     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
 130     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
 131     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 132     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
 133     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
 134     UINT64  MustBe1:1;                // Must be 1
 135     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 136     UINT64  Available:3;              // Available for use by system software
 137     UINT64  PAT:1;                    //
 138     UINT64  MustBeZero:17;            // Must be zero;
 139     UINT64  PageTableBaseAddress:22;  // Page Table Base Address
 140     UINT64  AvabilableHigh:11;        // Available for use by system software
 141     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
 142   } Bits;
 143   UINT64    Uint64;
 144 } PAGE_TABLE_1G_ENTRY;
 145
 146 #pragma pack()
 147
 148 #define IA32_PG_P                   BIT0
 149 #define IA32_PG_RW                  BIT1
 150
 151 /**
 152   Enable Execute Disable Bit.
 153
 154 **/
 155 VOID
 156 EnableExecuteDisableBit (
 157   VOID
 158   );
 159
 160 /**
 161   Split 2M page to 4K.
 162
 163   @param[in]      PhysicalAddress       Start physical address the 2M page covered.
 164   @param[in, out] PageEntry2M           Pointer to 2M page entry.
 165   @param[in]      StackBase             Stack base address.
 166   @param[in]      StackSize             Stack size.
 167
 168 **/
 169 VOID
 170 Split2MPageTo4K (
 171   IN EFI_PHYSICAL_ADDRESS               PhysicalAddress,
 172   IN OUT UINT64                         *PageEntry2M,
 173   IN EFI_PHYSICAL_ADDRESS               StackBase,
 174   IN UINTN                              StackSize
 175   );
 176
 177 /**
 178   Allocates and fills in the Page Directory and Page Table Entries to
 179   establish a 1:1 Virtual to Physical mapping.
 180
 181   @param[in] StackBase  Stack base address.
 182   @param[in] StackSize  Stack size.
 183
 184   @return The address of 4 level page map.
 185
 186 **/
 187 UINTN
 188 CreateIdentityMappingPageTables (
 189   IN EFI_PHYSICAL_ADDRESS   StackBase,
 190   IN UINTN                  StackSize
 191   );
 192
 193
 194 /**
 195
 196   Fix up the vector number in the vector code.
 197
 198   @param VectorBase   Base address of the vector handler.
 199   @param VectorNum    Index of vector.
 200
 201 **/
 202 VOID
 203 EFIAPI
 204 AsmVectorFixup (
 205   VOID    *VectorBase,
 206   UINT8   VectorNum
 207   );
 208
 209
 210 /**
 211
 212   Get the information of vector template.
 213
 214   @param TemplateBase   Base address of the template code.
 215
 216   @return               Size of the Template code.
 217
 218 **/
 219 UINTN
 220 EFIAPI
 221 AsmGetVectorTemplatInfo (
 222   OUT   VOID  **TemplateBase
 223   );
 224
 225
 226 #endif