MdeModulePkg/Core/Pei/Ipf/IpfCpuCore.i

   1 //++
   2 // Copyright (c) 2006, Intel Corporation
   3 // All rights reserved. This program and the accompanying materials
   4 // are licensed and made available under the terms and conditions of the BSD License
   5 // which accompanies this distribution.  The full text of the license may be found at
   6 // http://opensource.org/licenses/bsd-license.php
   7 //
   8 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   9 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10 //
  11 // Module Name:
  12 //
  13 //   IpfCpuCore.i
  14 //
  15 // Abstract:
  16 //   IPF CPU definitions
  17 //
  18 //--
  19
  20 #ifndef _IPF_CPU_CORE_
  21 #define _IPF_CPU_CORE_
  22
  23 //
  24 // Include common header file for this module.
  25 //
  26 #include "CommonHeader.h"
  27
  28 #define  PEI_BSP_STORE_SIZE                     0x4000
  29 #define  ResetFn                                0x00
  30 #define  MachineCheckFn                         0x01
  31 #define  InitFn                                 0x02
  32 #define  RecoveryFn                             0x03
  33 #define  GuardBand                              0x10
  34
  35 //
  36 // Define hardware RSE Configuration Register
  37 //
  38
  39 //
  40 // RS Configuration (RSC) bit field positions
  41 //
  42 #define RSC_MODE       0
  43 #define RSC_PL         2
  44 #define RSC_BE         4
  45 //
  46 // RSC bits 5-15 reserved
  47 //
  48 #define RSC_MBZ0       5
  49 #define RSC_MBZ0_V     0x3ff
  50 #define RSC_LOADRS     16
  51 #define RSC_LOADRS_LEN 14
  52 //
  53 // RSC bits 30-63 reserved
  54 //
  55 #define RSC_MBZ1       30
  56 #define RSC_MBZ1_V     0x3ffffffffULL
  57
  58 //
  59 // RSC modes
  60 //
  61
  62 //
  63 // Lazy
  64 //
  65 #define RSC_MODE_LY (0x0)
  66 //
  67 // Store intensive
  68 //
  69 #define RSC_MODE_SI (0x1)
  70 //
  71 // Load intensive
  72 //
  73 #define RSC_MODE_LI (0x2)
  74 //
  75 // Eager
  76 //
  77 #define RSC_MODE_EA (0x3)
  78
  79 //
  80 // RSC Endian bit values
  81 //
  82 #define RSC_BE_LITTLE 0
  83 #define RSC_BE_BIG    1
  84
  85 //
  86 // RSC while in kernel: enabled, little endian, pl = 0, eager mode
  87 //
  88 #define RSC_KERNEL ((RSC_MODE_EA<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
  89 //
  90 // Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
  91 //
  92 #define RSC_KERNEL_LAZ ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
  93 //
  94 // RSE disabled: disabled, pl = 0, little endian, eager mode
  95 //
  96 #define RSC_KERNEL_DISABLED ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
  97
  98 #endif